Test control method and device of memory, chip, equipment and storage medium

Abstract

The embodiment of the invention discloses a test control method and device of a memory, a chip, equipment and a storage medium, the method is applied to a system control processor SCP, and the method comprises the following steps: responding to a starting operation of a system on chip of the chip, and starting the SCP; after a second-level boot loader of the SCP is executed, if it is detected that the power-on state register information is power-on starting information, whether memory self-test MBIST needs to be carried out in current starting or not is determined on the basis of test running field information in the nonvolatile memory; if MBIST needs to be carried out on the current starting, locking configuration of the test clock frequency is carried out on the phase-locked loop, and when locking succeeds, based on configured test link information, the MBIST device is controlled to carry out self-test on a target memory of the chip. Through the technical scheme of the embodiment of the invention, the memory test in the chip can be effectively controlled, so that the test resources are saved, and the memory test flexibility is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory test control method, device, chip, equipment and storage medium. Background Art

[0002] As chip design scale and complexity increase, memory accounts for an increasingly large proportion of the chip, resulting in higher and higher requirements for memory reliability and quality, necessitating the need to test the memory in the chip.

[0003] At present, the test code is usually fixed and written into the system startup program, so that the memory test operation is directly executed every time the system is started. However, this method will execute the memory test operation even when the memory does not need to be tested, resulting in a waste of test resources. It can be seen that there is an urgent need for an effective control method for memory testing to improve the flexibility of memory testing. Summary of the invention

[0004] The present invention provides a memory test control method, device, chip, equipment and storage medium to effectively control the memory test in the chip, and perform the memory test operation when the memory needs to be tested, thereby saving test resources and improving the flexibility of memory testing.

[0005] According to one aspect of the present invention, a memory test control method is provided, which is applied to a system control processor SCP, comprising:

[0006] In response to a startup operation of the system on chip of the chip, the SCP starts up;

[0007] After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is power-on startup information, it is determined whether the memory self-test test MBIST is required for the current startup based on the test run field information in the non-volatile memory;

[0008] If MBIST is required for the current startup, the phase-locked loop is configured to lock the test clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test on the target memory of the chip based on the configured test link information.

[0009] According to another aspect of the present invention, there is provided a memory test control device, which is integrated in a system control processor SCP, comprising:

[0010] The SCP startup module is used to start the SCP in response to the startup operation of the chip system on chip;

[0011] A detection module, used for determining whether a memory self-test MBSIT is required for the current startup based on the test run field information in the non-volatile memory after the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information;

[0012] The control module is used to lock the test clock frequency of the phase-locked loop if the MBSIT condition is met during the current startup, and when the locking is successful, control the MBSIT device to perform a self-test on the target memory of the chip based on the configured test link information.

[0013] According to another aspect of the present invention, an embodiment of the present invention further provides a chip, the chip comprising: a system control processor SCP, a memory self-test test MBIST device and a target memory to be tested, wherein:

[0014] The system control processor SCP is used to execute the memory test control method provided by any embodiment of the present invention.

[0015] According to another aspect of the present invention, an embodiment of the present invention further provides an electronic device, characterized in that the electronic device includes the chip provided by the embodiment of the present invention.

[0016] According to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the memory test control method described in any embodiment of the present invention when executed.

[0017] The technical solution of the embodiment of the present invention is that the system control processor SCP responds to the startup operation of the chip system on chip, and the SCP is started. After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information, it is determined based on the test operation field information in the non-volatile memory whether the current startup needs to perform a memory self-test MBIST; if the current startup needs to perform MBIST, the phase-locked loop is locked and configured to test the clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test test on the target memory of the chip based on the configured test link information, so that when the system control processor SCP detects that the current startup needs to perform MBIST, the MBIST device is controlled to perform a self-test test on the memory, thereby realizing effective control of the memory test, avoiding the situation that the memory test is still performed when the memory test is not needed, thereby saving test resources and improving the flexibility of the memory test.

[0018] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 It is a flowchart of a memory test control method provided in the first embodiment of the present invention;

[0021] Figure 2 It is a flowchart of another memory test control method provided by the second embodiment of the present invention;

[0022] Figure 3 It is a structural diagram of an MBIST device involved in Embodiment 2 of the present invention;

[0023] Figure 4 It is a flowchart of another memory test control method provided by the third embodiment of the present invention;

[0024] Figure 5 It is a structural schematic diagram of a memory test control device provided by a fourth embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of the structure of a chip provided by Embodiment 5 of the present invention;

[0026] Figure 7 It is a structural schematic diagram of an electronic device provided in Embodiment 6 of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the term "target" and the like in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] Embodiment 1

[0030] Figure 1 The flowchart of a memory test control method provided in the first embodiment of the present invention is applicable to the case of testing the memory inside the chip. The method can be executed by a memory test control device, which can be implemented in the form of hardware and / or software, and can be integrated into a system control processor SCP (System Controll Processor). Figure 1 As shown, the method specifically comprises the following steps:

[0031] S110 , in response to a startup operation of the system on chip of the chip, the SCP starts up.

[0032] Among them, the chip can be a device that is a miniaturized integrated circuit. For example, the chip can include but is not limited to: CPU (Central Processing Unit), GPU (Graphics Processing Unit) or DPU (Data Processing Unit). System on Chip SOC (System On Chip) refers to a complete system integrated on a chip, which can include all the contents of embedded software. SCP is a dedicated processor for system control and power management. SCP firmware is the first CPU mini-system to run in a multi-CPU architecture, so that it can be detected in the SCP firmware whether a memory test is required during the current startup.

[0033] Specifically, after the chip system is reset and started, the SCP is started first, so that the SCP can effectively control the memory test by using its own firmware.

[0034] S120: After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is power-on startup information, it is determined whether a memory self-test MBIST is required for the current startup based on the test run field information in the non-volatile memory.

[0035] Among them, the boot loader is a program for booting the operating system. The second-level boot loader BL2 (2ndlevel Boot Loader) is booted and authenticated by the first-level boot loader BL1 (1st level Boot Loader). The system on chip has only one ROM (Read-Only Memory). The first-level boot loader BL1 is stored in the ROM. The first-level boot loader BL1 is the first boot loader executed. The power-on status register stores information for indicating whether power-on startup is performed. The power-on startup information can be information for indicating power-on startup, such as a value of 1. Non-volatile memory (NVM) is a memory in which the stored data will not disappear after the current is turned off. For example, the non-volatile memory can be a ROM or a Flash memory. The test run field information can be pre-configured based on business requirements, and is used to indicate whether a memory self-test test is required, such as the Run_mbist field. For example, the test run field information can include a first value or a second value, wherein the first value is used to indicate a value for which a memory self-test test is required, such as 1. The second value is used to represent a value that does not require a memory self-test, such as 0. The memory self-test MBIST (Memory Built-In Self-Test) is a memory built-in self-test, and its test vector for the memory is automatically generated by a built-in memory test logic rather than an external tester.

[0036] Specifically, during the startup process of SCP, the first-level boot loader BL1 of SCP is executed first, and the first-level boot loader BL1 can guide and authenticate the second-level boot loader BL2, and then the second-level boot loader BL2 of SCP is executed, so as to ensure the stability of ROM code. The detection of memory test is performed in the stage after the execution of the second-level boot loader of SCP. For example, after SCP starts to execute the second-level boot loader BL2 from ROM, it can be determined whether the current startup is power-on startup by detecting whether the power-on status register information is power-on startup information. If the power-on status register information is power-on startup information, it indicates that the current startup is power-on startup, and then based on the test run field information in the non-volatile memory, it is determined whether the current startup needs to perform a memory self-test test MBIST, so that MBIST is only performed for power-on startup. If the power-on status register information is not power-on startup information, it indicates that the current startup may be a software restart, etc., and there is no need to not perform MBIST, and the system on chip can be normally started at this time.

[0037] Exemplarily, "determining whether a memory self-test test MBIST is required at the current startup based on the test running field information in the non-volatile memory" in S120 may include: if the test running field information in the non-volatile memory is a first value, determining that a memory self-test test MBIST is required at the current startup; if the test running field information in the non-volatile memory is a second value, determining that a memory self-test test MBIST is not required at the current startup.

[0038] Specifically, when a memory test needs to be performed after the system on chip is started, the test running field information in the non-volatile memory can be configured as a first value. When a memory test is not required after the system on chip is started, the test running field information in the non-volatile memory can be configured as a second value, so that by configuring different test running field information, whether the memory test is performed at the current startup can be effectively controlled, thereby improving the flexibility of the memory test.

[0039] Exemplarily, "determining whether a memory self-test test MBIST is required at the current startup based on the test run field information in the non-volatile memory" in S120 may also include: if the test run field information in the non-volatile memory is a third value, determining whether a memory self-test test MBIST is required at the current startup based on the first power-on control word information.

[0040] Among them, the third value can be a value used to characterize whether the memory self-test is performed by the first power-on control word information, such as 2. The first power-on control word information can refer to the information of the hardware external pin, which is used to characterize whether the memory self-test is performed. The first power-on control word information can be characterized by a numerical value. For example, the first power-on control word information may include a fourth numerical value or a fifth numerical value. The fourth numerical value can be used to characterize a numerical value for which a memory self-test needs to be performed, such as 1, which can correspond to a high level. The fifth numerical value can be used to characterize a numerical value for which a memory self-test does not need to be performed, such as 0, which can correspond to a low level.

[0041] Particularly, when whether the memory needs to be tested needs to be controlled by external hardware, the test operation field information can be configured to the 3rd numerical value, so that the decision power of whether to test is given to the first power-on control word information.Can be the 4th numerical value or the 5th numerical value to decide whether to carry out the memory self-test test MBIST when starting according to the first power-on control word information.By deciding whether the MBIST function comes into effect by the first power-on control word information of outside, can carry out test control more conveniently, need not to revise internal information, further improve the convenience and the flexibility of test control.

[0042] Exemplarily, determining whether a memory self-test test MBIST is required at the current startup based on the first power-on control word information may include: if the first power-on control word information is a fourth value, determining that a memory self-test test MBSIT is required at the current startup; if the first power-on control word information is a fifth value, determining that a memory self-test test MBIST is not required at the current startup.

[0043] Specifically, when a memory test is required after the system on chip is started, the first power-on control word information can be adjusted to the fourth value by adjusting the external pin level. When a memory test is not required after the system on chip is started, the first power-on control word information can be adjusted to the fifth value, so that by configuring different first power-on control word information, it is possible to more conveniently and effectively control whether to perform a memory test during the current startup, thereby improving the convenience and flexibility of the memory test.

[0044] S130, if MBIST is required for the current startup, the phase-locked loop is configured to lock the test clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test on the target memory of the chip based on the configured test link information.

[0045] Wherein, phase locked loop (PLL) is a kind of feedback control circuit, and it utilizes the reference signal of external input to control the frequency and phase of loop internal oscillation signal, realizes the automatic tracking of output signal frequency to input signal frequency.Test clock frequency can be the clock frequency used for MBIST that is pre-configured.Test link information can be the link information that is pre-configured, used for testing memory in MBIST device.MBIST device is connected to SCP for communication.MBIST device can be used for carrying out self-check test to memory under SCP control.The target memory of chip can refer to the memory that needs to be tested in chip.

[0046] Particularly, when determining that the second startup needs to carry out MBIST, SCP can configure the clock frequency of the phase-locked loop as the test clock frequency, and locks this test clock frequency. If the locking is successful, then it shows that the MBIST test can be normally started, and SCP can send the test link information of configuration to the MBIST device, so that the MBIST device carries out a self-check test to the target memory based on this test link information, thereby realizing the detection of the memory hard failure of the chip interior, avoiding fault leakage to the client side, improving the abnormal detectability of the chip interior, and performing the memory test operation again when only needing to test, greatly saving test resources, and improving the flexibility of memory test.

[0047] Exemplarily, if the test clock frequency lock fails, it indicates that there is a problem with this test channel and the MBIST test cannot be started normally. At this time, the cause of the error can be recorded and reported to the CPU of the chip, so that the CPU processes the reported cause of the error accordingly, such as storing the cause of the error in a log, etc., so that the R&D personnel can analyze and solve the problem.

[0048] Exemplarily, after the MBIST device carries out the self-check test to the target memory, the MBIST device can actively send the test result to SCP, or, SCP can also actively inquire about and obtain the test result from the MBIST device.If the test result of the target memory is the test failure result, then can according to the preset processing mode, the test failure result is processed, such as the test failure result is reported in the designated device.Exemplarily, if the test result of the target memory is the test success result, promptly does not have the MBIST test failure mark, then the phase-locked loop is carried out the locking configuration of non-test clock frequency, and normally starts the system on chip.The clock frequency by configuring the phase-locked loop is the non-test clock frequency, can normally start, continue to run the system on chip, thereby guarantee the normal storage of the target memory in the system on chip operation process.

[0049] The technical solution of the embodiment of the present invention is that the system control processor SCP responds to the startup operation of the chip system on chip, and the SCP is started. After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information, it is determined based on the test operation field information in the non-volatile memory whether the current startup needs to perform a memory self-test MBIST; if the current startup needs to perform MBIST, the phase-locked loop is locked and configured to test the clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test test on the target memory of the chip based on the configured test link information, so that when the system control processor SCP detects that the current startup needs to perform MBIST, the MBIST device is controlled to perform a self-test test on the memory, thereby realizing effective control of the memory test, avoiding the situation that the memory test is still performed when the memory test is not needed, thereby saving test resources and improving the flexibility of the memory test.

[0050] Embodiment 2

[0051] Figure 2 A flow chart of another method for controlling the test of a memory provided in Embodiment 2 of the present invention. In this embodiment, based on the above-mentioned embodiment, an MBIST device may include: an SCP system control module, a read-only memory ROM module, an MBIST interface processing module and an MBIST control module. On this basis, the step of "controlling the MBIST device to perform a self-test on the target memory of the chip based on the configured test link information" is optimized, and the explanation of the terms identical or corresponding to the above-mentioned embodiments is not repeated here.

[0052] See also Figure 2 The memory test control method provided in this embodiment specifically includes the following steps:

[0053] S210 : In response to a startup operation of the system on chip of the chip, the SCP starts up.

[0054] S220: After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is power-on startup information, it is determined whether a memory self-test MBIST is required for the current startup based on the test run field information in the non-volatile memory.

[0055] S230, if MBIST is required for the current startup, the phase-locked loop is locked and configured to test the clock frequency, and when the locking is successful, the SCP controls the test startup field information in the SCP system control module to be configured as startup information, and sends the configured test link information to the SCP system control module.

[0056] Wherein, the SCP system control module is the interface module that the firmware running on the SCP gives orders.The test start field information is used to characterize the field information of whether needing to start the MBIST test.Startup information can be used to characterize the information that needs to start the MBIST test, and it can utilize modes such as numerical value to characterize.

[0057] Specifically, see Figure 3 , when the current startup needs to perform MBIST, and the test clock frequency is locked successfully, the SCP can configure the test startup field information in the SCP system control module as startup information, thereby allowing the test of the MBIST device to be started. In addition, the SCP sends the configured test link information to the SCP system control module, so that the MBIST device performs the MBIST test based on the test link information.

[0058] S240, the SCP system control module sends the received test link information to the MBIST interface processing module.

[0059] Among them, the MBIST interface processing module is a module used to convert and send instructions between SCP and MBIST.

[0060] Specifically, see Figure 3 , SCP can send the configured test link information to the MBIST interface processing module through the SCP system control module.

[0061] S250, the MBIST interface processing module decodes and translates the received test link information based on the MBIST microinstructions stored in the ROM module, determines the target test instructions, and sends the target test instructions to the MBIST control module.

[0062] The ROM module is used to store microinstructions in the MBIST mode. Figure 3 After the MBIST interface processing module receives the test link information sent by the SCP system control module, it can read the actually required MBIST microinstructions from the ROM module, decode and translate the test link information into target test instructions that can be recognized by the MBIST control module, and send the target test instructions to the corresponding MBIST control module.

[0063] S260, the MBIST control module performs a self-test on the target memory of the chip by executing the target test instruction.

[0064] Wherein, the MBIST control module is connected with the target memory of chip.The MBIST control module can be used for carrying out the MBIST test to the memory for which it is responsible.The quantity of the MBIST control module can be multiple.Can specify the required MBIST control module used by the test link information of configuration, thereby utilize the MBIST control module to complete the self-test test of the target memory.

[0065] Exemplarily, the MBIST control module can use different algorithms to produce corresponding incentives and the detection of results for different error models, and can develop corresponding algorithm mode registers for the upper control module to select, and can also provide a group of self-defined test registers to add some targeted tests outside the standard algorithm.

[0066] Exemplarily, after S260, the process further includes: the MBIST control module stores the test result of the target memory in a status register in the SCP system control module; and the SCP reads the test result of the target memory from the status register in the SCP system control module.

[0067] Specifically, the MBIST control module can report the MBIST test result of the target memory to the SCP system control module, and the SCP system control module stores the reported test result in its own status register, so that the SCP can quickly obtain the test result of the target memory by querying the status register in the SCP system control module.

[0068] The technical solution of this embodiment can realize information communication between SCP and MBIST by utilizing the SCP system control module, the read-only memory ROM module, the MBIST interface processing module and the MBIST control module, so that the SCP can effectively control the MBIST test of the memory and ensure the accuracy and flexibility of the memory test control.

[0069] Embodiment 3

[0070] Figure 4 This is a flowchart of another memory test control method provided in Embodiment 3 of the present invention. Based on the above embodiments, this embodiment describes in detail the processing process of test failure results, and the explanations of terms that are the same or corresponding to the above embodiments are not repeated here.

[0071] See also Figure 4 The memory test control method provided in this embodiment specifically includes the following steps:

[0072] S410 : In response to a startup operation of the system on chip of the chip, the SCP starts up.

[0073] S420: After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is power-on startup information, it is determined whether a memory self-test MBIST is required for the current startup based on the test run field information in the non-volatile memory.

[0074] S430: If MBIST is required for the current startup, the phase-locked loop is configured to lock the test clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test on the target memory of the chip based on the configured test link information.

[0075] S440: If the test result of the target memory is a test failure result, determine a target processing method based on the test failure log field information in the non-volatile memory, and process the test failure result based on the target processing method.

[0076] The test failure log field information is stored in a non-volatile memory and is used to characterize the storage and reporting method of the failure result, such as mbist_err_log information.

[0077] Specifically, when the MBIST test result of the target memory is a test failure result, the test failure log field information in the non-volatile memory can be obtained, the target processing method corresponding to the test failure log field information can be determined, and the test failure result can be processed according to the target processing method, thereby improving the diversity and flexibility of failure processing and meeting personalized needs.

[0078] Exemplarily, S440 may include: if the first element information in the test failure log field information in the non-volatile memory is the sixth value, based on the FLASH storage method, storing the test failure result in the FLASH device, so that the baseboard management controller obtains the test failure result by querying the FLASH device.

[0079] The test failure log field information may be an array, and the first element information refers to the first element value in the array, namely, mbist_err_log[0]. The sixth value may be used to indicate that the first element information is valid information. For example, the sixth value may be 1. The FLASH device may refer to a non-volatile flash memory device. The baseboard management controller (BMC) may perform some operations such as firmware upgrade and device status check on the system on chip when the system on chip is not started.

[0080] Specifically, the first element information in the test failure log field information in the non-volatile memory is the sixth value. For example, when mbist_err_log[0] is 1, it can be determined that the target processing method is the FLASH storage method. At this time, SCP can access the FLASH device through the QSPI (Quad Serial Peripheral Interface) bus and store the test failure result in the FLASH device. The subsequent baseboard management controller can obtain the test failure result by querying the FLASH device. Therefore, when the memory test is abnormal, the user can obtain the test failure result through the baseboard management controller, so that the technician can handle the abnormality in time.

[0081] Exemplarily, S440 may further include: if the second bit element information in the test failure log field information in the non-volatile memory is a sixth value, reporting the test failure result to the baseboard management controller based on the general input and output port mode.

[0082] The test failure log field information may be an array, and the second element information refers to the second element value in the array, namely, mbist_err_log[1]. The sixth value may be used to indicate that the second element information is valid information. For example, the sixth value may be 1. A general purpose input output port (GPIO) is a port that inputs or outputs information through a pin high or low level.

[0083] Specifically, the second element information in the test failure log field information in the non-volatile memory is the sixth value. For example, when mbist_err_log[1] is 1, it can be determined that the target processing mode is the general input and output port mode. At this time, the SCP can report the test failure result notification to the baseboard management controller through GPIO, so that the baseboard management controller can obtain the test failure result in time.

[0084] Exemplarily, S440 may further include: if the third bit element information in the test failure log field information in the non-volatile memory is a sixth value, reporting the test failure result to the baseboard management controller based on a watchdog timer method.

[0085] The test failure log field information may be an array, and the third element information refers to the third element value in the array, namely, mbist_err_log[2]. The sixth value may be used to indicate that the third element information is valid information. For example, the sixth value may be 1. The watchdog timer method is a method of generating interrupts at a fixed time.

[0086] Specifically, when the third element information in the test failure log field information in the non-volatile memory is the sixth value, for example, when mbist_err_log[2] is 1, it can be determined that the target processing method is the watchdog timer method. At this time, the SCP can report the test failure result notification to the baseboard management controller through the watchdog timer, so that the baseboard management controller can obtain the test failure result in time.

[0087] Exemplarily, based on the watchdog timer method, reporting the test failure result to the baseboard management controller may include: if it is detected that the second power-on control word information is the seventh value, initializing the communication bus and starting the watchdog timer, and when the time is reached, reporting the test failure result to the baseboard management controller.

[0088] Among them, the second power-on control word information may refer to the information of the hardware external pin, which is used to characterize whether the timing report is allowed. The second power-on control word information can be characterized by a numerical value. For example, the second power-on control word information may include a seventh numerical value or an eighth numerical value. The seventh numerical value can be used to characterize a numerical value that allows the timing report, such as 1, which can correspond to a high level. The eighth numerical value can be used to characterize a numerical value that does not allow the timing report, such as 0, which can correspond to a low level.

[0089] Specifically, it is possible to first detect whether the second power-on control word information out_wdg_enable is enabled. If the second power-on control word information out_wdg_enable is the seventh value, it is determined that out_wdg_enable is enabled, and when enabled, the communication bus SPI (Serial Peripheral Interface) is initialized, and the watchdog timer can be started by shutting down through code 706. When the time is reached, an interrupt is generated. After the baseboard management controller detects the interrupt, the baseboard management controller obtains the test failure result from the SCP.

[0090] The technical solution of this embodiment determines the target processing method based on the test failure log field information in the non-volatile memory, and processes the test failure result according to the target processing method, thereby improving the diversity and flexibility of failure processing and meeting personalized needs.

[0091] The following is an embodiment of a memory test control device provided in an embodiment of the present invention. The device and the memory test control method of the above-mentioned embodiments belong to the same inventive concept. For details not described in detail in the embodiment of the memory test control device, reference can be made to the embodiment of the memory test control method.

[0092] Embodiment 4

[0093] Figure 5 This is a schematic diagram of the structure of a memory test control device provided by the fourth embodiment of the present invention. Figure 5 As shown, the device is integrated in a system control processor SCP, and specifically comprises: an SCP starting module 510 , a detection module 520 and a control module 530 .

[0094] Among them, the SCP startup module 510 is used to start the SCP in response to the startup operation of the chip's on-chip system; the detection module 520 is used to determine whether the memory self-test test MBSIT is required for the current startup based on the test run field information in the non-volatile memory after the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information; the control module 530 is used to lock the test clock frequency of the phase-locked loop if the current startup meets the MBSIT condition, and when the locking is successful, control the MBSIT device to perform a self-test test on the target memory of the chip based on the configured test link information.

[0095] The technical solution of the embodiment of the present invention is that the system control processor SCP responds to the startup operation of the chip system on chip, and the SCP is started. After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information, it is determined based on the test operation field information in the non-volatile memory whether the current startup needs to perform a memory self-test MBIST; if the current startup needs to perform MBIST, the phase-locked loop is locked and configured to test the clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test test on the target memory of the chip based on the configured test link information, so that when the system control processor SCP detects that the current startup needs to perform MBIST, the MBIST device is controlled to perform a self-test test on the memory, thereby realizing effective control of the memory test, avoiding the situation that the memory test is still performed when the memory test is not needed, thereby saving test resources and improving the flexibility of the memory test.

[0096] Optionally, the detection module 520 includes:

[0097] A first detection unit, configured to determine that a memory self-test MBIST needs to be performed at the current startup if the test run field information in the non-volatile memory is a first value;

[0098] A second detection unit is used for determining that a memory self-test MBIST is not required for the current startup if the test run field information in the non-volatile memory is a second value;

[0099] The third detection unit is used to determine whether a memory self-test MBIST is required at the current startup based on the first power-on control word information if the test run field information in the non-volatile memory is a third value.

[0100] Optionally, the third detection unit is specifically used to:

[0101] If the first power-on control word information is the fourth value, it is determined that the memory self-test test MBSIT needs to be performed during the current startup; if the first power-on control word information is the fifth value, it is determined that the memory self-test test MBIST does not need to be performed during the current startup.

[0102] Optionally, the MBIST device comprises: an SCP system control module, a read-only memory ROM module, an MBIST interface processing module and an MBIST control module;

[0103] The control module 530 is specifically configured to:

[0104] The SCP controls the test start field information in the SCP system control module to be configured as start information, and sends the configured test link information to the SCP system control module;

[0105] Described SCP system control module sends the test link information received to described MBIST interface processing module;

[0106] Described MBIST interface processing module is based on the MBIST micro-instruction stored in described ROM module, and the test link information received is decoded and translated, determines the target test instruction, and described target test instruction is sent to described MBIST control module;

[0107] The MBIST control module performs a self-test test on the target memory of the chip by executing the target test instruction.

[0108] Optionally, the control module 530 is further configured to:

[0109] Described mbist control module is stored in the status register in described SCP system control module with the test result of described target memory;

[0110] The SCP reads the test result of the target memory from the status register in the SCP system control module.

[0111] Optionally, the device further comprises:

[0112] A failure processing module is used to determine a target processing method based on the test failure log field information in the non-volatile memory if the test result of the target memory is a test failure result, and process the test failure result based on the target processing method.

[0113] Optionally, the failure handling module includes:

[0114] A first processing unit is configured to store the test failure result in a FLASH device based on a FLASH storage method if the first element information in the test failure log field information in the non-volatile memory is a sixth value, so that a baseboard management controller obtains the test failure result by querying the FLASH device;

[0115] a second processing unit, configured to report the test failure result to a baseboard management controller based on a general input / output port mode if the second bit element information in the test failure log field information in the non-volatile memory is a sixth value;

[0116] The third processing unit is configured to report the test failure result to the baseboard management controller based on a watchdog timer method if the third bit element information in the test failure log field information in the non-volatile memory is a sixth value.

[0117] Optionally, the third processing unit is specifically configured to:

[0118] If it is detected that the second power-on control word information is the seventh value, the communication bus is initialized and the watchdog timer is started. When the time is reached, the test failure result is reported to the baseboard management controller.

[0119] Optionally, the device further comprises:

[0120] The success processing module is used for, if the test result of the target memory is a test success result, locking the non-test clock frequency of the phase-locked loop and starting the system on chip normally.

[0121] The memory test control device provided in the embodiment of the present invention can execute the memory test control method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the memory test control method.

[0122] It is worth noting that in the embodiment of the test control device of the above-mentioned memory, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0123] Embodiment 5

[0124] Figure 6 This is a schematic diagram of the structure of a chip provided in Embodiment 5 of the present invention. Figure 6 As shown, the chip 600 includes: a system control processor SCP610, a memory self-test test MBIST device 620 and a target memory 630 to be tested.

[0125] Wherein, system control processor SCP610 is used for the test control method of the memory provided by any embodiment of the present invention.MBIST device 620 is connected to communicate with SCP610.MBIST device 620 can be used for under SCP610 control, target memory 630 is carried out self-check test.For example, MBIST device 620 can comprise SCP system control module, read-only memory ROM module, MBIST interface processing module and MBIST control module.The target memory 630 of chip can refer to the memory that needs to be tested in the chip.

[0126] The chip provided by the embodiment of the present invention responds to the startup operation of the chip system on chip through SCP610, and SCP610 starts up. After the second-level boot loader of SCP610 is executed, if it is detected that the power-on status register information is the power-on startup information, it is determined whether the memory self-test MBIST is required for the current startup based on the test run field information in the non-volatile memory; if the MBIST is required for the current startup, the phase-locked loop is locked and configured to test the clock frequency, and when the locking is successful, the MBIST device 620 is controlled to perform a self-test on the target memory 630 of the chip based on the configured test link information, so that when SCP610 detects that the MBIST is required for the current startup, the MBIST device 620 is controlled to perform a self-test on the target memory 630, thereby realizing effective control of the memory test, avoiding the situation that the memory test is still performed when the memory test is not required, thereby saving test resources and improving the flexibility of the memory test.

[0127] Embodiment 6

[0128] Figure 7 This is a schematic diagram of the structure of an electronic device provided by Embodiment 6 of the present invention. Figure 7 As shown, the electronic device 700 includes a chip 600 provided in an embodiment of the present invention. The system control processor SCP in the chip 600 is used to execute the memory test control method provided in any embodiment of the present invention.

[0129] Figure 7The electronic device 700 shown is only an example and should not limit the functions and scope of use of the embodiments of the present invention. The electronic device 700 can be any device including the chip 600, such as a server, a computer, a mobile phone, etc. In addition to the chip 600, the electronic device 700 can also include other input and output devices, such as a keyboard, a pointing device, a display, etc.

[0130] The electronic device provided by the embodiment of the present invention responds to the startup operation of the chip system on chip through the SCP in the chip 600, and the SCP is started. After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information, it is determined whether the memory self-test MBIST is required for the current startup based on the test run field information in the non-volatile memory; if the MBIST is required for the current startup, the phase-locked loop is locked and configured to test the clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test test on the target memory of the chip based on the configured test link information, so that when the SCP detects that the MBIST is required for the current startup, the MBIST device is controlled to perform a self-test test on the target memory, thereby realizing effective control of the memory test, avoiding the situation that the memory test is still performed when the memory test is not required, thereby saving test resources and improving the flexibility of the memory test.

[0131] Of course, those skilled in the art can understand that the chip 600 can also implement the technical solution of the memory test control method provided by any embodiment of the present invention.

[0132] Embodiment 7

[0133] This embodiment provides a computer-readable storage medium storing computer instructions, which are used to enable a processor to implement the steps of the memory test control method described in any embodiment of the present invention when the computer instructions are executed. The method includes:

[0134] In response to a startup operation of the system on chip of the chip, the SCP starts up;

[0135] After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is power-on startup information, it is determined whether the memory self-test test MBIST is required for the current startup based on the test run field information in the non-volatile memory;

[0136] If MBIST is required for the current startup, the phase-locked loop is configured to lock the test clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test on the target memory of the chip based on the configured test link information.

[0137] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing instructions, which can be used by an instruction execution system, device or device or used in combination with it.

[0138] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable instruction codes. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit instructions for use by or in conjunction with an instruction execution system, apparatus, or device.

[0139] The instruction code contained on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the foregoing.

[0140] Computer instruction codes for performing the operations of the present invention may be written in one or more programming languages ​​or combinations thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0141] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0142] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory test control method, characterized in that: Applicable to system control processor SCP, including: In response to a startup operation of the system on chip of the chip, the SCP starts up; After the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is power-on startup information, it is determined whether the memory self-test test MBIST is required for the current startup based on the test run field information in the non-volatile memory; If MBIST is required for the current startup, the phase-locked loop is configured to lock the test clock frequency, and when the locking is successful, the MBIST device is controlled to perform a self-test on the target memory of the chip based on the configured test link information.

2. The method according to claim 1, characterized in that The method of determining whether a memory self-test MBIST is required at the current startup based on the test run field information in the non-volatile memory comprises: If the test run field information in the non-volatile memory is a first value, it is determined that a memory self-test MBIST needs to be performed during the current startup; If the test run field information in the non-volatile memory is the second value, it is determined that the memory self-test test MBIST does not need to be performed during the current startup; If the test run field information in the non-volatile memory is a third value, it is determined based on the first power-on control word information whether a memory self-test MBIST is required for the current startup.

3. The method according to claim 2, characterized in that The method of determining whether a memory self-test MBIST is required for the current startup based on the first power-on control word information comprises: If the first power-on control word information is the fourth value, it is determined that the memory self-test MBSIT needs to be performed during the current startup; If the first power-on control word information is the fifth value, it is determined that the memory self-test MBIST does not need to be performed during the current startup.

4. The method according to claim 1, characterized in that: Described MBIST device comprises: SCP system control module, read-only memory ROM module, MBIST interface processing module and MBIST control module; The test link information based on the configuration controls the MBIST device to perform a self-test on the target memory of the chip, comprising: The SCP controls the test start field information in the SCP system control module to be configured as start information, and sends the configured test link information to the SCP system control module; Described SCP system control module sends the test link information received to described MBIST interface processing module; Described MBIST interface processing module is based on the MBIST micro-instruction stored in described ROM module, and the test link information received is decoded and translated, determines the target test instruction, and described target test instruction is sent to described MBIST control module; The MBIST control module performs a self-test test on the target memory of the chip by executing the target test instruction.

5. The method according to claim 4, characterized in that The method further comprises: Described mbist control module is stored in the status register in described SCP system control module with the test result of described target memory; The SCP reads the test result of the target memory from the status register in the SCP system control module.

6. The method according to claim 1, characterized in that The method further comprises: If the test result of the target memory is a test failure result, a target processing method is determined based on the test failure log field information in the non-volatile memory, and the test failure result is processed based on the target processing method.

7. The method according to claim 6, characterized in that Determining a target processing method based on the test failure log field information in the non-volatile memory, and processing the test failure result based on the target processing method, including: If the first element information in the test failure log field information in the non-volatile memory is the sixth value, based on the FLASH storage method, the test failure result is stored in the FLASH device, so that the baseboard management controller obtains the test failure result by querying the FLASH device; If the second bit element information in the test failure log field information in the non-volatile memory is a sixth value, reporting the test failure result to the baseboard management controller based on a general input and output port mode; If the third bit element information in the test failure log field information in the non-volatile memory is the sixth value, the test failure result is reported to the baseboard management controller based on the watchdog timer method.

8. The method according to claim 7, characterized in that The method of reporting the test failure result to the baseboard management controller based on the watchdog timer method includes: If it is detected that the second power-on control word information is the seventh value, the communication bus is initialized and the watchdog timer is started. When the time is reached, the test failure result is reported to the baseboard management controller.

9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: If the test result of the target memory is a test success result, the phase-locked loop is locked and configured to have a non-test clock frequency, and the system on chip is started normally.

10. A memory test control device, characterized in that: Integrated into the system control processor SCP, including: The SCP startup module is used to start the SCP in response to the startup operation of the chip system on chip; A detection module, used for determining whether a memory self-test MBSIT is required for the current startup based on the test run field information in the non-volatile memory after the second-level boot loader of the SCP is executed, if it is detected that the power-on status register information is the power-on startup information; The control module is used to lock the test clock frequency of the phase-locked loop if the MBSIT condition is met during the current startup, and when the locking is successful, control the MBSIT device to perform a self-test on the target memory of the chip based on the configured test link information.

11. A chip, characterized in that: The chip comprises: a system control processor SCP, a memory self-test test MBIST device and a target memory to be tested, wherein: The system control processor SCP is used to execute the memory test control method according to any one of claims 1 to 9.

12. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 11.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the memory test control method according to any one of claims 1 to 9 when executed.

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