Direct connection structure and direct connection method of RGMII interface and MII interface

Abstract

The invention discloses a direct connection structure and a direct connection method of an RGMII interface and an MII interface. The direct connection structure is specifically characterized in that a data pin, an enabling pin and a clock pin of the RGMII interface are directly connected with a data pin, an enabling pin and a clock pin of the MII interface respectively; an external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, and the external clock generating circuit outputs clock signals conforming to matched time sequences for the RGMII interface and the MII interface. According to the invention, under the condition that the RGMII interface is directly connected with the MII interface, the external clock generation circuit can be adopted to output the clock signal conforming to the matched time sequence for the RGMII interface and the MII interface, so that the data communication can be realized by directly connecting the RGMII interface and the MII interface, and compared with the prior art, the PHY intermediate line is reduced, the cost is saved, and the electromagnetic interference is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet communication, and in particular to a direct connection structure and a direct connection method between an RGMII interface and an MII interface. Background Art

[0002] Currently, many circuit boards are equipped with both CPU and MCU. The network interface of CPU is usually RGMII interface (Gigabit network interface) and cannot be reused as MII interface, while the network interface of most MCU is MII interface (100M network interface). Since the network interfaces of the two are different in transmission rate, clock signal receiving and sending timing, they cannot communicate by directly connecting. Therefore, Figure 1 As shown, the industry usually sets a PHY (Physical Layer) on the CPU side and the MCU side, and connects through PHY. The process of CPU sending data to MCU is as follows: CPU transmits data to the first PHY through RGMII interface, the first PHY converts the data from digital signal to analog signal and transmits it to the second PHY on the MCU side, the second PHY on the MCU side converts the analog signal from RGMII interface to digital signal recognizable by MII interface, and then transmits it to the MII interface of MCU. The process of MCU sending data to CPU is as follows: MCU transmits data to the second PHY through MII interface, the second PHY converts the data from digital signal to analog signal and then transmits it to the first PHY on the CPU side, the first PHY on the CPU side converts the analog signal from MII interface to digital signal recognizable by RGMII interface, and then transmits it to the RGMII interface of CPU. This connection method requires two additional PHYs, which consumes a certain cost, and there is electromagnetic interference due to the addition of PHY intermediate line. Summary of the invention

[0003] The technical problem to be solved by the present invention is how to realize data communication between the RGMII interface and the MII interface without adding a PHY intermediate line.

[0004] In order to solve the above technical problems, the present invention provides a direct connection structure between an RGMII interface and an MII interface, as follows: the data pin, enable pin, and clock pin of the RGMII interface are directly connected to the data pin, enable pin, and clock pin of the MII interface respectively; an external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, and the external clock generating circuit outputs a clock signal that conforms to the timing matched by the RGMII interface and the MII interface.

[0005] Furthermore, the connection of each of the data pin, the enable pin, and the clock pin is specifically that the sending pin of the RGMII interface corresponds to the receiving pin of the MII interface, and the receiving pin of the RGMII interface corresponds to the sending pin of the MII interface.

[0006] Furthermore, the external clock generating circuit is specifically connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface. The external clock generating circuit outputs a clock signal that conforms to the matched timing to the clock receiving pin of the RGMII interface, and outputs a clock signal that conforms to the matched timing to the clock sending pin of the MII interface.

[0007] Further, the carrier monitoring pin, the conflict collision monitoring pin, the data error signal sending pin and the data error receiving pin of the MII interface that are not connected to the RGMII interface are all connected to the signal ground.

[0008] The present invention also provides a method for directly connecting the RGMII interface to the MII interface, as follows:

[0009] The data pin, enable pin and clock pin of the RGMII interface are directly connected to the data pin, enable pin and clock pin of the MII interface respectively;

[0010] An external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, so that the external clock generating circuit outputs a clock signal that meets the timing matched by the RGMII interface and the MII interface;

[0011] Configure both the RGMII interface and the MII interface to forced mode, including the following configuration operations: (1) Initialize the built-in PHY driver of this interface by default; (2) Disable the auto-negotiation function and set the transmission rate to 100MBits / s; (3) Set to full-duplex mode.

[0012] Furthermore, the connection of each of the data pin, the enable pin, and the clock pin is specifically made so that the sending pin of the RGMII interface corresponds to the receiving pin of the MII interface, and the receiving pin of the RGMII interface corresponds to the sending pin of the MII interface.

[0013] Furthermore, the external clock generating circuit is specifically connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface, so that the external clock generating circuit outputs a clock signal that conforms to the matched timing to the clock receiving pin of the RGMII interface, and outputs a clock signal that conforms to the matched timing to the clock sending pin of the MII interface.

[0014] Furthermore, the carrier monitoring pin, the conflict monitoring pin, the data error signal sending pin and the data error receiving pin of the MII interface that are not connected to the RGMII interface are all connected to the signal ground.

[0015] Regardless of whether it is an RGMII interface or an MII interface, data can be correctly sent and received as long as the clock signal at the receiving end of the interface can meet the timing specified in the IEEE802.3 standard. The industry uses PHY to make the clock signals at the receiving ends of the RGMII interface and the MII interface meet the specified timing, thereby realizing data communication between the two. The reason why the RGMII interface and the MII interface cannot communicate data directly is that the timing of their clock signals is inconsistent, resulting in the inability of the two to directly receive a clock signal that meets the matched timing from each other. The present invention takes into account that when the RGMII interface and the MII interface are directly connected, an external clock generating circuit can be used to output a clock signal that meets the matched timing for the RGMII interface and the MII interface. In this way, the direct connection between the two can realize data communication. Compared with the prior art, the PHY intermediate line is reduced, cost is saved, and electromagnetic interference is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a network connection structure diagram of the MAC unit of the CPU and the MAC unit of the single-chip microcomputer in the prior art.

[0017] Figure 2 It is a direct connection structure diagram of the MAC unit of the CPU of the present invention and the MAC unit of the single-chip microcomputer.

[0018] Figure 3 It is a pin connection diagram for directly connecting the MAC unit of the CPU of the present invention with the MAC unit of the single-chip microcomputer. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below in conjunction with specific implementation methods.

[0020] The RGMII interface and the MII interface direct connection structure of this embodiment are as follows Figure 2 As shown, the RGMII interface is directly connected to the MII interface, and then an external clock generation circuit is connected between the RGMII interface and the MII interface. The specific connection method is described in detail below.

[0021] like Figure 3As shown, the technicians connect the data transmission pin of the RGMII interface directly to the data receiving pin of the MII interface, connect the data receiving pin of the RGMII interface directly to the data transmission pin of the MII interface, connect the receive data valid pin (enable receive pin) of the RGMII interface directly to the enable send pin of the MII interface, connect the enable send pin of the RGMII interface directly to the receive data valid pin (enable receive pin) of the MII interface, and connect the clock transmission pin of the RGMII interface directly to the clock receiving pin of the MII interface. The clock transmission pin of the RGMII interface can send a clock signal, while the clock receiving pin of the MII interface needs to be connected to the clock signal from the outside. Therefore, the clock transmission pin of the RGMII interface can directly send a clock signal that meets the timing matched by the clock receiving pin of the MII interface to the clock receiving pin of the MII interface. The clock receiving pin of the RGMII interface needs to receive a clock signal from the outside, and the clock sending pin of the MII interface also needs to receive a clock signal from the outside. Therefore, in this embodiment, the above-mentioned external clock generating circuit is connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface (this embodiment uses a 25MHz active crystal oscillator as the external clock generating circuit), that is, the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface are connected through the above-mentioned external clock generating circuit. In this way, the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface both receive clock signals from the external clock generating circuit. The external clock generating circuit outputs a clock signal that matches the timing matched by the clock receiving pin of the RGMII interface on the one hand, and outputs a clock signal that matches the timing matched by the pin on the other hand to the clock sending pin of the MII interface. The clock signal of the timing matched by the clock receiving pin of the RGMII interface, the clock signal of the timing matched by the clock receiving pin and the clock sending pin of the MII interface respectively refer to the clock signals of the timing specified in the IEEE 802.3 standard. The other pins of the MII interface that are not connected to the RGMII interface are connected to the power supply. Specifically, the CRS pin (carrier monitoring pin), COL pin (collision monitoring pin), TXER pin (data error signal sending pin) and RXER pin (data error receiving pin) of the MII interface are all connected to the signal ground.

[0022] After the technicians have connected the RGMII interface and the MII interface according to the above process, they also need to configure the RGMII interface and the MII interface to the forced mode, which includes the following configuration operations: (1) The built-in PHY driver of this interface is initialized by default; (2) The auto-negotiation function is turned off and the transmission rate is set to 100MBits / s; (3) Set to full-duplex mode. After the configuration is completed, the RGMII interface and the MII interface can directly communicate data. Compared with the existing technology, the PHY intermediate line is reduced, which saves costs and reduces electromagnetic interference.

[0023] The above is only an implementation method of the invention, and does not limit the scope of patent protection. Those skilled in the art can make non-substantial changes or substitutions based on the invention, which still fall within the scope of patent protection.

Claims

1. The RGMII interface is directly connected to the MII interface, and its characteristics are: The data pin, enable pin and clock pin of the RGMII interface are directly connected to the data pin, enable pin and clock pin of the MII interface respectively; an external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, and the external clock generating circuit outputs a clock signal that meets the matching timing for the RGMII interface and the MII interface.

2. The RGMII interface and MII interface direct connection structure as claimed in claim 1, characterized in that: Specifically, the connection of each of the data pin, the enable pin, and the clock pin is that the sending pin of the RGMII interface corresponds to the receiving pin of the MII interface, and the receiving pin of the RGMII interface corresponds to the sending pin of the MII interface.

3. The RGMII interface and MII interface direct connection structure as claimed in claim 2, characterized in that the external The clock generating circuit is specifically connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface. The external clock generating circuit outputs a clock signal that conforms to the matched timing to the clock receiving pin of the RGMII interface, and outputs a clock signal that conforms to the matched timing to the clock sending pin of the MII interface.

4. The RGMII interface and MII interface direct connection structure as claimed in claim 2, characterized in that: The carrier monitoring pin, the conflict collision monitoring pin, the data error signal sending pin and the data error receiving pin of the MII interface that are not connected to the RGMII interface are all connected to the signal ground.

5. A method for directly connecting an RGMII interface to an MII interface, characterized in that: The data pin, enable pin and clock pin of the RGMII interface are directly connected to the data pin, enable pin and clock pin of the MII interface respectively; An external clock generating circuit is connected between the clock pin of the RGMII interface and the clock pin of the MII interface, so that the external clock generating circuit outputs a clock signal that meets the timing matched by the RGMII interface and the MII interface; Configure both the RGMII interface and the MII interface to forced mode, including the following configuration operations: (1) Initialize the built-in PHY driver of this interface by default; (2) Disable the auto-negotiation function and set the transmission rate to 100MBits / s; (3) Set to full-duplex mode.

6. The method for directly connecting the RGMII interface to the MII interface as claimed in claim 5, characterized in that: Specifically, the connection of each of the data pin, the enable pin, and the clock pin is such that the sending pin of the RGMII interface is connected to the receiving pin of the MII interface, and the receiving pin of the RGMII interface is connected to the sending pin of the MII interface.

7. The method for directly connecting the RGMII interface to the MII interface as claimed in claim 6, characterized in that: Specifically, the external clock generating circuit is connected between the clock receiving pin of the RGMII interface and the clock sending pin of the MII interface, so that the external clock generating circuit outputs a clock signal that conforms to the matched timing to the clock receiving pin of the RGMII interface, and outputs a clock signal that conforms to the matched timing to the clock sending pin of the MII interface.

8. The method for directly connecting the RGMII interface and the MII interface as claimed in claim 6, characterized in that: The carrier monitoring pin, the conflict collision monitoring pin, the data error signal sending pin and the data error receiving pin of the MII interface that are not connected to the RGMII interface are all connected to the signal ground.

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