Grid integral acceleration calculation method and device, equipment, storage medium and product

Abstract

The invention discloses a grid integral acceleration calculation method and device, equipment, a storage medium and a product, and relates to the technical field of data processing, and the grid integral acceleration calculation method comprises the steps: carrying out the batch division of grid points, and obtaining batch processing subtasks; generating descriptors of the batch processing subtasks; processing the batch processing subtasks based on the descriptors to obtain an integral calculation matrix; and performing grid integral calculation based on the integral calculation matrix to obtain a grid integral. For a single grid, the value of an integrated function in the grid can be expressed as an outer product of two vectors, and the integral of the function in the grid position can be obtained by accumulating the results of a plurality of outer products. Due to the fact that the grid points are processed in batches, after batch processing, the multiple vectors and the outer product of the multiple vectors are converted into matrix multiplication operation between the two matrixes. Therefore, the grid integration problem of density functional calculation is converted into accumulation of large-batch small matrix multiplication calculation results, and the calculation speed of grid integration is increased.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to grid integral accelerated calculation methods, devices, equipment, storage media and products. Background Art

[0002] In density functional theory calculations of numerical atomic orbital basis sets, the influence of each atom on a specific point in space is converted into the cumulative effect of the influence of each orbital of that atom on that point. For two atoms that overlap within a certain cutoff radius, the integral value at a specific grid point can be approximated as the outer product of the vectors of all the orbitals of the two atoms at that grid point, where each vector represents the value of all the atomic orbitals of a certain atom at that grid point.

[0003] Traditional heterogeneous computing acceleration methods directly use standard batch matrix multiplication libraries (such as cuBLAS, rocBLAS, CUTLASS, MAGMA), which is difficult to meet the special needs of the above scenarios. At the same time, changes in matrix dimensions and differences in heterogeneous computing device types will affect performance, requiring fine optimization of computing strategies. Summary of the invention

[0004] The main purpose of this application is to provide a grid integral accelerated computing method, device, equipment, storage medium and product, aiming to solve the technical problem that existing heterogeneous computing acceleration methods are difficult to meet the accelerated computing needs of grid integrals and will affect device performance.

[0005] To achieve the above purpose, the present application proposes a grid integral accelerated calculation method, which includes: Divide the grid points into batches to obtain batch processing subtasks; generating a descriptor of the batch processing subtask; Based on the descriptor and the batch processing subtask, an integral calculation matrix is ​​obtained; A grid integral calculation is performed based on the integral calculation matrix to obtain a grid integral.

[0006] In one embodiment, the step of obtaining an integral calculation matrix based on the descriptor and processing the batch processing subtasks includes: Obtaining the integrand function value at each grid point in the batch processing subtask based on the descriptor calculation; An integral calculation matrix is ​​constructed based on the integrand function value.

[0007] In one embodiment, the step of performing grid integral calculation based on the integral calculation matrix to obtain grid integrals includes: A batch processing kernel based on a preset block matrix multiplication performs batch processing multiplication operations on the integral calculation matrix to obtain grid integrals.

[0008] In one embodiment, when executing the step of performing batch multiplication operation on the integral calculation matrix based on the batch kernel of the preset block matrix multiplication, the method further includes: An atomic operation and / or a memory locking operation is performed on the batch multiplication operation.

[0009] In one embodiment, before the step of performing batch multiplication operation on the integral calculation matrix by using the batch kernel based on the preset block matrix multiplication to obtain the grid integral, the step further includes: The computation kernel is divided into different sizes to generate batch kernels with different block sizes.

[0010] In one embodiment, the step of performing batch multiplication operation on the integral calculation matrix based on a batch kernel of a preset block matrix multiplication to obtain a grid integral comprises: determining a matrix size of the integral calculation matrix based on the descriptor; Determining a batch kernel of a preset block matrix multiplication corresponding to the integral calculation matrix according to the matrix size; The batch processing kernel performs batch multiplication operation on the integral calculation matrix to obtain grid integrals.

[0011] In addition, to achieve the above-mentioned purpose, the present application also proposes a grid integral accelerated computing device, the grid integral accelerated computing device comprising: A descriptor generation module, used for generating a descriptor of the batch processing subtask; A matrix determination module, used for processing the batch processing subtask based on the descriptor to obtain an integral calculation matrix; The integral calculation module is used to perform grid integral calculation based on the integral calculation matrix to obtain grid integral.

[0012] In addition, to achieve the above-mentioned purpose, the present application also proposes a grid integral accelerated computing device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the grid integral accelerated computing method as described above.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the grid integral accelerated calculation method described above are implemented.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the grid integral accelerated calculation method as described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: This application obtains batch processing subtasks by dividing the grid points into batches; generates descriptors of the batch processing subtasks; processes the batch processing subtasks based on the descriptors to obtain an integral calculation matrix; and performs grid integral calculation based on the integral calculation matrix to obtain grid integrals. For a single grid, the value of the integrand function at this grid can be expressed as the outer product of two vectors. The integral of this function at this grid position can be obtained by accumulating the results of multiple outer products. Since the grid points are processed in batches, after batch processing, the outer products of multiple vectors and multiple vectors are converted into matrix multiplication operations between two matrices. In this way, the grid integral problem of density functional calculation is converted into the accumulation of large batches of small matrix multiplication calculation results, which improves the calculation speed of grid integrals. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A schematic diagram of a flow chart provided for the first embodiment of the grid integral accelerated calculation method of the present application; Figure 2 A schematic diagram of a flow chart provided for the second embodiment of the grid integral accelerated calculation method of the present application; Figure 3 A schematic diagram of a flow chart provided for the third embodiment of the grid integral accelerated calculation method of the present application; Figure 4 A schematic diagram of the pipeline timing of CPU and GPU computing collaboration in one implementation of the grid integral accelerated computing method of this application; Figure 5 This is a schematic diagram of the module structure of the grid integral accelerated computing device according to an embodiment of the present application; Figure 6 Schematic diagram of the device structure of the hardware operating environment involved in the grid integral accelerated calculation method in the embodiment of the present application.

[0019] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0021] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0022] The main solution of the embodiment of the present application is: divide the grid points into batches to obtain batch processing subtasks; generate descriptors of the batch processing subtasks; based on the descriptors and the batch processing subtasks, process the batch processing subtasks to obtain an integral calculation matrix; perform grid integral calculation based on the integral calculation matrix to obtain grid integrals.

[0023] Traditional heterogeneous computing acceleration methods directly use standard batch matrix multiplication libraries, which makes it difficult to calculate the integral value of a specific grid point. In addition, changes in matrix dimensions and differences in heterogeneous computing device types will affect performance, requiring fine optimization of computing strategies.

[0024] The present application provides a grid integral accelerated calculation method, which realizes efficient calculation of grid integrals in density functional theory accelerated by heterogeneous computing devices. The method of the present application significantly improves the calculation efficiency through the calculation coordination of the central processing module and the graphics processing module and the dynamic optimization of performance.

[0025] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a computer, server, etc., or an electronic device, virtual device, etc. that can realize the above functions. In the embodiment of this application, a grid integral acceleration computing device (referred to as computing device) is taken as an example, and the embodiment of this application and the following embodiments are explained.

[0026] Based on this, the present application embodiment provides a grid integral accelerated calculation method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the grid integral accelerated calculation method of the present application.

[0027] In this embodiment, the grid integral accelerated calculation method includes steps S10 to S40: Step S10, dividing the grid points into batches to obtain batch processing subtasks; Step S20, generating a descriptor of the batch processing subtask; It should be noted that in order to improve the computational efficiency in the underlying computation process, the grid points are batched. After batching, the outer products of multiple vectors and multiple vectors are converted into matrix multiplication operations between two matrices. As a result, the grid integration problem of density functional calculation is converted into the accumulation of large batches of small matrix multiplication calculation results.

[0028] It should be explained that the present application is to realize grid integral accelerated calculation through a pipeline method based on collaborative calculation between a central processing module and a graphics processing module.

[0029] Specifically, the computing device of the embodiment of the present application may include at least two functional modules, one of which is a central processing module and the other is a graphics processing module. The above two functional modules may be virtual modules or physical modules with physical computing devices, which are not limited in the embodiment of the present application. At the same time, the number of each functional module is not limited in the embodiment of the present application, and can be selected according to the needs of actual applications.

[0030] In the embodiment of the present application, a physical module having a physical computing device, namely a central processing unit (CPU) and a graphics processing unit (GPU) is taken as an example to illustrate the method of the embodiment of the present application and the following embodiments.

[0031] It should be noted that in the embodiment of the present application, the central processing module divides the subtasks and generates subtask descriptors. The subtask descriptors may encapsulate key information required for calculating matrix elements and matrix multiplication, and are sequentially stored in the memory through indexes.

[0032] Furthermore, the central processing unit can transmit the subtask descriptor to the graphics processing unit through the system bus, and the graphics processing unit can perform matrix element generation and matrix multiplication calculation according to the subtask descriptor, thereby realizing accelerated calculation of grid integral.

[0033] It can be understood that in the density functional theory calculation of the numerical atomic orbital basis set, the grid points are a series of points used to discretize continuous physical quantities in real space. These physical quantities may include electron density, potential energy, and other quantities that may need to be integrated or gradiented in space. Since computing devices cannot directly process continuous functions, it is necessary to convert continuous physical quantities into discrete data that can be operated on computing devices. Grid points are also tools for achieving this discretization. By dividing the space into a series of small areas, each small area can be represented by a grid point, so that the values ​​of physical quantities can be calculated at these grid points, and these discrete values ​​can be used to approximate the distribution of physical quantities in the entire space.

[0034] It should be noted that, in the embodiment of the present application, each grid point in the computing task can be divided into several batches to obtain batch processing subtasks, wherein each batch processing subtask may include a certain number of grid points and their neighboring atoms. The basis for dividing the batch processing subtasks may be to segment the three-dimensional space of the computing task, and the number of grid points and their neighboring atoms included in each batch processing subtask, that is, the scale of the batch processing subtask may be selected according to the needs in the actual application, and the embodiment of the present application does not limit this.

[0035] It can be understood that when the grid points are divided into several batch processing subtasks, the key information of the corresponding calculation matrix elements and matrix multiplication can be determined based on the scale of each batch processing subtask and the number of grid points and neighborhood atoms included therein, and these key information can be encapsulated in the descriptor of the batch processing subtask.

[0036] In a specific implementation, the computing device in the embodiment of the present application can divide the grid points in the computing task into batches to obtain batch processing subtasks; and generate descriptors of the batch processing subtasks based on the grid points and neighborhood atoms in the batch processing subtasks.

[0037] Step S30, processing the batch processing subtask based on the descriptor to obtain an integral calculation matrix; Step S40, performing grid integral calculation based on the integral calculation matrix to obtain grid integral.

[0038] It should be noted that in the embodiment of the present application, the CPU can generate a descriptor for each batch processing subtask and transmit the descriptor to the GPU device via PCIe. The CPU generates the descriptor, the PCIe transmits the descriptor and the GPU calculates through multiple execution streams concurrently to realize pipeline operation.

[0039] It can be understood that through the descriptors transmitted by the CPU, the GPU can determine the storage location, data size, data type and other parameters of the batch processing subtasks, and then allocate computing kernels to each batch processing subtask to achieve accelerated computing.

[0040] It should be understood that the GPU of the embodiment of the present application supports running multiple execution flows at the same time, where each execution flow can contain multiple commands, such as memory transfer, kernel execution, etc. By assigning different execution flows to different batch processing subtasks, the pipeline operation between the CPU and the GPU can be realized. At the same time, multiple execution flows can be executed concurrently, which improves the parallel processing capability of the GPU and thereby improves the calculation speed of the grid integral.

[0041] It should be noted that by allocating a computing kernel to each batch processing subtask and processing the batch processing subtask, several small matrices, namely integral computing matrices, can be obtained. By performing batch multiplication operations on the integral computing matrices, the grid integral can be obtained.

[0042] It should be explained that, through the solution of the present application, parallel processing of heterogeneous computing can be realized, and the computing efficiency of heterogeneous computing is improved by executing each step in series or in parallel in the form of a pipeline. At the same time, the above steps can be executed on a heterogeneous computing device (such as a computing device), for example, the process of step S30 and step S40 can be accelerated on a graphics processor of a heterogeneous computing device.

[0043] The embodiment of the present application obtains batch processing subtasks by dividing the grid points into batches; generates descriptors of the batch processing subtasks; processes the batch processing subtasks based on the descriptors to obtain an integral calculation matrix; and performs grid integral calculation based on the integral calculation matrix to obtain grid integrals. For a single grid, the value of the integrand function at this grid can be expressed as the outer product of two vectors. The integral of this function at this grid position can be obtained by accumulating the results of multiple outer products. Since the grid points are processed in batches, after batch processing, the outer products of multiple vectors and multiple vectors are converted into matrix multiplication operations between two matrices. The grid integral problem of the density functional calculation is thus converted into the accumulation of large batches of small matrix multiplication calculation results, which improves the calculation speed of the grid integral.

[0044] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 2 In the embodiment of the present application, the step of obtaining an integral calculation matrix based on the descriptor and processing the batch subtask includes: Step S31, calculating and obtaining the integrand function value at each grid point in the batch processing subtask based on the descriptor; Step S32, constructing an integral calculation matrix based on the integrand function value.

[0045] It should be noted that a precompiled kernel may be provided in the GPU of the embodiment of the present application, and the kernel may be a CUDA kernel. The precompiled CUDA kernel may calculate the interaction between each grid point in the batch processing subtask and the atoms within the stage radius of the grid point, and the interaction may be represented by a numerical atomic orbital as a basis group, and the values ​​of these interactions (i.e., the values ​​of the integrated functions) may be stored in the form of an integral calculation matrix for subsequent matrix multiplication processing.

[0046] Further, in order to realize the calculation of the grid integral, in the embodiment of the present application, the step of performing the grid integral calculation based on the integral calculation matrix to obtain the grid integral includes: Step S41, performing batch multiplication operation on the integral calculation matrix based on a preset batch kernel of block matrix multiplication to obtain grid integrals.

[0047] It should be noted that when obtaining the integral calculation matrix, the GPU can perform batch multiplication operations on these integral calculation matrices through an improved block matrix multiplication (that is, a preset block matrix multiplication) batch kernel to obtain grid integrals. At the same time, during the batch multiplication operation, atomic operations and memory lock operations can also be used to solve the problem of write conflicts. That is, when executing the step of performing batch multiplication operations on the integral calculation matrix based on the preset block matrix multiplication batch kernel, the method also includes: An atomic operation and / or a memory locking operation is performed on the batch multiplication operation.

[0048] The embodiment of the present application determines the atomic orbital value at each grid point in the batch subtask based on the descriptor and through the precompiled kernel; constructs the integral calculation matrix based on the atomic orbital value; and performs batch multiplication operations on the integral calculation matrix based on the batch kernel of the preset block matrix multiplication to obtain the grid integral. Since the grid integral problem of density functional calculation is converted into the problem of accumulating the multiplication results of many integral calculations, the speed of grid integral calculation is improved; at the same time, through the calculation synergy of CPU and GPU, the calculation advantage of individual characters is fully utilized, the control logic of GPU is simplified, and the overall calculation efficiency is improved.

[0049] Based on the first embodiment and / or the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those of the first embodiment and / or the second embodiment can be referred to the above introduction, and will not be described in detail later. Figure 3 In the embodiment of the present application, the step of performing batch multiplication operation on the integral calculation matrix based on the batch kernel of the preset block matrix multiplication to obtain the grid integral includes: Step 411, determining the matrix size of the integral calculation matrix based on the descriptor; Step S412, determining a batch kernel of a preset block matrix multiplication corresponding to the integral calculation matrix according to the matrix size; Step S413, performing batch multiplication operation on the integral calculation matrix through the batch kernel to obtain grid integrals.

[0050] It should be noted that a dynamic online automatic tuning algorithm for block size is also proposed in the embodiment of the present application. The embodiment of the present application uses template programming to divide the computing kernel in the compilation stage to generate several device computing kernels with different block sizes, that is, to generate several batch processing kernels. Specifically, the number of batch processing kernels is related to the following parameters: 1. The dimension of the thread block.

[0051] 2. The dimensions of the submatrix computed by a thread block.

[0052] 3. The dimensions used when storing the A matrix in blocks in shared memory.

[0053] 4. The dimensions used when storing the B matrix blocks in shared memory.

[0054] It should be understood that the above parameters can be selected according to the requirements of actual applications, and the number of batch processing kernels generated is the product of the values ​​of the above parameters.

[0055] Specifically, before the step of performing batch multiplication operation on the integral calculation matrix by using the batch kernel based on the preset block matrix multiplication to obtain the grid integral, the step further includes: The computation kernel is divided into different sizes to generate batch kernels with different block sizes.

[0056] It should be noted that, at runtime, these batch processing kernels are executed online to dynamically select the batch processing kernel with the best performance for the current batch processing subtask and computing device. Specifically, the embodiment of the present application can automatically construct matrix multiplication parameters such as matrix size, size and number representing the current task according to the user's input, thereby realizing the test of the batch processing kernel.

[0057] In specific applications, the calculation scale remains relatively fixed and will not expand with the increase of computing systems. In actual calculations, the computing device can determine the size of the matrix multiplication according to the atomic type of this calculation. Each calculation will use a variety of different matrix multiplication sizes. When testing the batch kernel, each size of the matrix can determine the batch number during the test according to the computing task. In actual applications, the matrix size of the integral calculation matrix can be determined according to the descriptor of the batch subtask, and then the corresponding batch kernel can be selected. The batch kernel can be used to implement the batch multiplication operation of the integral calculation matrix and obtain the grid integral.

[0058] The embodiment of the present application determines the matrix size of the integral calculation matrix based on the descriptor; determines the batch kernel of the preset block matrix multiplication corresponding to the integral calculation matrix according to the matrix size; and performs batch multiplication operations on the integral calculation matrix through the batch kernel to obtain grid integrals. The present application adopts an online automatic block size tuning method, which can adaptively select the optimal calculation strategy according to the size of the integral calculation matrix corresponding to the batch subtask and the change of the memory type of the device, thereby ensuring high performance during calculation.

[0059] In one implementation of the embodiment of the present application, the pipeline timing diagram of CPU and GPU computing collaboration can be as follows: Figure 4 shown.

[0060] Reference Figure 4 In the embodiment of the present application, the grid can be divided, and then multiple batch processing subtasks (ie, subtask 1, subtask 2, subtask 3) are generated in the host (CPU) task queue, and descriptors are generated based on each batch processing subtask.

[0061] Furthermore, the host may generate a host and device transfer task queue based on PCIe, and transmit the descriptors corresponding to each batch processing subtask to the device (GPU) respectively.

[0062] It is understandable that when the device receives the descriptors corresponding to each batch processing subtask, it can select the corresponding calculation matrix element (ie, batch processing kernel) based on the descriptor to process the batch processing subtask and implement batch matrix multiplication calculation.

[0063] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the grid integral accelerated calculation method of the present application. More forms of simple transformations based on this technical concept are all within the scope of protection of the present application.

[0064] This application also provides a grid integral accelerated computing device, please refer to Figure 5 , the grid integral accelerated computing device comprises: The task division module 10 is used to divide the grid points into batches to obtain batch processing subtasks; A descriptor generating module 20, used for generating a descriptor of the batch processing subtask; A matrix determination module 30, for obtaining an integral calculation matrix based on the descriptor and processing the batch processing subtask; The integral calculation module 40 is used to perform grid integral calculation based on the integral calculation matrix to obtain grid integral.

[0065] It should be noted that the above modules can be executed in series or in parallel in the form of pipelines. The above modules can be executed on heterogeneous computing devices. For example, the matrix determination module and the integral calculation module can be accelerated on the graphics processor of the heterogeneous computing device.

[0066] The grid integral accelerated computing device provided by the present application adopts the grid integral accelerated computing method in the above-mentioned embodiment, which can solve the technical problem that the existing heterogeneous computing acceleration method is difficult to meet the accelerated computing requirements of grid integrals and will affect the performance of the device. Compared with the prior art, the beneficial effects of the grid integral accelerated computing device provided by the present application are the same as the beneficial effects of the grid integral accelerated computing method provided by the above-mentioned embodiment, and the other technical features in the grid integral accelerated computing device are the same as the features disclosed in the above-mentioned embodiment method, which will not be repeated here.

[0067] The present application provides a grid integral accelerated computing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the grid integral accelerated computing method in the above-mentioned embodiment one.

[0068] Reference below Figure 6 , which shows a schematic diagram of the structure of a grid integral accelerated computing device suitable for implementing the embodiments of the present application. The grid integral accelerated computing device in the embodiments of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The grid integral accelerated computing device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0069] like Figure 6As shown, the grid integral accelerated computing device may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the grid integral accelerated computing device are also stored. The processing device 1001, ROM1002 and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the grid integration accelerated computing device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a grid integration accelerated computing device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or provided instead.

[0070] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0071] The grid integral accelerated computing device provided by the present application adopts the grid integral accelerated computing method in the above embodiment, which can solve the technical problem that the existing heterogeneous computing acceleration method is difficult to meet the accelerated computing requirements of grid integrals and will affect the performance of the device. Compared with the prior art, the beneficial effects of the grid integral accelerated computing device provided by the present application are the same as the beneficial effects of the grid integral accelerated computing method provided by the above embodiment, and the other technical features in the grid integral accelerated computing device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0072] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0073] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0074] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the grid integral accelerated calculation method in the above-mentioned embodiment.

[0075] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0076] The computer-readable storage medium may be included in the grid integration accelerated computing device; or may exist independently without being assembled into the grid integration accelerated computing device.

[0077] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the grid integral accelerated computing device, the grid integral accelerated computing device: Divide the grid points into batches to obtain batch processing subtasks; generating a descriptor of the batch processing subtask; Based on the descriptor and the batch processing subtask, an integral calculation matrix is ​​obtained; A grid integral calculation is performed based on the integral calculation matrix to obtain a grid integral.

[0078] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0079] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0080] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0081] The readable storage medium provided in this application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned grid integral accelerated calculation method, which can solve the technical problem that the existing heterogeneous computing acceleration method is difficult to meet the accelerated calculation requirements of grid integrals and will affect the performance of the device. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the grid integral accelerated calculation method provided in the above-mentioned embodiment, and will not be repeated here.

[0082] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned grid integral accelerated calculation method when executed by a processor.

[0083] The computer program product provided by the present application can solve the technical problem that the existing heterogeneous computing acceleration method is difficult to meet the accelerated computing requirements of grid integrals and will affect the performance of the device. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the grid integral accelerated computing method provided by the above embodiment, and will not be repeated here.

[0084] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A grid integral accelerated calculation method, characterized in that: The method comprises: Divide the grid points into batches to obtain batch processing subtasks; generating a descriptor of the batch processing subtask; Based on the descriptor and the batch processing subtask, an integral calculation matrix is ​​obtained; A grid integral calculation is performed based on the integral calculation matrix to obtain a grid integral.

2. The grid integral accelerated calculation method according to claim 1, characterized in that: The step of obtaining an integral calculation matrix based on the descriptor and processing the batch processing subtask comprises: Obtaining the integrand function value at each grid point in the batch processing subtask based on the descriptor calculation; An integral calculation matrix is ​​constructed based on the integrand function value.

3. The grid integral accelerated calculation method according to claim 2, characterized in that: The step of performing grid integral calculation based on the integral calculation matrix to obtain grid integrals comprises: A batch processing kernel based on a preset block matrix multiplication performs batch processing multiplication operations on the integral calculation matrix to obtain grid integrals.

4. The grid integral accelerated calculation method according to claim 3, characterized in that: When executing the step of performing batch multiplication operation on the integral calculation matrix using the batch kernel based on the preset block matrix multiplication, the method further includes: An atomic operation and / or a memory locking operation is performed on the batch multiplication operation.

5. The grid integral accelerated calculation method according to claim 3, characterized in that: Before the step of performing batch multiplication operation on the integral calculation matrix by the batch processing kernel based on the preset block matrix multiplication to obtain the grid integral, the method further includes: The computation kernel is divided into different sizes to generate batch kernels with different block sizes.

6. The grid integral accelerated calculation method according to claim 5, characterized in that: The step of performing batch multiplication operation on the integral calculation matrix based on the batch kernel of the preset block matrix multiplication to obtain the grid integral comprises: determining a matrix size of the integral calculation matrix based on the descriptor; Determining a batch kernel of a preset block matrix multiplication corresponding to the integral calculation matrix according to the matrix size; The batch processing kernel performs batch multiplication operation on the integral calculation matrix to obtain grid integrals.

7. A grid integral accelerated computing device, characterized in that: The grid integral accelerated computing device comprises: The task division module is used to divide the grid points into batches to obtain batch processing subtasks; A descriptor generation module, used for generating a descriptor of the batch processing subtask; A matrix determination module, used for processing the batch processing subtask based on the descriptor to obtain an integral calculation matrix; The integral calculation module is used to perform grid integral calculation based on the integral calculation matrix to obtain grid integral.

8. A grid integral accelerated computing device, characterized in that: The device comprises: a memory, a processor, and a grid integral accelerated calculation program stored in the memory and executable on the processor, wherein the grid integral accelerated calculation program is configured to implement the steps of the grid integral accelerated calculation method according to any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium stores a grid integral accelerated calculation program, which, when executed by a processor, implements the steps of the grid integral accelerated calculation method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the grid integral accelerated calculation method according to any one of claims 1 to 6 are implemented.

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