Simulation model generation method, device, storage medium and electronic device

Abstract

The embodiment of the present invention provides a method, device, storage medium and electronic device for generating a simulation model, the method comprising: determining a first model parameter necessary for generating a target simulation model, wherein the target simulation model is used to simulate a target chip; generating a basic simulation model based on the first model parameter; performing simulation using the basic simulation model to obtain a simulation result; determining a second model parameter for adjusting the basic simulation model when the first model evaluation index of the basic simulation model is greater than a predetermined threshold value based on the test result obtained by testing the target chip and the simulation result; repeatedly performing the optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold value, and determining the optimized simulation model as the target simulation model. Through the present invention, the problem of high cost of generating simulation models in the related art is solved, thereby achieving the effect of reducing the cost of generating simulation models.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of electronics, and in particular, to a method, device, storage medium and electronic device for generating a simulation model. Background Art

[0002] In related technologies, when generating simulation models, such as IBIS (Input / output buffer information specification) models, protocols can be generated through IBIS models, special fixture boards for chip testing can be made, and parameter values ​​can be recorded and combined to generate models through testing. However, making special test fixtures is expensive and time-consuming, and is not suitable for large-scale production.

[0003] It can be seen from this that the related art has the problem of high cost in generating simulation models.

[0004] Currently, no effective solution has been proposed for the above-mentioned problems existing in the related technologies. Summary of the invention

[0005] The embodiments of the present invention provide a method, device, storage medium and electronic device for generating a simulation model, so as to at least solve the problem of high cost of generating a simulation model in the related art.

[0006] According to one embodiment of the present invention, a method for generating a simulation model is provided, comprising: determining a first model parameter required for generating a target simulation model, wherein the target simulation model is used to simulate a target chip; generating a basic simulation model based on the first model parameter; performing simulation using the basic simulation model to obtain a simulation result; determining a second model parameter for adjusting the basic simulation model when a first model evaluation index of the basic simulation model is greater than a predetermined threshold value based on a test result obtained by testing the target chip and the simulation result; repeatedly performing an optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold value, and determining the optimized simulation model as the target simulation model, wherein the optimization operation comprises: performing optimization training on the first model parameter and the second model parameter to obtain a first optimization parameter and a second optimization parameter, and updating the first optimization parameter and the second optimization parameter to the basic simulation model to obtain the optimized simulation model.

[0007] According to another embodiment of the present invention, a simulation model generation device is provided, comprising: a first determination module, used to determine a first model parameter required for generating a target simulation model, wherein the target simulation model is used to simulate a target chip; a generation module, used to generate a basic simulation model based on the first model parameter; a simulation module, used to perform simulation using the basic simulation model to obtain a simulation result; a second determination module, used to determine a second model parameter for adjusting the basic simulation model when a first model evaluation index of the basic simulation model is determined to be greater than a predetermined threshold based on a test result obtained by testing the target chip and the simulation result; an execution module, used to repeatedly perform an optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, and determine the optimized simulation model as the target simulation model, wherein the optimization operation comprises: performing optimization training on the first model parameter and the second model parameter to obtain a first optimization parameter and a second optimization parameter, and updating the first optimization parameter and the second optimization parameter to the basic simulation model to obtain the optimized simulation model.

[0008] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0009] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0010] According to yet another embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0011] Through the present invention, firstly, the first model parameter for generating a target simulation model for simulating a target chip is determined, and a basic simulation model is generated and simulated according to the first model parameter to obtain a simulation result. When the first model evaluation index of the basic simulation model determined by the simulation result and the test result of the target chip is greater than a predetermined threshold, the second model parameter is determined, and the second model parameter is used to adjust the basic simulation model. Finally, the optimization operation is repeated, and when the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, the optimized simulation model is determined as the target simulation model. That is, it is achieved that there is no need to make a special fixture plate when generating the target simulation model. Therefore, the problem of high cost of generating simulation models in the related art can be solved, and the effect of reducing the cost of generating simulation models can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a hardware structure block diagram of a mobile terminal according to a method for generating a simulation model according to an embodiment of the present invention;

[0013] Figure 2 is a flow chart of a method for generating a simulation model according to an embodiment of the present invention;

[0014] Figure 3 is a schematic diagram of IBIS model parameters of a three-state output gate circuit according to an embodiment of the present invention;

[0015] Figure 4 is a characteristic schematic diagram of a pull-up curve according to an embodiment of the present invention;

[0016] Figure 5 is a characteristic diagram of a pull-down curve according to an embodiment of the present invention;

[0017] Figure 6 is a schematic diagram of simulation and test data according to an embodiment of the present invention;

[0018] Figure 7 is a schematic diagram of a three-dimensional particle swarm algorithm according to an embodiment of the present invention;

[0019] Figure 8 is a flow chart of a method for generating an IBIS model according to an embodiment of the present invention;

[0020] Fig. 9 4 is a structural block diagram of a device for generating a simulation model according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal of a method for generating a simulation model according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0024] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for generating the simulation model in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0025] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0026] In this embodiment, a method for generating a simulation model is provided. Figure 2 is a flow chart of a method for generating a simulation model according to an embodiment of the present invention, such as Figure 2 As shown, the process includes the following steps:

[0027] Step S202, determining a first model parameter required for generating a target simulation model, wherein the target simulation model is used to simulate a target chip;

[0028] Step S204, generating a basic simulation model based on the first model parameters;

[0029] Step S206, performing simulation using the basic simulation model to obtain simulation results;

[0030] Step S208, determining a second model parameter for adjusting the basic simulation model when it is determined based on the test result obtained by testing the target chip and the simulation result that the first model evaluation index of the basic simulation model is greater than a predetermined threshold;

[0031] Step S210, repeatedly perform the optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, and determine the optimized simulation model as the target simulation model, wherein the optimization operation includes: optimizing the first model parameters and the second model parameters to obtain first optimization parameters and second optimization parameters, updating the first optimization parameters and the second optimization parameters to the basic simulation model to obtain the optimized simulation model.

[0032] In the above embodiment, the target simulation model may be an IBIS (Input / output buffer information specification) model, which may be understood as a behavioral level description model applied to signal simulation. The basic simulation model may be understood as a basic model for generating the target simulation model, the first model parameter is a parameter necessary for generating the basic simulation model, and the simulation result may be understood as the result data obtained by simulating the basic model.

[0033] In the above embodiment, the first model evaluation index can be determined based on the simulation results and the test results, and the predetermined threshold value indicates that the first model evaluation index to be set needs to reach a threshold value where the difference between the simulation and the test is less than or equal to the predetermined threshold value. The second model parameter can be a recommended parameter required to generate a complete IBIS model (i.e., the above-mentioned target simulation model), which can improve the accuracy of the simulation test. When the first model evaluation index is greater than the predetermined threshold value, it is determined that the second model parameter of the basic simulation model can be adjusted and repeated optimization operations are performed; when the first model evaluation index is continuously optimized and reaches less than or equal to the predetermined threshold value (i.e., the first model evaluation index becomes the second model evaluation index), the optimized simulation model at this time is determined as the target simulation model.

[0034] In the above embodiment, the optimization operation can be understood as finding the optimal parameter configuration to maximize or minimize the goal of optimizing the simulation model. Commonly used parameter optimization algorithms may include: Grid Search, RadomSearch, Genetic Algorithm, GA, and Particle SwarmOptimization, PSO, etc. The first optimization parameter can be understood as the parameter obtained by optimizing the first model parameter training, and the second optimization parameter can be understood as the parameter obtained by optimizing the second model parameter training. The first model parameter in the basic simulation model is updated to the first optimization parameter, and the second model parameter in the basic simulation model is updated to the optimized second optimization parameter to obtain the optimized simulation model. When the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, the optimized simulation model is determined as the target simulation model, that is, the generation of the target simulation model is completed.

[0035] Through the present invention, firstly, the first model parameter for generating a target simulation model for simulating a target chip is determined, and a basic simulation model is generated and simulated according to the first model parameter to obtain a simulation result. When the first model evaluation index of the basic simulation model determined by the simulation result and the test result of the target chip is greater than a predetermined threshold, the second model parameter is determined, and the second model parameter is used to adjust the basic simulation model. Finally, the optimization operation is repeated, and when the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, the optimized simulation model is determined as the target simulation model. That is, it is achieved that there is no need to make a special fixture plate when generating the target simulation model. Therefore, the problem of high cost of generating simulation models in the related art can be solved, and the effect of reducing the cost of generating simulation models can be achieved.

[0036] Optionally, the execution subject of the above steps may be an application client, a server, or an agent, etc., but is not limited thereto.

[0037] In an exemplary embodiment, determining first model parameters necessary for generating a target simulation model includes: determining a target type of the target simulation model; and determining the first model parameters based on the target type.

[0038] In the above embodiment, the target type of the target simulation model can be understood as the type of the target simulation model, that is, the target simulation model can include three types: input, output, and input / output (I / O). Different types of target simulation models correspond to different first model parameters. Therefore, before generating the target simulation model, the first model parameter needs to be determined according to the target type of the target simulation model. Taking the output model as an example, the first model parameter can refer to Figure 3 , Figure 3 Schematic diagram of IBIS model parameters of a three-state output gate circuit according to an embodiment of the present invention. Figure 3 As shown: The IBIS output model mainly includes 6 first model parameters, namely: pull-up (Pullup), pull-down (Pulldown), power clamp (Power-Clamp), ground clamp (Power-Clamp), junction capacitance (C_comp), and package (Package, L / C / R).

[0039] In an exemplary embodiment, determining the first model parameters based on the target type includes: when the target type indicates that the target simulation model is an input type model, determining that the first model parameters include the transistor junction capacitance of the target chip; when the target type indicates that the target simulation model is an output type model or an input-output type model, determining that the first model parameters include the transistor junction capacitance of the target chip, a pull-up voltage-current curve when the pin of the target chip is pulled up, a pull-down voltage-current curve when the pin of the target chip is pulled down, a first slope when the pin of the target chip is pulled up, and a second slope when the pin of the target chip is pulled down.

[0040] In the above embodiment, when the target simulation model is an IBIS model, the first model parameters required by different IBIS types can be seen in Table 1, which is an IBIS model parameter requirement table. As can be seen from Table 1, when the target simulation model is an input type model, the required IBIS keyword (i.e., the above first model parameter) is C_comp, and C_comp can be understood as the transistor junction capacitance of the target chip; when the target simulation model is an output type model or an input-output type, the required IBIS keywords are C_comp (i.e., the above transistor junction capacitance), pull-up, pull-down, and slope, wherein the pull-up can be the pull-up voltage-current curve when the pin of the target chip is pulled up, the pull-down can be the pull-down voltage-current curve when the pin of the target chip is pulled down, and the slope can be the slope when the pin is pulled up (i.e., the first slope) and the slope when the pin of the target chip is pulled down (i.e., the second slope).

[0041] Table 1

[0042]

[0043] In the above embodiment, the required parameters in Table 1 can be established by bidirectional deduction based on the data manual and the test results, and then weighted processing. First, the data manual content that can be found can be obtained based on the information provided in the data manual, or the manufacturer can be asked to obtain it, and then the test result information and the data found in the data manual are filled in the table together to perform bidirectional deduction to establish parameter information.

[0044] In an exemplary embodiment, determining the first model parameters necessary for generating a target simulation model includes: in a case where the first model parameters include a transistor junction capacitance of the target chip, determining a capacitive load of the target chip, determining a package type of the target chip, determining an initial capacitance of the target chip based on the package type, and determining a difference between the capacitive load and the initial capacitance as the transistor junction capacitance; in a case where the first model parameters include a pull-up voltage-current curve of the target chip, determining a drive current and a load resistance of a transistor included in the target chip, and determining the pull-up voltage-current curve based on the drive current and the load resistance; in a case where the first model parameters include a pull-down voltage-current curve of the target chip, determining a drive current and a load resistance of a transistor included in the target chip, and determining the pull-down voltage-current curve based on the drive current and the load resistance; in a case where the first model parameters include a pull-down voltage-current curve of the target chip, determining a drive current and a load resistance of a transistor included in the target chip, and determining the pull-down voltage-current curve based on the drive current and the load resistance; In the case where the first slope when the pin of the target chip is pulled up is included, the rising edge time of the pin is determined, the first scattering parameter of the transmission link where the pin is located at the rising edge time is determined, the first test frequency domain response obtained by testing the transmission link is determined, the first point product result of the inverse of the first scattering parameter and the first test frequency domain response is determined as the first simulation frequency domain response, and the first simulation frequency domain response is inversely transformed to obtain the first slope; in the case where the first model parameter includes the second slope when the pin of the target chip is pulled down, the falling edge time of the pin is determined, the second scattering parameter of the transmission link where the pin is located at the falling edge time is determined, the second test frequency domain response obtained by testing the transmission link is determined, the second point product result of the inverse of the second scattering parameter and the second test frequency domain response is determined as the second simulation frequency domain response, and the second simulation frequency domain response is inversely transformed to obtain the second slope.

[0045] In the above embodiment, the transistor junction capacitance C in the target chip comp It can be determined by the following formula: C comp =C in – C pkg , where C in It can be understood as C load (i.e. the capacitive load of the target chip mentioned above), C pkg Indicates the initial capacitance determined according to the package type of the target chip. Usually, the IC package parameters cannot be found in the manual. Therefore, for the setting of IC package parameters, an initial value can be set according to the package type. You can refer to Table 2. The values ​​in Table 2 are examples and can be adjusted according to the target simulation model.

[0046] Table 2

[0047]

[0048] In the above embodiment, the determination of the pull-up voltage-current curve of the target chip includes two aspects: the driving current of the transistor and the load resistance. The driving current in the transistor is determined by the chip circuit, and can be recorded in the data manual of some manufacturers. Since there are three types of pull-up curves in the load resistance, namely maximum, typical and minimum, and they are all set according to the load resistance, you can also refer to the marked records in some data manuals. If it is already marked in the manual, you can calculate it according to the following circuit calculation formula: I = U / R, where the meaning of each parameter can be referred to. Figure 4 As shown, Figure 4 : is a characteristic diagram of a pull-up curve according to an embodiment of the present invention, U represents a voltage value between -VDD and 2VDD; R can take three values ​​of 35, 50 and 65, corresponding to the maximum, typical and minimum conditions in the pull-up voltage and current curve. Figure 4 The figure corresponds to the pull-up curve with a load driving R of 50Ω; VTH can be understood as the transistor turn-on voltage; ID can represent the size of the driving current.

[0049] In the above embodiment, the process of determining the pull-down voltage-current curve of the target chip is similar to that of the pull-up voltage-current curve, and also includes the driving current and load resistance of the transistor. It can also be calculated using the circuit calculation formula I = U / R. Figure 5 : is a characteristic diagram of a pull-down curve according to an embodiment of the present invention, wherein U represents a voltage value between -VDD and 2VDD; R can take three values ​​of 35, 50 and 65, corresponding to the maximum, typical and minimum conditions in the pull-down voltage and current curve.

[0050] In the above embodiment, the first slope when the pin is pulled up and the second slope when the pin is pulled down cannot be provided by the data book, so they can be generated by reverse deduction using the test data: determine the rising edge time and falling edge time of the pin waveform determined by the test, as shown in Table 3, and the S parameter (scattering parameter) results of the transmission link obtained by simulation (i.e., the above first scattering parameter and second scattering parameter). According to the relationship between the link S parameter and the signal, the following calculation can be performed: , where S parameters are frequency domain matrix parameters. The above formula can be used to obtain the frequency domain response of the signal after transmission (i.e. the first test frequency domain response and the second test frequency domain response mentioned above). However, the edge data obtained by the test is a time domain result, and the test result needs to be processed by FFT (Fourier transform). Since the test result is , and the frequency domain slope of the target model is V(f), so the reverse calculation of the above formula can be obtained as [S] -1 = [S] -1 [S] V(f), where [S] -1 represents the inverse of the first scattering parameter. Therefore, the slope in the frequency domain (i.e., the first simulated frequency domain response and the second simulated frequency domain response) V(f) can be expressed as V(f) = [S] -1 , the slope in the time domain (i.e. the first slope and the second slope mentioned above) can be obtained by performing an inverse Fourier transform on the slope in the frequency domain.

[0051] Table 3

[0052]

[0053] In an exemplary embodiment, determining the second model parameters for adjusting the basic simulation model includes: when the target simulation model is an input type model, determining that the second model parameters include a power clamp and a ground clamp; when the target simulation model is an output type model or an input-output type model, determining that the second model parameters include a power clamp, a ground clamp, a first rising waveform of the target chip's voltage loaded to an operating voltage, a second rising waveform of the target chip's voltage loaded to a ground voltage, a first falling waveform of the target chip's voltage loaded to an operating voltage, and a second falling waveform of the target chip's voltage loaded to a ground voltage.

[0054] In the above embodiment, it can be seen from Table 1 that the complete target IBIS model requires recommended parameters (i.e., the above-mentioned second model parameters) in addition to the required parameters to improve the accuracy of the simulation. When the IBIS model is an input type model, it can be seen from Table 1 that the second model parameters include Power_Clamp (i.e., the above-mentioned power clamp) and GND_Clamp (i.e., the above-mentioned ground clamp), which can be directly generated using the ideal data of the transistor. When the IBIS model is an output type model or an input-output type model, the second model parameters include Power_Clamp power clamp, GND_Clamp ground clamp, rising waveforms loaded to VDD and GND (i.e., the above-mentioned first rising waveform and second rising waveform), and falling waveforms loaded to VDD and GND (i.e., the above-mentioned first falling waveform and second falling waveform), and the rising waveform and falling waveform can directly use ideal data.

[0055] In an exemplary embodiment, before determining the second model parameter for adjusting the basic simulation model, the method also includes: determining a first eigenvalue included in the test result and a second eigenvalue included in the simulation result; determining an eigenvalue pair from the first eigenvalue and the second eigenvalue, wherein the eigenvalues ​​included in the eigenvalue pair have the same name and one eigenvalue pair includes an eigenvalue included in the first eigenvalue and an eigenvalue included in the second eigenvalue; determining the mean square error between the first sub-eigenvalue and the second sub-eigenvalue included in the eigenvalue pair for each eigenvalue pair; and determining the average value of the mean square error as the first model evaluation index.

[0056] In the above embodiment, after the basic IBIS model is generated, a simulation test comparison is performed to adjust the parameters of the basic simulation model. Figure 6 , Figure 6 Schematic diagram of simulation and test data of an embodiment of the present invention. Figure 6 As shown, the test data and the link are one-to-one corresponding, so each time the model modifies the parameters, a set of simulation data will be generated. In order to make the comparison between simulation and test results more efficient, the mean square error weighted comparison method of eigenvalues ​​can be used to achieve this: Since the test results and simulation results are both time domain waveform data, the data can be characterized according to the eigenvalues ​​of the waveform signal analysis and processing. The eigenvalues ​​can be eigenvalues ​​in the time domain or in the frequency domain, such as: peak-to-peak value, maximum value, minimum value, edge rate, period, spectrum, etc., and can also be the characteristics of the eye diagram, such as: eye height, eye width, jitter, bathtub curve, bit error rate, etc. According to the eigenvalues ​​of the test data and the eigenvalues ​​of the simulation data, the two eigenvalue data corresponding to each parameter change (that is, a pair of eigenvalue pairs can be formed) are determined, and the mean square error is calculated, as shown in the following formula: , where A is the weighting coefficient and n is the number of eigenvalues. is a specific eigenvalue of the simulation data (i.e., the second eigenvalue mentioned above), and T is a specific eigenvalue of the test data (i.e., the first eigenvalue mentioned above). The above formula is used to calculate the difference between the simulation and the test (i.e., the average value of the mean square error is determined as the first model evaluation index). The influence of the eigenvalue is balanced by weighting. The weighting value can be set by yourself, and the selection and number of eigenvalues ​​can also be selected by yourself. The type and number of eigenvalues ​​are not limited.

[0057] In the above embodiment, determining the average value of the mean square error as the first model evaluation index may include: determining the arithmetic mean value of the mean square error as the first model evaluation index. It may also include determining the weighted average value of the mean square error as the first model evaluation index.

[0058] In an exemplary embodiment, the first model parameter and the second model parameter are optimized and trained to obtain the first optimization parameter and the second optimization parameter, including: determining a first adjustment range of the first model parameter and a second adjustment range of the second model parameter; adjusting the first model parameter within the first adjustment range to obtain the first optimization parameter; adjusting the second model parameter within the second adjustment range to obtain the second optimization parameter.

[0059] In the above embodiment, a first adjustment range of the first model parameter can be preset, and the first model parameter can be adjusted within the first adjustment range to obtain the first optimized parameter. A second adjustment range of the second model parameter can also be preset, and the second model parameter can be adjusted within the second adjustment range to obtain the second optimized parameter.

[0060] In the above embodiment, the IBIS model structure is componentized. Before optimizing the IBIS model, the parameters can be selected by variables, that is, the corresponding parameters can be changed by variables. The variable selection of IBIS model parameters can refer to Table 1 and Figure 3 , the variable junction capacitance C can be included in the first model parameter comp , package Package, pull-up and pull-down curves in VI data, slope parameters in VT data; the second model parameters can select Power_Clamp, GND_Clamp parameters in VI data, rising waveform loaded to VDD and GND in VT data, and falling waveform loaded to VDD and GND. Among them, junction capacitance C comp 1. Package includes three variables: R (resistance), L (inductance), and C (capacitance); the VI curve includes four variables about I, and the VT curve includes five variables about T, for a total of 13 variable parameters.

[0061] In the above embodiment, after selecting the variables, the variables need to be trained so that the simulation and test results match, and the training target is the weighted mean square error. The particle swarm algorithm can be used to optimize the parameters, and the above 13 dimensions are set, the package R / L / C and junction capacitance are set as the first dimension, the 4 variables of the VI curve are set as the second dimension, and the 5 variables of the VT curve are set as the third dimension. The particle swarm algorithm can be used for training process. Figure 7 , Figure 7 It is a schematic diagram of the three-dimensional particle swarm algorithm. Figure 7 As shown in the figure, the set condition is dimensionalization, and the particle swarm algorithm is used to perform step-by-step optimization training in three dimensions. The optimization convergence can be achieved more efficiently by gradually increasing the three dimensions. Finally, the parameters obtained by training (i.e., the first optimization parameters and the second optimization parameters mentioned above) are written back to the IBIS model to complete the generation of the entire IBIS model.

[0062] In an exemplary embodiment, the IBIS model generation method flow diagram is as follows: Figure 8 As shown, it includes: testing the demonstration PCB board or product PCB board through the chip data sheet or gate circuit level protocol and using the simulator to obtain simulation and test results, and establishing a basic IBIS model containing necessary parameters. The simulation and test results form a training set, and the necessary parameters and recommended parameters of the basic model are optimized and generated through the intelligent training algorithm, and finally a complete and high-precision IBIS simulation model is trained and generated.

[0063] In the above embodiment, when generating the basic IBIS model of the necessary parameters, the method of bidirectional derivation of the data manual and the test results is adopted. By obtaining the elements such as table lookup, feature extraction, testing, link S parameter simulation, S parameter inverse matrix, and using the signal time domain frequency domain conversion processing method, the necessary components of the basic IBIS model are generated, which is no longer affected by the limitations of the chip manufacturer's own capabilities and the constraints of confidential information. After the training collection composed of simulation and test results, multiple eigenvalues ​​are extracted and weighted, and the training target is established based on the mean square error. It is no longer necessary to make special fixtures for testing, saving a lot of costs. When generating the recommended parameters, an ideal approximation method is used to quickly generate them. When optimizing the basic model, parameter variableization is adopted, and the parameters are optimized and adjusted using the corresponding specific variables. A total of 13 parameter variables are used, and then the optimization algorithm is used to optimize the model parameters. During optimization, a step-by-step improvement method of 3 dimensions is adopted, and finally a complete and high-precision IBIS model is generated.

[0064] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0065] In the present embodiment, a generation device of a simulation model is also provided, and the device is used to implement the above-mentioned embodiment and preferred implementation mode, and the description has been made no further. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0066] Fig. 9 is a structural block diagram of a device for generating a simulation model according to an embodiment of the present invention, such as Fig. 9 As shown, the device comprises:

[0067] A first determination module 902 is used to determine a first model parameter required for generating a target simulation model, wherein the target simulation model is used to simulate a target chip;

[0068] A first generating module 904, configured to generate a basic simulation model based on the first model parameters;

[0069] A simulation module 906 is used to perform simulation using the basic simulation model to obtain simulation results;

[0070] A second determination module 908 is used to determine a second model parameter for adjusting the basic simulation model when it is determined based on the test result obtained by testing the target chip and the simulation result that the first model evaluation index of the basic simulation model is greater than a predetermined threshold;

[0071] The second generation module 910 is used to repeatedly perform the optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, and the optimized simulation model is determined as the target simulation model, wherein the optimization operation includes: optimizing the first model parameters and the second model parameters to obtain the first optimization parameters and the second optimization parameters, and updating the first optimization parameters and the second optimization parameters to the basic simulation model to obtain the optimized simulation model.

[0072] In an exemplary embodiment, the first determination module 902 may determine the first model parameters necessary for generating the target simulation model in the following manner: determining the target type of the target simulation model; and determining the first model parameters based on the target type.

[0073] In an exemplary embodiment, the first determination module 902 can determine the first model parameters based on the target type in the following manner: when the target type indicates that the target simulation model is an input type model, determine that the first model parameters include the transistor junction capacitance of the target chip; when the target type indicates that the target simulation model is an output type model or an input-output type model, determine that the first model parameters include the transistor junction capacitance of the target chip, the pull-up voltage-current curve when the pin of the target chip is pulled up, the pull-down voltage-current curve when the pin of the target chip is pulled down, the first slope when the pin of the target chip is pulled up, and the second slope when the pin of the target chip is pulled down.

[0074] In an exemplary embodiment, the first determination module 902 can determine the first model parameters necessary for generating the target simulation model in the following manner: in the case where the first model parameters include the transistor junction capacitance of the target chip, determine the capacitive load of the target chip, determine the package type of the target chip, determine the initial capacitance of the target chip based on the package type, and determine the difference between the capacitive load and the initial capacitance as the transistor junction capacitance; in the case where the first model parameters include the pull-up voltage-current curve of the target chip, determine the drive current and load resistance of the transistor included in the target chip, and determine the pull-up voltage-current curve based on the drive current and the load resistance; in the case where the first model parameters include the pull-down voltage-current curve of the target chip, determine the drive current and load resistance of the transistor included in the target chip, and determine the pull-down voltage-current curve based on the drive current and the load resistance; In the case where the first model parameter includes a first slope when the pin of the target chip is pulled up, the rising edge time of the pin is determined, the first scattering parameter of the transmission link where the pin is located at the rising edge time is determined, the first test frequency domain response obtained by testing the transmission link is determined, the first point product result of the inverse of the first scattering parameter and the first test frequency domain response is determined as the first simulation frequency domain response, and the first simulation frequency domain response is inversely transformed to obtain the first slope; in the case where the first model parameter includes a second slope when the pin of the target chip is pulled down, the falling edge time of the pin is determined, the second scattering parameter of the transmission link where the pin is located at the falling edge time is determined, the second test frequency domain response obtained by testing the transmission link is determined, the second point product result of the inverse of the second scattering parameter and the second test frequency domain response is determined as the second simulation frequency domain response, and the second simulation frequency domain response is inversely transformed to obtain the second slope.

[0075] In an exemplary embodiment, the second determination module 908 can determine the second model parameters for adjusting the basic simulation model in the following manner: when the target simulation model is an input type model, determine that the second model parameters include power clamping and ground clamping; when the target simulation model is an output type model or an input-output type model, determine that the second model parameters include power clamping, ground clamping, a first rising waveform of the target chip's voltage loaded to the working voltage, a second rising waveform of the target chip's voltage loaded to the ground voltage, a first falling waveform of the target chip's voltage loaded to the working voltage, and a second falling waveform of the target chip's voltage loaded to the ground voltage.

[0076] In an exemplary embodiment, the device can also be used to, before determining the second model parameter for adjusting the basic simulation model: determine the first eigenvalue included in the test result, and the second eigenvalue included in the simulation result; determine an eigenvalue pair from the first eigenvalue and the second eigenvalue, wherein the eigenvalues ​​included in the eigenvalue pair have the same name, and one eigenvalue pair includes an eigenvalue included in the first eigenvalue and an eigenvalue included in the second eigenvalue; determine the mean square error between the first sub-eigenvalue and the second sub-eigenvalue included in the eigenvalue pair for each eigenvalue pair; and determine the average value of the mean square error as the first model evaluation index.

[0077] In an exemplary embodiment, the second generation module 910 can implement optimization training on the first model parameter and the second model parameter in the following manner to obtain the first optimization parameter and the second optimization parameter, including: determining a first adjustment range of the first model parameter and a second adjustment range of the second model parameter; adjusting the first model parameter within the first adjustment range to obtain the first optimization parameter; adjusting the second model parameter within the second adjustment range to obtain the second optimization parameter.

[0078] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0079] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0080] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0081] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0082] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0083] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of the method in each embodiment of the present application when the computer program is executed by a processor.

[0084] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0085] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for generating a simulation model, characterized in that: include: Determining first model parameters necessary for generating a target simulation model, wherein the target simulation model is used to simulate a target chip; generating a basic simulation model based on the first model parameters; Performing simulation using the basic simulation model to obtain simulation results; Determining a second model parameter for adjusting the basic simulation model when it is determined based on a test result obtained by testing the target chip and the simulation result that the first model evaluation index of the basic simulation model is greater than a predetermined threshold; Repeat the optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, and determine the optimized simulation model as the target simulation model, wherein the optimization operation includes: optimizing the first model parameter and the second model parameter to obtain the first optimization parameter and the second optimization parameter, and updating the first optimization parameter and the second optimization parameter to the basic simulation model to obtain the optimized simulation model; Optimizing and training the first model parameter and the second model parameter to obtain the first optimization parameter and the second optimization parameter includes: determining a first adjustment range of the first model parameter and a second adjustment range of the second model parameter; adjusting the first model parameter within the first adjustment range to obtain the first optimization parameter; adjusting the second model parameter within the second adjustment range to obtain the second optimization parameter; Determining the first model parameters necessary for generating the target simulation model includes: when the target simulation model is an input type model, determining that the first model parameters include the transistor junction capacitance of the target chip; when the target simulation model is an output type model or an input-output type model, determining that the first model parameters include the transistor junction capacitance of the target chip, a pull-up voltage-current curve when the pin of the target chip is pulled up, a pull-down voltage-current curve when the pin of the target chip is pulled down, a first slope when the pin of the target chip is pulled up, and a second slope when the pin of the target chip is pulled down; Determining the second model parameters for adjusting the basic simulation model includes: when the target simulation model is an input type model, determining that the second model parameters include a power clamp and a ground clamp; when the target simulation model is an output type model or an input-output type model, determining that the second model parameters include a power clamp, a ground clamp, a first rising waveform of the target chip's voltage loaded to the working voltage, a second rising waveform of the target chip's voltage loaded to the ground voltage, a first falling waveform of the target chip's voltage loaded to the working voltage, and a second falling waveform of the target chip's voltage loaded to the ground voltage.

2. The method according to claim 1, characterized in that Determining the first model parameter necessary for generating the target simulation model includes: Determining a target type of the target simulation model; The first model parameters are determined based on the target type.

3. The method according to claim 1, characterized in that Determining the first model parameter necessary for generating the target simulation model includes: In a case where the first model parameter includes a transistor junction capacitance of the target chip, determining a capacitive load of the target chip, determining a package type of the target chip, determining an initial capacitance of the target chip based on the package type, and determining a difference between the capacitive load and the initial capacitance as the transistor junction capacitance; In a case where the first model parameter includes a pull-up voltage-current curve of the target chip, determining a drive current and a load resistance of a transistor included in the target chip, and determining the pull-up voltage-current curve based on the drive current and the load resistance; In a case where the first model parameter includes a pull-down voltage-current curve of the target chip, determining a drive current and a load resistance of a transistor included in the target chip, and determining the pull-down voltage-current curve based on the drive current and the load resistance; In a case where the first model parameter includes a first slope when a pin of the target chip is pulled up, determining a rising edge time of the pin, determining a first scattering parameter of a transmission link where the pin is located at the rising edge time, determining a first test frequency domain response obtained by testing the transmission link, determining a first point product result of an inverse of the first scattering parameter and the first test frequency domain response as a first simulation frequency domain response, and performing an inverse Fourier transform on the first simulation frequency domain response to obtain the first slope; In a case where the first model parameter includes a second slope when a pin of the target chip is pulled down, a falling edge time of the pin is determined, a second scattering parameter of a transmission link where the pin is located at the falling edge time is determined, a second test frequency domain response obtained by testing the transmission link is determined, a second point product result of an inverse of the second scattering parameter and the second test frequency domain response is determined as a second simulation frequency domain response, and an inverse Fourier transform is performed on the second simulation frequency domain response to obtain the second slope.

4. The method according to claim 1, characterized in that Before determining the second model parameter for adjusting the basic simulation model, the method further includes: Determine a first characteristic value included in the test result and a second characteristic value included in the simulation result; Determine a feature value pair from the first feature value and the second feature value, wherein the feature values ​​included in the feature value pair have the same name, and one feature value pair includes a feature value included in the first feature value and a feature value included in the second feature value; For each of the eigenvalue pairs, determining a mean square error between a first sub-eigenvalue and a second sub-eigenvalue included in the eigenvalue pair; The average value of the mean square error is determined as the first model evaluation indicator.

5. A device for generating a simulation model, characterized in that: include: A first determination module, used to determine a first model parameter required for generating a target simulation model, wherein the target simulation model is used to simulate a target chip; A first generating module, used for generating a basic simulation model based on the first model parameters; A simulation module, used to perform simulation using the basic simulation model to obtain simulation results; A second determination module is used to determine a second model parameter for adjusting the basic simulation model when it is determined based on the test result obtained by testing the target chip and the simulation result that the first model evaluation index of the basic simulation model is greater than a predetermined threshold; A second generation module is used to repeatedly perform the optimization operation until the second model evaluation index of the optimized simulation model is less than or equal to the predetermined threshold, and the optimized simulation model is determined as the target simulation model, wherein the optimization operation includes: performing optimization training on the first model parameter and the second model parameter to obtain the first optimization parameter and the second optimization parameter, and updating the first optimization parameter and the second optimization parameter to the basic simulation model to obtain the optimized simulation model; The second generation module optimizes and trains the first model parameter and the second model parameter to obtain the first optimization parameter and the second optimization parameter by: determining a first adjustment range of the first model parameter and a second adjustment range of the second model parameter; adjusting the first model parameter within the first adjustment range to obtain the first optimization parameter; adjusting the second model parameter within the second adjustment range to obtain the second optimization parameter; The first determination module determines the first model parameters necessary for generating the target simulation model in the following manner: when the target simulation model is an input type model, the first model parameters are determined to include the transistor junction capacitance of the target chip; when the target simulation model is an output type model or an input-output type model, the first model parameters are determined to include the transistor junction capacitance of the target chip, the pull-up voltage-current curve when the pin of the target chip is pulled up, the pull-down voltage-current curve when the pin of the target chip is pulled down, the first slope when the pin of the target chip is pulled up, and the second slope when the pin of the target chip is pulled down; The second determination module determines the second model parameters for adjusting the basic simulation model in the following manner: when the target simulation model is an input type model, determining that the second model parameters include power clamping and ground clamping; when the target simulation model is an output type model or an input-output type model, determining that the second model parameters include power clamping, ground clamping, a first rising waveform of the target chip's voltage loaded to the working voltage, a second rising waveform of the target chip's voltage loaded to the ground voltage, a first falling waveform of the target chip's voltage loaded to the working voltage, and a second falling waveform of the target chip's voltage loaded to the ground voltage.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 4 when executed.

7. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 4 are implemented.

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