Shifting register, display substrate and display device

Abstract

The invention provides a shifting register, a display substrate and a display device, belongs to the technical field of display, and can solve the problems that an existing shifting register is complex in structure and large in occupied area. The shift register includes a first input sub-circuit configured to transmit a first level signal to a first node in response to a first clock signal; a second input sub-circuit configured to transmit the input signal to a second node in response to the first clock signal; the control sub-circuit is configured to input a second level signal to the first node in response to a second clock signal; the protection sub-circuit is configured to input the voltage of the third node to the second node when the second input sub-circuit does not work, and enable the voltage of the second node to be lower than the voltage of the third node; the first output sub-circuit is configured to output a second level signal in response to the voltage of the first node; the second output sub-circuit is configured to output a second clock signal in response to the voltage of the third node.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and in particular relates to a shift register, a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology.

[0003] The GOA technology is used to integrate a shift register circuit composed of a thin film transistor (TFT) on an array substrate of a display substrate to form a scan drive for the display substrate, thereby eliminating the gate drive integrated circuit part. This can not only reduce product costs in terms of material costs and manufacturing processes, but also enable the display substrate to achieve an aesthetically pleasing design with symmetry on both sides and a narrow frame. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a display substrate and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a shift register, wherein the shift register comprises: a first input subcircuit, a second input subcircuit, a control subcircuit, a protection subcircuit, a first output subcircuit, and a second output subcircuit;

[0006] The first input subcircuit is configured to transmit a first level signal to a first node in response to a first clock signal; the first node is a connection point between the first input subcircuit, the first output subcircuit and the control subcircuit;

[0007] The second input subcircuit is configured to transmit the input signal to a second node in response to the first clock signal; the second node is a connection point between the second input subcircuit and the protection subcircuit;

[0008] The control subcircuit is configured to input a second level signal to the first node in response to a second clock signal;

[0009] The protection subcircuit is configured to transmit the voltage of the second node to the third node when the second input subcircuit is working; when the second input subcircuit is not working, input the voltage of the third node to the second node and make the voltage of the second node lower than the voltage of the third node; the third node is a connection point between the protection subcircuit and the second output subcircuit;

[0010] The first output subcircuit is configured to output a second level signal in response to the voltage of the first node;

[0011] The second output sub-circuit is configured to output a second clock signal in response to a voltage of the third node.

[0012] Optionally, the first input subcircuit includes: a third transistor;

[0013] The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node.

[0014] Optionally, the second input subcircuit comprises: a first transistor;

[0015] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node.

[0016] Optionally, the protection subcircuit includes: a sixth transistor;

[0017] The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node.

[0018] Optionally, the control subcircuit includes: a second transistor;

[0019] The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node.

[0020] Optionally, the first output subcircuit includes: a fifth transistor and a first storage capacitor;

[0021] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal;

[0022] One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line.

[0023] Optionally, the second output subcircuit includes: a fourth transistor and a second storage capacitor;

[0024] The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal;

[0025] One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

[0026] Optionally, the transistors in each sub-circuit are all oxide thin film transistors.

[0027] Optionally, a width-to-length ratio of the second transistor is greater than a width-to-length ratio of the third transistor.

[0028] In a second aspect, an embodiment of the present disclosure provides a shift register, wherein the shift register comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first storage capacitor, and a second storage capacitor;

[0029] The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node;

[0030] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node;

[0031] The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node;

[0032] The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node;

[0033] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal;

[0034] One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line;

[0035] The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal;

[0036] One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

[0037] In a third aspect, an embodiment of the present disclosure provides a display substrate, wherein the display substrate comprises: a substrate, and a plurality of shift registers provided above that are cascaded on the substrate.

[0038] Optionally, the display substrate further comprises: a plurality of clock signal lines and power signal lines; the clock signal lines at least comprise: a first clock signal line and a second clock signal line; the power signal lines at least comprise: a first level signal line and a second level signal line;

[0039] A plurality of the clock signal lines and the power signal lines extend along a first direction and are arranged side by side along a second direction; the first direction and the second direction intersect;

[0040] The width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction.

[0041] Optionally, the first transistor, the second transistor, the third transistor and the sixth transistor in each of the shift registers are divided into a first transistor group;

[0042] The active layers in the first transistor group are arranged along a first direction and are disposed side by side along the first direction.

[0043] Optionally, each active layer in the first transistor group is located between adjacent power signal lines, and a width of each active layer along the second direction is smaller than a distance between adjacent power signal lines.

[0044] Optionally, the width of each active layer in the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

[0045] Optionally, a width of the first transistor group along the second direction is smaller than a width of the clock signal line along the second direction, and is greater than or equal to a width of the power signal line along the second direction.

[0046] Optionally, the fourth transistor and the fifth transistor in each of the shift registers are divided into a second transistor group;

[0047] The active layers in the second transistor group are arranged along the first direction and are arranged side by side along the second direction.

[0048] Optionally, each active layer in the second transistor group is located on a side of the power signal line away from the clock signal line.

[0049] Optionally, a width of each active layer in the second transistor group along the second direction is greater than a width of the clock signal line along the second direction.

[0050] Optionally, the orthographic projection of the first storage capacitor on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the fourth transistor on the substrate;

[0051] The orthographic projection of the second storage capacitor on the substrate is located on a side of the orthographic projection of the fifth transistor on the substrate away from the orthographic projection of the second level signal line on the substrate.

[0052] Optionally, an orthographic projection of the first storage capacitor on the substrate at least partially overlaps with an orthographic projection of the second level signal line on the substrate.

[0053] In a fourth aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes a display substrate as provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 Schematic diagram of a circuit structure of an exemplary shift register.

[0055] Figure 2 for Figure 1 The planar structure diagram of the shift register shown.

[0056] Figure 3 A schematic diagram of the circuit structure of a shift register provided in an embodiment of the present disclosure.

[0057] Figure 4 for Figure 3 The planar structure diagram of the shift register shown.

[0058] Figure 5 for Figure 3 The timing diagram of the shift register is shown.

[0059] Figure 6 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present disclosure.

[0060] Figure 7a A schematic structural diagram of a first gate conductive layer in a display substrate provided in an embodiment of the present disclosure.

[0061] Figure 7b A schematic structural diagram of a second gate conductive layer in a display substrate provided in an embodiment of the present disclosure.

[0062] Figure 7c A schematic diagram of the structure of a semiconductor layer in a display substrate provided in an embodiment of the present disclosure.

[0063] Figure 7d A schematic structural diagram of a third gate conductive layer in a display substrate provided in an embodiment of the present disclosure.

[0064] Figure 7e A schematic structural diagram of a source-drain conductive layer in a display substrate provided in an embodiment of the present disclosure.

[0065] Figure 7f For the above Figures 7a to 7e The laminated structure of each film layer. DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0067] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "electrically connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0068] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are described with N-type transistors. When N-type transistors are used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when the gate inputs a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative labor, so it is also within the scope of protection of the embodiments of the present disclosure. In addition, according to the material of the active layer in the transistor, the transistor can be divided into oxide thin film transistors, low temperature polysilicon thin film transistors and other types. Generally, oxide thin film transistors are N-type transistors, and low temperature polysilicon thin film transistors are P-type transistors.

[0069] Among them, since the transistor used in the embodiment of the present disclosure is an N-type transistor, the working level signal, i.e., the first level signal, in the embodiment of the present disclosure is a high level signal, and the non-working level signal, i.e., the second level signal, is a low level signal; the corresponding first level signal line is a high level signal line, and the second level signal line is a low level signal line.

[0070] Usually, the display substrate includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are cross-arranged to define a plurality of pixel areas, and each pixel area is provided with a pixel unit. The structure of the display substrate is described by taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example. When the display substrate is driven to display, a scanning signal can be written to the gate line row by row according to the picture to be displayed, and a data voltage signal can be written to each data line at the same time, so that the pixel units in the display substrate are lit up row by row.

[0071] Among them, the scanning signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit; in the related technology, the gate driving circuit can be integrated into the gate driving chip, and the source driving circuit can be integrated into the source driving chip; and currently, in order to reduce the number of chips and realize narrow frame or no frame, a technology of integrating the gate driving circuit on the array substrate (Gate On Array; GOA) is provided; wherein the gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is electrically connected to the gate line one by one, and is used to provide a scanning signal for the gate line electrically connected thereto.

[0072] In order to make it clearer how the shift register realizes the output of the scanning signal, a specific example of the shift register is used for explanation below.

[0073] Figure 1 Schematic diagram of a circuit structure of an exemplary shift register, such as Figure 1 The shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first storage capacitor C1, and a second storage capacitor C2.

[0074] The gate of the first transistor T1 is electrically connected to the first clock signal line GCK, the source is electrically connected to the signal input terminal Input, and the drain is electrically connected to the first node N1; the first node N1 is a connection point between the drain of the first transistor T1, the gate of the second transistor T2, the source of the seventh transistor T7 and the source of the eighth transistor T8.

[0075] The gate of the second transistor T2 is electrically connected to the first node N1, the source is electrically connected to the first clock signal line GCK, and the drain is electrically connected to the second node N2; the second node N2 is a connection point between the drain of the second transistor T2, the drain of the third transistor T3, the gate of the sixth transistor T6, the gate of the fourth transistor T4, and one end of the first storage capacitor C1.

[0076] The third transistor T3 has a gate electrically connected to the first clock signal line GCK, a source electrically connected to the low level signal line VGL, and a drain electrically connected to the second node N2.

[0077] The gate of the fourth transistor T4 is electrically connected to the second node N2, the source is electrically connected to the high level signal line VGH and the other end of the first storage capacitor C2, and the drain is electrically connected to the signal output terminal Output.

[0078] The gate of the fifth transistor T5 is electrically connected to the third node N3, the source is electrically connected to the second clock signal line GCB, and the drain is electrically connected to the signal output terminal Output and the other end of the second storage capacitor C2; the third node N3 is the connection point between the gate of the fifth transistor T5, the drain of the eighth transistor T8 and one end of the second storage capacitor C2.

[0079] The gate of the sixth transistor T6 is electrically connected to the second node N2 , the source is electrically connected to the high-level signal line VGH, and the drain is electrically connected to the source of the seventh transistor T7 .

[0080] The gate of the seventh transistor T7 is electrically connected to the second clock signal line GCB, the source is electrically connected to the drain of the sixth transistor T6, and the drain is electrically connected to the first node N1.

[0081] The eighth transistor T8 has a gate electrically connected to the low-level signal line VGL, a source electrically connected to the first node N1, and a drain electrically connected to the third node N3.

[0082] One end of the first storage capacitor C1 is electrically connected to the first node N1 , and the other end is electrically connected to the high level signal line VGH and the source of the fourth transistor T4 .

[0083] One end of the second storage capacitor C2 is electrically connected to the third node N3, and the other end is electrically connected to the drain of the fifth transistor T5 and the signal output terminal Output.

[0084] Figure 1 The shift register shown can be a first-stage shift register in a gate drive circuit, and its signal input terminal Input can be connected to the frame start signal line GSTV. When the shift register is not a first-stage shift register, its input terminal Input is cascaded with shift registers of other stages, and a high-level signal or a second clock signal can be output from the signal output terminal Output according to a preset timing. The specific implementation process can refer to the description in the relevant technology and will not be described in detail here.

[0085] Figure 1 In the shift register shown, in order to make each transistor have a higher mobility, each transistor can be set as a low temperature polysilicon (LTPS) thin film transistor. Since the number of transistors is large, the area occupied by the entire shift register is large. Figure 2 for Figure 1The planar structure diagram of the shift register shown in FIG. Figure 2 As shown, the shift register has a relatively complex structure, and its width along the row direction is 266 micrometers. When the width along the column direction is constant, the area it occupies is relatively large, which affects the narrow frame design of the display substrate.

[0086] In order to solve at least one of the above technical problems, the embodiments of the present disclosure provide a shift register, a display substrate and a display device. The shift register, display substrate and display device provided by the embodiments of the present disclosure will be further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0087] In a first aspect, an embodiment of the present disclosure provides a shift register, Figure 3 A schematic diagram of the circuit structure of a shift register provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the shift register includes: a first input sub-circuit 301 , a second input sub-circuit 302 , a control sub-circuit 303 , a protection sub-circuit 304 , a first output sub-circuit 305 and a second output sub-circuit 306 .

[0088] The first input subcircuit 301 is configured to transmit a first level signal to a first node N1 in response to a first clock signal; the first node N1 is a connection point between the first input subcircuit 301, the first output subcircuit 305 and the control subcircuit 302. The second input subcircuit 302 is configured to transmit an input signal to a second node N2 in response to a first clock signal; the second node N2 is a connection point between the second input subcircuit 302 and the protection subcircuit 304. The control subcircuit 303 is configured to input a second level signal to the first node N1 in response to a second clock signal. The protection subcircuit 304 is configured to transmit a voltage of the second node N2 to a third node N3 when the second input subcircuit 302 is working; when the second input subcircuit 302 is not working, the voltage of the third node N3 is input to the second node N2, and the voltage of the second node N2 is lower than the voltage of the third node N3; the third node N3 is a connection point between the protection subcircuit 304 and the second output subcircuit 306. The first output sub-circuit 305 is configured to output a second level signal in response to the voltage of the first node N1. The second output sub-circuit 306 is configured to output a second clock signal in response to the voltage of the third node N3.

[0089] In the shift register provided in the embodiment of the present disclosure, the signal in the first input subcircuit 301 is output through the first output subcircuit 305, and the signal in the second input subcircuit 302 is output through the second output subcircuit 306, so that when the display substrate is driven to display, the scanning signal can be written to the gate line row by row according to the picture to be displayed, so that the pixel units in the display substrate are lit up row by row. It can be seen that the shift register provided in the embodiment of the present disclosure has a simple structure, which can reduce the number of transistors in the shift register, thereby reducing the area occupied by the shift register, which is conducive to the narrow frame design of the display substrate, thereby improving the user's use effect. At the same time, the protection subcircuit 304 can transmit the voltage of the third node N3 to the second node N2 when the second input subcircuit 302 is not working, so that the voltage of the second node N2 is lower than the voltage of the third node N3, thereby preventing the voltage of the third node N3 from being directly transmitted to the second input subcircuit 302, thereby preventing a higher voltage from breaking down the components in the second input subcircuit 302 that are in a non-working state, thereby improving the stability and service life of the components in the shift register, and further improving the display effect.

[0090] Specifically, Figure 3 As shown, the first input sub-circuit 301 includes: a third transistor T3; the gate of the third transistor T3 is electrically connected to the first clock signal line GCK, the source is electrically connected to the high level signal line VGH, and the drain is electrically connected to the first node N1. The control sub-circuit 304 includes: a second transistor T2; the gate of the second transistor T2 is electrically connected to the second clock signal line GCB, the source is electrically connected to the low level signal line VGL, and the drain is electrically connected to the first node N1.

[0091] When the first clock signal input by the first clock signal line GCK is a high-level signal and the second clock signal input by the second clock signal line GCB is a low-level signal, the third transistor T3 is turned on and the second transistor T2 is turned off, and the high-level signal input by the high-level signal line VGH can be input to the first node N1 through the third transistor T3 to charge the first node N1 to pull up the voltage of the first node N1. When the first clock signal input by the first clock signal line GCK is a low-level signal and the second clock signal input by the second clock signal line GCB is a high-level signal, the second transistor T2 is turned on and the third transistor T3 is turned off, and the low-level signal input by the low-level signal line VGL can be input to the first node N1 through the second transistor T2 to pull down the voltage of the first node N1.

[0092] Continue to refer to Figure 3The second input sub-circuit 302 includes: a first transistor T1; the gate of the first transistor T1 is electrically connected to the first clock signal line GCK, the source is electrically connected to the signal input terminal Input, and the drain is electrically connected to the second node N2. The protection sub-circuit 303 includes: a sixth transistor T6; the gate of the sixth transistor T6 is electrically connected to the high level signal line VGH, the source is electrically connected to the second node N2, and the drain is electrically connected to the third node N3.

[0093] When the first clock signal line GCK is a high level signal, the first transistor T1 is turned on, and the high level signal (which can be a frame start signal) input by the signal input terminal Input can be input to the second node N2 through the first transistor T1, charging the second node N2 to pull up the voltage of the second node N2. At the same time, the sixth transistor T6 is in a normally open state under the control of the high level signal, and the voltage of the second node N2 is transmitted to the third node N3 through the sixth transistor T6. When the first clock signal line GCK is a low level signal, the first transistor T1 is turned off. At this time, the third node N3 has a higher voltage due to a long time of charging. If it is directly transmitted to the drain of the closed first transistor T1, it is easy to break down the first transistor T, causing damage to the first transistor T1. The sixth transistor T6 is in a normally open state, which has a certain impedance, and can play a good role in reducing the voltage of the third node N3 in the process of transmitting it to the second node N2, avoiding the breakdown of the first transistor T2, thereby ensuring the performance stability of the first transistor T1.

[0094] Continue to refer to Figure 3 , the first output sub-circuit 305 includes: a fifth transistor T5 and a first storage capacitor C1; the gate of the fifth transistor T5 is electrically connected to the first node N1, the source is electrically connected to the low-level signal line VGL, and the drain is electrically connected to the signal output terminal Output; one end of the first storage capacitor C1 is electrically connected to the first node N1, and the other end is electrically connected to the low-level signal line VGL. The second output sub-circuit 306 includes: a fourth transistor T4 and a second storage capacitor C2; the gate of the fourth transistor T4 is electrically connected to the third node N3, the source is electrically connected to the second clock signal line GCB, and the drain is electrically connected to the signal output terminal Output; one end of the second storage capacitor C2 is electrically connected to the third node N3, and the other end is electrically connected to the signal output terminal Output.

[0095] When the voltage of the first node N1 is a high level signal, the fifth transistor T5 is turned on, and the low level signal input by the low level signal line VGL can be output by the signal output terminal Output. At the same time, when the voltage of the third node N3 is a high level signal, the fourth transistor T4 is turned on, and the low level signal in the second clock signal input by the second clock signal line GCB can be output by the signal output terminal Output. At this time, the low level signal in the second clock signal is the same as the level signal input by the low level signal line VGL. When the voltage of the first node N1 is a level signal, the fifth transistor T5 is turned off. At the same time, when the voltage of the third node N3 is a high level signal, the fourth transistor T4 is turned on, and the high level signal in the second clock signal input by the second clock signal line GCB can be output by the signal output terminal Output.

[0096] In some embodiments, the width-to-length ratio of the second transistor T2 is greater than the width-to-length ratio of the third transistor T3 .

[0097] In practical applications, the width-to-length ratio of the second transistor T2 can be appropriately increased so that the second transistor T2 has higher stability and can transmit a larger current. When the second transistor T2 is turned on, the low-level signal input by the low-level signal line VGL can be stably input to the first node N1, so that the fifth transistor T5 can be controlled to be completely turned off to avoid leakage current, thereby improving the stability of the signal output at the signal output terminal Output.

[0098] Figure 4 for Figure 3 The planar structure diagram of the shift register shown in FIG. Figure 4 As shown, the shift register is only provided with 6 transistors. Figure 1 and Figure 2 The structure of the shift register shown in FIG. 1 can significantly reduce the number of transistors and simplify the circuit structure. At the same time, the width of the shift register along the row direction is 226 microns, which is relatively Figure 1 and Figure 2 The width of the shift register shown is reduced by 40 micrometers, which is 15% of the original width, which is beneficial to the narrow frame design of the display substrate, thereby improving the user's use effect.

[0099] Figure 5 for Figure 3 The timing diagram of the shift register shown in FIG. 1 is used to further describe the working principle of the shift register provided in the embodiment of the present disclosure in combination with the timing diagram.

[0100] In the first stage, the signal of the first clock signal line GCK is a high-level signal, the signal of the second clock signal line GCB is a low-level signal, the first transistor T1 and the third transistor T3 are both turned on, the second transistor T2 is turned off, the high-level signal input by the high-level signal line VGH can charge the first node N1, and the frame start signal input by the signal input terminal Input can charge the second node N2 and the third node N3, so that the voltages of the first node N1, the second node N2 and the third node N3 are all high-level voltages. At this time, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the voltage of the signal output terminal Output is reset by the low-level signal input by the low-level signal line VGL and the low-level signal of the second clock signal line GCB.

[0101] In the second stage, the signal of the first clock signal line GCK is a low level signal, the signal of the second clock signal line GCB is a high level signal, the first transistor T1 and the third transistor T3 are both turned off, the second transistor T2 is turned on, and the voltage of the first node N1 is pulled down by the low level signal input by the low level signal line VGL, so that the fourth transistor T4 is turned off. The voltage of the third node N3 continues to maintain a high level signal state under the action of the second storage capacitor C2, the fifth transistor T5 is turned on, and the high level signal of the second clock signal GCB is output by the signal output terminal Output.

[0102] In the third stage, the signal of the first clock signal line GCK is a high-level signal, the signal of the second clock signal line GCB is a low-level signal, the first transistor T1 and the third transistor T3 are both turned on, the second transistor T2 is turned off, the voltage of the first node N1 is pulled up again, the fourth transistor T4 is turned on, and the low-level signal input by the low-level signal line VGL is output by the signal output terminal Output. At this time, the signal input terminal Input inputs a low-level signal, and the fifth transistor T5 is turned off.

[0103] In the fourth stage, the signal of the first clock signal line GCK is a low-level signal, the signal of the second clock signal line GCB is a high-level signal, the first transistor T1 and the third transistor T3 are both turned off, the second transistor T2 is turned on, and the voltage of the first node N1 is pulled down by the low-level signal input by the low-level signal line VGL, so that the fourth transistor T4 is turned off. At the same time, the signal input terminal Input inputs a low-level signal, the fifth transistor T5 is turned off, and the signal output terminal Output has no signal output and is in a noise reduction state.

[0104] In a second aspect, an embodiment of the present disclosure provides a shift register, Figure 6 A schematic diagram of a circuit structure of another shift register provided in an embodiment of the present disclosure is shown in FIG. Figure 6As shown, the shift register includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first storage capacitor C1, and a second storage capacitor C2. The gate of the third transistor T3 is electrically connected to the first clock signal line GCK, the source is electrically connected to the high level signal line VGH, and the drain is electrically connected to the first node N1. The gate of the second transistor T2 is electrically connected to the second clock signal line GCB, the source is electrically connected to the low level signal line VGL, and the drain is electrically connected to the first node N1. The gate of the first transistor T1 is electrically connected to the first clock signal line GCK, the source is electrically connected to the signal input terminal Input, and the drain is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the high level signal line VGH, the source is electrically connected to the second node N2, and the drain is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the first node N1, the source is electrically connected to the low-level signal line VGL, and the drain is electrically connected to the signal output terminal Output; one end of the first storage capacitor C1 is electrically connected to the first node N1, and the other end is electrically connected to the low-level signal line VGL. The gate of the fourth transistor T4 is electrically connected to the third node N3, the source is electrically connected to the second clock signal line GCB, and the drain is electrically connected to the signal output terminal Output; one end of the second storage capacitor C2 is electrically connected to the third node N3, and the other end is electrically connected to the signal output terminal Output.

[0105] The shift register provided in the embodiment of the present disclosure is a specific circuit structure of the shift register provided in any of the above embodiments, and its implementation principle is the same as the implementation principle of the shift register provided in any of the above embodiments, which will not be described again here.

[0106] In a third aspect, an embodiment of the present disclosure provides a display substrate, which includes: a substrate (not shown in the figure), and a plurality of shift registers provided in any of the above embodiments cascaded on the substrate. Figures 7a to 7f The following are schematic diagrams of the structures of various film layers in the display substrate provided in the embodiments of the present disclosure. The display substrate provided in the embodiments of the present disclosure will be further described in detail in combination with the structures of various film layers.

[0107] Figure 7a A schematic diagram of the structure of the first gate conductive layer in the display substrate provided in an embodiment of the present disclosure, as shown in FIG. Figure 7a As shown, the first gate conductive layer includes: first plates of the first storage capacitor C1 and the second storage capacitor C2, and connecting lines electrically connecting the first plates.

[0108] Figure 7b A schematic diagram of the structure of the second gate conductive layer in the display substrate provided in an embodiment of the present disclosure, as shown in FIG. Figure 7bAs shown, the second gate conductive layer includes: a second electrode plate of the first storage capacitor C1 and the second storage capacitor C2, and a connecting line electrically connecting the second electrode plates. The first gate conductive layer and the second gate conductive layer are both formed on the substrate, and the orthographic projections of the corresponding first electrode plate and the second electrode plate on the substrate overlap to form the first storage capacitor C1 and the second storage capacitor C2.

[0109] Figure 7c A schematic diagram of the structure of a semiconductor layer in a display substrate provided in an embodiment of the present disclosure, such as Figure 7c As shown, the semiconductor layer includes: active layers of a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6. The active layers of each transistor are made of oxide materials, such as metal oxides such as Indium Gallium Zinc Oxide (IGZO).

[0110] Figure 7d A schematic diagram of the structure of the third gate conductive layer in the display substrate provided in an embodiment of the present disclosure, such as Figure 7d As shown, the third gate conductive layer includes: gates of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, and connecting lines electrically connecting the gates.

[0111] Figure 7e A schematic diagram of the structure of the source-drain conductive layer in the display substrate provided for the embodiment of the present disclosure, as shown in the figure, the source-drain conductive layer includes: the source and drain of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, as well as the frame start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the high-level signal line VGH and the low-level signal line VGL, and the connecting lines electrically connecting the respective sources, drains and the respective signal lines.

[0112] Figure 7f For the above Figures 7a to 7e The stacked structure of each film layer in the display substrate can be formed by stacking the above-mentioned film layers together to form a shift register in the display substrate. Figure 4 The structures shown are the same.

[0113] Continue to refer Figure 7e and Figure 7fThe display substrate further includes: a plurality of clock signal lines and power signal lines; the clock signal lines include at least: a first clock signal line GCK and a second clock signal line GCB; the power signal lines include at least: a high level signal line VGH and a low level signal line VGL; the plurality of clock signal lines and the power signal lines extend along a first direction and are arranged side by side along a second direction; the second direction intersects with the first direction; the width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction.

[0114] In the embodiment of the present disclosure, the first direction may be the row direction of the display substrate, and the second direction may be the column direction of the display substrate. The first clock signal line GCK, the second clock signal line GCB, the high level signal line VGH and the low level signal line VGL may extend along the same direction (first direction), i.e., the column direction. Among them, the first clock signal line GCK and the second clock signal line GCB in the clock signal line transmit a constantly changing voltage signal, and the high level signal line VGH and the low level signal line VGL in the power signal line transmit a stable voltage signal. In order to avoid the first clock signal line from generating a large parasitic capacitance, the width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction. For example, the width of the first clock signal line GCK along the second direction is greater than the width of the high level signal line VGH along the second direction to ensure efficient transmission of the signal. It should be noted here that, taking the first clock signal line GCK as an example, the first clock signal line GCK is not a straight line, but is generally extended along the first direction, and may be bent at certain positions. At a certain section of the bend, the section may extend along the second direction, and the width of the first clock signal line GCK along the second direction may be the length of the section along the second direction.

[0115] Continue to refer Figure 7c , the first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 are divided into a first transistor group; each active layer in the first transistor group is arranged along a first direction and arranged side by side along the first direction.

[0116] The drains of the first transistor T1 and the sixth transistor T6 are connected together. In practical applications, the active layer of the first transistor T1 and the active layer of the sixth transistor T6 can be directly connected together, that is, the active layers of the two are part of a whole, so as to reduce the process of drilling when forming the drain and save the preparation cost.

[0117] According to the position of each transistor relative to the power signal line in the display substrate, each transistor can be divided into multiple groups. For example, the first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 can be divided into a first transistor group, and the fourth transistor T4 and the fifth transistor T5 can be divided into a second transistor group.

[0118] The shape of the active layer of the first transistor group can be a rectangle, the longer side of the rectangle is arranged along the first direction, that is, arranged along the column direction, and the shorter side is arranged along the second direction, that is, arranged along the row direction. Each active layer in the first transistor group can be divided into three parts, wherein the first part is the active layer of the first transistor T1 and the sixth transistor T6, the second part is the active layer of the second transistor T2, and the third part is the active layer of the third transistor. Each active layer in the first transistor group can be arranged along the first direction and arranged side by side along the first direction, which can reduce the width occupied by each active layer in the first transistor group along the row direction, thereby reducing the width of the entire shift register in the display substrate, which is conducive to the narrow frame design of the display substrate, thereby improving the user's use effect.

[0119] Continue to refer to 7c, Figure 7e and Figure 7f , each active layer in the first transistor group is located between adjacent power signal lines, and the width of each active layer along the second direction is smaller than the distance between adjacent power signal lines.

[0120] Since the high-level signal line VGH and the low-level signal line VGL transmit stable voltage signals, they will not interfere with other conductive layers. Each active layer in the first transistor group can be arranged between the high-level signal line VGH and the low-level signal line VGL, and the width of each active layer along the second direction is smaller than the distance between adjacent high-level signal lines VGH and low-level signal lines VGL, so as to further reduce the width occupied by the first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 in the first transistor group along the first direction, thereby reducing the width of the entire shift register, which is beneficial to the narrow frame design of the display substrate, thereby improving the user's use effect.

[0121] Continue to refer to 7c, Figure 7e and Figure 7f , the width of each active layer in the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

[0122] The first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 in the first transistor group do not directly output to the pixel circuit in the display area, and the width of the active layer along the second direction can be smaller. For example, the width along the second direction can be smaller than the width of the clock signal line (the first clock signal line GCK or the second clock signal line GCB) along the second direction, and greater than or equal to the width of the power signal line (the high-level signal line VGH or the low-level signal line VGL) along the second direction. While ensuring the performance stability of each transistor, the width occupied by each transistor along the row direction can be reduced, thereby reducing the width of the entire shift register, which is beneficial to the narrow frame design of the display substrate, thereby improving the user experience.

[0123] In some embodiments, Figure 7f As shown, the width of the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

[0124] The first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 in the first transistor group are arranged side by side along the first direction, that is, the first transistor group is arranged along the first direction as a whole, and the width of the first transistor group along the second direction is the width of each transistor therein along the second direction, wherein the width of each transistor along the second direction includes not only the width of the above-mentioned active layer along the second direction, but also the width of the thin film transistor of the source, drain, gate and other structures along the second direction as a whole. If the widths of each transistor along the second direction are different, the maximum width of each transistor along the second direction is the width of the first transistor group along the second direction. For example, the width of the first transistor group along the second direction can be less than the width of the clock signal line (the first clock signal line GCK or the second clock signal line GCB) along the second direction, and is greater than or equal to the width of the power signal line (the high level signal line VGH or the low level signal line VGL) along the second direction. While ensuring the performance stability of each transistor in the first transistor group, the width occupied by the first transistor group along the row direction can be reduced, thereby reducing the width of the entire shift register, which is conducive to the narrow frame design of the display substrate, thereby improving the user's use effect.

[0125] Continue to refer to 7c, Figure 7e and Figure 7f , the fourth transistor T4 and the fifth transistor T5 are divided into a second transistor group; the active layers in the second transistor group are arranged along the first direction and arranged side by side along the second direction.

[0126] The fourth transistor T4 and the fifth transistor T5 in the second transistor group are used as output transistors, which are directly output to the pixel circuit in the display area. They can be set in different areas from the first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 in the first transistor group mentioned above to ensure the performance of the fourth transistor T4 and the fifth transistor T5 in the second transistor group and improve the stability of the output gate drive signal. Specifically, the active layers in the second transistor group can be arranged along the first direction and arranged side by side along the second direction to increase the area of ​​each active layer in the second transistor group. At the same time, it can be set on the side of the power signal line away from the clock signal line, and it is not necessary to set it between the adjacent signal lines to form an active layer with a larger area to ensure the performance stability of the output transistor.

[0127] Continue to refer to 7c, Figure 7e and Figure 7f , the width of each active layer in the second transistor group along the second direction is greater than the width of the clock signal line along the second direction.

[0128] The width of each active layer in the second transistor group along the second direction is larger. For example, the width of each active layer in the second transistor group along the second direction is greater than the width of the clock signal line (the first clock signal line GCK or the second clock signal line GCB), so as to ensure that the fourth transistor T4 and the fifth transistor T5 in the second transistor group have higher stability as a whole, thereby improving the stability of the output gate drive signal.

[0129] Continue to refer to 7a. Figure 7b to Figure 7f The orthographic projection of the first storage capacitor C1 on the substrate is located between the orthographic projection of the high-level signal line VGH on the substrate and the orthographic projection of the fourth transistor T4 on the substrate; the orthographic projection of the second storage capacitor C2 on the substrate is located on the side of the orthographic projection of the fifth transistor T5 on the substrate away from the orthographic projection of the low-level signal line VGL on the substrate.

[0130] The first storage capacitor C1 and the film layers of each transistor are arranged in different film layers. The first storage capacitor C1 can be arranged between the high-level signal line VGH and the fourth transistor T4, so as to facilitate stable electrical connection between it and each transistor. Similarly, the second storage capacitor C2 can be arranged on the side of the fifth transistor T5 away from the low-level signal line VGL, so as to facilitate stable electrical connection between it and each transistor.

[0131] Continue to refer to 7a. Figure 7b to Figure 7f , the orthographic projection of the first storage capacitor C1 on the substrate at least partially overlaps with the orthographic projection of the low-level signal line VGL on the substrate.

[0132] The first storage capacitor C1 can be arranged in a different film layer from the film layers of each transistor, and its positive projection on the substrate can at least partially overlap with the positive projection of the low-level signal line VGL on the substrate, so as to further reduce the width of the first storage capacitor C1 along the row direction, thereby reducing the width of the entire shift register, which is conducive to the narrow frame design of the display substrate, thereby improving the user's use effect. At the same time, the first storage capacitor C1 and the second storage capacitor C2 can be rectangular or similar to a rectangular shape, the longer side of the rectangle can be arranged along the first direction, and the narrower side can be arranged along the second direction, which can further reduce the width of the first storage capacitor C1 and the second storage capacitor C2 along the row direction, thereby reducing the width of the entire shift register, which is conducive to the narrow frame design of the display substrate, thereby improving the user's use effect.

[0133] In a fourth aspect, an embodiment of the present disclosure provides a display device, which includes a shift register and a display substrate as provided in any of the above embodiments. The display device can be any product or component with a display function, such as a television, a mobile phone, a display, a notebook computer, a digital photo frame, a navigator, etc. The implementation principle is similar to that of the above shift register and display substrate, and will not be described in detail here.

[0134] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, wherein: The shift register comprises: a first input subcircuit, a second input subcircuit, a control subcircuit, a protection subcircuit, a first output subcircuit and a second output subcircuit; The first input subcircuit is configured to transmit a first level signal to a first node in response to a first clock signal; the first node is a connection point between the first input subcircuit, the first output subcircuit and the control subcircuit; The second input subcircuit is configured to transmit the input signal to a second node in response to the first clock signal; the second node is a connection point between the second input subcircuit and the protection subcircuit; The control subcircuit is configured to input a second level signal to the first node in response to a second clock signal; The protection subcircuit is configured to transmit the voltage of the second node to the third node when the second input subcircuit is working; when the second input subcircuit is not working, input the voltage of the third node to the second node and make the voltage of the second node lower than the voltage of the third node; the third node is a connection point between the protection subcircuit and the second output subcircuit; The first output subcircuit is configured to output a second level signal in response to the voltage of the first node; The second output sub-circuit is configured to output a second clock signal in response to a voltage of the third node.

2. The shift register according to claim 1, wherein: The first input subcircuit comprises: a third transistor; The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node.

3. The shift register according to claim 2, wherein: The second input subcircuit includes: a first transistor; The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node.

4. The shift register according to claim 3, wherein: The protection subcircuit comprises: a sixth transistor; The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node.

5. The shift register according to claim 4, wherein: The control subcircuit includes: a second transistor; The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node.

6. The shift register according to claim 5, wherein: The first output subcircuit includes: a fifth transistor and a first storage capacitor; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal; One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line.

7. The shift register according to claim 6, wherein: The second output subcircuit includes: a fourth transistor and a second storage capacitor; The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal; One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

8. The shift register according to any one of claims 1 to 7, wherein: The transistors in each sub-circuit are all oxide thin film transistors.

9. The shift register according to claim 8, wherein: The width-to-length ratio of the second transistor is greater than the width-to-length ratio of the third transistor.

10. A shift register, wherein: The shift register comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first storage capacitor, and a second storage capacitor; The control electrode of the third transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the first level signal line, and the second electrode is electrically connected to the first node; The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode is electrically connected to the signal input terminal, and the second electrode is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the first level signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the second clock signal line, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the first node; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode is electrically connected to the second level signal line, and the second electrode is electrically connected to the signal output terminal; One end of the first storage capacitor is electrically connected to the first node, and the other end is electrically connected to the second level signal line; The control electrode of the fourth transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal line, and the second electrode is electrically connected to the signal output terminal; One end of the second storage capacitor is electrically connected to the third node, and the other end is electrically connected to the signal output end.

11. A display substrate, wherein: The display substrate comprises: a base, and a plurality of shift registers according to any one of claims 1 to 10 cascaded on the base.

12. The display substrate according to claim 11, wherein: The display substrate further comprises: a plurality of clock signal lines and power signal lines; the clock signal lines at least comprise: a first clock signal line and a second clock signal line; the power signal lines at least comprise: a first level signal line and a second level signal line; A plurality of the clock signal lines and the power signal lines extend along a first direction and are arranged side by side along a second direction; the first direction and the second direction intersect; The width of the clock signal line along the second direction is greater than the width of the power signal line along the second direction.

13. The display substrate according to claim 12, wherein: The first transistor, the second transistor, the third transistor and the sixth transistor in each of the shift registers are divided into a first transistor group; The active layers in the first transistor group are arranged along a first direction and are disposed side by side along the first direction.

14. The display substrate according to claim 13, wherein: Each active layer in the first transistor group is located between adjacent power signal lines, and a width of each active layer along the second direction is smaller than a distance between adjacent power signal lines.

15. The display substrate according to claim 14, wherein: The width of each active layer in the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

16. The display substrate according to claim 15, wherein: The width of the first transistor group along the second direction is smaller than the width of the clock signal line along the second direction, and is greater than or equal to the width of the power signal line along the second direction.

17. The display substrate according to claim 12, wherein: The fourth transistor and the fifth transistor in each of the shift registers are divided into a second transistor group; The active layers in the second transistor group are arranged along the first direction and are arranged side by side along the second direction.

18. The display substrate according to claim 17, wherein: Each active layer in the second transistor group is located on a side of the power signal line away from the clock signal line.

19. The display substrate according to claim 17, wherein: The width of each active layer in the second transistor group along the second direction is greater than the width of the clock signal line along the second direction.

20. The display substrate according to claim 12, wherein: The orthographic projection of the first storage capacitor on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the fourth transistor on the substrate; The orthographic projection of the second storage capacitor on the substrate is located on a side of the orthographic projection of the fifth transistor on the substrate away from the orthographic projection of the second level signal line on the substrate.

21. The display substrate according to claim 20, wherein: An orthographic projection of the first storage capacitor on the substrate at least partially overlaps with an orthographic projection of the second level signal line on the substrate.

22. A display device, wherein: The display device comprises the display substrate according to any one of claims 11 to 21.

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