Scanning driving circuit, display device, and method of operating display device

Abstract

The invention discloses a scan driving circuit, a display device, and a method of operating the display device. The scan driving circuit includes an input transistor, an output transistor, and a discharge control transistor. The input transistor is connected between an input terminal receiving a start signal and a first node. The input transistor includes a gate electrode connected to a clock terminal. The output transistor is connected between an output terminal outputting a scan signal and a first voltage terminal. The output transistor includes a gate electrode connected to the first node. The discharge control transistor is connected between the first node and a second voltage terminal, and includes a gate electrode connected to the second voltage terminal. Each of the second plurality of frames of the start signal includes an addressing period and a self-scanning period. In the addressing period, the discharge voltage provided to the second voltage terminal is a high voltage. In the self-scan period, the voltage level of the discharge voltage is lower than the voltage level of the high voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0081412 filed in the Korean Intellectual Property Office on June 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a scan driving circuit, a display device, and a method of operating the display device, and more particularly, to a scan driving circuit, a display device including the scan driving circuit, and a method of operating the display device. Background Art

[0004] An electronic device that provides images to a user, such as a smart phone, a digital camera, a notebook computer, a navigation system, a monitor, or a smart TV, includes a display device for displaying images. The display device generates images and provides the generated images to the user through a display screen.

[0005] The display device includes a display panel and a driving controller for controlling the display panel. When the driving controller supplies a data signal to the display panel and a current corresponding to the data signal is supplied to pixels of the display panel, a given image may be displayed. Summary of the invention

[0006] Embodiments of the present disclosure may provide a scan driving circuit capable of reducing power consumption, a display device including the scan driving circuit, and a method of operating the display device.

[0007] According to an embodiment, a scan driving circuit includes: an input transistor connected between an input terminal receiving a start signal and a first node, the input transistor including a gate electrode connected to a clock terminal; an output transistor connected between an output terminal outputting a scan signal and a first voltage terminal, the output transistor including a gate electrode connected to the first node; and a discharge control transistor connected between the first node and a second voltage terminal, the discharge control transistor including a gate electrode connected to the second voltage terminal. Each of the second plurality of frames of the start signal includes an address period and a self-scan period. In the address period, a discharge voltage supplied to the second voltage terminal is a high voltage. In the self-scan period, a voltage level of the discharge voltage is lower than a voltage level of the high voltage.

[0008] In an embodiment, in the address period, the clock signal supplied to the clock terminal may be a signal switched between the high voltage and a first low voltage, and in the self-scan period, the clock signal may be maintained at the high voltage.

[0009] In an embodiment, in the self-scan period, the discharge voltage may be a second low voltage lower than the first low voltage.

[0010] In an embodiment, during the self-scan period, the output transistor and the discharge control transistor may maintain a turned-on state.

[0011] In an embodiment, during the self-scan period, the scan signal may be maintained at a first low voltage.

[0012] In an embodiment, when the driving frequency of the start signal is a first frequency, each frame in the first plurality of frames includes the address period. When the driving frequency of the start signal is a second frequency lower than the first frequency, each frame in the second plurality of frames may include the address period and the self-scan period.

[0013] According to an embodiment, a display device may include: a display panel including pixels; a drive controller receiving an input image signal and outputting an output image signal; a data drive circuit outputting a data signal corresponding to the output image signal; a scan drive circuit providing a first scan signal to the pixel; and a voltage generator providing a first low voltage and a discharge voltage in response to a voltage control signal. The drive controller may provide the voltage control signal to the voltage generator, and may provide a start signal and a clock signal to the scan drive circuit, the voltage control signal being used to select a voltage level of the discharge voltage. Each of the second plurality of frames of the start signal may include an address period and a self-scan period. The discharge voltage may be a high voltage in the address period, and may be a second low voltage lower than the first low voltage in the self-scan period. The scan drive circuit may output the first scan signal in response to the start signal, the clock signal, and the discharge voltage. In the self-scan period, the scan drive circuit may maintain the first scan signal at the first low voltage in response to the discharge voltage.

[0014] In an embodiment, the scan drive circuit may include: an input transistor connected between an input terminal receiving the start signal and a first node, the input transistor may include a gate electrode connected to a clock terminal receiving the clock signal; an output transistor connected between an output terminal outputting the first scan signal and a first voltage terminal receiving the first low voltage, the output transistor includes a gate electrode connected to the first node; and a discharge control transistor connected between the first node and a second voltage terminal receiving the discharge voltage, the discharge control transistor includes a gate electrode connected to the second voltage terminal.

[0015] In an embodiment, in the address period, the clock signal supplied to the clock terminal may be a signal switched between the high voltage and the first low voltage, and in the self-scan period, the clock signal may be maintained at the high voltage.

[0016] In an embodiment, in the self-scan period, the discharge voltage may be the second low voltage lower than the first low voltage.

[0017] In an embodiment, during the self-scan period, the output transistor and the discharge control transistor may maintain a turned-on state.

[0018] In an embodiment, when the driving frequency of the start signal is a first frequency, each frame in the first plurality of frames may include the address period. When the driving frequency of the start signal is a second frequency lower than the first frequency, each frame in the second plurality of frames may include the address period and the self-scan period.

[0019] In an embodiment, the pixel may include: a light-emitting element; a first pixel transistor, including a first electrode, a second electrode and a gate electrode, the second electrode of the first pixel transistor being connected to the light-emitting element; a second pixel transistor, connected between the first electrode of the first pixel transistor and a data line receiving the data signal, the second pixel transistor including a gate electrode receiving a second scanning signal different from the first scanning signal; and a third pixel transistor, connected between the gate electrode of the first pixel transistor and a voltage line receiving an initialization voltage, the third pixel transistor including a gate electrode receiving the first scanning signal.

[0020] In an embodiment, the scan driving circuit may include a first scan driving circuit providing the first scan signal and a second scan driving circuit providing the second scan signal.

[0021] In an embodiment, in the address period, the first scan signal may be activated to a level at which the third pixel transistor is turned on, and the second scan signal may be activated to a level at which the second pixel transistor is turned on.

[0022] In an embodiment, in the self-scan period, the first scan signal may be maintained at an inactive level, and the second scan signal may be activated to a level at which the second pixel transistor is turned on.

[0023] According to an embodiment, a display device may include: a display panel including pixels; a scan drive circuit providing a scan signal to the pixels; and an emission drive circuit providing an emission signal to the pixels. The pixels may include: a light emitting element; a first pixel transistor including a first electrode, a second electrode and a gate electrode, the second electrode of the first pixel transistor being connected to the light emitting element; a second pixel transistor connected between the gate electrode of the first pixel transistor and a voltage line receiving an initialization voltage, and the second pixel transistor including a gate electrode receiving the scan signal; and a third pixel transistor connected between a first driving voltage line receiving a first driving voltage and the first electrode of the first pixel transistor, and the third pixel transistor including a gate electrode for receiving the emission signal. The scan drive circuit may include: an input transistor connected between an input terminal receiving a start signal and a first node, the input transistor including a gate electrode connected to a clock terminal; an output transistor connected between an output terminal outputting the scan signal and a first voltage terminal, the output transistor including a gate electrode connected to the first node; and a discharge control transistor connected between the first node and a second voltage terminal, the discharge control transistor including a gate electrode connected to the second voltage terminal. In the first mode, each of the second pixel transistor and the third pixel transistor may be turned on, and the discharge voltage supplied to the second voltage terminal may be a high voltage. In the second mode, the second pixel transistor may be turned off, the third pixel transistor may be turned on, and a voltage level of the discharge voltage may be lower than a voltage level of the high voltage.

[0024] In an embodiment, in the second mode, the output transistor and the discharge control transistor may maintain a turned-on state.

[0025] In an embodiment, in the second mode, the scan signal may be maintained at a first low voltage.

[0026] In an embodiment, in the first mode, the clock signal provided to the clock terminal may be a signal that switches between the high voltage and the first low voltage, and in the second mode, the clock signal may be maintained at the high voltage.

[0027] According to an embodiment, a method of operating a display device including a scan driving circuit may include: generating a start signal, a clock signal, and a voltage control signal; generating a first low voltage and a discharge voltage in response to the voltage control signal; generating a first scan signal in response to the start signal, the clock signal, the first low voltage, and the discharge voltage; and displaying an image in response to the first scan signal and a data signal. Each of a plurality of frames of the start signal may include an address period and a self-scan period. The discharge voltage may be a high voltage in the address period, and may be a second low voltage lower than the first low voltage in the self-scan period. The scan driving circuit may include: a discharge control transistor that maintains a first node at the discharge voltage during the self-scan period; and an output transistor that discharges the first scan signal to the first low voltage in response to the discharge voltage of the first node.

[0028] In an embodiment, generating the start signal, the clock signal and the voltage control signal may include: generating the clock signal that swings between the high voltage and the first low voltage during the addressing period; and maintaining the clock signal at the high voltage during the self-scanning period.

[0029] In an embodiment, the method further comprises: generating a second scanning signal different from the first scanning signal.

[0030] In an embodiment, the display panel may further include pixels, and the pixels may include: a light-emitting element; a first pixel transistor, including a first electrode, a second electrode and a gate electrode, the second electrode of the first pixel transistor being connected to the light-emitting element; a second pixel transistor, connected between the first electrode of the first pixel transistor and a data line receiving the data signal, and the second pixel transistor includes a gate electrode receiving the second scanning signal; and a third pixel transistor, connected between the gate electrode of the first pixel transistor and a voltage line receiving an initialization voltage, and the third pixel transistor includes a gate electrode receiving the first scanning signal.

[0031] In an embodiment, generating the first scan signal may include: activating the first scan signal during the addressing period so that the third pixel transistor is turned on; and activating the second scan signal during the addressing period so that the second pixel transistor is turned on.

[0032] In an embodiment, generating the first scanning signal may further include: maintaining the first scanning signal at a non-active level during the self-scanning period; and activating the second scanning signal during the self-scanning period so that the second pixel transistor is turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0034] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0035] Figure 2 It is shown Figure 1 Block diagram of the scan driving circuit shown in .

[0036] Figure 3 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0037] Figure 4 Is used to describe Figure 3 A timing diagram of the operation of a pixel is shown in FIG.

[0038] Figure 5 It is used to describe when the driving frequency is the first frequency Figure 3 A timing diagram of the operation of a pixel is shown in FIG.

[0039] Figure 6 It is used to describe when the driving frequency is the second frequency Figure 3 A timing diagram of the operation of a pixel is shown in FIG.

[0040] Figure 7 yes Figure 2 A block diagram of a first scan driving circuit is shown in FIG.

[0041] Figure 8 yes Figure 7 The circuit diagram of the driver stage is shown in .

[0042] Fig. 9 It is used to describe when the driving frequency is the first frequency Figure 8 The timing diagram of the operation of the driver stage is shown in FIG.

[0043] Fig.10 It is used to describe when the driving frequency is the second frequency Figure 8 The timing diagram of the operation of the driver stage is shown in FIG. DETAILED DESCRIPTION

[0044] In this specification, the statement that a first component (or region, layer, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is between the first component and the second component.

[0045] The same reference numerals / symbols refer to the same components. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for the effectiveness of the description of the technical contents.

[0046] The terms "first", "second", etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present invention, the first component may be referred to as the "second component", and similarly, the second component may be referred to as the "first component". The articles "a", "one", and "the" are singular because they have a single referent, but in this specification, the use of the singular form should not exclude the presence of more than one referent.

[0047] In addition, the terms "below", "under", "on", "over", etc. are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0048] It should be understood that the terms "include", "comprising", "having", etc. indicate the existence of the features, quantities, steps, operations, elements or components or combinations thereof described in this specification, but do not exclude the existence or additional possibility of one or more other features, quantities, steps, operations, elements or components or combinations thereof.

[0049] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formalized meaning.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0052] Reference Figure 1 , the display device DD includes a display panel DP, a driving controller 100 , a data driving circuit 200 , a scan driving circuit SDC, an emission driving circuit EDC, and a voltage generator 300 .

[0053] The driving controller 100 receives the input image signal RGB and the control signal CTRL. The driving controller 100 generates the output image signal DATA corresponding to the input image signal RGB. The driving controller 100 outputs the scanning control signal SCS, the data control signal DCS, the emission control signal (also called emission signal) ECS and the voltage control signal VCS.

[0054] The driving controller 100 according to an embodiment of the present disclosure may output the voltage control signal VCS according to driving frequency information included in the control signal CTRL.

[0055] The data driving circuit 200 receives the data control signal DCS and the output image signal DATA from the driving controller 100. The data driving circuit 200 converts the output image signal DATA into a data signal and then outputs the data signal to a plurality of data lines DL1, DL2, ... and DLm to be described later. m may be a positive integer.

[0056] The voltage generator 300 generates voltages required for the operation of the display device DD. In an embodiment, the voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, a first low voltage VGL1, and a discharge voltage VVF. In an embodiment, the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2 may be provided to the display panel DP, and the first low voltage VGL1 and the discharge voltage VVF may be provided to the scan driving circuit SDC.

[0057] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. n may be a positive integer.

[0058] The display panel DP may include a display area DA and a non-display area NDA. The pixel PX is disposed in the display area DA. The scan drive circuit SDC and the emission drive circuit EDC may be disposed in the non-display area NDA of the display panel DP. In an embodiment, the scan drive circuit SDC is disposed adjacent to a first side of the display area DA. The scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 extend from the scan drive circuit SDC along a second direction DR2.

[0059] The emission driving circuit EDC is disposed adjacent to the second side of the display area DA. The emission control lines EML1 to EMLn extend from the emission driving circuit EDC in a direction away from the second direction DR2.

[0060] Scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 and emission control lines EML1 to EMLn are arranged to be spaced apart from each other in a first direction DR1. Data lines DL1 to DLm extend from the data driving circuit 200 in the first direction DR1 and are arranged to be spaced apart from each other in a second direction DR2.

[0061] exist Figure 1 In the example shown in , the scan driving circuit SDC and the emission driving circuit EDC are arranged to face each other, and the pixel PX is interposed between the scan driving circuit SDC and the emission driving circuit EDC, but the present disclosure is not limited thereto. For example, the scan driving circuit SDC and the emission driving circuit EDC may be disposed adjacent to each other on the first side or the second side of the display area DA. In an embodiment, the scan driving circuit SDC and the emission driving circuit EDC may be implemented with one circuit.

[0062] The plurality of pixels PX are electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, the emission control lines EML1 to EMLn and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines and one emission control line. Figure 1 As shown in , the pixels PX belonging to the first row can be connected to the scan lines GIL1, GCL1, GWL1 and GWL2 and the emission control line EML1. In addition, the pixels PX belonging to the i-th row can be connected to the scan lines GILi, GCLi, GWLi and GWLi+1 and the emission control line EMLi. The pixels PX belonging to the n-th row can be connected to the scan lines GILn, GCLn, GWLn and GWLn+1 and the emission control line EMLn. i is a positive integer less than or equal to n.

[0063] Each of the plurality of pixels PX includes a light emitting element ED (see Figure 3 ) and a pixel circuit PXC (refer to Figure 3 ). The pixel circuit PXC may include one or more pixel transistors and one or more capacitors. The scan driving circuit SDC and the emission driving circuit EDC may include transistors formed by the same process as the pixel circuit PXC.

[0064] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1 , and a second initialization voltage VINT2 from the voltage generator 300 .

[0065] The scan driving circuit SDC receives a scan control signal SCS from the driving controller 100, and receives a discharge voltage VVF and a first low voltage VGL1 from the voltage generator 300. The scan driving circuit SDC may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 in response to the scan control signal SCS. A circuit configuration and operation of the scan driving circuit SDC will be described in detail later.

[0066] Figure 2 It is shown Figure 1 . Block diagram of the scan driving circuit SDC shown in FIG.

[0067] Reference Figure 2 The scan driving circuit SDC includes a first scan driving circuit SDR1, a second scan driving circuit SDR2 and a third scan driving circuit SDR3. In response to the scan control signal SCS, the first scan driving circuit SDR1 outputs a signal to be provided to the first scan driving circuit SDR1. Figure 1 In an embodiment, the first scan driving circuit SDR1 may operate in response to the discharge voltage VVF so that the scan signals GI1 to GIn are discharged. In response to the scan control signal SCS, the second scan driving circuit SDR2 outputs the scan signals to be provided to the scan lines GIL1 to GILn. Figure 1 In response to the scan control signal SCS, the third scan drive circuit SDR3 outputs the scan signals GC1, GC2, ... and GCn to be provided to the scan lines GCL1 to GCLn. Figure 1 , GWn and GWn+1 of the scanning lines GWL1 to GWLn+1 shown in FIG.

[0068] Figure 3 is a circuit diagram of a pixel PXij according to an embodiment of the present disclosure.

[0069] Reference Figure 3 , also refer to Figure 1 ,exist Figure 3 Pixels PXij are shown as examples, and pixels PXij are connected to data lines DL1 to DLm (refer to Figure 1 ) among the j-th data line DLj, the scanning lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 (refer to Figure 1 ) among the i-th scanning line GILi, GCLi and GWLi and the i+1-th scanning line GWLi+1 and the emission control lines EML1 to EMLn (refer to Figure 1 ) is an i-th emission control line EMLi. j is a positive integer less than or equal to m.

[0070] Figure 1Each of the plurality of pixels PX shown in FIG. Figure 3 The pixels PXij shown in have the same circuit configuration. In the display device DD according to the embodiment, the pixel PXij includes a pixel circuit PXC and at least one light emitting element ED. In the embodiment, the light emitting element ED may be an organic light emitting diode. The pixel circuit PXC includes a first pixel transistor T1, a second pixel transistor T2, a third pixel transistor T3, a fourth pixel transistor T4, a fifth pixel transistor T5, a sixth pixel transistor T6, and a seventh pixel transistor T7 and a capacitor Cst.

[0071] In an embodiment, the third pixel transistor T3 and the fourth pixel transistor T4 among the first pixel transistor T1 to the seventh pixel transistor T7 are N-type transistors using an oxide semiconductor as a semiconductor layer, and each of the first pixel transistor T1, the second pixel transistor T2, the fifth pixel transistor T5, the sixth pixel transistor T6, and the seventh pixel transistor T7 is a P-type transistor including a low temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, all of the first pixel transistor T1 to the seventh pixel transistor T7 may be P-type transistors or N-type transistors. In an embodiment, at least one of the first pixel transistor T1 to the seventh pixel transistor T7 may be an N-type transistor, and the other transistors of the first pixel transistor T1 to the seventh pixel transistor T7 may be P-type transistors. In addition, the circuit configuration of the pixel PXij according to the present disclosure is not limited to Figure 3 . Figure 3 The pixel circuit PXC shown in FIG. 1 is provided only as an example, and the configuration of the pixel circuit PXC may be variously modified and implemented.

[0072] The i-th scan line GILi, GCLi and GWLi may transmit the i-th scan signal GIi, GCi and GWi, respectively, and the i+1-th scan line GWLi+1 may transmit the i+1-th scan signal GWi+1. The i-th emission control line EMLi transmits the i-th emission control signal EMi, and the j-th data line DLj transmits the j-th data signal Dj. In the following description, the j-th data signal Dj is referred to as "data signal Dj", the j-th data line DLj is referred to as "data line DLj", the i-th scan line GILi, GCLi and GWLi are referred to as "scan lines GILi, GCLi and GWLi", the i+1-th scan line GWLi+1 is referred to as "scan line GWLi+1", the i-th emission control signal EMi is referred to as "emission control signal EMi", and the i-th emission control line EMLi is referred to as "emission control line EMLi".

[0073] The data signal Dj may have the same Figure 1) outputted output image signal DATA or a voltage level corresponding to a bias voltage. In this article, voltage level and level may have the same meaning. The bias voltage will be described in detail later. The first drive voltage line VL1, the second drive voltage line VL2, the third drive voltage line VL3 and the fourth drive voltage line VL4 may transmit the first drive voltage ELVDD, the second drive voltage ELVSS, the first initialization voltage VINT1 and the second initialization voltage VINT2, respectively.

[0074] The first pixel transistor T1 includes a first electrode electrically connected to the first driving voltage line VL1 through the fifth pixel transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth pixel transistor T6, and a gate electrode connected to the first end of the capacitor Cst. The first pixel transistor T1 can provide a current corresponding to the data signal Dj transmitted through the data line DLj to the light emitting element ED according to the switching operation of the second pixel transistor T2.

[0075] The second pixel transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first pixel transistor T1, and a gate electrode connected to the scan line GWLi. The second pixel transistor T2 can be turned on according to the scan signal GWi transmitted through the scan line GWLi, and can transmit the data signal Dj from the data line DLj to the first electrode of the first pixel transistor T1.

[0076] The third pixel transistor T3 includes a first electrode connected to the gate electrode of the first pixel transistor T1, a second electrode connected to the second electrode of the first pixel transistor T1, and a gate electrode connected to the scan line GCLi. The third pixel transistor T3 may be turned on according to the scan signal GCi transmitted through the scan line GCLi, and therefore, the gate electrode and the second electrode of the first pixel transistor T1 may be connected to each other, that is, the first pixel transistor T1 may be connected in a diode manner.

[0077] The fourth pixel transistor T4 includes a first electrode connected to the gate electrode of the first pixel transistor T1, a second electrode connected to the third driving voltage line VL3 transmitting the first initialization voltage VINT1, and a gate electrode connected to the scan line GILi. The fourth pixel transistor T4 can be turned on according to the scan signal GIi transmitted through the scan line GILi, and therefore, the first initialization voltage VINT1 can be transmitted to the gate electrode of the first pixel transistor T1. In this way, the voltage of the gate electrode of the first pixel transistor T1 can be initialized. This operation can be referred to as an "initialization operation".

[0078] The fifth pixel transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first pixel transistor T1, and a gate electrode connected to the emission control line EMLi.

[0079] The sixth pixel transistor T6 includes a first electrode connected to the second electrode of the first pixel transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission control line EMLi.

[0080] The fifth pixel transistor T5 and the sixth pixel transistor T6 may be turned on simultaneously according to the emission control signal EMi transmitted through the emission control line EMLi. As such, the first driving voltage ELVDD may be compensated by the diode-connected first pixel transistor T1 to be supplied to the light emitting element ED.

[0081] The seventh pixel transistor T7 includes a first electrode connected to the second electrode of the sixth pixel transistor T6, a second electrode connected to the fourth driving voltage line VL4, and a gate electrode connected to the scanning line GWLi+1. The seventh pixel transistor T7 is turned on according to the scanning signal GWi+1 transmitted through the scanning line GWLi+1, and bypasses the current of the anode of the light emitting element ED to the fourth driving voltage line VL4.

[0082] As described above, the first end of the capacitor Cst is connected to the gate electrode of the first pixel transistor T1, and the second end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The pixel PXij according to the embodiment is not limited to Figure 3 The circuit shown in . In the pixel PXij, the number of pixel transistors, the number of capacitors, and the connection relationship of the transistors and capacitors can be variously changed or modified.

[0083] Figure 4 Is used to describe Figure 3 The timing diagram of the operation of the pixel PXij shown in FIG. Figure 3 and Figure 4 The display device DD according to the embodiment is described (see Figure 1 ) operation.

[0084] Reference Figure 3 and Figure 4During the initialization period within one frame Fs, a high-level scan signal GIi is provided through the scan line GILi. When the fourth pixel transistor T4 is turned on in response to the high-level scan signal GIi, the first initialization voltage VINT1 is supplied to the gate electrode of the first pixel transistor T1 through the fourth pixel transistor T4. The gate electrode of the first pixel transistor T1 can be initialized with the first initialization voltage VINT1.

[0085] Next, when a high-level scan signal GCi is supplied through the scan line GCLi during the data programming and compensation period, the third pixel transistor T3 is turned on. The first pixel transistor T1 is connected in a diode manner through the third pixel transistor T3 thus turned on, and is forward biased. In this case, the second pixel transistor T2 is turned on by the low-level scan signal GWi. In this way, the compensation voltage obtained by subtracting the threshold voltage of the first pixel transistor T1 from the voltage of the data signal Dj supplied from the data line DLj is applied to the gate electrode of the first pixel transistor T1. That is, the gate voltage applied to the gate electrode of the first pixel transistor T1 can be the compensation voltage.

[0086] The first driving voltage ELVDD and the compensation voltage are respectively applied to opposite ends of the capacitor Cst, and charges corresponding to a voltage difference between the opposite ends of the capacitor Cst may be stored in the capacitor Cst.

[0087] At the same time, the seventh pixel transistor T7 is turned on in response to the low-level scan signal GWi+1 transmitted through the scan line GWLi+1. A portion of the current of the anode of the light emitting element ED may be discharged as a bypass current through the seventh pixel transistor T7.

[0088] Even in the case where the light emitting element ED emits light under the condition that the minimum current of the first pixel transistor T1 flows as a driving current for the purpose of displaying a black image, the black image may not be displayed normally. Therefore, the seventh pixel transistor T7 of the pixel PXij according to the embodiment of the present disclosure can cause a part of the minimum current of the first pixel transistor T1 to be discharged as a bypass current to a current path different from the current path to the light emitting element ED. Here, the minimum current of the first pixel transistor T1 means the current flowing under the condition that the gate-source voltage of the first pixel transistor T1 is less than the threshold voltage (that is, the first pixel transistor T1 is turned off). When the minimum driving current (for example, a current of 10pA or less) is transmitted to the light emitting element ED when the first pixel transistor T1 is turned off, an image of black brightness is expressed. When the minimum driving current for displaying a black image flows, the influence of the bypass transmission of the bypass current is large; in contrast, when a large driving current for displaying an image (such as a regular image or a white image) flows, the influence of the bypass current can be almost non-existent. Therefore, when the driving current for displaying a black image flows, the light emitting current of the light emitting element ED corresponding to the result of subtracting the bypass current discharged by the seventh pixel transistor T7 from the driving current can have a minimum current amount to the extent of accurately expressing a black image. Therefore, by accurately realizing an image of black brightness by using the seventh pixel transistor T7, the contrast can be improved. In an embodiment, the bypass signal for turning on the seventh pixel transistor T7 is a low-level scanning signal GWi+1, but the present disclosure is not limited thereto.

[0089] Next, during the emission period, the emission control signal EMi supplied from the emission control line EMLi changes from a high level to a low level. During the emission period, the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned on by the low-level emission control signal EMi. In this case, a driving current according to a voltage difference between a gate voltage of the gate electrode of the first pixel transistor T1 and the first driving voltage ELVDD is generated and supplied to the light emitting element ED through the sixth pixel transistor T6, and thus, the current flows through the light emitting element ED. Therefore, the light emitting element ED can emit light having a brightness corresponding to the current.

[0090] Figure 5 It is used to describe when the driving frequency is the first frequency Figure 3 The timing diagram of the operation of the pixel PXij shown in FIG. Figure 2 , Figure 3 and Figure 5 The display device DD according to the embodiment is described (see Figure 1 ) operation.

[0091] Reference Figure 2 , Figure 3 and Figure 5 , when the driving frequency is the first frequency (e.g., 120 Hz), the pixel PXij can operate sequentially from the 1st frame F1 to the 120th frame F120 (e.g., from the 1st frame F1, the 2nd frame F2, the 3rd frame F3, the 4th frame F4,..., the 119th frame F119 to the 120th frame F120).

[0092] The first scan driving circuit SDR1 of the scan driving circuit SDC responds to the drive controller 100 (refer to Figure 1 ) and outputs the scan signal GIi according to the start signal FLM_I included in the scan control signal SCS provided by the first frame F1. The start signal FLM_I may be transitioned to an active level (ie, a high level) in each of the first to 120th frames F1 to F120.

[0093] The second scan driving circuit SDR2 of the scan driving circuit SDC responds to the drive controller 100 (refer to Figure 1 ) outputs the scan signal GCi according to the start signal FLM_I included in the scan control signal SCS provided.

[0094] The third scan driving circuit SDR3 of the scan driving circuit SDC may respond to the drive controller 100 (refer to Figure 1 ) outputs the scanning signal GWi based on the scanning control signal SCS provided.

[0095] although Figure 5 The scan signal GCi is not shown in the figure, but the second scan driving circuit SDR2 of the scan driving circuit SDC may respond to the scan signal GCi from the driving controller 100 (refer to FIG. 1 ). Figure 1 ) provides a scan control signal SCS and outputs a scan signal GCi.

[0096] In the address period AP, when the scan signal GWi turns to a low level, the data signal Dj transmitted through the data line DLj may be provided to the first electrode of the first pixel transistor T1. The data signal Dj provided through the data line DLj in the address period AP may be the same as that provided by the drive controller 100 (refer to Figure 1 ) provides a signal corresponding to the output image signal DATA.

[0097] Each of the 1st to 120th frames F1 to F120 may be referred to as an address period AP or an effective period in which the data signal Dj is provided to the pixel PXij. Therefore, each of the 1st to 120th frames F1 to F120 may be the same as the address period AP.

[0098] Figure 6 It is used to describe when the driving frequency is the second frequency Figure 3 The timing diagram of the operation of the pixel PXij shown in FIG. Figure 2, Figure 3 and Figure 6 The display device DD according to the embodiment is described (see Figure 1 ) operation.

[0099] Reference Figure 2 , Figure 3 and Figure 6 , when the driving frequency is the second frequency (eg, 60 Hz), the pixels PXij may be sequentially operated from the 1st frame F1 to the 60th frame F60.

[0100] The first scan driving circuit SDR1 of the scan driving circuit SDC responds to the drive controller 100 (refer to Figure 1 ) and outputs the scan signal GIi according to the start signal FLM_I included in the scan control signal SCS provided by the first frame F1 to the sixth frame F60. The start signal FLM_I may be activated to a high level in each of the first to sixth frames F1 to F60.

[0101] Each of the 1st frame F1 to the 60th frame F60 may include an address period AP (or an effective period or a first mode) and a self-scan period SP (or a second mode). When the driving frequency is 60 Hz, in the address period AP of each of the 1st frame F1 to the 60th frame F60, the operation of the pixel PXij is the same as that in the address period AP of each of the 1st frame F1 to the 120th frame F120.

[0102] In the self-scanning period SP of each of the 1st frame F1 to the 60th frame F60, the scanning signal GIi may be maintained at an inactive level (i.e., a low level). In the self-scanning period SP, when the scanning signal GWi is converted to a low level, the data signal Dj transmitted through the data line DLj may be provided to the first electrode of the first pixel transistor T1. In the self-scanning period SP, the data signal Dj provided through the data line DLj may correspond to a bias signal for initializing the first electrode of the first pixel transistor T1.

[0103] Despite Figure 6 The scan signal GCi is not shown in the figure, but similar to the scan signal GIi, the scan signal GCi may transition to a high level once in the address period AP and may be maintained at an inactive level (ie, a low level) in the self-scan period SP.

[0104] Figure 7 yes Figure 2 A block diagram of a first scan driving circuit SDR1 is shown in FIG.

[0105] Reference Figure 7, the scan driving circuit SDC includes driving stages GID1, GID2, GID3, and GID4. Each of the driving stages GID1, GID2, GID3, and GID4 may include an input terminal IN, a first clock terminal CK1, a second clock terminal CK2, and an output terminal OUT.

[0106] The driving stages GID1, GID2, GID3, and GID4 output scanning signals GI1, GI2, GI3, and GI4 to the output terminal OUT in response to the scanning control signal SCS. The scanning signals GI1, GI2, GI3, and GI4 may be provided to Figure 1 The pixel PX shown in FIG. Figure 7 Only four driving stages GID1, GID2, GID3, and GID4 are shown, but the display panel DP (see FIG. Figure 1 ) determines the number of driving stages included in the scan driving circuit SDC. For example, when the pixels PX are arranged in n rows, the scan driving circuit SDC may include n driving stages.

[0107] The scan control signal SCS may include a start signal FLM_I and first, second, third, and fourth clock signals CLK1, CLK2, CLK3, and CLK4. Figure 7 4 shows an example in which the scan control signal SCS includes four clock signals (ie, a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4), but the present disclosure is not limited thereto.

[0108] The driving stage GID1 among the driving stages GID1 , GID2 , GID3 , and GID4 receives the start signal FLM_I through the input terminal IN.

[0109] The driving stages GID2, GID3 and GID4 receive the output of the previous driving stage, that is, the scanning signals GI1, GI2 and GI3, respectively. For example, the driving stage GID2 receives the scanning signal GI1 through the input terminal IN, the driving stage GID3 receives the scanning signal GI2 through the input terminal IN, and the driving stage GID4 receives the scanning signal GI3 through the input terminal IN.

[0110] Each of the driver stages GID1, GID2, GID3, and GID4 receives two corresponding clock signals among the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 through the first clock terminal CK1 and the second clock terminal CK2. For example, the driver stage GID1 may receive the first clock signal CLK1 and the second clock signal CLK2, the driver stage GID2 may receive the second clock signal CLK2 and the third clock signal CLK3, the driver stage GID3 may receive the third clock signal CLK3 and the fourth clock signal CLK4, and the driver stage GID4 may receive the fourth clock signal CLK4 and the first clock signal CLK1.

[0111] Each of the driving stages GID1 , GID2 , GID3 , and GID4 receives the first low voltage VGL1 and the discharge voltage VVF through the first and second voltage terminals VIN1 and VIN2 .

[0112] In an embodiment, Figure 2 The second scan drive circuit SDR2 shown in FIG. Figure 7 The first scan driving circuit SDR1 shown in FIG. 1 includes the same circuit configuration.

[0113] Figure 8 yes Figure 7 The circuit diagram of the driver stage GID1 is shown in .

[0114] Figure 7 The driver levels GID2, GID3 and GID4 shown in the figure can be used with Figure 8 The driver stage GID1 shown in FIG. 1 includes the same circuit configuration.

[0115] Reference Figure 8 The driving stage GID1 receives the start signal FLM_I through the input terminal IN, receives the first clock signal CLK1 and the second clock signal CLK2 through the first clock terminal CK1 and the second clock terminal CK2, and outputs the scan signal GI1 to the output terminal OUT. The driving stage GID1 receives the first low voltage VGL1 through the first voltage terminal VIN1, and receives the discharge voltage VVF through the second voltage terminal VIN2.

[0116] The driving stage GID1 includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, an eighth transistor ST8, a ninth transistor ST9, a tenth transistor ST10, an eleventh transistor ST11, and a twelfth transistor ST12, and a first capacitor C1, a second capacitor C2, and a third capacitor C3. In an embodiment, all of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, the eighth transistor ST8, the ninth transistor ST9, the tenth transistor ST10, the eleventh transistor ST11, and the twelfth transistor ST12 may be P-type transistors. However, the present disclosure is not limited thereto. Figure 8 The driving stage GID1 shown in is provided only as an example, and the circuit configuration of the driving stage GID1 may be variously modified and implemented.

[0117] In an embodiment, the first transistor ST1 , the tenth transistor ST10 , and the twelfth transistor ST12 may be referred to as an “input transistor,” an “output transistor,” and a “discharge control transistor,” respectively.

[0118] The first transistor ST1 and the eighth transistor ST8 are sequentially (i.e., connected in series) connected between the input terminal IN and the first node N1. The gate electrode of the first transistor ST1 is connected to the first clock terminal CK1, and the gate electrode of the eighth transistor ST8 is connected to the first voltage terminal VIN1. The second transistor ST2 is connected between the first electrode of the third capacitor C3 and the second clock terminal CK2, and includes a gate electrode connected to the second electrode of the third capacitor C3.

[0119] The third transistor ST3 is connected between the third node N3 and the first voltage terminal VIN1, and includes a gate electrode connected to the first clock terminal CK1. The fourth transistor ST4 is connected between the third node N3 and the fourth node N4, and includes a gate electrode connected to the first voltage terminal VIN1. The fifth transistor ST5 is connected between the first clock terminal CK1 and the third node N3, and includes a gate electrode connected to the sixth node N6. The sixth transistor ST6 is connected between the fifth node N5 and the second clock terminal CK2, and includes a gate electrode connected to the fourth node N4. The seventh transistor ST7 is connected between the fifth node N5 and the second node N2, and includes a gate electrode connected to the second clock terminal CK2. The ninth transistor ST9 is connected between the first clock terminal CK1 and the output terminal OUT, and includes a gate electrode connected to the second node N2. The tenth transistor ST10 is connected between the output terminal OUT and the first voltage terminal VIN1, and includes a gate electrode connected to the first node N1. The eleventh transistor ST11 is connected between the first clock terminal CK1 and the second node N2, and includes a gate electrode connected to the sixth node N6. The twelfth transistor ST12 is connected between the first node N1 and the second voltage terminal VIN2 , and includes a gate electrode connected to the second voltage terminal VIN2 .

[0120] The first capacitor C1 is connected between the first clock terminal CK1 and the second node N2. The second capacitor C2 is connected between the fourth node N4 and the fifth node N5. The third capacitor C3 includes a first electrode connected to the second transistor ST2 and a second electrode connected to the first node N1.

[0121] Fig. 9 It is used to describe when the driving frequency is the first frequency Figure 8 . A timing diagram of the operation of the driver stage GID1 is shown in FIG.

[0122] Reference Figure 8 and Fig. 9 , the driving frequency of the start signal FLM_I may be the first frequency. When the first frequency is 120 Hz, the frequency of each of the scanning signals GI1 and GI2 may be 120 Hz. Each of the scanning signals GI1 and GI2 may transition to a high level once in each of the first frame F1 and the second frame F2.

[0123] Because the first clock signal CLK1 is at a low level at the first time point P1 of the first frame F1, the first transistor ST1 can be turned on, and the high-level start signal FLM_I can be transmitted to the first node N1 through the first transistor ST1 and the eighth transistor ST8. When the signal of the first node N1 is at a high level, the fifth transistor ST5, the tenth transistor ST10 and the eleventh transistor ST11 remain in a cut-off state. In this case, the second node N2 can be maintained at a previous signal level (i.e., a low level) through the first capacitor C1. In this way, the low-level first clock signal CLK1 is output as a scan signal GI1 through the ninth transistor ST9. In addition, because the first clock signal CLK1 is at a low level, the third transistor ST3 can be turned on, and the first low voltage VGL1 can be transmitted to the third node N3 and the fourth node N4.

[0124] At the second time point P2, the first clock signal CLK1 changes from a low level to a high level, and therefore, the first transistor ST1 is turned off. In this case, when the second clock signal CLK2 is at a low level, the seventh transistor ST7 is turned on. Because the fifth node N5 is at a low level through the second capacitor C2 and the sixth transistor ST6, the second node N2 can be set to a low level. In this case, when the ninth transistor ST9 is turned on, the high-level first clock signal CLK1 can be output as a scan signal GI1 through the ninth transistor ST9.

[0125] At the third time point P3, because the first clock signal CLK1 is changed from a high level to a low level, the first transistor ST1 may be turned on, and the low level start signal FLM_I may be transmitted to the first node N1 through the first transistor ST1 and the eighth transistor ST8. Because the tenth transistor ST10 is turned on in response to the low level signal of the first node N1, the scan signal GI1 is changed to a low level (ie, the first low voltage VGL1).

[0126] Because the first node N1 is at a low level, the eleventh transistor ST11 can be turned on, and the low-level first clock signal CLK1 can be transmitted to the second node N2. The scan signal GI1 can even be discharged to the first clock terminal CK1 through the ninth transistor ST9. Therefore, the scan signal GI1 can be quickly discharged to a low level through the first clock terminal CK1 and the first voltage terminal VIN1.

[0127] At the fourth time point P4, because the start signal FLM_I is at a low level, the first node N1 can be maintained at a low level. In addition, when the second clock signal CLK2 is transformed to a low level at the fourth time point P4, the first node N1 can be set to a voltage level lower than the low level of the second clock signal CLK2 by the third capacitor C3. As a result, the voltage of the gate electrode of the tenth transistor ST10 (i.e., the voltage level of the first node N1) can be maintained at a sufficiently low voltage, and the tenth transistor ST10 can be maintained in a fully turned-on state. Therefore, the scan signal GI1 output to the output terminal OUT can be maintained at a low level (i.e., the first low voltage VGL1).

[0128] At the 2nd frame F2, the driving stage GID1 may operate the same as that in the 1st frame F1. When the driving frequency is the first frequency (eg, 120 Hz), each of the 1st frame F1 and the 2nd frame F2 may be an address period AP.

[0129] In an embodiment, when the driving frequency of the start signal FLM_I is a first frequency (e.g., 120 Hz), each of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 may be a pulse signal swinging between a high voltage VGH and a first low voltage VGL1.

[0130] When the driving frequency of the start signal FLM_I is the first frequency (eg, 120 Hz), Figure 1 The driving controller 100 shown in FIG. 1 may output a voltage control signal VCS so that the discharge voltage VVF is maintained at a high voltage VGH.

[0131] When the driving frequency of the start signal FLM_I is the first frequency (eg, 120 Hz), the twelfth transistor ST12 is maintained in a turned-off state while the discharge voltage VVF is maintained at the high voltage VGH.

[0132] Fig.10 It is used to describe when the driving frequency is the second frequency Figure 8 . A timing diagram of the operation of the driver stage GID1 is shown in FIG.

[0133] Reference Figure 8 and Fig.10 , the driving frequency of the start signal FLM_I may be the second frequency. When the second frequency is 60 Hz lower than the first frequency, the frequency of each of the scan signals GI1 and GI2 may be 60 Hz. When the driving frequency is the second frequency (e.g., 60 Hz), the first frame F1 may include an address period AP and a self-scan period SP. Each of the scan signals GI1 and GI2 may transition to a high level once in each of the address periods AP of the first frame F1.

[0134] The operation of the driving stage GID1 in the address period AP of the first frame F1 when the driving frequency is the second frequency (for example, 60 Hz) may be different from the operation of the driving stage GID1 in the address period AP of the first frame F1 when the driving frequency is the first frequency (for example, 120 Hz) (refer to Fig. 9 )same.

[0135] When the driving frequency is the second frequency (eg, 60 Hz), each of the first to fourth clock signals CLK1 , CLK2 , CLK3 , and CLK4 may be maintained at the high voltage VGH in the self-scan period SP of the first frame F1 .

[0136] When the driving frequency of the start signal FLM_I is the second frequency (for example, 60 Hz), Figure 1 The driving controller 100 shown in FIG. 1 may output the voltage control signal VCS so that the discharge voltage VVF is maintained at the high voltage VGH during the address period AP of the first frame F1 .

[0137] When the driving frequency of the start signal FLM_I is the second frequency (for example, 60 Hz), Figure 1 The driving controller 100 shown in FIG. 1 may output the voltage control signal VCS so that the discharge voltage VVF is maintained at the second low voltage VGL2 in the self-scan period SP of the first frame F1 .

[0138] When the discharge voltage VVF is maintained at the second low voltage VGL2, the twelfth transistor ST12 is maintained in the on state. When the twelfth transistor ST12 is turned on, the discharge voltage VVF as the second low voltage VGL2 is transmitted to the first node N1 through the twelfth transistor ST12.

[0139] Since the voltage of the first node N1 is maintained at a voltage level sufficient to turn on the tenth transistor ST10 (ie, maintained at the discharge voltage VVF), the scan signal GI1 may be maintained at the first low voltage VGL1.

[0140] In the self-scan period SP, even if all of the first, second, third, and fourth clock signals CLK1, CLK2, CLK3, and CLK4 are maintained at the high voltage VGH, the scan signal GI1 may be maintained at the first low voltage VGL1 through the tenth and twelfth transistors ST10 and ST12.

[0141] That is, during the self-scan period SP, the driving stage GID1 may maintain the scan signal GI1 at the first low voltage VGL1 in response to the discharge voltage VVF.

[0142] Since the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 are maintained at a given voltage level (eg, the high voltage VGH) without switching during the self-scan period SP, the power consumption in the driving stage GID1 can be minimized. Figure 2 . The power consumption of the display device DD of the scan driving circuit SDC shown in FIG.

[0143] According to the above configuration, the clock signal provided to the scan drive circuit during the self-scan period can be maintained at a given level without switching. Therefore, the power consumption of the scan drive circuit can be minimized. This can mean that the power consumption of the display device including the scan drive circuit is reduced.

[0144] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A scanning driving circuit, wherein: The scanning driving circuit comprises: an input transistor connected between an input terminal receiving the start signal and the first node, the input transistor including a gate electrode connected to a clock terminal; an output transistor connected between an output terminal outputting a scanning signal and a first voltage terminal, the output transistor including a gate electrode connected to the first node; and a discharge control transistor connected between the first node and a second voltage terminal, the discharge control transistor including a gate electrode connected to the second voltage terminal, wherein each of the second plurality of frames of the start signal comprises an addressing period and a self-scanning period, wherein, in the address period, the discharge voltage supplied to the second voltage terminal is a high voltage, and In the self-scan period, a voltage level of the discharge voltage is lower than a voltage level of the high voltage.

2. The scan driving circuit according to claim 1, wherein: In the address period, the clock signal supplied to the clock terminal is a signal switching between the high voltage and a first low voltage, and In the self-scan period, the clock signal is maintained at the high voltage.

3. The scan driving circuit according to claim 2, wherein: In the self-scan period, the discharge voltage is a second low voltage lower than the first low voltage.

4. The scan driving circuit according to claim 1, wherein: In the self-scan period, the output transistor and the discharge control transistor are maintained in an on state.

5. The scan driving circuit according to claim 1, wherein: In the self-scan period, the scan signal is maintained at a first low voltage.

6. The scan driving circuit according to claim 1, wherein: When the driving frequency of the start signal is the first frequency, each frame of the first plurality of frames includes the address period, and Wherein, when the driving frequency of the start signal is a second frequency lower than the first frequency, each of the second plurality of frames includes the address period and the self-scan period.

7. A display device, wherein: The display device comprises: Display panel, including pixels; a drive controller configured to receive an input image signal and output an output image signal; a data driving circuit configured to output a data signal corresponding to the output image signal; a scan driving circuit configured to provide a first scan signal to the pixel; and a voltage generator configured to provide a first low voltage and a discharge voltage in response to a voltage control signal, The driving controller provides the voltage control signal to the voltage generator and provides a start signal and a clock signal to the scan driving circuit, wherein the voltage control signal is used to select a voltage level of the discharge voltage. wherein each of the second plurality of frames of the start signal comprises an addressing period and a self-scanning period, wherein the discharge voltage is a high voltage in the address period and a second low voltage lower than the first low voltage in the self-scan period, The scanning driving circuit outputs the first scanning signal in response to the start signal, the clock signal and the discharge voltage, and In the self-scan period, the scan driving circuit maintains the first scan signal at the first low voltage in response to the discharge voltage.

8. The display device according to claim 7, wherein: The scanning driving circuit comprises: an input transistor connected between an input terminal receiving the start signal and the first node, the input transistor comprising a gate electrode connected to a clock terminal receiving the clock signal; an output transistor connected between an output terminal outputting the first scan signal and a first voltage terminal receiving the first low voltage, the output transistor including a gate electrode connected to the first node; and A discharge control transistor is connected between the first node and a second voltage terminal receiving the discharge voltage, and includes a gate electrode connected to the second voltage terminal.

9. The display device according to claim 8, wherein: In the address period, the clock signal supplied to the clock terminal is a signal that switches between the high voltage and the first low voltage, and In the self-scan period, the clock signal is maintained at the high voltage.

10. The display device according to claim 8, wherein: In the self-scan period, the discharge voltage is the second low voltage which is lower than the first low voltage.

11. The display device according to claim 8, wherein: In the self-scan period, the output transistor and the discharge control transistor are maintained in an on state.

12. The display device according to claim 7, wherein: When the driving frequency of the start signal is the first frequency, each frame of the first plurality of frames includes the address period, and Wherein, when the driving frequency of the start signal is a second frequency lower than the first frequency, each of the second plurality of frames includes the address period and the self-scan period.

13. The display device according to claim 7, wherein: The pixels include: Light emitting element; A first pixel transistor, comprising a first electrode, a second electrode and a gate electrode, wherein the second electrode of the first pixel transistor is connected to the light emitting element; a second pixel transistor connected between the first electrode of the first pixel transistor and a data line receiving the data signal, the second pixel transistor comprising a gate electrode receiving a second scanning signal different from the first scanning signal; and The third pixel transistor is connected between the gate electrode of the first pixel transistor and a voltage line receiving an initialization voltage, and the third pixel transistor includes a gate electrode receiving the first scanning signal.

14. A display device, wherein: The display device comprises: Display panel, including pixels; a scan driving circuit configured to provide a scan signal to the pixel; and an emission driving circuit configured to provide an emission signal to the pixel, Wherein, the pixels include: Light emitting element; A first pixel transistor, comprising a first electrode, a second electrode and a gate electrode, wherein the second electrode of the first pixel transistor is connected to the light emitting element; a second pixel transistor connected between the gate electrode of the first pixel transistor and a voltage line receiving an initialization voltage, the second pixel transistor comprising a gate electrode receiving the scan signal; and a third pixel transistor connected between a first driving voltage line receiving a first driving voltage and the first electrode of the first pixel transistor, the third pixel transistor comprising a gate electrode receiving the emission signal, Wherein, the scanning driving circuit comprises: an input transistor connected between an input terminal receiving the start signal and the first node, the input transistor including a gate electrode connected to a clock terminal; an output transistor connected between an output terminal outputting the scanning signal and a first voltage terminal, the output transistor including a gate electrode connected to the first node; and a discharge control transistor connected between the first node and a second voltage terminal, the discharge control transistor including a gate electrode connected to the second voltage terminal, wherein, in the first mode, each of the second pixel transistor and the third pixel transistor is turned on, and the discharge voltage supplied to the second voltage terminal is a high voltage, and Wherein, in the second mode, the second pixel transistor is turned off, the third pixel transistor is turned on, and the voltage level of the discharge voltage is lower than the voltage level of the high voltage.

15. The display device according to claim 14, wherein: In the second mode, the output transistor and the discharge control transistor are maintained in an on state.

16. The display device according to claim 14, wherein: In the second mode, the scan signal is maintained at a first low voltage.

17. The display device according to claim 16, wherein: In the first mode, the clock signal supplied to the clock terminal is a signal switching between the high voltage and the first low voltage, and Wherein, in the second mode, the clock signal is maintained at the high voltage.

18. A method for operating a display device, the display device comprising a scan drive circuit, wherein: The method comprises: Generate a start signal, a clock signal and a voltage control signal; generating a first low voltage and a discharge voltage in response to the voltage control signal; generating a first scan signal in response to the start signal, the clock signal, the first low voltage, and the discharge voltage; and displaying an image in response to the first scanning signal and the data signal, Each of the plurality of frames of the start signal includes an addressing period and a self-scanning period. wherein the discharge voltage is a high voltage in the address period and a second low voltage lower than the first low voltage in the self-scan period, and Wherein, the scanning driving circuit comprises: a discharge control transistor configured to maintain the first node at the discharge voltage during the self-scan period; and An output transistor is configured to discharge the first scan signal to the first low voltage in response to the discharge voltage of the first node.

19. The method according to claim 18, wherein: The generating the start signal, the clock signal and the voltage control signal comprises: generating the clock signal that swings between the high voltage and the first low voltage during the address period; and During the self-scan period, the clock signal is maintained at the high voltage.

Images