Chip packaging structure and method for preparing chip packaging structure

Abstract

The present invention provides a chip packaging structure and a method for preparing the chip packaging structure, and relates to the field of chip packaging technology. The chip packaging structure includes a base wiring layer, a first chip, a heat dissipation cover, a first heat dissipation adhesive layer, a packaging module and a solder ball, wherein the front of the first chip is attached to one side of the base wiring layer; the heat dissipation cover is arranged on the base wiring layer; the first heat dissipation adhesive layer is filled in the receiving groove of the heat dissipation cover; the packaging module includes a module substrate, a second chip, a third chip and a plastic package, wherein the back of the second chip is attached to the first heat dissipation adhesive layer, and the plastic package is arranged on the other side of the module substrate and covers the third chip. Compared with the prior art, the chip packaging structure provided by the embodiment of the present invention can greatly improve the heat dissipation effect, and there is no need to design an additional heat dissipation cover on the periphery, which reduces the device volume, and can reduce the parasitic effect and capacitance effect between the wiring layers, thereby improving the product performance.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a method for preparing the chip packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, chip packaging has emerged with double-sided packaging product structures or multi-chip packaging product structures. It mainly packages multiple chips on the front and back sides of the substrate to form a packaging structure. It usually adopts a flip chip structure and uses flip chip bumps to provide a higher density I / O layout. Compared with the traditional packaging form, its area can be reduced by 30% to 60%. With the increase in the number of integrated chips, its double-sided packaging products require greater heat dissipation performance to meet its performance requirements. At present, the heat dissipation of products is mostly carried out by using an external heat dissipation cover after the overall packaging. The heat dissipation cover is huge in size, which is not conducive to the miniaturization of the device and has poor heat dissipation performance. At the same time, the double-sided packaging substrate / substrate usually has a groove structure to mount the chip. For the substrate / substrate structure with double-sided grooves, the setting of the groove will lead to local thinning and reduce the wiring layer. The increase in the number of chips will lead to an increase in the number of wiring layers required for the substrate / substrate design. The conventional substrate / substrate structure is difficult to meet the wiring requirements and is prone to parasitic effects and capacitance effects between the wiring layers of the substrate / substrate, affecting its performance. Summary of the invention

[0003] The purpose of the present invention includes providing a chip packaging structure and a method for preparing the chip packaging structure, which can greatly improve the heat dissipation effect and does not require an additional heat dissipation cover to be designed on the periphery, thereby reducing the device volume and being able to reduce the parasitic effects and capacitance effects between wiring layers, thereby improving product performance.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a chip packaging structure, comprising:

[0006] Base wiring layer;

[0007] A first chip, wherein a front side of the first chip is attached to one side of the base wiring layer and is electrically connected to the base wiring layer;

[0008] A heat dissipation cover, the heat dissipation cover is arranged on the base wiring layer and covers the first chip, and a receiving groove is arranged on the heat dissipation cover, and the receiving groove corresponds to the back side of the first chip;

[0009] A first heat dissipation adhesive layer, which is filled in the receiving groove and bonded to the back side of the first chip;

[0010] A packaging module, the packaging module comprising a module substrate, a second chip, a third chip and a plastic package, wherein the front side of the second chip is attached to one side of the module substrate and is electrically connected to the module substrate, the back side of the second chip is attached to the first heat dissipation adhesive layer and is bonded to the first chip through the first heat dissipation adhesive layer, the third chip is attached to the other side of the module substrate, and the plastic package is arranged on the other side of the module substrate and covers the third chip;

[0011] A solder ball is disposed on a side of the base wiring layer away from the first chip.

[0012] In an optional embodiment, the accommodating groove passes through the heat dissipation cover, and the thickness of the first heat dissipation adhesive layer is the same as the depth of the accommodating groove.

[0013] In an optional embodiment, the back width of the first chip is the same as the back width of the second chip, and the opening width of the accommodating groove is the same as the back width of the first chip, so that the first heat dissipation adhesive layer covers the back of the first chip.

[0014] In an optional embodiment, the module substrate is spaced apart from the base wiring layer, and a first conductive column is provided on one side of the base wiring layer on which the first chip is attached. The first conductive column is correspondingly connected to the module substrate for supporting the module substrate, and the module substrate is electrically connected to the base wiring layer through the first conductive column.

[0015] In an optional embodiment, a boss portion is provided on the side of the module substrate facing away from the third chip, a first groove is formed on one side of the boss portion, the second chip is accommodated in the first groove, the first conductive column is staggered with the first groove and is correspondingly connected to the surface of the boss portion.

[0016] In an optional embodiment, a first positioning groove is provided on the boss portion, a first soldering pad is provided in the first positioning groove, and the first conductive column is correspondingly provided in the first positioning groove and connected to the first soldering pad.

[0017] In an optional embodiment, a second groove is further provided on the side of the module substrate facing away from the third chip, and the second groove is located on the side of the boss portion away from the first groove. A second conductive column is also provided on the side of the base wiring layer on which the first chip is attached, and a height of the second conductive column relative to the base wiring layer is greater than a height of the first conductive column relative to the base wiring layer. The second conductive column and the first chip are respectively arranged on both sides of the first conductive column, and the second conductive column corresponds to the second groove and is connected to the module substrate.

[0018] In an optional embodiment, a second positioning groove is provided in the second groove, a second soldering pad is provided in the second positioning groove, and the second conductive column is correspondingly provided in the second positioning groove and connected to the second soldering pad.

[0019] In an optional embodiment, the packaging module also includes a fourth chip, and a second groove is provided on the side of the module substrate facing away from the third chip, the second groove is located on the side of the boss portion away from the first groove, and the fourth chip is attached to the second groove, the front side of the fourth chip is attached to the module substrate, and a heat dissipation metal block is provided on the side of the base wiring layer on which the first chip is attached, the heat dissipation metal block and the first chip are respectively arranged on both sides of the first conductive column, and the heat dissipation metal block corresponds to the second groove and is connected to the back side of the fourth chip.

[0020] In an optional implementation, a second heat dissipation adhesive layer is provided on a side of the heat dissipation metal block facing away from the base wiring layer, and the heat dissipation metal block is bonded to the back side of the fourth chip through the second heat dissipation adhesive layer.

[0021] In an optional embodiment, a boss portion is provided on the side of the module substrate facing away from the third chip, a first groove is formed on one side of the boss portion, the second chip portion is partially fitted in the first groove and extends to fit to the boss portion, and the first conductive column is staggered with the first groove and is correspondingly connected to the surface of the boss portion.

[0022] In an optional implementation, a filling glue layer is further provided between the module substrate and the base wiring layer, and the filling glue layer covers the first conductive pillar, the first chip and the second chip.

[0023] In a second aspect, the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure as described in any one of the above embodiments, and the preparation method comprises:

[0024] Provide a carrier

[0025] forming a base wiring layer on the carrier;

[0026] Mounting a first chip on the base wiring layer, wherein the first chip is electrically connected to the base wiring layer;

[0027] A heat dissipation cover is provided on the base wiring layer, and the heat dissipation cover is provided on the first chip, wherein a receiving groove is provided on the heat dissipation cover, and the receiving groove corresponds to the back side of the first chip;

[0028] forming a first heat dissipation adhesive layer on the back side of the first chip, wherein the first heat dissipation adhesive layer is filled in the receiving groove;

[0029] Prepare a packaging module, the packaging module comprising a module substrate, a second chip, a third chip and a plastic package, the front side of the second chip is attached to one side of the module substrate and is electrically connected to the module substrate, the third chip is attached to the other side of the module substrate, and the plastic package is arranged on the other side of the module substrate and covers the third chip;

[0030] Mounting the packaging module on the back of the first chip, wherein the back of the second chip is attached to the first heat dissipation adhesive layer and bonded to the first chip through the first heat dissipation adhesive layer;

[0031] The carrier is removed, and solder balls are formed on a side of the substrate wiring layer away from the first chip.

[0032] In an optional implementation, before the step of mounting the packaging module on the back side of the first chip, the method further includes:

[0033] forming a first conductive column on one side of the base wiring layer;

[0034] forming a second conductive column on one side of the base wiring layer;

[0035] Among them, the second conductive column and the first chip are respectively located on both sides of the first conductive column, and the height of the second conductive column relative to the base wiring layer is greater than the height of the first conductive column relative to the base wiring layer, and the first conductive column and the second conductive column are used to be connected to the module substrate accordingly.

[0036] In an optional embodiment, before the step of mounting the packaging module on the back side of the first chip, the preparation method further includes:

[0037] forming a first conductive column on one side of the base wiring layer;

[0038] forming a heat dissipation metal block on one side of the base wiring layer;

[0039] The heat dissipation metal block and the first chip are respectively located on two sides of the first conductive column.

[0040] The chip packaging structure and the method for preparing the chip packaging structure provided by the embodiments of the present invention have the following beneficial effects:

[0041] The chip packaging structure and preparation method provided by the embodiment of the present invention are as follows: the first chip is flip-chip mounted on the base wiring layer, the heat dissipation cover is mounted on the first chip, and then the first heat dissipation adhesive layer is formed on the back of the first chip, the second chip in the packaging module is mounted on the first heat dissipation adhesive layer, and the second chip and the third chip are mounted on both sides of the module substrate respectively, and finally the third chip is plastic-sealed with a plastic package. On the one hand, since the heat dissipation cover is designed on the first chip, and the heat of the first chip and the second chip is transferred to the heat dissipation cover by the first heat dissipation adhesive layer at the same time, the heat dissipation capacity of the first chip and the second chip is greatly improved, and the heat dissipation cover is arranged inside the packaging structure, rather than outside, and the heat dissipation cover is designed with a receiving groove to accommodate the first heat dissipation adhesive layer, so the horizontal occupied area and occupied height of the heat dissipation cover can be reduced, and there is no need to design an additional heat dissipation cover outside the packaging structure, which is conducive to the miniaturization of the overall packaging structure. On the other hand, since the second chip and the third chip are arranged on the module substrate and the first chip is arranged on the base wiring layer, they can be wired separately, and the wiring area is wider, thereby reducing the parasitic effect and capacitance effect between the wiring layers, and improving the product performance. Compared with the prior art, the chip packaging structure provided by the embodiment of the present invention can greatly improve the heat dissipation effect, and there is no need to design an additional heat dissipation cover on the periphery, thereby reducing the device volume and being able to reduce the parasitic effects and capacitance effects between wiring layers, thereby improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A schematic structural diagram of a chip packaging structure provided by a first embodiment of the present invention;

[0044] Figures 2 to 11 A schematic diagram of a process flow of a method for preparing a chip packaging structure provided by a first embodiment of the present invention;

[0045] Fig.12 A schematic diagram of a chip packaging structure provided in accordance with a second embodiment of the present invention;

[0046] Figures 13 to 17 A schematic diagram of a process flow of a method for preparing a chip packaging structure provided by a second embodiment of the present invention;

[0047] Fig.18 A schematic structural diagram of a chip packaging structure provided by a third embodiment of the present invention;

[0048] Figures 19 to 22 A schematic diagram of the process flow of a method for preparing a chip packaging structure provided in the third embodiment of the present invention.

[0049] Icons: 100-chip packaging structure; 110-base wiring layer; 111-first conductive column; 112-second conductive column; 113-heat dissipation metal block; 114-second heat dissipation adhesive layer; 120-first chip; 130-heat dissipation cover; 131-accommodating groove; 140-first heat dissipation adhesive layer; 150-packaging module; 151-module substrate; 152-second chip; 153-third chip; 154-plastic package; 155-boss; 1551-first positioning groove; 1552-first solder pad; 156-first groove; 157-second groove; 1571-second positioning groove; 1572-second solder pad; 158-fourth chip; 160-solder ball; 170-filling adhesive layer; 200-carrier; 210-adhesive adhesive layer. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0053] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0054] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0055] As disclosed in the background technology, the existing multi-chip packaging technology usually requires a larger heat dissipation cover to be designed outside the packaging structure due to the high heat dissipation requirements. This design increases the package size (horizontally and vertically), making it difficult to miniaturize the overall package product. In addition, for multiple chips, especially double-sided mounted chips, the heat dissipation effect of the external heat dissipation cover is poor, and it is difficult to meet the heat dissipation requirements of the internal chips.

[0056] In addition, in conventional technology, multiple chips are mounted and wired using the same substrate / underlay, and grooves are usually designed on the substrate to accommodate the chips. The setting of the grooves will reduce the wiring area, and the increase in the number of chips will lead to an increase in the number of wiring layers of the substrate wiring layer. Therefore, conventional substrates are difficult to meet the wiring requirements, and parasitic effects and capacitance effects are likely to occur between the wiring layers of different lines, affecting product performance.

[0057] Furthermore, the double-sided mounted stacked chip structure in the prior art has a small stacking space, which makes it difficult to achieve chip stacking on one hand, and also makes the heat dissipation space small on the other hand, which is not conducive to improving the heat dissipation capacity.

[0058] In order to solve the above problems, an embodiment of the present invention provides a novel chip packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0059] First embodiment

[0060] See also Figure 1 The embodiment of the present invention provides a chip packaging structure 100, which can greatly improve the heat dissipation effect and does not need to design an additional heat dissipation cover 130 on the periphery, thereby reducing the device volume and reducing the parasitic effect and capacitance effect between wiring layers, thereby improving product performance.

[0061] The chip packaging structure 100 provided in the embodiment of the present invention includes a base wiring layer 110, a first chip 120, a heat dissipation cover 130, a first heat dissipation adhesive layer 140, a packaging module 150 and a solder ball 160. The front side of the first chip 120 is attached to one side of the base wiring layer 110 and is electrically connected to the base wiring layer 110. The heat dissipation cover 130 is arranged on the base wiring layer 110 and covers the first chip 120. The heat dissipation cover 130 is provided with a receiving groove 131, and the receiving groove 131 corresponds to the back side of the first chip 120. The first heat dissipation adhesive layer 140 is filled in the receiving groove 131 and is bonded to the first chip 120. The back side of the packaging module 150 includes a module substrate 151, a second chip 152, a third chip 153 and a plastic package 154. The front side of the second chip 152 is attached to one side of the module substrate 151 and is electrically connected to the module substrate 151. The back side of the second chip 152 is attached to the first heat dissipation adhesive layer 140 and is bonded to the first chip 120 through the first heat dissipation adhesive layer 140. The third chip 153 is attached to the other side of the module substrate 151. The plastic package 154 is arranged on the other side of the module substrate 151 and covers the third chip 153. The solder ball 160 is arranged on the side of the base wiring layer 110 away from the first chip 120.

[0062] In the present embodiment, the first chip 120, the second chip 152 and the third chip 153 are all flip chips, and the first chip 120 and the second chip 152 are mounted back to back and fixedly connected by the first heat dissipation adhesive layer 140. The chip packaging structure 100 provided in the present embodiment, on the one hand, because the heat dissipation cover 130 is designed on the first chip 120, and the first heat dissipation adhesive layer 140 simultaneously transfers the heat of the first chip 120 and the second chip 152 to the heat dissipation cover 130, the heat dissipation capacity of the first chip 120 and the second chip 152 is greatly improved, and the heat dissipation cover 130 is arranged inside the packaging structure, rather than outside, and the receiving groove 131 is designed on the heat dissipation cover 130 to accommodate the first heat dissipation adhesive layer 140, so that the horizontal occupied area and occupied height of the heat dissipation cover 130 can be reduced, and there is no need to additionally design the heat dissipation cover 130 outside the packaging structure, which is conducive to the miniaturization of the overall packaging structure. On the other hand, since the second chip 152 and the third chip 153 are arranged on the module substrate 151 and the first chip 120 is arranged on the base wiring layer 110, they can be wired separately, and the wiring area is wider, thereby reducing parasitic effects and capacitance effects between wiring layers and improving product performance.

[0063] In this embodiment, the receiving groove 131 penetrates the heat dissipation cover 130, and the thickness of the first heat dissipation adhesive layer 140 is the same as the depth of the receiving groove 131. Specifically, the receiving groove 131 corresponds to the back side of the first chip 120, so that the back side of the first chip 120 is configured as the bottom wall of the receiving groove 131, and the depth of the receiving groove 131 is the same as the thickness of the first heat dissipation adhesive layer 140, so that the first heat dissipation adhesive layer 140 can just fill the entire receiving groove 131, and ensure that the first heat dissipation adhesive layer 140 can contact with the back side of the first chip 120, and also ensure that the back side of the second chip 152 can be attached to the first heat dissipation adhesive layer 140.

[0064] In other preferred embodiments of the present invention, the thickness of the first heat dissipation adhesive layer 140 may also be greater than the depth of the accommodating groove 131, so that the first heat dissipation adhesive layer 140 can protrude from the heat dissipation cover 130, further ensuring that the back side of the second chip 152 is firmly attached to the first heat dissipation adhesive layer 140.

[0065] In this embodiment, the back width of the first chip 120 is the same as the back width of the second chip 152, and the opening width of the accommodating groove 131 is the same as the back width of the first chip 120, so that the first heat dissipation adhesive layer 140 covers the back of the first chip 120. Specifically, the first chip 120 and the second chip 152 are symmetrically arranged up and down, and the first heat dissipation adhesive layer 140 can cover the backs of the first chip 120 and the second chip 152 respectively, thereby ensuring the bonding and fixing effect between the first chip 120 and the second chip 152 and improving the thermal conductivity.

[0066] It should be noted that, in this embodiment, the first heat dissipation adhesive layer 140 can be in full contact with the heat dissipation cover 130, and the first heat dissipation adhesive layer 140 can be made of an adhesive material with good thermal conductivity. Since the thickness of the first heat dissipation adhesive layer 140 is the same as the depth of the receiving groove 131 on the heat dissipation cover 130, and the first heat dissipation adhesive layer 140, the first chip 120 and the second chip 152 are adapted in size, the first heat dissipation adhesive layer 140 can balance the stress of the first chip 120 and the second chip 152, and the heat dissipation between the stacked first chip 120 and the second chip 152 can be achieved through the heat dissipation cover 130, and the heat dissipation is achieved inside the packaging structure without the need to design an additional external heat dissipation structure.

[0067] In this embodiment, the base wiring layer 110 may include a multi-layer wiring structure, and its specific structure may refer to the multi-layer wiring layer structure in the prior art. In addition, the bottom of the third chip 153 may be filled with a glue layer, and the plastic package 154 may be completely covered outside the third chip 153 to play a protective role.

[0068] In this embodiment, the module substrate 151 is spaced apart from the base wiring layer 110, and a first conductive column 111 is further provided on one side of the base wiring layer 110 on which the first chip 120 is attached. The first conductive column 111 is correspondingly connected to the module substrate 151 and is used to support the module substrate 151, and the module substrate 151 is electrically connected to the base wiring layer 110 through the first conductive column 111. Specifically, the module substrate 151 is spaced apart from the base wiring layer 110, so there is enough stacking space to stack the first chip 120 and the second chip 152. The first conductive column 111 is located outside the first chip 120, and there may be a plurality of first conductive columns 111. By providing a plurality of first conductive columns 111, on the one hand, the electrical connection between the module substrate 151 and the base wiring layer 110 can be achieved, and on the other hand, the module substrate 151 can be supported by the plurality of first conductive columns 111 to ensure the stability of the structure.

[0069] Furthermore, a boss portion 155 is provided on one side of the module substrate 151 away from the third chip 153, a first groove 156 is formed on one side of the boss portion 155, the second chip 152 is accommodated in the first groove 156, the first conductive column 111 is staggered with the first groove 156, and is correspondingly connected to the surface of the boss portion 155. Specifically, by providing the first groove 156, the second chip 152 can be flip-chip arranged in the first groove 156, the second chip 152 can be accommodated, and the local thinning of the module substrate 151 is achieved. This design can thin the stack thickness in the vertical direction, help reduce the overall height of the package structure, and facilitate the miniaturization of the device.

[0070] It should be noted that, in actual preparation, the packaging module 150 in this embodiment can be prepared separately in advance, and the provision of the first groove 156 can also facilitate the positioning of the second chip 152 , thereby achieving rapid mounting of the second chip 152 .

[0071] In this embodiment, a first positioning groove 1551 is provided on the boss portion 155, a first solder pad 1552 is provided in the first positioning groove 1551, and the first conductive column 111 is correspondingly provided in the first positioning groove 1551 and connected to the first solder pad 1552. Specifically, the opening width of the first positioning groove 1551 is adapted to the width of the first conductive column 111. When the packaging module 150 is actually mounted, the first positioning groove 1551 and the first conductive column 111 can be aligned and mounted, so that the first conductive column 111 extends into the first positioning groove 1551 and is fixed by welding with the first solder pad 1552. During actual welding, the solder can be contained in the first positioning groove 1551. By providing the first positioning groove 1551, the welding reliability and welding area can be improved, and the desoldering situation can be avoided.

[0072] Furthermore, a second groove 157 is further provided on the side of the module substrate 151 away from the third chip 153, and the second groove 157 is located on the side of the boss portion 155 away from the first groove 156. A second conductive column 112 is further provided on the side of the base wiring layer 110 on which the first chip 120 is attached, and the height of the second conductive column 112 relative to the base wiring layer 110 is greater than the height of the first conductive column 111 relative to the base wiring layer 110. The second conductive column 112 and the first chip 120 are respectively provided on both sides of the first conductive column 111, and the second conductive column 112 corresponds to the second groove 157 and is connected to the module substrate 151. Specifically, there may be multiple second conductive columns 112, and the multiple second conductive columns 112 are all located on the side of the multiple first conductive columns 111 away from the first chip 120. By providing the second conductive columns 112, on the one hand, the module substrate 151 can be electrically connected to the base wiring layer 110, and on the other hand, the module substrate 151 can be supported.

[0073] It is worth noting that in this embodiment, by providing the second groove 157, the second groove 157 extends to the side wall of the module substrate 151, which can further thin the module substrate 151, and the second conductive column 112 is correspondingly welded on the module substrate 151 where the second groove 157 is located, so that the stacking gap space between the module substrate 151 and the base wiring layer 110 can be further expanded, the heat dissipation space can be increased, and the heat dissipation effect between the module substrate 151 and the base wiring layer 110 can be further improved. In addition, the second groove 157 and the first groove 156 are symmetrically distributed on both sides of the boss portion 155, which can balance the structural stress of the module substrate 151.

[0074] In this embodiment, a second positioning groove 1571 is provided in the second groove 157, a second pad 1572 is provided in the second positioning groove 1571, and the second conductive column 112 is correspondingly provided in the second positioning groove 1571 and connected to the second pad 1572. Specifically, the opening width of the second positioning groove 1571 is adapted to the width of the second conductive column 112. When the packaging module 150 is actually mounted, the second positioning groove 1571 and the second conductive column 112 can be aligned and mounted, so that the second conductive column 112 extends into the second positioning groove 1571 correspondingly and is fixed by welding with the second pad 1572. During actual welding, the solder can be contained in the second positioning groove 1571. By providing the second positioning groove 1571, the welding reliability and welding area of ​​the second conductive column 112 can be improved, and the desoldering situation can be avoided.

[0075] It should be noted that, in this embodiment, the first positioning groove 1551 and the second positioning groove 1571 can respectively partially accommodate the first conductive column 111 and the second conductive column 112, preferably half of the copper column, so that the first conductive column 111 and the second conductive column 112 can be protected, and the welding structure can be protected. In this embodiment, the first conductive column 111 and the second conductive column 112 can both be made of metal materials, such as copper columns, which can achieve the functions of electrical conduction and structural support on the one hand, and can also play the role of heat conduction and heat dissipation on the other hand. The first conductive column 111 and the second conductive column 112 can be directly formed on the dielectric layer of the base wiring layer 110, and connected to the wiring structure in the base wiring layer 110, so as to achieve electrical connection.

[0076] The embodiment of the present invention further provides a method for preparing a chip packaging structure 100, which is used to prepare the aforementioned chip packaging structure 100. The method comprises the following steps:

[0077] S1: Provide a carrier 200.

[0078] Specifically, see Figure 2 First, a carrier 200 can be provided. The carrier 200 can be made of metal, glass, silicon dioxide, silicon nitride, etc., and then an adhesive layer 210 can be coated on the surface of the carrier 200. The adhesive layer 210 can be a UV adhesive layer and can be peeled off in a subsequent process.

[0079] S2 : forming a base wiring layer 110 on the carrier 200 .

[0080] Specifically, see Figure 3 First, a metal layer is sputtered on the carrier 200, and then a dielectric layer is formed by a deposition process or a coating process. Then, a groove is made on the dielectric layer by an etching process. Then, the first wiring layer is prepared on the dielectric layer by a sputtering process. Then, the dielectric layer and the wiring layer are prepared in sequence to complete the preparation of multiple wiring layers. Finally, a base pad is formed on the dielectric layer.

[0081] S3 : forming a first conductive pillar 111 on one side of the base wiring layer 110 .

[0082] Specifically, see Figure 4 An opening can be made on the top dielectric layer of the base wiring layer 110, and then a layer of photoresist is coated, and then a groove is made on the photoresist through an etching process, so that the groove can expose the opening on the dielectric layer, and then a first conductive column 111 is formed by electroplating in the groove, and the first conductive column 111 is directly connected to the wiring structure in the base wiring layer 110.

[0083] S4 : forming a second conductive pillar 112 on one side of the base wiring layer 110 .

[0084] See also Figure 5 After forming the first conductive pillar 111, a layer of photoresist is coated again, and then a groove is made on the photoresist through an etching process, so that another opening on the dielectric layer is exposed, and then the second conductive pillar 112 is formed by electroplating in the groove. The second conductive pillar 112 is directly connected to the wiring structure in the base wiring layer 110, and the height of the second conductive pillar 112 relative to the base wiring layer 110 is greater than the height of the first conductive pillar 111 relative to the base wiring layer 110. The first conductive pillar 111 and the second conductive pillar 112 are used to be connected to the module substrate 151 accordingly. The first conductive pillar 111 and the second conductive pillar 112 are used to be connected to the module substrate 151 accordingly.

[0085] It should be noted that the first conductive pillar 111 and the second conductive pillar 112 are both copper pillars. When preparing the first conductive pillar 111 and the second conductive pillar 112, a mask plate can be set above the dielectric layer, and the dielectric layer can be chemically changed by using exposure and development technology. The exposed area is removed by using a developer to form an opening to leak the bottom circuit layer, and then titanium Ti, titanium / tungsten Ti / Wu and nickel Ni are electroplated in the opening by electroplating, and Snag is electroplated. Then, formic acid is refluxed to form a top solder ball, wherein formic acid is used as a reducing agent to remove oxides on the surface of the copper pillar bumps through high temperature and chemical reaction, thereby promoting the bonding strength between copper and solder.

[0086] S5 : mounting the first chip 120 on the base wiring layer 110 .

[0087] See also Figure 6 Specifically, the first chip 120 is electrically connected to the base wiring layer 110 , and the first chip 120 can be mounted on the base wiring layer 110 using a flip-chip process through chip mounting technology, and the first chip 120 and the second conductive column 112 are respectively located on both sides of the first conductive column 111 .

[0088] It should be noted that the chip mounting here uses the TCB hot pressing process, which applies a certain pressure at a relatively high temperature (for example, about 200°C to about 300°C). Through the TCB process, the flip chip and the pad are filled with non-conductive film (NCF), non-conductive paste (NCP), etc. for welding filling, so the flow of solder between the flip chip bumps and the pads can be reduced or minimized, thereby reducing or preventing defects such as short circuits, solder deformation, and non-wetting.

[0089] S6 : disposing a heat dissipation cover 130 on the base wiring layer 110 , and covering the first chip 120 with the heat dissipation cover 130 .

[0090] See also Figure 7, wherein a receiving groove 131 is provided on the heat dissipation cover 130, and the receiving groove 131 corresponds to the back side of the first chip 120. Specifically, the heat dissipation cover 130 can be prepared in advance. During the actual mounting, the legs of the heat dissipation cover 130 can be fixedly bonded to the surface of the base wiring layer 110, and then the receiving groove 131 on the heat dissipation cover 130 corresponds to the back side of the first chip 120, so that the back side of the first chip 120 can be exposed in the receiving groove 131.

[0091] S7 : forming a first heat dissipation adhesive layer 140 on the back side of the first chip 120 .

[0092] See also Figure 8 Specifically, the first heat dissipation adhesive layer 140 can be formed in the receiving groove 131 by a dispensing process or a coating process, wherein the first heat dissipation adhesive layer 140 is filled in the receiving groove 131 .

[0093] S8: preparing the packaging module 150 .

[0094] See also Fig. 9 Specifically, the packaging module 150 includes a module substrate 151, a second chip 152, a third chip 153 and a plastic package 154. The front side of the second chip 152 is attached to one side of the module substrate 151 and is electrically connected to the module substrate 151. The third chip 153 is attached to the other side of the module substrate 151. The plastic package 154 is arranged on the other side of the module substrate 151 and covers the third chip 153.

[0095] In actual preparation, a module substrate 151 may be provided first, with a boss portion 155 and a first groove 156 and a second groove 157 formed on one side of the module substrate 151, and then the boss portion 155 is set downward, and the third chip 153 is mounted on the side of the module substrate 151 away from the boss portion 155. The third chip 153 is a flip chip, and after the filling glue is dispensed, the module substrate 151 is plastic-sealed to form a plastic cover, and the plastic cover 154 can cover the third chip 153. Then the module substrate 151 is turned over, and the mounting of the second chip 152 is completed, and the second chip 152 is flipped and set in the first groove 156.

[0096] S9 : Mounting the packaging module 150 on the back side of the first chip 120 .

[0097] See also Fig.10, wherein the back side of the second chip 152 is attached to the first heat dissipation adhesive layer 140, and is bonded to the first chip 120 through the first heat dissipation adhesive layer 140. During actual mounting, the boss portion 155 of the package module 150 can be mounted downward on the base wiring layer 110, wherein the back side of the second chip 152 is attached to the first heat dissipation adhesive layer 140, so that the second chip 152 is attached to the first chip 120 through the first heat dissipation adhesive layer 140, and the first positioning groove 1551 on the boss portion 155 corresponds to the first conductive column 111, and the second positioning groove 1571 in the second groove 157 corresponds to the second conductive column 112, thereby completing the welding and fixing of the first conductive column 111 and the second conductive column 112.

[0098] S10 : removing the carrier 200 , and forming solder balls 160 on a side of the substrate wiring layer 110 away from the first chip 120 .

[0099] See also Fig.11 Specifically, after the carrier 200 is peeled off, the metal layer of the base wiring layer 110 is exposed, and then the solder balls 160 are formed on the metal layer through a ball planting process, and finally cut into single products.

[0100] To sum up, the chip packaging structure 100 and the preparation method thereof provided in this embodiment flip-chip mount the first chip 120 on the base wiring layer 110, and at the same time cover the first chip 120 with a heat dissipation cover 130, and then form a first heat dissipation adhesive layer 140 on the back of the first chip 120, and mount the second chip 152 in the packaging module 150 on the first heat dissipation adhesive layer 140, and the second chip 152 and the third chip 153 are respectively mounted on both sides of the module substrate 151, and finally the third chip 153 is plastic-encapsulated with a plastic encapsulation body 154. On the one hand, since the heat dissipation cover 130 is designed on the first chip 120, and the first heat dissipation adhesive layer 140 transfers the heat of the first chip 120 and the second chip 152 to the heat dissipation cover 130 at the same time, the heat dissipation capacity of the first chip 120 and the second chip 152 is greatly improved, and the heat dissipation cover 130 is arranged inside the packaging structure, rather than outside, and the heat dissipation cover 130 is designed with a receiving groove 131 to accommodate the first heat dissipation adhesive layer 140, so the horizontal occupied area and occupied height of the heat dissipation cover 130 can be reduced, and there is no need to design an additional heat dissipation cover 130 outside the packaging structure, which is conducive to the miniaturization of the overall packaging structure. On the other hand, since the second chip 152 and the third chip 153 are arranged on the module substrate 151, and the first chip 120 is arranged on the base wiring layer 110, they can be wired separately, and the wiring area is wider, thereby reducing the parasitic effect and capacitance effect between the wiring layers and improving the product performance. Compared with the prior art, the chip packaging structure 100 provided in the embodiment of the present invention can greatly improve the heat dissipation effect, and there is no need to design an additional heat dissipation cover 130 on the periphery, thereby reducing the device volume and being able to reduce the parasitic effect and capacitance effect between wiring layers, thereby improving product performance.

[0101] Second embodiment

[0102] See also Fig.12 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0103] In this embodiment, the packaging module 150 further includes a fourth chip 158. A second groove 157 is further provided on the side of the module substrate 151 away from the third chip 153. The second groove 157 is located on the side of the boss portion 155 away from the first groove 156. The fourth chip 158 is further provided in the second groove 157. The front surface of the fourth chip 158 is attached to the module substrate 151. A heat dissipation metal block 113 is further provided on the side of the base wiring layer 110 attached to the first chip 120. The heat dissipation metal block 113 and the first chip 120 are respectively provided on both sides of the first conductive column 111. The heat dissipation metal block 113 corresponds to the second groove 157 and is connected to the back surface of the fourth chip 158. Specifically, there is no direct electrical connection between the heat dissipation metal block 113 and the base wiring layer 110. The heat dissipation metal block 113 can be a copper block, which can play a good role in heat dissipation and structural support. The back surface of the fourth chip 158 is attached to the top surface of the heat dissipation metal block 113.

[0104] In this embodiment, a second heat dissipation adhesive layer 114 is provided on the side of the heat dissipation metal block 113 away from the base wiring layer 110, and the heat dissipation metal block 113 is bonded to the back side of the fourth chip 158 through the second heat dissipation adhesive layer 114. Specifically, the width of the heat dissipation metal block 113 can be greater than or equal to the width of the fourth chip 158 to ensure the structural support effect, and the width of the second heat dissipation adhesive layer 114 is the same as the width of the fourth chip 158. By providing the second heat dissipation adhesive layer 114, the heat generated by the fourth chip 158 can be quickly conducted to the heat dissipation metal block 113, thereby improving the heat dissipation effect.

[0105] The embodiment of the present invention further provides a method for preparing a chip packaging structure 100, the basic steps and principles and the technical effects produced by the method are the same as those of the first embodiment. For the sake of brief description, for the parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment. The preparation method provided in this embodiment includes the following steps:

[0106] S1: Provide a carrier 200.

[0107] S2 : forming a base wiring layer 110 on the carrier 200 .

[0108] S3 : forming a first conductive pillar 111 on one side of the base wiring layer 110 .

[0109] Among them, step S1 to step S3 are the same as those in the first embodiment.

[0110] S4 : mounting the first chip 120 on the base wiring layer 110 .

[0111] See also Fig.13Specifically, the first chip 120 can be mounted on the base wiring layer 110 by a flip-chip process through chip mounting technology, and the first chip 120 is located on one side of the first conductive column 111.

[0112] S5 : forming a heat dissipation metal block 113 on one side of the base wiring layer 110 .

[0113] See also Fig.14 Specifically, the heat dissipation metal block 113 prepared in advance can be bonded and fixed to the surface of the base wiring layer 110 through a bonding process, wherein the heat dissipation metal block 113 and the first chip 120 are respectively located on both sides of the first conductive column 111.

[0114] S6 : disposing a heat dissipation cover 130 on the base wiring layer 110 , and covering the first chip 120 with the heat dissipation cover 130 .

[0115] Step S5 and step S6 can be performed simultaneously. The heat dissipation cover 130 is provided with a receiving groove 131, and the receiving groove 131 corresponds to the back side of the first chip 120. Specifically, the heat dissipation cover 130 can be prepared in advance. During the actual mounting, the legs of the heat dissipation cover 130 can be fixedly bonded to the surface of the base wiring layer 110, and then the receiving groove 131 on the heat dissipation cover 130 is made to correspond to the back side of the first chip 120, so that the back side of the first chip 120 can be exposed in the receiving groove 131.

[0116] S7 : forming a first heat dissipation adhesive layer 140 on the back side of the first chip 120 .

[0117] S8: preparing the packaging module 150 .

[0118] See also Fig.15 Specifically, the package module 150 includes a module substrate 151, a second chip 152, a third chip 153, a fourth chip 158 and a plastic package 154. The front surface of the second chip 152 is attached to one side of the module substrate 151 and is electrically connected to the module substrate 151. The third chip 153 is attached to the other side of the module substrate 151. The plastic package 154 is disposed on the other side of the module substrate 151 and covers the third chip 153. A boss portion 155 is disposed on one side of the module substrate 151. A first groove 156 and a second groove 157 are formed on both sides of the boss portion 155. The second chip 152 is mounted in the first groove 156. The fourth chip 158 is also mounted in the second groove 157.

[0119] In actual preparation, a module substrate 151 may be provided first, with a boss portion 155 and a first groove 156 and a second groove 157 formed on one side of the module substrate 151, and then the boss portion 155 is set downward, and the third chip 153 is mounted on the side of the module substrate 151 away from the boss portion 155. The third chip 153 is a flip chip, and after dispensing glue to form a filling glue, the module substrate 151 is plastic-sealed to form a plastic cover, and the plastic cover 154 can cover the outside of the third chip 153. Then the module substrate 151 is turned over, and the mounting of the second chip 152 and the fourth chip 158 is completed. The second chip 152 is flipped and set in the first groove 156, and the fourth chip 158 is flipped and set in the second groove 157.

[0120] S9 : Mounting the packaging module 150 on the back side of the first chip 120 .

[0121] See also Fig.16 , wherein the back side of the second chip 152 is attached to the first heat dissipation adhesive layer 140, and is bonded to the first chip 120 through the first heat dissipation adhesive layer 140, and the back side of the fourth chip 158 is attached to the second heat dissipation adhesive layer 114, and is bonded to the heat dissipation metal block 113 through the second heat dissipation adhesive layer 114. During the actual mounting, the boss portion 155 of the package module 150 can be mounted downward on the base wiring layer 110, wherein the back side of the second chip 152 is attached to the first heat dissipation adhesive layer 140, so that the second chip 152 is attached to the first chip 120 through the first heat dissipation adhesive layer 140, and the back side of the fourth chip 158 is attached to the second heat dissipation adhesive layer 114, so that the fourth chip 158 is attached to the heat dissipation metal block 113 through the second heat dissipation adhesive layer 114, and the first positioning groove 1551 on the boss portion 155 corresponds to the first conductive column 111, and the first conductive column 111 is welded and fixed.

[0122] S10 : removing the carrier 200 , and forming solder balls 160 on a side of the substrate wiring layer 110 away from the first chip 120 .

[0123] See also Fig.17The chip packaging structure 100 and the preparation method thereof provided by the embodiment of the present invention are as follows: the first chip 120 is flip-chip mounted on the base wiring layer 110, and the heat dissipation cover 130 is covered on the first chip 120, and then a first heat dissipation adhesive layer 140 is formed on the back of the first chip 120, and the second chip 152 in the packaging module 150 is mounted on the first heat dissipation adhesive layer 140, and the second chip 152 and the third chip 153 are respectively mounted on both sides of the module substrate 151, and finally the third chip 153 is plastic-encapsulated with a plastic encapsulation body 154. On the one hand, since the heat dissipation cover 130 is designed on the first chip 120, and the first heat dissipation adhesive layer 140 transfers the heat of the first chip 120 and the second chip 152 to the heat dissipation cover 130 at the same time, the heat dissipation capacity of the first chip 120 and the second chip 152 is greatly improved, and the heat dissipation cover 130 is arranged inside the packaging structure, rather than outside, and the heat dissipation cover 130 is designed with a receiving groove 131 to accommodate the first heat dissipation adhesive layer 140, so the horizontal occupied area and occupied height of the heat dissipation cover 130 can be reduced, and there is no need to design an additional heat dissipation cover 130 outside the packaging structure, which is conducive to the miniaturization of the overall packaging structure. On the other hand, since the second chip 152 and the third chip 153 are arranged on the module substrate 151, and the first chip 120 is arranged on the base wiring layer 110, they can be wired separately, and the wiring area is wider, thereby reducing the parasitic effect and capacitance effect between the wiring layers, and improving the product performance. At the same time, the design of the heat dissipation metal block 113 also further improves the heat dissipation and support effects.

[0124] Third embodiment

[0125] See also Fig.18 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0126] In this embodiment, a boss portion 155 is provided on one side of the module substrate 151 away from the third chip 153, a first groove 156 is formed on one side of the boss portion 155, the second chip 152 is partially fitted in the first groove 156, and extends to fit to the boss portion 155, the first conductive column 111 is staggered with the first groove 156, and is correspondingly connected to the surface of the boss portion 155. Specifically, the second chip 152 can form a bridge chip, directly electrically connecting the first pad 1552 on the boss portion 155 with the chip pad in the first groove 156, thereby eliminating the electrical interconnection line layer inside the module substrate 151 and reducing parasitic effects.

[0127] Specifically, the module substrate 151 is thinned due to the first groove 156, which leads to a reduction in the internal wiring space, which is not conducive to using high-density chips to improve performance and difficult to form a wiring layer structure stacking module. Here, the second chip 152 is used as a bridge chip, which can replace the role of a part of the electrical connection line layer, reduce the wiring pressure of the module substrate 151, improve the performance and transmission performance of the stacked chips, and reduce the parasitic effects between the wiring layers.

[0128] In this embodiment, a filling glue layer 170 is further provided between the module substrate 151 and the base wiring layer 110, and the filling glue layer 170 covers the first conductive pillar 111, the first chip 120 and the second chip 152. Specifically, the structures of the first conductive pillar 111 and the second conductive pillar 112 are the same as those in the first embodiment, and the filling glue layer 170 can completely cover the first conductive pillar 111, the second conductive pillar 112, the first chip 120 and the second chip 152. When dispensing glue, a dispensing glue channel can be formed between the first conductive pillar 111 and the second conductive pillar 112, and the fluidity of the colloid is improved by capillary action, thereby improving the filling performance.

[0129] In addition, in this embodiment, the distance between the module substrate 151 and the base wiring layer 110 is not the same on the left and right sides. For example, the opening width at the second groove 157 is smaller than the opening width at the first groove 156. At the same time, combined with the setting of the boss portion 155, the contact area between the filling glue layer 170 and the module substrate 151 is increased, which greatly improves the bonding force between the filling glue layer 170 and the module substrate 151.

[0130] The embodiment of the present invention further provides a method for preparing a chip packaging structure 100, the basic steps of which are the same as those of the first embodiment, that is, steps S1 to S7 can refer to the first embodiment, except that the packaging module 150 in this embodiment is prepared separately and cut into a single structure. The preparation method further includes the following steps:

[0131] S8: preparing the packaging module 150 .

[0132] See also Fig.19In actual preparation, a module substrate 151 may be provided first, with a boss portion 155 and a first groove 156 and a second groove 157 formed on one side of the module substrate 151, and then the boss portion 155 is set downward, and the third chip 153 is mounted on the side of the module substrate 151 away from the boss portion 155. The third chip 153 is a flip chip, and after the filling glue layer 170 is formed by dispensing glue, a plastic cover body is formed on the module substrate 151, and the plastic cover body 154 can cover the outside of the third chip 153. Then the module substrate 151 is turned over, and the mounting of the second chip 152 is completed. The second chip 152 is flipped and set in the first groove 156, and extended to the boss portion 155, and finally cut into single products.

[0133] S9: Mounting a plurality of package modules 150 on the base wiring layer 110 at intervals.

[0134] See also Fig. 20 Specifically, the back of the second chip 152 is attached to the first heat dissipation adhesive layer 140, and is bonded to the first chip 120 through the first heat dissipation adhesive layer 140. During actual mounting, the boss portion 155 of the package module 150 can be mounted downward on the base wiring layer 110, wherein the back of the second chip 152 is attached to the first heat dissipation adhesive layer 140, so that the second chip 152 is attached to the first chip 120 through the first heat dissipation adhesive layer 140, and the first positioning groove 1551 on the boss portion 155 corresponds to the first conductive column 111, and the second positioning groove 1571 in the second groove 157 corresponds to the second conductive column 112, thereby completing the welding and fixing of the first conductive column 111 and the second conductive column 112.

[0135] S10 : dispensing glue on the base wiring layer 110 to form a filling glue layer 170 .

[0136] See also Fig.21 Here, the packaging module 150 is an independent module structure and is distributed at intervals, so glue can be dispensed through the gaps. During glue dispensing, the colloid improves the filling performance due to the capillary action of the first conductive column 111 and the second conductive column 112, and forms a filling glue layer 170 after curing.

[0137] S11 : removing the carrier 200 , and forming solder balls 160 on a side of the substrate wiring layer 110 away from the first chip 120 .

[0138] See also Fig. 22 Specifically, after the carrier 200 is peeled off, the metal layer of the base wiring layer 110 is exposed, and then the solder balls 160 are formed on the metal layer through a ball planting process, and finally cut into single products.

[0139] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: Base wiring layer; A first chip, wherein a front side of the first chip is attached to one side of the base wiring layer and is electrically connected to the base wiring layer; a heat dissipation cover, the heat dissipation cover is arranged on the base wiring layer and covers the first chip, and a receiving groove is arranged on the heat dissipation cover, and the receiving groove corresponds to the back side of the first chip; A first heat dissipation adhesive layer, which is filled in the receiving groove and bonded to the back side of the first chip; A packaging module, the packaging module comprising a module substrate, a second chip, a third chip and a plastic package, wherein the front side of the second chip is attached to one side of the module substrate and is electrically connected to the module substrate, the back side of the second chip is attached to the first heat dissipation adhesive layer and is bonded to the first chip through the first heat dissipation adhesive layer, the third chip is attached to the other side of the module substrate, and the plastic package is arranged on the other side of the module substrate and covers the third chip; A solder ball, wherein the solder ball is arranged on a side of the base wiring layer away from the first chip; Among them, the module substrate is spaced apart from the base wiring layer, and a first conductive column is also provided on the side of the base wiring layer on which the first chip is attached. The first conductive column is correspondingly connected to the module substrate and is used to support the module substrate, and the module substrate is electrically connected to the base wiring layer through the first conductive column; a boss portion is provided on the side of the module substrate facing away from the third chip, a first groove is formed on one side of the boss portion, the second chip is accommodated in the first groove, and the first conductive column is staggered with the first groove and is correspondingly connected to the surface of the boss portion.

2. The chip packaging structure according to claim 1, characterized in that: The containing groove passes through the heat dissipation cover, and the thickness of the first heat dissipation adhesive layer is the same as the depth of the containing groove.

3. The chip packaging structure according to claim 2, characterized in that: The back width of the first chip is the same as the back width of the second chip, and the opening width of the accommodating groove is the same as the back width of the first chip, so that the first heat dissipation adhesive layer covers the back of the first chip.

4. The chip packaging structure according to claim 1, characterized in that: The boss portion is provided with a first positioning groove, a first pad is provided in the first positioning groove, and the first conductive column is correspondingly provided in the first positioning groove and connected to the first pad.

5. The chip packaging structure according to claim 1, characterized in that: A second groove is further provided on the side of the module substrate away from the third chip, and the second groove is located on the side of the boss portion away from the first groove. A second conductive column is further provided on the side of the base wiring layer on which the first chip is attached, and a height of the second conductive column relative to the base wiring layer is greater than a height of the first conductive column relative to the base wiring layer. The second conductive column and the first chip are respectively arranged on both sides of the first conductive column, and the second conductive column corresponds to the second groove and is connected to the module substrate.

6. The chip packaging structure according to claim 5, characterized in that: A second positioning groove is disposed in the second groove, a second pad is disposed in the second positioning groove, and the second conductive column is correspondingly disposed in the second positioning groove and connected to the second pad.

7. The chip packaging structure according to claim 1, characterized in that: The packaging module also includes a fourth chip, and a second groove is provided on the side of the module substrate facing away from the third chip, the second groove is located on the side of the boss portion away from the first groove, and the fourth chip is attached to the second groove, the front side of the fourth chip is attached to the module substrate, and a heat dissipation metal block is provided on the side of the base wiring layer on which the first chip is attached, the heat dissipation metal block and the first chip are respectively arranged on both sides of the first conductive column, and the heat dissipation metal block corresponds to the second groove and is connected to the back side of the fourth chip.

8. The chip packaging structure according to claim 7, characterized in that: A second heat dissipation adhesive layer is provided on a side of the heat dissipation metal block away from the base wiring layer, and the heat dissipation metal block is bonded to the back side of the fourth chip through the second heat dissipation adhesive layer.

9. The chip packaging structure according to claim 1 or 5, characterized in that: A boss portion is provided on the side of the module substrate facing away from the third chip, a first groove is formed on one side of the boss portion, the second chip portion is partially fitted in the first groove and extends to fit to the boss portion, the first conductive column is staggered with the first groove and is correspondingly connected to the surface of the boss portion.

10. The chip packaging structure according to claim 9, characterized in that: A filling glue layer is further arranged between the module substrate and the base wiring layer, and the filling glue layer covers the first conductive column, the first chip and the second chip.

11. A method for preparing a chip packaging structure, used for preparing the chip packaging structure according to any one of claims 1 to 10, characterized in that: The preparation method comprises: Provide a carrier forming a base wiring layer on the carrier; Mounting a first chip on the base wiring layer, wherein the first chip is electrically connected to the base wiring layer; A heat dissipation cover is provided on the base wiring layer, and the heat dissipation cover is provided on the first chip, wherein a receiving groove is provided on the heat dissipation cover, and the receiving groove corresponds to the back side of the first chip; forming a first heat dissipation adhesive layer on the back side of the first chip, wherein the first heat dissipation adhesive layer is filled in the receiving groove; Prepare a packaging module, the packaging module comprising a module substrate, a second chip, a third chip and a plastic package, the front side of the second chip is attached to one side of the module substrate and is electrically connected to the module substrate, the third chip is attached to the other side of the module substrate, and the plastic package is arranged on the other side of the module substrate and covers the third chip; Mounting the packaging module on the back of the first chip, wherein the back of the second chip is attached to the first heat dissipation adhesive layer and bonded to the first chip through the first heat dissipation adhesive layer; The carrier is removed, and solder balls are formed on a side of the substrate wiring layer away from the first chip.

12. The method for preparing a chip packaging structure according to claim 11, characterized in that: Before the step of mounting the packaging module on the back side of the first chip, the method further comprises: forming a first conductive column on one side of the base wiring layer; forming a second conductive column on one side of the base wiring layer; The height of the second conductive pillar relative to the base wiring layer is greater than the height of the first conductive pillar relative to the base wiring layer, and the first conductive pillar and the second conductive pillar are used to be connected to the module substrate accordingly.

13. The method for preparing a chip packaging structure according to claim 12, characterized in that: Before the step of mounting the packaging module on the back side of the first chip, the preparation method further comprises: forming a first conductive column on one side of the base wiring layer; A heat dissipation metal block is formed on one side of the base wiring layer.

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