Chip components

Abstract

The present invention provides a chip assembly, comprising: a chip, a first bonding area is arranged on the chip; an enlarged structure is arranged to overlap with the first bonding area, the enlarged structure comprises an insulating substrate and a second bonding area arranged on the insulating substrate, the second bonding area is conductively connected to the first bonding area, and the area of ​​the second bonding area is larger than the area of ​​the first bonding area. The technical solution of the present application effectively solves the problem of difficult operation of the bonding process in the related art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power device packaging, and in particular to a chip assembly. Background Art

[0002] In the design and manufacture of power devices, the connection between the bonding area on the chip surface (such as the gate area) and the external circuit is achieved through interconnection components such as bonding wires or conductive tapes. In order to maximize the current flow capacity of the chip, the design tends to expand the source area, which inevitably compresses the size of the bonding area. Although the reduction of the bonding area is conducive to improving the electrical performance of power devices, there are still the following problems:

[0003] 1. The difficulty of bonding process operation increases: The small bonding area limits the operating space of wire bonding, increases the difficulty of bonding process operation, and limits the wire diameter selection of bonding wires, thereby affecting the electrical parameters of power devices, such as parasitic inductance and resistance.

[0004] 2. Risk of mechanical damage: Wire bonding directly on the chip surface can easily cause mechanical damage to the bonding area, affecting the chip packaging quality and the long-term reliability of the power device.

[0005] 3. Limited heat dissipation performance: The small bonding area limits the effective area of ​​the heat dissipation path. In high-power applications, good heat dissipation is critical to the performance and life of power devices. Summary of the invention

[0006] The main purpose of the present invention is to provide a chip assembly to solve the problem of difficult bonding process operation in the related art.

[0007] In order to achieve the above-mentioned purpose, the present invention provides a chip component, including: a chip, on which a first bonding area is arranged; an enlarged structure, which is arranged to overlap with the first bonding area, and the enlarged structure includes an insulating substrate and a second bonding area arranged on the insulating substrate, the second bonding area is conductively connected to the first bonding area, and the area of ​​the second bonding area is larger than the area of ​​the first bonding area.

[0008] Furthermore, the second bonding area is conductively connected to the first bonding area through the conductive sheet.

[0009] Furthermore, the chip assembly also includes a heat sink conductively connected to the second bonding area.

[0010] Furthermore, the heat sink includes a heat dissipation column vertically or obliquely conductively connected to the second bonding area.

[0011] Furthermore, a first heat dissipation channel is provided on the heat dissipation element.

[0012] Furthermore, the first heat dissipation channel includes a heat dissipation through hole provided through the side wall of the heat dissipation element.

[0013] Furthermore, the heat sink comprises a heat dissipation column, and there are a plurality of heat dissipation through holes, and the plurality of heat dissipation through holes are radially and spaced apart on the heat dissipation column.

[0014] Furthermore, there are a plurality of first heat dissipation channels, and the plurality of first heat dissipation channels are arranged at intervals along the direction in which the enlarged structure overlaps the first bonding area.

[0015] Furthermore, the first heat dissipation channel includes a heat dissipation ring groove extending along the circumference of the heat dissipation element.

[0016] Furthermore, the heat sink includes a carrier core conductively connected to the second bonding area and a second heat dissipation channel surrounding the outside of the carrier core.

[0017] Furthermore, the heat sink includes a heat sink body conductively connected to the second bonding area and a conductive platform conductively connected to the upper end surface of the heat sink body.

[0018] Furthermore, the chip assembly also includes a conductive member conductively connected to the heat sink and an insulating member surrounding an edge of the conductive member.

[0019] Furthermore, the chip assembly also includes a conductive member conductively connected to the heat sink, and in the direction in which the expanded structure overlaps the first bonding area, the conductive member is located on the side of the heat sink away from the insulating substrate. The chip assembly also includes an enclosure connected to the insulating substrate and the conductive member, the enclosure is arranged on the outside of the heat sink, a third heat dissipation channel is arranged between the enclosure and the heat sink, and an air inlet and an air outlet connected to the third heat dissipation channel are arranged on the enclosure.

[0020] Furthermore, there are a plurality of first bonding regions arranged at intervals, a fracture is arranged on the surface of the insulating substrate facing the first bonding region, and a portion between two adjacent first bonding regions corresponds to the fracture.

[0021] Furthermore, the enlarged structure is connected to the chip via a connecting sheet.

[0022] Furthermore, the chip assembly also includes a substrate for carrying the chip, the substrate has a conductive layer, and the chip is fixed on the conductive layer.

[0023] Furthermore, a thickened portion is provided on the insulating substrate, and the thickened portion is fixed on the conductive layer.

[0024] The technical solution of the present invention is applied, and the chip assembly includes: a chip and an enlarged structure. A first bonding area is provided on the chip. The enlarged structure is arranged to overlap with the first bonding area, so that the size of the first bonding area on the original chip surface is not directly changed, so that the mature and available chip can continue to be used, and the bonding process can be operated by using the external enlarged structure. The enlarged structure includes an insulating substrate and a second bonding area arranged on the insulating substrate, the second bonding area is conductively connected to the first bonding area, and the insulating substrate insulates the second bonding area and the chip to prevent short circuit. The area of ​​the second bonding area is larger than the area of ​​the first bonding area. The above-mentioned second bonding area can increase the area of ​​the first bonding area. The second bonding area with a larger area allows the use of a larger wire diameter welding wire or a wider conductive belt for further conductive connection to the outside, which reduces the difficulty of the bonding process operation, reduces the parasitic parameters of the power device, and optimizes the electrical performance. In addition, the second bonding area with a larger area makes the connection of the welding wire or the conductive belt-shaped component more stable, reduces the damage of the bonding process to the chip surface, and improves the packaging yield. Moreover, the setting of the second bonding area with a larger area allows the actual bonding position of the bonding wire to be adjusted, and the design can be optimized according to the chip and auxiliary circuit layout, thereby improving the flexibility and efficiency of the overall device design. Therefore, the technical solution of the present application effectively solves the problem of difficult bonding process operation in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0026] Figure 1 A schematic diagram of the exploded structure of a chip assembly according to a first embodiment of the present invention is shown;

[0027] Figure 2 Shows Figure 1 A schematic diagram of the three-dimensional structure of a chip component;

[0028] Figure 3 Shows Figure 1 A schematic diagram of a three-dimensional structure of a chip assembly and an expanded structure viewed from an upward angle;

[0029] Figure 4 A schematic diagram of the exploded structure of the second embodiment of the chip assembly according to the present invention is shown, wherein a heat sink is additionally provided compared to the first embodiment of the chip assembly;

[0030] Figure 5 A schematic diagram of the exploded structure of the third embodiment of the chip assembly according to the present invention is shown, wherein compared with the second embodiment of the chip assembly, a first heat dissipation channel is provided on the heat dissipation element;

[0031] Figure 6 Shows Figure 5 A vertical cross-sectional schematic diagram of a first embodiment of a heat sink of a chip assembly, wherein a first heat dissipation channel passes through a side wall of the heat sink;

[0032] Figure 7 Shows Figure 5 A schematic transverse cross-sectional view of a first embodiment of a heat sink for a chip assembly;

[0033] Figure 8 Shows Figure 5 A vertical cross-sectional schematic diagram of a second embodiment of a heat sink for a chip assembly, wherein the heat sink has a load-bearing core inside;

[0034] Fig. 9 Shows Figure 5 A schematic transverse cross-sectional view of a second embodiment of a heat sink for a chip assembly;

[0035] Fig.10 A schematic diagram of the exploded structure of a fourth embodiment of the chip assembly according to the present invention is shown, wherein compared with the second embodiment of the chip assembly, the heat sink includes a heat sink body and a conductive platform;

[0036] Fig.11 A schematic diagram of the exploded structure of the fifth embodiment of the chip assembly according to the present invention is shown, wherein, compared with the second embodiment of the chip assembly, a conductive member and an insulating member are additionally provided;

[0037] Fig.12 A schematic diagram of the exploded structure of the sixth embodiment of the chip assembly according to the present invention is shown, wherein, compared with the fifth embodiment of the chip assembly, an enclosure is additionally provided;

[0038] Fig.13 Shows Fig.12 A schematic transverse cross-sectional view of the enclosure and heat sink of a chip assembly.

[0039] The above drawings include the following reference numerals:

[0040] 10. chip; 11. first bonding area; 12. substrate;

[0041] 20. enlarged structure; 21. insulating substrate; 211. fracture; 212. thickened portion; 22. second bonding area; 23. conductive sheet; 24. connecting sheet;

[0042] 30. heat sink; 31. heat sink column; 32. first heat dissipation channel; 321. heat dissipation through hole; 33. load-bearing core; 34. second heat dissipation channel; 35. heat dissipation body; 36. conductive platform;

[0043] 41. Conductive parts; 42. Insulating parts; 43. Enclosure; 431. Air inlet; 432. Air outlet. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0046] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0047] like Figures 1 to 3 As shown, the present application provides a chip assembly, and the first embodiment of the chip assembly includes: a chip 10 and an expansion structure 20. A first bonding area 11 is arranged on the chip 10. The expansion structure 20 is arranged to overlap with the first bonding area 11, so that the size of the first bonding area on the surface of the original chip is not directly changed, so that the mature and usable chip can continue to be used, and the bonding process can be operated using the additional expansion structure. The expansion structure 20 includes an insulating substrate 21 and a second bonding area 22 arranged on the insulating substrate 21, the second bonding area 22 is conductively connected to the first bonding area 11, and the area of ​​the second bonding area 22 is larger than the area of ​​the first bonding area 11.

[0048] According to the technical solution of the first embodiment of the chip assembly, the second bonding area 22 is arranged on the insulating substrate 21, and the insulating substrate 21 insulates the second bonding area 22 and the chip 10 to prevent short circuit. At the same time, the area of ​​the second bonding area 22 is larger than the area of ​​the first bonding area 11. The above-mentioned setting of the second bonding area 22 can increase the area of ​​the first bonding area 11. The second bonding area 22 with a larger area allows the use of a larger wire diameter welding wire or a wider conductive belt for further external conductive connection, which reduces the difficulty of the bonding process operation, and also reduces the parasitic parameters of the power device, such as resistance and inductance, and optimizes the electrical performance. In addition, the second bonding area 22 with a larger area makes the connection of the welding wire or the conductive belt-shaped component more stable, reduces the damage of the bonding process to the surface of the chip 10, and improves the packaging yield. Moreover, the setting of the second bonding area 22 with a larger area allows the actual bonding position of the welding wire to be adjusted, and the design is optimized according to the chip 10 and the auxiliary circuit layout, which improves the flexibility and efficiency of the overall device design. Therefore, the technical solution of the first embodiment of the chip assembly effectively solves the problem of difficult bonding process operation in the related art. The insulating substrate 21 is preferably made of ceramic.

[0049] It should be noted that the overlapping arrangement of the enlarged structure 20 and the first bonding area 11 means that in a direction perpendicular to the first bonding area 11 , the projection of the enlarged structure 20 on the first bonding area 11 overlaps the first bonding area 11 .

[0050] The above-mentioned enlarged structure 20 is overlapped with the first bonding area 11, and has a larger area of ​​the second bonding area 22. Different from the existing literature that directly changes the size of the first bonding area, the enlarged structure of the present application does not directly change the size of the first bonding area 11 on the surface of the original chip, so that mature and usable chips can continue to be used, and the second bonding area 22 of the additional enlarged structure is used to facilitate the operation of the bonding process.

[0051] Furthermore, the bonding process of the second bonding area 22 with an additional enlarged structure proposed in the present application does not directly act on the chip surface, thereby avoiding additional damage to the chip gate caused by bonding stress and improving the packaging yield.

[0052] In addition, the second bonding area 22 of the enlarged structure makes the actual bonding area position of the wire bond adjustable, and a comprehensive and reasonable design can be performed according to the overall chip layout and auxiliary circuit layout, thereby improving the flexibility of the chip layout and auxiliary circuit layout, which is beneficial to improving the production efficiency and service reliability of power devices.

[0053] Moreover, after using the second bonding area 22 of the expanded structure, the actual bonding area area of ​​the wire can be designed to be larger than the area of ​​the original first bonding area 11 on the chip surface, thereby increasing the allowable upper limit of the bonding wire specification, so that the user can reasonably customize the selection of the bonding wire specification and the area of ​​the second bonding area 22 of the bonding area expansion structure according to the overall situation of the interconnection.

[0054] Therefore, the use of the second bonding area 22 with an enlarged structure not only improves the reliability of bonding and reduces signal attenuation, but also provides a more stable electrical connection for chip components. This design is particularly suitable for high-heat load application scenarios such as high-performance computing, artificial intelligence, and data centers. By optimizing heat dissipation and current management, the service life of the chip is extended and maintenance costs are reduced.

[0055] The ratio of the area of ​​the second bonding area 22 to the area of ​​the first bonding area 11 is a real number greater than 1, and can be between 1 and 51, specifically determined according to the size of the space allowed for the installation of the chip component and the size of the space required for the interconnection of the chip components.

[0056] like Figures 1 to 3 As shown, the second bonding area 22 is conductively connected to the first bonding area 11 through the conductive sheet 23. The use of the conductive sheet 23 increases the electrical connection stability between the bonding areas. Compared with direct bonding wire connection, the conductive sheet has a larger contact area, which can reduce the connection resistance and improve the current transmission efficiency. When subjected to bonding pressure, the local stress of the chip 10 is more dispersed, reducing chip damage.

[0057] The above-mentioned conductive sheet 23 not only serves as a connection medium, but also plays the role of current and signal transmission. The selection of its thickness and material has a direct impact on the electrical and thermal properties of the chip components. In practical applications, the thickness of the conductive sheet 23 is usually between 0.1 mm and 1 mm, and the material is preferably a metal with good electrical and thermal conductivity, such as copper or aluminum. Among them, using copper as the material of the conductive sheet can significantly reduce thermal resistance and improve heat conduction efficiency, which is particularly important for high-speed computing chips. It can help reduce heat accumulation and avoid performance degradation or hardware damage caused by overheating.

[0058] Specifically, there are three first bonding areas 11 arranged at intervals, two of which are the first Kelvin source and the second Kelvin source, respectively, and the remaining one of the three first bonding areas 11 is the gate; there are two conductive sheets 23 arranged at intervals, and there is one connecting sheet 24, and the two conductive sheets 23 correspond to the first Kelvin source and the gate, respectively, and are in contact with each other for conduction; the second Kelvin source corresponds to the connecting sheet 24, and is in contact with each other for connection. There are two second bonding areas 22 arranged at intervals, and the two second bonding areas 22 are conductively connected to the two conductive sheets 23 in a one-to-one correspondence.

[0059] The first bonding area 11 is three As arranged at intervals, and the three As are recorded as A1, A2 and A3 in sequence. A1 and A3 are both Kelvin sources, and A2 is a gate. Only one A (A1) of these two As (A1 and A3) needs to be electrically connected to the outside. In addition, the gate referred to by A2 also needs to be connected to the outside. The conductive sheet 23 is arranged at intervals from the connecting sheet 24 described below, and there are two conductive sheets 23 arranged at intervals. The two conductive sheets 23 and one connecting sheet 24 together form three Bs, and the three Bs are recorded as B1, B2 and B3 in sequence, where two conductive sheets 23 are two Bs (B1 and B2), and one connecting sheet 24 is one B (B3). B1, B2 and B3 correspond to A1, A2 and A3 in sequence. However, among the three Bs (B1, B2 and B3), only two Bs (B1 and B2) actually play the role of electrical conduction, that is, corresponding to A1 and A2 (1 Kelvin source, 1 gate); B3 is only connected to A3, but there is no current conduction between the two. B3 is used as the connection surface between the interconnection expansion structure and the chip surface, aiming to increase the interconnection area between the interconnection expansion structure and the chip surface, and increase the overall interconnection interface strength between the interconnection expansion structure and the chip. The second bonding area 22 is two spaced apart, both recorded as C, and the two Cs are the actual expansion of A1 and A2 used.

[0060] In other embodiments, only two Bs ( B1 and B2 ) may be reserved on the interconnection expansion structure to be connected to the two used As ( A1 and A2 ).

[0061] B1, B2 and B3 can be called interconnection surfaces of the interconnection expansion structure, and the two Cs are called expanded interconnection surfaces. Only two Bs (B1 and B2) are electrically connected to the two Cs, and they are electrically conductive inside the interconnection area expansion structure. For example, two Bs (B1 and B2) correspond to two Cs one by one, and each B (B1 or B2) and each C are two surfaces of a simple integrally formed conductive sheet. Specifically, the upper surface of the sheet is C, the lower surface of the sheet is B, and the area of ​​C is greater than the area of ​​B.

[0062] like Figures 1 to 3As shown, in the first embodiment of the chip assembly, the first bonding area 11 is arranged in multiple intervals, and a break 211 is arranged on the surface of the insulating substrate 21 facing the first bonding area 11, and the portion between two adjacent first bonding areas 11 corresponds to the break 211. This design can effectively isolate the two adjacent first bonding areas 11, avoid the conductive penetration between different bonding areas, and avoid the mutual interference of signals and currents, thereby improving the electrical performance of the chip assembly. If the break 211 is not provided, when the interconnection expansion structure and the chip surface are connected by melting and resolidifying the solder, the solder is easy to make A1 and A2 conductive, and A2 and A3 conductive. The width and depth of the break 211 should be precisely controlled according to the requirements of electrical isolation. Usually, the width of the break 211 is between 0.2mm and 1mm, and the depth of the break 211 does not exceed 0.5mm, so as to ensure the electrical isolation effect while avoiding mechanical damage to the insulating substrate 21 during service.

[0063] Specifically, the first bonding area 11 is composed of three A's arranged at intervals, and the three A's are sequentially recorded as A1, A2 and A3. In order to avoid conductive connection between A1 and A2, and to avoid conductive connection between A2 and A3, the parts between A1 and A2, and between A2 and A3 are all made of insulating materials to ensure that A1 and A2, and between A2 and A3 are not electrically connected to each other.

[0064] like Figures 1 to 3 As shown, the expansion structure 20 is connected to the chip 10 through a connecting piece 24. The connecting piece 24 serves as an intermediary between the interconnection expansion structure and the chip surface, and is intended to increase the interconnection area between the interconnection expansion structure and the chip surface, and to increase the overall interconnection interface strength between the interconnection expansion structure and the chip. The connecting piece 24 is the above-mentioned B3.

[0065] like Figures 1 to 3 As shown, the chip assembly further includes a substrate 12 carrying the chip 10 . The substrate 12 has a conductive layer, and the chip 10 is fixed on the conductive layer.

[0066] like Figures 1 to 3 As shown, a thickened portion 212 is provided on the insulating base 21, and the thickened portion 212 is fixed on the conductive layer. The thickened portion 212 is fixed on the conductive layer, which increases the contact area between the enlarged structure 20 and the substrate 12, improves the structural stability, and the thickened portion can serve as an additional thermal resistance buffer to optimize the overall thermal management.

[0067] The thickened portion 212 can be interconnected to the conductive layer by welding (solder melting and then solidifying) technology; or, bonding can be used directly.

[0068] like Figure 4As shown, in the second embodiment of the chip assembly, the chip assembly further includes a heat sink 30 conductively connected to the second bonding area 22. Adding the heat sink 30 can significantly improve the heat dissipation capacity of the power device, help reduce the temperature of the device during operation, and extend the life of the device.

[0069] like Figure 4 As shown, the heat sink 30 includes a heat sink 31 vertically or obliquely conductively connected to the second bonding area 22. The design of the heat sink 31 makes the heat dissipation path more direct and effective, and the vertical connection method can optimize the heat dissipation structure layout, adapt to different packaging design requirements, and further improve the heat dissipation efficiency.

[0070] Of course, in an embodiment not shown in the drawings, the heat sink includes a heat sink column obliquely and conductively connected to the second bonding region.

[0071] The length and diameter of the heat dissipation column 31 can be adjusted according to the heat output of the chip. Generally speaking, the length of the heat dissipation column 31 ranges from 1 mm to 10 mm, and the diameter of the heat dissipation column 31 ranges from 0.5 mm to 2 mm. For example, the diameter of the heat dissipation column 31 is 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.5 mm, 1.8 mm, or 2 mm. The design of the heat dissipation column 31 not only enhances the heat conduction of the chip assembly, but also improves the effect of natural or forced convection heat dissipation by increasing the surface area.

[0072] The second bonding area 22 is integrated with the heat sink 30 , which not only forms an electrical connection with the second bonding area 22 , but is also provided with a vertical heat sink 31 , which effectively increases the heat dissipation area and improves the heat conduction efficiency.

[0073] like Figure 4 As shown, the welding wire can be bonded to the upper surface of the heat dissipation column 31, so as to facilitate further external electrical connection using the welding wire bonding process on the heat dissipation column 31.

[0074] Specifically, when a wire bonding process is used on the second bonding area 22 to perform further external electrical connection and heat dissipation needs to be further improved, a plurality of heat dissipation columns 31 may be preferably arranged in an array on the second bonding area 22 .

[0075] like Figures 5 to 7 As shown, in the third embodiment of the chip assembly and in the first embodiment of the heat sink, a first heat dissipation channel 32 is provided on the heat sink 30. The first heat dissipation channel 32 is provided to allow gas or other cooling medium to flow therein, thereby taking away heat. This heat dissipation method is similar to wind-guided heat dissipation, and can provide a better heat dissipation effect when there is fluid flow.

[0076] The term "plurality" in this application refers to a number of two or more.

[0077] like Figures 5 to 7 As shown, the first heat dissipation channel 32 includes a heat dissipation through hole 321 that passes through the side wall of the heat dissipation element 30. The through heat dissipation through hole 321 formed inside or on the side of the heat dissipation element 30 can increase the contact area between the heat dissipation element 30 and the outside world, accelerate the transfer of heat, and the heat dissipation through hole 321 can also serve as a flow path for fluid such as coolant or gas to improve heat dissipation performance.

[0078] The diameter of the heat dissipation through holes 321 is between 0.1 mm and 0.5 mm, and the number of the heat dissipation through holes 321 may be as many as dozens to hundreds to ensure uniformity and efficiency of heat dissipation.

[0079] like Figures 4 to 7 As shown, the heat sink 30 includes a heat sink column 31, and a plurality of heat dissipation through holes 321, which are radially arranged at intervals on the heat sink column 31. The radial layout of the plurality of heat dissipation through holes 321 can evenly dissipate heat, avoid local overheating, and improve the heat dissipation uniformity of the heat sink 30.

[0080] If the load on the heat sink 31 is small during the subsequent process or the service life of the power device, such as the pressure in the bonding process, the heat dissipation hole 321 adopts a simple through-hole shape. The hole shape can be a simple circle or other suitable curve shape as long as it can facilitate heat dissipation.

[0081] The uniform distribution of the heat dissipation through holes 321 can form an effective heat dissipation network, which can keep the chip temperature within a safe range even under high-load working conditions. This design is particularly suitable for fields such as mobile devices and smart wearable devices that have strict requirements on volume and weight. Through tiny and dense through holes, a balance between heat dissipation and miniaturization is achieved.

[0082] like Figure 5 As shown, there are multiple first heat dissipation channels 32, and the multiple first heat dissipation channels 32 are arranged at intervals along the direction in which the enlarged structure 20 overlaps the first bonding area 11. The design of multiple first heat dissipation channels 32 can provide multi-path heat transfer, and can effectively manage heat even in high-power and high-density packaging scenarios.

[0083] In other embodiments, the first heat dissipation channel 32 includes a heat dissipation annular groove extending along the circumference of the heat dissipation element 30. The annular groove increases the heat conduction efficiency of the heat dissipation element 30 in the circumferential direction, helps to diffuse heat laterally, reduces heat concentration, and improves heat dissipation performance.

[0084] like Figure 5 , Figure 8 and Fig. 9As shown, in the third embodiment of the chip assembly and in the second embodiment of the heat sink, the heat sink 30 includes a carrier core 33 conductively connected to the second bonding area 22 and a second heat dissipation channel 34 surrounding the outside of the carrier core 33. The carrier core 33 is combined with the heat dissipation column to enhance the rigidity of the heat sink in its length direction, and the second heat dissipation channel 34 further optimizes the heat dissipation path and improves the heat dissipation efficiency.

[0085] Specifically, if the load on the heat sink 30 is large, such as the pressure in the bonding process, during the subsequent process or the service of the power device, and if the heat sink 30 has a small stiffness in the length direction, the upper surface of the heat sink 30 will have a large displacement during wire bonding, the interface interconnection effect will be poor, and the interface will be unreliable. In order to avoid this situation, the bearing core 33 must have a large stiffness in the direction of its busbar to ensure the stability of the component on the heat sink 30, and further ensure the stable implementation of the related processes involved. At the same time, in order to ensure the heat dissipation function of the heat sink 30, a second heat dissipation channel 34 is arranged around the outside of the bearing core 33. The bearing core 33 is a column, preferably a cylinder.

[0086] In the above structure, a bearing core 33 with a smaller cross-sectional area is retained inside the heat sink 30, and the second heat dissipation channel 34 does not penetrate the bearing core 33 radially, and only forms a number of annular channels around the bearing core 33, and there are four annular channels separately along the busbar direction of the bearing core 33, which ensures a better heat dissipation effect of the heat sink 30. In addition, the part with the annular channel on the outside provides good lateral support for the bearing core 33 with a smaller cross-sectional area inside, greatly improving the ability of the relatively slender bearing core 33 inside to resist compression instability during the process and service, and ensuring the stability and reliability of the heat sink 30 in the subsequent process and the service process of the power device. Similarly, the pattern of the second heat dissipation channel 34 can also be other suitable curves.

[0087] like Fig.10 As shown, in the fourth embodiment of the chip assembly, the heat sink 30 includes a heat sink body 35 conductively connected to the second bonding area 22 and a conductive platform 36 conductively connected to the upper end surface of the heat sink body 35. The conductive platform 36 provides a flat surface with a large contact area, which is convenient for subsequent connection of welding wires or ribbon components, and as a part of the heat sink body 35, it can also assist in heat dissipation.

[0088] The above-mentioned conductive platform 36 can be arranged according to the requirements of working conditions, and the platform structure and shape matched with the heat dissipation body 35 can be selected to be suitable for different external interconnection process requirements.

[0089] The conductive platform 36 is located on the upper end surface of the heat sink body 35. This double-layer structure not only enhances the thermal conductivity of the heat sink 30, but also provides an additional bonding area to facilitate electrical connection with other components, thereby improving the overall stability and reliability of the chip assembly. Moreover, this design can effectively disperse heat, simplify the connection between components, and reduce the difficulty of connection.

[0090] like Fig.11 As shown, in the fifth embodiment of the chip assembly, the chip assembly further includes a conductive member 41 conductively connected to the heat sink 30 and an insulating member 42 arranged around the edge of the conductive member 41. The conductive member 41 is conductively connected to the heat sink 30, further optimizing the current path and reducing the resistance; and the provision of the insulating member 42 ensures electrical safety and avoids short circuits between different electrical paths to meet the insulation requirements.

[0091] like Fig.12 and Fig.13 As shown, in the sixth embodiment of the chip assembly, the chip assembly further includes a conductive member 41 conductively connected to the heat sink 30. In the direction in which the enlarged structure 20 overlaps with the first bonding area 11, the conductive member 41 is located on the side of the heat sink 30 away from the insulating substrate 21. The chip assembly further includes a baffle 43 connected to the insulating substrate 21 and the conductive member 41. The baffle 43 is arranged outside the heat sink 30. A third heat dissipation channel is arranged between the baffle 43 and the heat sink 30. The baffle 43 is provided with an air inlet 431 and an air outlet 432 connected to the third heat dissipation channel. The addition of the baffle 43, the air inlet 431 and the air outlet 432 allows gas or liquid to pass through the third heat dissipation channel, thereby enhancing the cooling effect around the heat sink, and can effectively control the device temperature, especially in high-power applications.

[0092] The technical effects of the present application are described below one by one in combination with different drawings:

[0093] Figures 1 to 3 The basic structure of the chip assembly is shown in FIG. 1 . It can be seen that the chip 10 is the core part of the assembly, and a first bonding area 11 is arranged on it. The enlarged structure 20 is stacked with the chip 10. The enlarged structure 20 includes an insulating substrate 21, and a second bonding area 22 is arranged on the insulating substrate 21. The second bonding area 22 is conductively connected to the first bonding area 11 through a conductive sheet 23. The arrangement of the conductive sheet 23 not only increases the stability of the electrical connection, but also disperses the bonding pressure and reduces the local stress on the chip 10. It is worth noting that the first bonding area 11 is designed as three spaced areas A1, A2, and A3, while the second bonding area 22 has only two Cs. Inside the interconnection enlarged structure, A1 and B1, A2 and B2 form electrical conduction, and although B3 is not directly conductive, it increases the interconnection area, which helps to stabilize the overall structure.

[0094] Other technical effects corresponding to the above:

[0095] The implementation effect of this design is that it significantly improves the electrical performance and thermal management capabilities of chip components. In practical applications, this structure is particularly suitable for complex application scenarios such as high-power devices, high-performance computing chips and artificial intelligence processors. It can effectively control device temperature while ensuring stable electrical connections, extend the service life of the chip, and reduce the failure rate.

[0096] Figure 1 and Figure 3 The details of the first bonding area 11 on the chip 10 and the connection method between the conductive sheet 23 and the first bonding area 11 are further shown. It can be seen that A1 and A3 are Kelvin sources, and A2 is the gate, which are effectively isolated by insulating materials. The contact between the conductive sheet 23 (B1, B2) and the first bonding area 11 (A1, A2) ensures the reliability of the electrical connection, and also provides a larger interconnection area, which is conducive to reducing the connection resistance and improving the current transmission efficiency.

[0097] Other technical effects corresponding to the above:

[0098] Under the requirement of high-density packaging, this design can significantly reduce the voltage drop and heat caused by connection resistance, thereby improving the overall efficiency and stability of the system. For example, in the power amplifier of a 5G base station, this structure can ensure that the electrical connection will not become a performance bottleneck when the power output is high, while also reducing unnecessary heat generation and ensuring long-term stable operation of the equipment.

[0099] Figure 4 In the figure, we observe the addition of a heat sink 30 in the chip assembly, which forms an electrical and thermal connection with the chip 10 through the second bonding area 22. The heat sink 30 includes a heat sink 31, which is vertically or obliquely arranged on the second bonding area 22. This design optimizes the heat dissipation path and improves the heat dissipation efficiency. The length and diameter of the heat sink 31 can be adjusted according to the heat output of the chip, with a length ranging from 1mm to 10mm and a diameter ranging from 0.5mm to 2mm, ensuring the effective heat dissipation capacity of the heat sink 30.

[0100] Other corresponding technical effects mentioned above:

[0101] This design of the heat sink 30 is particularly suitable for applications where efficient heat dissipation is required in a compact space, such as the CPU of a notebook computer, the GPU of a high-performance server, etc. By adjusting the size of the heat sink, the packaging space occupied can be reduced while ensuring sufficient heat dissipation effect, achieving more efficient space utilization and meeting the requirements of modern electronic equipment for high performance and miniaturization.

[0102] Figures 5 to 7 In the invention, the first heat dissipation channel 32 on the heat sink 30 is specifically mentioned, which includes heat dissipation holes 321 arranged on the side wall of the heat sink 30. The diameter of the heat dissipation holes 321 is between 0.1 mm and 0.5 mm, and the number can reach dozens to hundreds, which is intended to promote heat dissipation by increasing the flow path of gas or other cooling media. This design not only increases the thermal contact area between the heat sink 30 and the outside world, but also improves the heat dissipation performance through the flow of fluid, especially in a high-load working environment, which can help keep the chip temperature within a safe range.

[0103] Other technical effects corresponding to the above:

[0104] By setting heat dissipation holes on the side walls, chip components can be kept within the ideal temperature range even in extreme environments to avoid performance degradation or damage caused by overheating. This design is particularly important in server chips and high-performance computing units in data centers, which can effectively improve the heat dissipation efficiency of the system and reduce the energy consumption of the cooling system, thereby achieving energy conservation and emission reduction while maintaining high performance.

[0105] Figure 5 , Figure 8 and Fig. 9 In the embodiment, the heat sink 30 is designed to include a bearing core 33 and a second heat dissipation channel 34. The bearing core 33 is a column, preferably a cylinder, which is conductively connected to the second bonding area 22, thereby enhancing the thermal stability of the heat sink. The second heat dissipation channel 34 is arranged around the outer side of the bearing core 33, thereby increasing the heat dissipation path and improving the heat conduction efficiency. The annular channel formed around the bearing core 33 ensures uniform distribution of heat, avoids heat concentration, and improves the thermal management capability.

[0106] Other technical effects corresponding to the above:

[0107] This double-layer structure design not only optimizes the thermal management performance of the heat sink 30, but also enhances its mechanical stability, so that it can better protect the chip 10 and maintain the stability of the electrical connection when facing external impact or vibration. This innovative structure is particularly suitable for fields with extremely high reliability requirements such as aerospace, automotive electronics and industrial automation, and can significantly improve the durability and safety of chip components.

[0108] Figure 8 and Fig. 9In the figure, details of the load-bearing core 33 and the second heat dissipation channel 34 on the heat sink 30. The small cross-sectional area load-bearing core 33 retained inside the heat sink 30 not only provides mechanical support, but also cooperates with the second heat dissipation channel 34 to achieve efficient heat conduction and heat dissipation. This double-layer structure design not only increases the stiffness of the heat sink 30 in its length direction, but also ensures its thermal management performance, and is particularly suitable for applications in scenarios that require high interconnection strength and efficient heat dissipation.

[0109] Other technical effects corresponding to the above:

[0110] In practical applications, this design can significantly reduce the temperature of the chip when it is running at high power, and improve its working stability and life. For example, in the inverter module of electric vehicles, this heat sink design can effectively deal with the heat dissipation problem under high current, ensure that the inverter maintains optimal performance under various driving conditions, reduce maintenance requirements, and improve user experience.

[0111] Figure 8 and Fig. 9 Details of the bearing core 33 and the second heat dissipation channel 34 on the heat sink 30 are shown. The bearing core 33 is preferably a cylinder with a regular shape for easy processing and molding. The setting of the second heat dissipation channel 34 further optimizes the heat dissipation path and improves the heat dissipation efficiency, especially in application scenarios that need to withstand large loads, such as pressure in the bonding process. The rigidity of the bearing core 33 ensures the stability of the structure and the bonding effect. The combination of the bearing core 33 and the second heat dissipation channel 34 provides a good heat dissipation solution for the chip assembly.

[0112] Other technical effects corresponding to the above:

[0113] The heat sink 30 of this structure can provide excellent heat dissipation performance under high load conditions, ensuring that the electrical performance of the chip components is not affected by thermal effects. In modern data centers and high-performance computing environments, this design can improve the energy efficiency of servers, reduce the complexity and cost of cooling systems, and ensure stable operation of the system under high computing loads, which is an effective way to achieve green computing and energy conservation and emission reduction.

[0114] Fig.10In the figure, we can see that the heat sink 30 includes a heat sink body 35 and a conductive platform 36. The conductive platform 36 is arranged at the upper end of the heat sink body 35, providing a surface with a large contact area, which is convenient for subsequent connection of welding wires or strip components. This design not only enhances the thermal conductivity of the heat sink 30, but also simplifies the connection between components, reduces the difficulty of connection, and improves the flexibility and efficiency of the overall device design. The setting of the conductive platform 36 not only facilitates the electrical connection between the heat sink and the outside, but also can effectively disperse the current and reduce local hot spots through its large contact area, which is crucial to avoid chip overheating and improve electrical performance and thermal management efficiency.

[0115] Other technical effects corresponding to the above:

[0116] This layout design can significantly improve connection reliability and reduce maintenance costs in server and data center applications that require large-scale electrical connections. It also provides new ideas for the development of future high-density packaging technology.

[0117] Fig.11 In the figure, we see a more complex layout of the chip assembly, including a conductive member 41 conductively connected to the heat sink 30 and an insulating member 42 surrounding the edge of the conductive member 41. The conductive member 41 is located above the heat sink 30 in the direction in which the enlarged structure 20 overlaps the first bonding area 11, further optimizing the current path. The setting of the insulating member 42 is to solve the short circuit problem between different electrical paths, meet the insulation requirements, and ensure electrical safety.

[0118] Other technical effects corresponding to the above:

[0119] By rationally planning current paths and isolating electrical paths, the safety and reliability of chip components are improved. In multi-core processors and complex electronic systems, this design can avoid interference between current paths and reduce electromagnetic compatibility (EMC) issues. At the same time, due to the reduced risk of short circuits, components can operate more stably in high temperature and high voltage environments, extending their service life. Moreover, the above-mentioned design of optimizing current paths and electrical safety is essential for building high-density, high-performance electronic systems. In high-precision analog circuits and complex digital signal processing systems, this design can significantly reduce signal interference, improve circuit accuracy and stability, and at the same time protect the continuity and reliability of the entire system by enhancing electrical safety. It is one of the important trends in the future development of electronic technology.

[0120] Fig.12 and Fig.13In the figure, the use of the enclosure 43 is shown. The enclosure 43 is arranged outside the heat sink 30. A third heat dissipation channel is arranged between the enclosure 43 and the heat sink 30. The enclosure 43 is also provided with an air inlet 431 and an air outlet 432 connected to the third heat dissipation channel. This design allows gas or liquid to pass through the third heat dissipation channel, significantly enhancing the cooling effect around the heat sink, especially in high-power applications, which can effectively control the device temperature and improve its stability and reliability.

[0121] Other corresponding technical effects mentioned above:

[0122] The addition of the enclosure 43 significantly improves the heat dissipation efficiency by forming a closed cooling cycle, which is particularly suitable for electronic devices that need to achieve efficient thermal management in a compact space, such as the chipset of a smartphone and the CPU of a portable gaming device. This design not only ensures the performance stability of the device when it is used under high load, but also reduces the internal temperature of the device by optimizing the heat dissipation solution, thereby improving the comfort and safety of the user.

[0123] Fig.12 and Fig.13 In the PCB design of enclosure 43, the design is further described in detail. The air inlet 431 and air outlet 432 set on enclosure 43, together with the third heat dissipation channel, form an effective heat dissipation network, which can keep the chip temperature within a safe range even under extreme working conditions. The addition of enclosure 43 not only improves the heat dissipation performance, but also improves the overall stability and reliability of chip components, which is particularly suitable for high-performance computing, artificial intelligence, data centers and other high-heat load application scenarios.

[0124] Other corresponding technical effects mentioned above:

[0125] The design of enclosure 43, combined with efficient heat dissipation channels, can ensure that chip components remain in optimal working condition under the most demanding computing tasks. In deep learning servers and high-performance computing centers in the field of artificial intelligence, this design can effectively cope with the large amount of heat generated by large amounts of data processing and parallel computing, reduce the impact of thermal management on system performance, and achieve longer continuous and stable operation, which is of great significance for accelerating scientific research computing and improving data processing capabilities.

[0126] Combination Figures 1 to 13 It can be seen that the insulating base 21 is provided with a thickened portion 212, which is fixed to the conductive layer of the substrate 12, thereby improving the stability of the structure. The thickened portion 212 can be connected to the conductive layer by welding technology, or directly using bonding technology. Such a design optimizes thermal management and current management, and realizes efficient heat dissipation and stable electrical connection of the chip component.

[0127] Other corresponding technical effects mentioned above:

[0128] By setting a thickened portion on the insulating substrate, the thermal conductivity and current management capabilities of the chip assembly are significantly improved. This design has significant advantages in RF power amplifiers and laser driver chips, and can effectively deal with the thermal stress and electrical performance degradation caused by high-frequency operation and high current output. By fixing the thickened portion using welding or bonding technology, it not only simplifies the manufacturing process, but also improves the durability and adaptability of the chip assembly, making it adaptable to a wider range of use environments and working conditions, and meeting the dual needs of modern electronic equipment for high performance and reliability.

[0129] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0130] The core of the chip assembly proposed in this application is the introduction of an innovative bonding area expansion structure, which significantly improves the stability and reliability of the bonding process, optimizes electrical performance, and enhances thermal management capabilities, providing a comprehensive solution for high-load applications.

[0131] Bonding process stability and reliability are improved and the bonding area is expanded: By setting a larger second bonding area 22, the present invention not only solves the problem that the bonding wire diameter is limited by the size of the bonding area, but also ensures that the bonding process is easier to implement and reduces the damage to the chip surface by the bonding process, thereby significantly improving the reliability of bonding. Bonding position adjustment: The actual bonding position of the second bonding area 22 can be adjusted and optimized according to the chip 10 and the auxiliary circuit layout, which improves the flexibility and efficiency of the bonding process and reduces the performance degradation or packaging failure caused by improper bonding position.

[0132] Optimized electrical performance and improved current transmission efficiency: Using the conductive sheet 23 as the connection medium between the bonding areas increases the contact area, reduces the connection resistance, and improves the current transmission efficiency. In particular, using metal materials with good electrical conductivity (such as copper or aluminum) as the conductive sheet further reduces thermal resistance and improves thermal conduction efficiency, which is particularly important for high-power and high-speed computing chips.

[0133] Application of heat dissipation column 31 with enhanced thermal management capability: The design of heat dissipation column 31 increases the heat dissipation area. By connecting vertically or obliquely to the second bonding area, the heat dissipation structure layout is optimized, the heat transfer is accelerated, and the effect of natural or forced convection heat dissipation is improved, especially in high heat load applications. Integration of heat dissipation channels: The setting of the first heat dissipation channel 32 and the second heat dissipation channel 34 provides multi-path heat transfer and enhances the heat dissipation efficiency of the heat sink 30. The configuration of the heat dissipation ring groove increases the circumferential heat conduction efficiency, helps the lateral diffusion of heat, avoids heat concentration, and improves the uniformity of heat dissipation. Dense distribution of heat dissipation through holes 321: The uniform distribution and dense design of heat dissipation through holes 321 form an effective heat dissipation network, which can keep the chip temperature within a safe range even under high-load working conditions. It is particularly suitable for mobile devices and smart wearable devices that have strict requirements on volume and weight.

[0134] Structural design of the bearing core 33 to enhance rigidity and stability: The setting of the bearing core 33 not only enhances the rigidity of the heat sink 30 in its length direction, but also provides good lateral support through the layout of the second heat dissipation channel 34, thereby improving the structural stability of the heat sink during the process and service, and avoiding failure due to compression instability.

[0135] Optimized layout of enclosure 43: The addition of enclosure 43 not only provides an additional heat dissipation path, but also ensures electrical safety and avoids the risk of short circuits between different electrical paths. The design of air inlet 431 and air outlet 432 allows gas or liquid to pass through the third heat dissipation channel, enhancing the cooling effect around the heat sink, especially in high-power applications, which can effectively control the device temperature.

[0136] The flexibility of chip layout and auxiliary circuit layout improves the adjustability of the second bonding area 22: the actual bonding position of the second bonding area 22 is adjustable, which makes the optimized design of chip layout and auxiliary circuit layout possible, improves the flexibility of the overall design, and helps to improve the production efficiency and service reliability of the device.

[0137] Continued use of mature chips with cost and production efficiency optimization advantages: The solution of the present invention does not directly change the first bonding area 11 on the surface of the chip, so that mature and usable chips can continue to be used, avoiding additional costs and production delays caused by design changes. Customized selection: By using the second bonding area 22 of the expanded structure, users can reasonably customize the selection of bonding wire specifications and bonding area areas according to the overall situation of the interconnection, reducing the scrap rate caused by mismatched specifications and improving production efficiency.

[0138] Insulation function of the insulating substrate 21: The use of the insulating substrate 21 not only increases the area of ​​the interconnection region, but also electrically isolates the first bonding region 11 from the second bonding region 22, thereby preventing short circuits and improving electrical safety. Design of the break 211: The setting of the break 211 further ensures effective isolation between adjacent first bonding regions, avoids mutual interference between signals and currents, and enhances the electrical performance of the chip assembly.

[0139] Adjustable heat sink 31 to meet various working conditions: The length and diameter of the heat sink 31 can be adjusted according to the heat output of the chip, so that the solution of the present invention can adapt to different working conditions and thermal management requirements, and can provide the best heat dissipation effect regardless of low load or high load application. Flexible heat sink structure: The structure of the heat sink 30 can be selected according to the specific working conditions, which can be either a single heat sink or an array layout. It can improve heat dissipation through simple through-hole digging, or through the optimized design of the load-bearing core 33 and the second heat dissipation channel 34 to enhance structural stability and heat dissipation uniformity.

[0140] To sum up, all embodiments of the chip assembly of the present application not only solve the problems of difficult bonding process operation and insufficient heat dissipation in power device packaging, but also optimize the electrical performance, improve the interface interconnection strength, improve the flexibility of chip layout and auxiliary circuit layout, reduce production costs, and ensure electrical safety and service reliability of devices. At the same time, it has a wide range of applications and adjustability, meeting the special needs of high-performance computing, artificial intelligence, data centers and other high-heat load application scenarios, and providing new ideas and solutions for power device packaging technology.

[0141] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0142] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0143] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip assembly, characterized in that: include: A chip (10), wherein a first bonding area (11) is provided on the chip (10); an enlarged structure (20) arranged to overlap with the first bonding area (11), the enlarged structure (20) comprising an insulating substrate (21) and a second bonding area (22) arranged on the insulating substrate (21), the second bonding area (22) being conductively connected to the first bonding area (11), and an area of ​​the second bonding area (22) being larger than an area of ​​the first bonding area (11); The chip assembly further comprises a heat sink (30) conductively connected to the second bonding area (22), the heat sink (30) being provided with a first heat dissipation channel (32), the first heat dissipation channel (32) comprising a heat dissipation through hole (321) provided through a side wall of the heat sink (30).

2. The chip assembly according to claim 1, characterized in that: The second bonding area (22) is conductively connected to the first bonding area (11) via a conductive sheet (23).

3. The chip assembly according to claim 1, characterized in that: The heat sink (30) comprises a heat sink column (31) vertically or obliquely conductively connected to the second bonding area (22).

4. The chip assembly according to claim 1, characterized in that: The heat sink (30) comprises a heat dissipation column (31), and there are a plurality of heat dissipation through holes (321), wherein the plurality of heat dissipation through holes (321) are radially arranged at intervals on the heat dissipation column (31).

5. The chip assembly according to claim 1, characterized in that: There are a plurality of the first heat dissipation channels (32), and the plurality of the first heat dissipation channels (32) are arranged at intervals along a direction in which the enlarged structure (20) and the first bonding area (11) overlap.

6. The chip assembly according to claim 1, characterized in that: The first heat dissipation channel (32) comprises a heat dissipation ring groove extending along the circumference of the heat dissipation element (30).

7. The chip assembly according to claim 1, characterized in that: The heat sink (30) comprises a carrier core (33) conductively connected to the second bonding area (22) and a second heat dissipation channel (34) arranged around the outside of the carrier core (33).

8. The chip assembly according to claim 1, characterized in that: The heat sink (30) comprises a heat sink body (35) conductively connected to the second bonding area (22) and a conductive platform (36) conductively connected to the upper end surface of the heat sink body (35).

9. The chip assembly according to claim 1, characterized in that: The chip assembly further comprises a conductive member (41) conductively connected to the heat sink (30) and an insulating member (42) arranged around the edge of the conductive member (41).

10. The chip assembly according to claim 1, characterized in that: The chip assembly further comprises a conductive member (41) conductively connected to the heat sink (30); in the direction in which the enlarged structure (20) and the first bonding area (11) overlap, the conductive member (41) is located on a side of the heat sink (30) away from the insulating substrate (21); the chip assembly further comprises an enclosure (43) connected to the insulating substrate (21) and the conductive member (41); the enclosure (43) is arranged on the outside of the heat sink (30); a third heat dissipation channel is arranged between the enclosure (43) and the heat sink (30); and an air inlet (431) and an air outlet (432) in communication with the third heat dissipation channel are arranged on the enclosure (43).

11. The chip assembly according to any one of claims 1 to 10, characterized in that: The first bonding areas (11) are multiple and spaced apart, a fracture (211) is provided on the surface of the insulating substrate (21) facing the first bonding area (11), and a portion between two adjacent first bonding areas (11) corresponds to the fracture (211).

12. The chip assembly according to any one of claims 1 to 10, characterized in that: The expansion structure (20) is connected to the chip (10) via a connecting sheet (24).

13. The chip assembly according to any one of claims 1 to 10, characterized in that: The chip assembly further comprises a substrate (12) carrying the chip (10), the substrate (12) having a conductive layer, and the chip (10) is fixed on the conductive layer.

14. The chip assembly according to claim 13, characterized in that: A thickened portion (212) is provided on the insulating base (21), and the thickened portion (212) is fixed on the conductive layer.

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