Coding method, decoding method and related device

Abstract

The invention discloses an encoding method, a decoding method and a related device, and aims to independently encode each path of second data stream in z paths of second data streams without performing operations such as deskewing and reordering, so that the operation complexity is reduced and the time delay is reduced. The coding method comprises the following steps: acquiring m paths of first data streams through m paths of input channels, wherein m is a positive integer; the m paths of first data streams are processed to obtain z paths of second data streams, and z is a positive integer; independently coding each path of second data stream in the z paths of second data streams to obtain z paths of third data streams; and multiplexing the z paths of third data streams to obtain n paths of fourth data streams, n being positive integers.

Description

[0001] This application is a divisional application of the application submitted to the China Intellectual Property Office with an application date of September 18, 2021, application number 202111127055.5, and invention name “A coding method, a decoding method and related devices”. Technical Field

[0002] The embodiments of the present application relate to the field of communication technology, and specifically to a coding method, a decoding method, and related devices. Background Art

[0003] The current fifth generation mobile communication technology (5G), artificial intelligence, virtual reality and other applications are driving the continued rapid growth of data center traffic. The existing 400GE technology cannot meet the underlying interconnection architecture of future data centers. Therefore, the next generation of Ethernet technology with a throughput of more than 400Gbps is needed to meet the bandwidth requirements of future data centers. As the Ethernet transmission rate increases, the transmission bit error rate increases, and forward error correction (FEC) becomes a key core technology to solve transmission errors. Designing an efficient, low-complexity, and low-latency FEC coding algorithm and implementation architecture has become the main technical challenge facing the next generation of Ethernet technology.

[0004] In the relevant existing Ethernet communication architecture, the physical sublayer of the Ethernet communication architecture can be divided into a physical coding sublayer (PCS), a physical medium attachment sublayer (PMA) and a physical media dependent (PMD). At the PCS layer, the data stream is sequentially processed with 64B / 66B encoding, 256B / 257B transcoding, alignment mark insertion, Reed-Solomon (RS) encoding and other major data stream operations. Then, the data stream obtained after RS ​​encoding is distributed to the physical coding sublayer channel (PCS lane), and after multiplexing through a multiplexer (MUX), the data stream obtained after multiplexing is sent to the PMA layer through m output channels. At the PMA layer, the received data stream is subjected to clock data recovery (CDR), bit multiplexing at the transmitting end, signal driving and other operations. The data stream output from the PMA layer completes optical modulation, electro-optical conversion and other operations of the data in the PMD layer, outputs the optical signal to the transmission medium, and completes the data operation of the entire sending end.

[0005] However, in the existing Ethernet communication architecture, the data stream is transmitted to the PMA layer of the optical module through m output channels at the PCS layer, and delay skew occurs between the physical channels. In order to ensure data stream alignment, operations such as alignment, de-skew, and reordering of multiple physical coding sublayer channels are required, which requires great complexity and latency. In addition, the existing Ethernet communication architecture is only applicable to scenarios with a throughput rate of less than 400Gbps. As the Ethernet transmission rate increases, the existing Ethernet communication architecture cannot meet the system error correction performance requirements required by the next generation of Ethernet communications with a throughput rate of more than 400Gbps. Summary of the invention

[0006] The embodiments of the present application disclose a coding method, a decoding method and related devices, which aim to reduce the operation complexity and delay by independently performing inner code coding processing on each of the z second data streams, without the need to perform de-skew, reordering and other operations on the z second data streams.

[0007] In the first aspect, the embodiment of the present application provides a coding method, which can be applied to an optical module or other coding device. In the coding method, m-way first data streams are obtained through m-way input channels, where m is a positive integer; the m-way first data streams are processed to obtain z-way second data streams, where z is a positive integer; each second data stream in the z-way second data stream is independently coded to obtain a z-way third data stream; the z-way third data stream is multiplexed to obtain an n-way fourth data stream, where n is a positive integer. It should be noted that in each second data stream, Y data blocks to be encoded can be included, and the data blocks to be encoded can be understood as information bits to be encoded. For each data block to be encoded in the second data stream, the mapping relationship between it and the RS codeword satisfies: Y×the length of the data block to be encoded=X×(N×the codeword length of the RS codeword) / z, where Y and X are positive integers greater than or equal to 1. It should be noted that the length of each data block to be encoded is k, the length of the check bit is p, and the total codeword length is n, wherein n, k and p satisfy n=k+p, and n, k, and p are integers greater than 0. For example, if the length k of the data block to be encoded is 170 bits, and after adding 10 bits of check bits, the total codeword length of the data block to be encoded is 180 bits. Alternatively, if the length k of the data block to be encoded is 170 bits, and after adding 9 bits of check bits, the total codeword length of the data block to be encoded is 179 bits. Alternatively, if the length k of the data block to be encoded is 170 bits, and after adding 11 bits of check bits, the total codeword length of the data block to be encoded is 181 bits. Alternatively, if the length k of the data block to be encoded is 120 bits, and after adding 8 bits of check bits, the total codeword length of the data block to be encoded is 128 bits, and so on. This is only used as an example for illustration and is not specifically limited in this application.

[0008] Through the above method, the embodiment of the present application independently performs inner code encoding processing on each of the z second data streams, and the FEC codewords in each encoded third data stream contain boundary markers, which not only ensures the decoupling of the inner code encoding from the data after encoding in the upper PCS layer, but also ensures the decoupling of the inner code encoding from the transmission of the lower PMD layer, which can save the delay of processing delay skew and disorder, so that the inner code encoding and decoding of the present application is suitable for scenarios that are sensitive to transmission delays.

[0009] In some possible implementations, each of the z second data streams includes a data block to be encoded. In the encoding method, the encoding process of the z second data streams can be performed in the following manner: the first data block is subjected to inner code encoding to obtain an FEC codeword, wherein the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, C is a positive integer, and C is an integer multiple of z. The encoding method also includes: inserting a first identifier at the codeword boundary position of any FEC codeword in the FEC codeword, the first identifier is used to identify the codeword boundary of the FEC codeword, and the throughput rate or baud rate of the FEC codeword after inserting the first identifier is an integer multiple of the reference clock. It should be noted that the codeword boundary position can be understood as the codeword head and / or the codeword tail, which is not limited here. The codeword boundary of the FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, so that the boundary position of each FEC codeword can be clearly identified, avoiding the situation where the inner code decoding fails in the case of delay skew and unknown data starting position.

[0010] In some other possible implementations, each of the z second data streams includes a data block to be encoded. In the encoding method, the encoding process of the z second data streams can also be carried out in the following manner: inserting a first identifier into each data block to be encoded in the first data block to obtain a second data block, wherein the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream; encoding the second data block to obtain an FEC codeword, and the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock. In the above manner, the codeword boundary of the encoded FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, and the boundary position of each FEC codeword can be clearly identified, thereby avoiding the failure of inner code decoding in the case of delay skew and unknown data starting position.

[0011] In some other possible implementations, the first identifier is a preset identifier sequence. For example, the first identifier can be a sequence of "1" and "0", or can be a sequence of "101010", "1010", etc., or can be other known sequences, which are not limited here. In the above manner, setting the first identifier as a preset identifier sequence can meet the needs of different scenarios.

[0012] In some other possible implementations, the first identifier is obtained according to the value of the first bit of the first data block, and the first bit is any one of at least one bit in the first data block; or, the first identifier is obtained according to the bit value of at least L second bits in the first data block, and there are s bits between each two adjacent second bits of the L second bits, L≥2, s≥0, and L and s are integers. For example, the first bit can be the 0th bit in the first data block. If the value of the 0th bit is "0", the first identifier, that is, "1", can be obtained by directly negating the value of the 0th bit. Or, if the value of the 0th bit is "1", the first identifier, that is, "0", can be obtained by directly negating the value of the 0th bit, which is not limited here. In practical applications, the first bit can also be the 1st bit, the 2nd bit, etc. in the first data block, which is not limited here. For example: the codeword length of the first data block is 180 bits, and the last bit can be selected to be negated, that is, the value of the 179th bit is selected to be directly negated to obtain the first identifier. The first identifier is obtained by performing an inversion operation on the bit at the very beginning or the very end of the codeword, which helps the receiving end to quickly determine the codeword boundary. Alternatively, when L=4 and s=2, the four second bits selected from the first data block are the 0th bit, the 2nd bit, the 4th bit and the 6th bit. In this way, the bit values ​​corresponding to the 0th bit, the 2nd bit, the 4th bit and the 6th bit are processed by an XOR operation, and the result of the processing can be used as the first identifier. It should be noted that in some examples, the four second bits selected may also be the 1st bit, the 3rd bit, the 5th bit and the 7th bit, etc., which are not limited here. In practical applications, L may also be 8 and s may be 3, or L may be 6 and s may be 4, etc. The value of L is not limited in this application, nor is the value of s. In the above manner, the first identifier is determined according to the bits in the first data block, which can also be applied to different scenarios.

[0013] In some other possible implementations, the m-way first data stream is processed to obtain the z-way second data stream, and the following method can be adopted, namely: the m-way first data stream is demultiplexed according to the second ratio to obtain the z-way second data stream, and the second ratio is the ratio of m to z. For example, if the first ratio is 16:4, the second ratio should be 4:16 at this time. Here, only 4:16 is used as an example for illustration, and other values ​​can also be used in practical applications, and this application does not limit it. Through the above method, the m-way first data stream is directly demultiplexed, which provides a variety of possible implementation methods for obtaining the z-way second data stream.

[0014] In some other possible implementations, demultiplexing the m first data streams according to the second ratio to obtain z second data streams includes: demultiplexing the m first data streams according to the second ratio to obtain z fifth data streams, and independently performing Q-level processing on each fifth data stream in the z third data streams to obtain z second data streams. Wherein, each level of processing in the Q-level processing includes: performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, delaying the first sub-data stream to obtain the sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain the output data stream after the processing at this level, the first sub-data stream is at least one sub-data stream in the at least two sub-data streams, the second sub-data stream is one sub-data stream in the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is a data stream after Q-level processing. Through the above method, multiple possible implementation methods are provided for obtaining z second data streams.

[0015] In some other possible implementations, the bit length of the sixth data stream is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of sub-data streams.

[0016] In some other possible implementations, the encoding method further includes: obtaining m seventh data streams through the m physical channels; demultiplexing the m seventh data streams according to the second ratio to obtain z eighth data streams; processing the m first data streams to obtain z second data streams, including: multiplexing the z second data streams and the z eighth data streams to obtain z multiplexed second data streams. Through the above method, multiple possible implementation methods are provided for obtaining z second data streams.

[0017] In some other possible implementations, the encoding method further includes: identifying an alignment mark in each of the second data streams, the alignment mark being used to identify a symbol boundary in the corresponding second data stream, and determining a symbol boundary in the corresponding second data stream based on the alignment mark. For example, a 120-bit AM alignment block of a known sequence is added to each of the first data streams, and in this 120-bit AM alignment block of a known sequence, there is a 48-bit common alignment marker. Then, in an operation that only requires RS codeword symbol boundaries, the alignment can be locked by identifying the 48-bit common alignment marker.

[0018] In some other possible implementations, the m-way first data stream is obtained by multiplexing the z-way data stream after Reed-Solomon RS encoding at a first ratio. It should be noted that the first ratio can be understood as the ratio of z to m. For example, the first ratio is 16:4, 32:4, 32:16, 16:8, etc., which are not limited here. In addition, the m-way first data streams collectively include N RS codewords, wherein each of the first data streams may include (N×codeword length of RS codeword) / m bits.

[0019] In the second aspect, the embodiment of the present application provides a decoding method, which can be applied to an optical module or other decoding devices. In the decoding method, n fourth data streams are obtained through n input channels; the n fourth data streams are demultiplexed to obtain z third data streams; each third data stream in the z third data streams is independently decoded to obtain the z second data streams; the z second data streams are multiplexed according to a first ratio to obtain the m first data streams, and the first ratio and the second ratio are reciprocal of each other.

[0020] In some other possible implementations, the z-path third data stream includes a first identifier, and the first identifier is used to identify a codeword boundary of an FEC codeword. In the decoding method, the decoding method further includes: identifying the codeword boundary of the FEC according to the first identifier and / or a decoding flag bit, and the decoding flag bit is used to indicate whether the inner code decoding process is successful.

[0021] In some other possible implementations, before identifying the codeword boundary of the FEC codeword according to the first identifier and / or the decoding flag, the decoding method also includes: generating a first signal according to the first identifier and / or the decoding flag, and the first signal is used to determine the data clock information. It should be noted that the data clock information can be determined by the first signal, so that the CDR unit accelerates the data and clock recovery process, determines the data clock information in advance, reduces the time required for system locking, and is conducive to determining the frequency of system transmission in advance. In addition, since the first identifier of the present application takes into account the autocorrelation characteristics of the sequence corresponding to the first identifier in the design sequence generation method, it helps the first identifier to be detected more quickly; and takes into account that the first identifier contains a fixed 0,1 jump characteristic, which improves the convergence speed of the data clock recovery of the CDR unit. It should be noted that if the CDR unit receives a signal for normal recovery of data and clock fed back by itself before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal recovery of data and clock, thereby completing the data and clock recovery operation.

[0022] In a third aspect, an embodiment of the present application provides another encoding method. In the encoding method, a data stream to be transmitted is obtained, and the data stream to be transmitted is RS encoded to obtain z data streams, each of which corresponds to one physical coding sublayer channel. Then, the z data streams are multiplexed according to the first ratio to obtain the m first data streams, and the m first data streams are sent through the m output channels.

[0023] In some other possible implementations, the encoding method may further include: performing Q-level processing on each of the z data streams to obtain z ninth data streams. Each level of processing in the Q-level processing includes performing round-robin distribution processing on the ninth data stream obtained at the previous level to obtain at least two sub-data streams, delaying the third sub-data stream to obtain the tenth data stream, and multiplexing the fourth sub-data stream and the tenth data stream to obtain the ninth data stream after the processing at this level, wherein the third sub-data stream is at least one of the at least two sub-data streams, and the fourth sub-data stream is one of the at least two sub-data streams that has not been delayed. Then, the z ninth data streams are multiplexed according to the first ratio to obtain the m first data streams.

[0024] In a fourth aspect, an embodiment of the present application provides an encoding device, which includes a first acquisition unit and a first processing unit. The first acquisition unit is used to acquire m first data streams through m input channels, where m is a positive integer. The first processing unit is used to process the m first data streams to obtain z second data streams, where z is a positive integer; independently encode each second data stream in the z second data streams to obtain z third data streams; and multiplex the z third data streams to obtain n fourth data streams, where n is a positive integer.

[0025] In some other possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit is used to: encode the first data block to obtain an FEC codeword, the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, C is a positive integer, and C is an integer multiple of z; insert a first identifier at the codeword boundary position of any FEC codeword in the FEC codeword, the first identifier is used to identify the codeword boundary of the FEC codeword, and the throughput rate or baud rate of the FEC codeword after inserting the first identifier is an integer multiple of the reference clock. In the above manner, the codeword boundary of the encoded FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, so that the boundary position of each FEC codeword can be clarified, avoiding the failure of inner code decoding in the case of delay skew and unknown data starting position.

[0026] In some other possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit is used to: insert a first identifier into each data block to be encoded in the first data block to obtain a second data block, the first data block is C / z consecutive data blocks to be encoded, C is a positive integer, and C is an integer multiple of z; encode the second data block to obtain an FEC codeword, and the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock. In the above manner, the codeword boundary of the FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, and the boundary position of each FEC codeword can be clearly identified, avoiding the failure of inner code decoding in the case of delay skew and unknown data starting position.

[0027] In some other possible implementations, the first identifier is a preset identifier sequence. In the above manner, setting the first identifier as a preset identifier sequence can meet the requirements of different scenarios.

[0028] In some other possible implementations, the first identifier is obtained based on the value of the first bit of the first data block, and the first bit is any one of at least one bit in the first data block; or, the first identifier is obtained based on the bit values ​​of at least L second bits in the first data block, and each two adjacent second bits of the L second bits are separated by s bits, L≥2, s≥0, and L and s are integers.

[0029] In some other possible implementations, the first processing unit is used to perform demultiplexing processing on the m first data streams according to a second ratio to obtain z second data streams, where the second ratio is a ratio of m to z.

[0030] In some other possible implementations, the first processing unit is used to demultiplex the m first data streams according to the second ratio to obtain z fifth data streams; independently perform Q-level processing on each of the z fifth data streams to obtain z second data streams; wherein each level of processing in the Q-level processing includes: performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, and delaying the first sub-data stream to obtain a sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream after processing at this level, the first sub-data stream is at least one sub-data stream of the at least two sub-data streams, the second sub-data stream is one sub-data stream of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is a data stream after Q-level processing.

[0031] In some other possible implementations, the bit length of the sixth data stream is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of the sub-data streams.

[0032] In some other possible implementations, the first acquisition unit is further configured to acquire m seventh data streams through the m input channels. The first processing unit is configured to demultiplex the m seventh data streams according to the second ratio to obtain z eighth data streams; and multiplex the z second data streams and the z eighth data streams to obtain z second data streams after multiplexing.

[0033] In some other possible implementations, the first processing unit is further used to identify an alignment mark in each of the second data streams, where the alignment mark is used to identify a symbol boundary in the corresponding second data stream; and determine a symbol boundary in the corresponding second data stream based on the alignment mark.

[0034] In some other possible implementations, the m-channel first data streams are obtained by multiplexing z-channel data streams that are Reed-Solomon (RS) encoded at a first ratio.

[0035] In a fifth aspect, an embodiment of the present application provides a decoding device, which includes a second acquisition unit and a second processing unit. The second acquisition unit is used to acquire n fourth data streams through n input channels. The second processing unit is used to: demultiplex the n fourth data streams to obtain z third data streams; independently decode each of the z third data streams to obtain the z second data streams; multiplex the z second data streams according to a first ratio to obtain the m first data streams, and the first ratio and the second ratio are reciprocal of each other.

[0036] In some other possible embodiments, the z-path third data stream includes a first identifier, and the first identifier is used to identify the codeword boundary of the FEC codeword; the second processing unit is also used to: identify the codeword boundary of the FEC codeword according to the first identifier and / or the decoding flag bit, and the decoding flag bit is used to indicate whether the decoding process is successful.

[0037] In some other possible implementations, the second processing unit is also used to generate a first signal according to the first identifier and / or the decoding flag bit before identifying the codeword boundary of the FEC codeword according to the first identifier and / or the decoding flag bit, and the first signal is used to determine the data clock information. It should be noted that the data clock information can be determined by the first signal, so that the CDR unit accelerates the data and clock recovery process, determines the data clock information in advance, reduces the time required for system locking, and is conducive to determining the frequency of system transmission in advance. In addition, since the first identifier of the present application is designed in a sequence generation method, it is helpful for the first identifier to be detected more quickly; and it is considered that the first identifier contains a fixed 0,1 jump characteristic, which improves the convergence speed of the data clock recovery of the CDR unit. It should be noted that if the CDR unit receives a signal for normal recovery of data and clock fed back by itself before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal recovery of data and clock, thereby completing the data and clock recovery operation.

[0038] In a sixth aspect, an embodiment of the present application provides a coding device, which may include: a memory for storing computer-readable instructions. It may also include a processor coupled to the memory, for executing the computer-readable instructions in the memory so that the coding device performs the coding method described in the first aspect or any possible implementation of the first aspect.

[0039] In a seventh aspect, an embodiment of the present application provides a decoding device, which may include: a memory for storing computer-readable instructions. It may also include a processor coupled to the memory for executing the computer-readable instructions in the memory so that the decoding device performs the method described in the second aspect or any possible implementation of the second aspect.

[0040] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions, which, when executed on a computer, enables the computer to execute a method such as the first aspect, any one of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0041] In the ninth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute a method such as the first aspect, any one of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0042] In the tenth aspect of the present application, a chip system is provided, which may include a processor for supporting an encoding device to implement the functions involved in the encoding method described in the first aspect or any possible implementation of the first aspect, or supporting a decoding device to implement the functions involved in the decoding method described in the second aspect or any possible implementation of the second aspect.

[0043] Optionally, in combination with the tenth aspect above, in a first possible implementation, the chip system may further include a memory, which is used to store program instructions and data necessary for the encoding device and the decoding device. The chip system may be composed of a chip, or may include a chip and other discrete devices. Among them, the chip system may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, etc. Further, the chip system may also include an interface circuit, etc.

[0044] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0045] In an embodiment of the present application, m first data streams are obtained through m input channels, where m is a positive integer, and the m first data streams are processed to obtain z second data streams, where z is a positive integer. Then, each second data stream in the z second data streams is independently encoded to obtain z third data streams, and the z third data streams are multiplexed to obtain n fourth data streams, where n is a positive integer. In the above manner, in an embodiment of the present application, each second data stream in the z second data streams is independently encoded, and each FEC codeword in the third data stream obtained after encoding contains a boundary identifier, which not only ensures the decoupling of the inner code encoding from the data encoded by the upper PCS layer, but also ensures the decoupling of the inner code encoding from the transmission of the lower PMD layer, and does not need to perform de-skewing, reordering and other operations on the second data stream, saving the delay of processing delay skew and disorder, so that the inner code encoding and decoding of the present application is suitable for scenes sensitive to transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application.

[0047] Figure 1A A schematic diagram of the Ethernet communication architecture provided in the relevant solution;

[0048] Figure 1B The diagram is a diagram showing the skew and disorder of data flow;

[0049] Figure 2 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0050] Figure 3 A flowchart of a compilation method provided in an embodiment of the present application;

[0051] Figure 4A A transmission schematic diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0052] Figure 4B Another transmission schematic diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0053] Figure 4C Another transmission schematic diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0054] Figure 4D Another transmission schematic diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0055] Figure 4E Another transmission schematic diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0056] Figure 4F Another transmission schematic diagram of a data stream in the encoding process provided in an embodiment of the present application;

[0057] Figure 5A A schematic diagram of performing an inner code encoding process in an embodiment of the present application;

[0058] Figure 5B Another schematic diagram of performing an inner code encoding process operation in an embodiment of the present application;

[0059] Fig. 6A A schematic diagram of adding a first identifier provided in an embodiment of the present application;

[0060] Figure 6B A schematic diagram of a method for obtaining a value of a first identifier provided in an embodiment of the present application;

[0061] Figure 6C A schematic diagram of another method for obtaining a value of a first identifier provided in an embodiment of the present application;

[0062] Figure 7 Another transmission diagram of data stream in the encoding process provided by an embodiment of the present application;

[0063] Figure 8 A schematic diagram of the overall transmission of data streams in the PMA layer;

[0064] Fig. 9 A flowchart of a decoding method provided in an embodiment of the present application;

[0065] Fig. 10A A transmission diagram of a data stream in the decoding process provided in an embodiment of the present application;

[0066] Fig. 10B Another transmission diagram of data stream in the decoding process provided by the embodiment of the present application;

[0067] Fig.11 A schematic diagram of the hardware structure of a communication device provided in an embodiment of the present application;

[0068] Fig.12 A schematic diagram of the structure of an encoding device provided in an embodiment of the present application;

[0069] Fig.13 A schematic diagram of the structure of a receiving device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The embodiments of the present application disclose an encoding method, a decoding method and related devices, which are intended to independently encode each of the z second data streams without performing de-skew, reordering and other operations on the z second data streams, thereby reducing the operation complexity and delay.

[0071] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0072] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the implementation of the application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. In this application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following items (individuals)" or similar expressions thereof refer to any combination of these items, including any combination of single items (individuals) or plural items (individuals). For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c or a and b and c, where a, b and c can be single or multiple. It is worth noting that "at least one" can also be interpreted as "one or more".

[0073] In the relevant existing Ethernet communication architecture, the physical sublayer of the Ethernet communication architecture can be divided into a PCS layer, a PMA layer and a PMD layer. Figure 1A This is a schematic diagram of the Ethernet communication architecture provided in the relevant solution. Figure 1A As shown, the data stream is obtained from the MAC module, and the PCS layer performs 64B / 66B encoding, 256B / 257B transcoding, alignment marker (AM) insertion, and RS encoding on the data stream in sequence. Then, the data stream obtained after RS ​​encoding is multiplexed, and the multiplexed data stream is transmitted to the PMA layer through m output channels. The PMA layer performs CDR processing and bit multiplexing on the data stream received through the m input channels in sequence, and transmits the processed data stream from the PMA layer to the PMD layer. Then, the PMD layer performs optical modulation and other processing on the data stream, and outputs the optical signal to the transmission medium, completing the data operation of the entire transmitting end. The processing operation of the data stream in the receiving end is a reverse operation, that is, the processing in the PMD layer and the processing in the PMA layer are completed in sequence in the receiving end. The data stream is then transmitted to the PCS layer through m output channels.

[0074] However, in Figure 1AIn the related Ethernet communication architecture shown in FIG, the data stream processed by the PCS layer is transmitted to the PMA layer through m output channels. Delay skew occurs between the m output channels, making the data streams obtained from the m output channels out of sync in time, resulting in the inability to align the data streams received at the PMA layer. For details, please refer to Figure 1B The diagram shows that the data flow is skewed and out of order. Figure 1A In the Ethernet communication architecture shown, the data streams between the input channels need to be aligned, and the alignment, de-skew, and reordering of multiple physical coding sublayer channels need to be completed before the encoding operation can be performed. The delay indication required to complete data alignment, de-skew, and reordering operations requires 180ns, which increases both the complexity of the operation and the delay. In addition, with the increase in Ethernet transmission rates, the existing Ethernet communication architecture is only suitable for scenarios within 400Gbps throughput, and cannot meet the system error correction performance requirements required by the next generation of Ethernet communications with throughput rates exceeding 400Gbps.

[0075] Therefore, in order to solve the above Figure 1A and Figure 1B In order to solve the problem described in , if the inner coding sublayer and the physical coding sublayer channel can be formed into a one-to-one correspondence in the PMA layer, so as to independently encode the data stream in each physical coding sublayer channel, then the Figure 1B The de-skew, reordering and other processing operations shown effectively reduce latency and complexity. Based on this, the embodiment of the present application provides a coding method and a decoding method, which are applied to various optical communication scenarios such as medium and short-distance interconnection communications, long-distance interconnection communications, cloud storage, cloud computing, 5G base station backbone networks, optical transmission, optical access, and base station fronthaul in data centers. The described coding method and decoding method can also be applied to the next generation Ethernet communication architecture with a throughput rate exceeding 400Gbps (for example: 800Gbps throughput, 1600Gbps throughput, etc.). The medium and short-distance interconnection communications described include but are not limited to optical transmission scenarios less than or equal to 40KM. Figure 2 A schematic diagram of an application scenario provided by an embodiment of the present application. Figure 2As shown, data communication is achieved between any two hosts through an optical module. For example, taking the data stream transmitted from host A to host B as an example, the optical module a is inserted in host A, and the optical module b is inserted in host B. Host A can send the data stream to host B through optical modules a and optical modules b in turn. In order to save processing operations such as de-skew and reordering, effectively reduce delay and complexity, and keep the processing flow of the host unchanged as much as possible, it is necessary to change the processing process of the optical module for the data stream, aiming to process the m-way first data stream obtained through the m-way input channel, restore the original z-way second data stream, and then independently perform inner code encoding processing on each of the z-way second data streams to obtain the z-way third data stream. Among them, each of the second data streams is independently subjected to inner code encoding processing, and there is no need to perform complex de-skew, reordering, etc. on the z-way second data streams. When the system has a breakout mode requirement, it is only necessary to uniquely correspond each input channel and each output channel of the PMA layer to a transmission medium, thereby ensuring that each second data stream can be transmitted independently, which is better adapted to the breakout mode.

[0076] It should be noted that the above-mentioned optical module can be understood as an optical module used when transmitting a data stream to a receiving end, and can also be understood as an optical module used when receiving a data stream from a receiving end, such as the above-mentioned optical module a and optical module b. In practical applications, data streams can also be transmitted from host B to host A, and this is not intended to be limited here. In addition, the described hosts (such as host A, host B, etc.) can include but are not limited to switching chips or interface chips used in routers, switches, optical transport networks (OTN) transmission equipment, and can also be mobile phone chips, CPU chips, and interface chips that require high-speed communication, etc., and this is not intended to be limited here.

[0077] Figure 3 A schematic diagram of a coding method provided in an embodiment of the present application. Figure 3 As shown, the encoding method may include the following steps:

[0078] 301. Obtain m first data streams through m input channels, where m is a positive integer.

[0079] In this example, after the PCS layer obtains the data stream to be transmitted sent by the MAC module, it sequentially processes the data stream to be transmitted through 64B / 66B encoding, 256B / 257B transcoding, and RS encoding to obtain z data streams. Moreover, each of the z data streams corresponds to a physical coding sublayer channel (PCS lane) in the PCS layer, so that one data stream can be transmitted through one physical coding sublayer channel. Then, after obtaining the z RS-encoded data streams, the z RS-encoded data streams can be multiplexed according to a first ratio to obtain m first data streams (for example: D1, D2, ... D m ), please refer to the above Figure 1A It should be noted that the RS coding described here can be understood as the first coding in the concatenated code, that is, the coding included in the PCS layer.

[0080] In some other possible examples, in the PCS layer, before multiplexing the z-way RS-encoded data streams according to the first ratio to obtain the m-way first data streams, the following operation may be performed first: each of the z-way RS-encoded data streams is subjected to Q-level processing to obtain the z-way ninth data stream; wherein each level of processing in the Q-level processing includes performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, delaying the third sub-data stream to obtain the tenth data stream, and multiplexing the fourth sub-data stream and the tenth data stream to obtain the output data stream after the processing at this level, wherein the third sub-data stream is at least one of the at least two sub-data streams, the fourth sub-data stream is one of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the ninth data stream is a Q-level processed data stream. Then, the z-way ninth data streams are multiplexed again according to the first ratio at the PCS layer to obtain the m-way first data streams.

[0081] It should be noted that the specific process of Q-level processing at the PCS layer can be referred to in the subsequent Figure 4B-4D You can understand the contents described in the article, and will not go into details here.

[0082] The above-mentioned first ratio is the ratio of z to m, which can also be understood as the ratio of the number of channels of the physical coding sublayer channel to the number of channels of the input channel. For example, in order to send 16 data streams to the PMA layer through 4 output channels at the PCS layer, it is necessary to multiplex these 16 data streams according to the first ratio of 16:4, so as to obtain 4 first data streams. It should be noted that only the first ratio of 16:4 is used as an example for explanation here. In actual applications, the first ratio can also be other values, such as: 32:4, 32:16, 16:8, etc., which are not limited here.

[0083] In addition, these m first data streams collectively include N RS codewords, for example, N can be 2, 4, 6, etc., which is not limited here. Among them, each first data stream can include (N×codeword length of RS codeword) / m bits. For example, the data block length of the RS codeword can be 514 symbols, the check bit length is 62 symbols, the total codeword length is 576 symbols, the size of each symbol is 10 bits, and the error correction capability of the codeword is 31 error symbols that can be corrected. Alternatively, the data block length of the RS codeword can be 514 symbols, the check bit length is 30 symbols, the total codeword length is 544 symbols, the size of each symbol is 10 bits, and the error correction capability of the codeword is 15 error symbols that can be corrected. It should be noted that the present application does not limit the codeword length of the RS codeword, and other codeword lengths may also be included in practical applications to achieve error correction of different error symbols.

[0084] In this way, after obtaining m first data streams in the PCS layer, the m first data streams are transmitted from the PCS layer to the PMA layer. At this time, the PMA layer can obtain the m first data streams through m input channels. It should be noted that the input channel described can be understood as a physical medium additional sublayer channel, a physical channel of an AUI interface, or an output channel of an upper PMA layer, etc., which is not limited in this application.

[0085] 302. Process m first data streams to obtain z second data streams, where z is a positive integer.

[0086] In this example, the PMA layer uses m input channels (for example, E1, E2, ... E m ) after receiving the m first data streams sent by the PCS layer, the m first data streams can be processed to obtain z second data streams (for example: F1, F2, ... F z ). It should be noted that the number of data streams of the described z-lane second data stream is equal to the number of data streams of the z-lane data stream obtained after the PCS layer performs RS encoding on the data stream to be transmitted in the aforementioned step 301. In addition, the z-lane second data stream may also be referred to as a PCS lane data stream in some possible examples.

[0087] Each second data stream may include Y data blocks to be encoded, and the data blocks to be encoded may be understood as information bits to be encoded. In addition, for each data block to be encoded in the second data stream, the mapping relationship between the data block to be encoded and the RS codeword satisfies: Y×the length of the data block to be encoded=X×(N×the codeword length of the RS codeword) / z, where Y and X are positive integers.

[0088] In addition, the length of each data block to be encoded is k, the length of the check bit is p, and the total codeword length is n, wherein n, k and p satisfy n=k+p, and n, k, and p are integers greater than 0. For example, if the length k of the data block to be encoded is 170 bits, and after adding 10 bits of check bits, the total codeword length of the data block to be encoded is 180 bits. Alternatively, the length k of the data block to be encoded is 170 bits, and after adding 9 bits of check bits, the total codeword length of the data block to be encoded is 179 bits. Alternatively, the length k of the data block to be encoded is 170 bits, and after adding 11 bits of check bits, the total codeword length of the data block to be encoded is 181 bits. Alternatively, the length k of the data block to be encoded is 120 bits, and after adding 8 bits of check bits, the total codeword length of the data block to be encoded is 128 bits, and so on. This is only used as an example for illustration and is not specifically limited in this application.

[0089] In some other possible examples, at the PMA layer, different processing operations can be performed on the m first data streams to obtain z second data streams. For example, the z second data streams can be obtained by directly demultiplexing the m first data streams; or by further delaying and multiplexing the demultiplexed data streams; or by multiplexing the data streams obtained from different RS encoding processes. The following will be described in detail with different embodiments:

[0090] (1) Directly demultiplex and process to obtain z second data streams.

[0091] In some optional examples, m first data streams are processed to obtain z second data streams by demultiplexing the m first data streams according to a second ratio to obtain z second data streams, where the second ratio is the reciprocal of the first ratio.

[0092] In this example, the second ratio is the ratio of m to z, and is the reciprocal of the first ratio. After the PMA layer obtains m first data streams through m input channels, it can directly demultiplex according to the second ratio to obtain data streams with the same number of channels as the physical coding sublayer, that is, z second data streams. For example, if the first ratio is 16:4, the second ratio should be 4:16. After obtaining 4 first data streams through 4 input channels, 16 second data streams can be demultiplexed according to the second ratio of 4:16. It should be noted that the bit length of each of the z second data streams is (N×codeword length of RS codeword) / z bits.

[0093] See also Figure 4A , is a schematic diagram of a data stream transmission provided in an embodiment of the present application. Figure 4A It can be seen that in the PMA layer, after obtaining m first data streams through m input channels, the first demultiplexing process is performed on the m first data streams according to the second ratio (for example: m / z) to obtain z second data streams. It should be noted that the first demultiplexing process may include but is not limited to DeMUX. Then, the inner code (Inner-FEC) sublayer independently performs inner code encoding processing on each of the z second data streams after demultiplexing. For details, please refer to the content described in the subsequent step 303 for understanding, which will not be repeated here. Then, the z third data streams are multiplexed to obtain n fourth data streams. For details, please refer to the content described in the subsequent step 304 for understanding, which will not be repeated here.

[0094] (2) The data stream obtained by the demultiplexing process is further delayed and multiplexed to obtain z second data streams.

[0095] In some optional examples, m first data streams are demultiplexed at the PMA layer according to the second ratio to obtain z second data streams, and the following method may also be adopted, namely: m first data streams are demultiplexed according to the second ratio to obtain z fifth data streams. Then, each fifth data stream in the z fifth data streams is subjected to Q-level processing to obtain z second data streams; wherein each level of processing in the Q-level processing includes performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, delaying the first sub-data stream to obtain the sixth data stream, and multiplexing the second sub-data stream and the sixth data stream to obtain the output data stream after the processing at this level, the first sub-data stream is at least one sub-data stream in the at least two sub-data streams, the second sub-data stream is one sub-data stream in the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is the data stream after the Q-level processing.

[0096] In this example, m first data streams are demultiplexed according to the second ratio to obtain z fifth data streams (for example, G1, G2, ..., G z ), please refer to the above Figure 4A The demultiplexing obtains the z-way second data stream for understanding, which will not be described in detail here.

[0097] Taking one of the fifth data streams (for example, G1) as an example, the PMA layer needs to perform the first-level round-robin distribution processing on the data stream obtained last time to obtain at least two sub-data streams, and delay processing on at least one of the sub-data streams to obtain the first-level sixth data stream. It should be noted that the data stream obtained at the previous level is obtained by performing round-robin distribution processing, delay processing and multiplexing processing on the fifth data stream of the previous level in sequence. The data stream obtained last time input to the first-level round-robin distribution processing can be understood as the fifth data stream G1. The data stream obtained last time input to the second-level round-robin distribution processing can be understood as the output data stream after the first-level first multiplexing processing. Then, one sub-data stream (i.e., the second sub-data stream) of the at least two sub-data streams that has not been delayed and the first-level sixth data stream are multiplexed to obtain the output data stream after the processing at this level. And so on, until the Q-level processing is performed, the corresponding second data stream can be obtained, that is, the second data stream is the data stream after the Q-level processing.

[0098] It should be noted that the Q-level processing described above can be understood as Q-level cascade processing or Q-level iterative processing. Figure 4B-4D The Q-level iterative processing can refer to the subsequent Figure 4E The following will be explained from different embodiments.

[0099] 1) Q-level cascade processing

[0100] Figure 4B Another schematic diagram of data stream transmission provided in the embodiment of the present application. Figure 4B It can be seen that in the above Figure 4AOn the basis of the structure shown, in the inner code sublayer, the first demultiplexing process is first performed on the m-way first data stream to obtain the z-way fifth data stream. Then, the z-way fifth data stream is processed together through the Q-level round-robin distribution process, the Q-level first delay process and the Q-level first multiplexing process to obtain the z-way second data stream. Specifically, after the first demultiplexing process demultiplexes the z-way fifth data stream, the z-way fifth data stream can be transmitted to the first-level round-robin distribution process through the z-way physical medium additional sublayer channel. It should be noted that the data stream obtained the previous time input to the first-level round-robin distribution process can be understood as the fifth data stream. In addition, the bit length of each level of processing in the Q-level cascade processing is (N×codeword length of RS codeword) / z bits.

[0101] Taking one of the fifth data streams (e.g., G1) as an example, the fifth data stream G1 is used as the input of the first-level round-robin distribution process, and the fifth data stream G1 is subjected to round-robin distribution processing by the first-level round-robin distribution process to obtain at least two first-level sub-data streams (e.g., G 11 1 , G 12 1 , G 13 1 , G 14 1 etc.) 11 1 and G 12 1 For example, one of the first-level sub-data streams (such as: G 11 1 ) as the input of the first-stage first delay processing, through which the sub-data stream G is processed 11 1 Delay processing is performed to output a first-level sixth data stream (for example: J1 1 ). Then, the first-level sixth data stream J1 1 and another first-level sub-data stream G 12 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J1 is processed by the first-stage first multiplexing process. 1 and another data stream G 12 1 After multiplexing, the first-level output data stream (for example, P1 1 ). It should be noted that the G 11 1 It can be understood as the first sub-data stream described above, the G 12 1 It can be understood as the second sub-data stream described above.

[0102] Then, the first-level output data stream P1 1 As the input of the second-stage round-robin distribution process, the first-stage output data stream P1 is processed by the second-stage round-robin distribution process. 1 Perform round-robin distribution processing to obtain at least two second-level sub-data streams (for example: G 11 2 , G 12 2 , G 13 2 , G 14 2 etc.) 11 2 and G 12 2 For example, one of the sub-data streams (such as: G 11 2 ) as the input of the second-stage first delay processing, through which the sub-data stream G is processed 11 2 Delay processing is performed to obtain a second-level sixth data stream (for example: J1 2 ). At this time, the second level sixth data stream J1 2 and another second-level sub-data stream G 12 2 As the input of the second-level second multiplexing process, through the multiplexing process of the second-level second multiplexing process, a second-level output data stream (for example: P1 2 ).

[0103] And so on, until the Q-1 level output data stream (for example: P1 Q-1 ) performs the Q-th level round-robin distribution processing, and the Q-th level can obtain at least two Q-th level sub-data streams (for example: G 11 Q , G 12 Q , G 13 Q , G 14 Q etc.) 11 Q and G 12 Q For example, one of the Q-level sub-data streams (such as: G 11 Q ) is used as the input of the Q-th stage first delay processing, and the Q-th stage sub-data stream G is processed by the Q-th stage first delay processing. 11 Q Delay processing is performed to output a sixth data stream of the Qth level (for example: J1 QThen, the Qth level sixth data stream J1 Q and another Q-level sub-data stream G 12 Q As the input of the Q-th level first multiplexing process, the Q-th level sixth data stream J1 is processed by the Q-th level first multiplexing process. Q and another Q-level sub-data stream G 12 Q By performing the multiplexing process, a data stream that is finally input into the encoding process, namely, the second data stream (eg, F1), can be obtained.

[0104] Similarly, for the fifth data streams of the remaining paths (eg, G2, ... G z ), or can be processed by the corresponding Q-level first delay processing and Q-level first multiplexing processing to obtain the corresponding second data stream. The specific processing process can be understood by referring to the processing process of the fifth data stream G1, which will not be described here.

[0105] Then, in the inner code sublayer, the obtained z-way second data streams are respectively and independently subjected to inner code encoding processing to obtain the corresponding z-way third data streams. The specific contents described in the subsequent step 303 can be understood, and no further description is given here. Then, the z-way third data streams are multiplexed to obtain the n-way fourth data streams, and the specific contents described in the subsequent step 304 can be understood, and no further description is given here.

[0106] It should be noted that in the process of performing any level of round-robin distribution processing, the granularity can be U bits, and the data stream input for the round-robin distribution processing of this level can be subjected to round-robin distribution processing according to the granularity. The mentioned U = w × N × (the bit length of a symbol in the RS codeword), w is a positive integer greater than or equal to 1. For example, taking the aforementioned first-level round-robin distribution processing as an example, if a fifth data stream (such as: G1) contains 4 RS codewords, a total of 136 symbols, and the bit length of each symbol is 10 bits. At this time, when w = 2, the granularity U = 80 bits. The sub-data stream G obtained after the round-robin distribution processing 11 1 , G 12 1 The length of each is 680 bits.

[0107] It should be noted that each level of the first multiplexing process in the Q-level first multiplexing process described above may include but is not limited to a symbol multiplexing unit (symbol MUX) or a bit multiplexing unit (bit MUX), etc. Each level of the first delay unit in the Q-level first delay process described above may also be understood as a buffer unit.

[0108] For example, Figure 4C Another schematic diagram of data stream transmission provided by an embodiment of the present application is shown. Figure 4C As shown, taking Q=1, z=16 as an example, after the 4 first data streams are subjected to the first demultiplexing process, 16 fifth data streams (for example: G1, G2, ... G 16 ). With the fifth data stream G 16 For example, in the inner code sublayer, the fifth data stream G 16 As the input of the first-level round-robin distribution process, the fifth data stream G1 is subjected to round-robin distribution processing by the first-level round-robin distribution process to obtain at least two first-level sub-data streams (for example: G 161 1 , G 162 1 , G 163 1 , G 164 1 etc.) 161 1 and G 162 1 For example, one of the first-level sub-data streams (such as: G 161 1 ) as the input of the first-stage first delay processing, through which the sub-data stream G is processed 161 1 Delay processing is performed to output a first-level sixth data stream (for example: J 16 1 ). Then, the first-level sixth data stream J 16 1 and another first-level sub-data stream G 162 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J is processed by the first-stage first multiplexing process. 161 1 and another data stream G 162 1 After multiplexing, a data stream that is finally input into the encoding process can be obtained, that is, the second data stream F 16 Then, the second data stream F after the multiplexing process is processed 16 The inner code encoding process is performed, and the details can be understood by referring to the contents described in the subsequent step 303, which will not be described here. 15 The processing process can also refer to the G 16 The processing process can be understood through the , which will not be elaborated here.

[0109] Alternatively, see Figure 4D, shows another schematic diagram of data stream transmission provided by an embodiment of the present application. Figure 4D As shown, taking Q=2, z=16 as an example, after the 4 first data streams are subjected to the first demultiplexing process, 16 fifth data streams (for example: G1, G2, ... G 16 ). With the fifth data stream G 16 For example, the fifth data stream G 16 As the input of the first-level round-robin distribution process, the fifth data stream G1 is subjected to round-robin distribution processing by the first-level round-robin distribution process to obtain at least two first-level sub-data streams (for example: G 161 1 , G 162 1 , G 163 1 , G 164 1 etc.) 161 1 and G 162 1 For example, one of the first-level sub-data streams (such as: G 161 1 ) as the input of the first-stage first delay processing, through which the sub-data stream G is processed 161 1 Delay processing is performed to output a first-level sixth data stream (for example: J 16 1 ). Then, the first-level sixth data stream J 16 1 and another first-level sub-data stream G 162 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J is processed by the first-stage first multiplexing process. 161 1 and another data stream G 162 1 After multiplexing, a first-level output data stream (for example: P 16 1 ). Further, the first-level output data stream P 16 1 As the input of the second-stage round-robin distribution process, the first-stage output data stream P1 is processed by the second-stage round-robin distribution process. 1 Perform round-robin distribution processing to obtain at least two second-level sub-data streams (for example: G 161 2 , G 162 2 , G 163 2 , G 1642 etc.) 161 2 and G 162 2 For example, one of the sub-data streams (such as: G 161 2 ) as the input of the first-stage first delay processing, through which the sub-data stream G is processed 161 2 Delay processing is performed to obtain a second-level sixth data stream (for example: J 16 2 ). At this time, the second level sixth data stream J 16 2 and another second-level sub-data stream G 162 2 As the input of the second-stage second multiplexing process, the second-stage second multiplexing process finally outputs a data stream that is finally input into the encoding process, that is, the second data stream, such as F 16 It should be noted that, then, the second data stream after the z-way multiplexing process is subjected to inner code encoding process, which can be understood by referring to the content described in the subsequent step 303, and will not be described in detail here.

[0110] Exemplarily, the number of bits of the sixth data stream described above is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of sub-data streams. Figure 4C For example, when Q=1, if the number of sub-data streams obtained after the first-level round-robin distribution processing is 4, then the first-level sub-data stream (such as G 161 1 , G 162 1 , G 163 1 , G 164 1 ) is (N×codeword length of RS codeword) / (z×4). Then the first-stage sixth data stream J 16 1 The bit length of is at least (N×codeword length of RS codeword) / (z×4) bits.

[0111] It should be understood that the above Figure 4C Take level one as an example. Figure 4D In practical applications, the value of Q can be any integer greater than or equal to 1, and the specific value can be determined according to the needs and is not limited here.

[0112] 2) Q-level iterative processing

[0113] Figure 4E Another schematic diagram of data stream transmission provided in the embodiment of the present application. Figure 4E It can be seen that in the above Figure 4A Based on the structure shown, in the inner code sublayer, the first demultiplexing process is first performed on m first data streams to obtain z fifth data streams. Then, the z fifth data streams are respectively subjected to Q-level iterative processing to obtain z second data streams.

[0114] Specifically, after the first demultiplexing process obtains the z fifth data streams through demultiplexing, the z fifth data streams can be transmitted to the first-level round-robin distribution process through the z physical medium additional sublayer channels. It should be noted that the data stream obtained the previous time input to the first-level round-robin distribution process can be understood as the fifth data stream. In addition, the bit length of each level of the Q-level iterative process is (N×codeword length of RS codeword) / z bits.

[0115] Taking one of the fifth data streams (e.g., G1) as an example, the fifth data stream G1 is used as the input of the first-level round-robin distribution process, and the fifth data stream G1 is subjected to round-robin distribution processing by the first-level round-robin distribution process to obtain at least two first-level sub-data streams (e.g., G 11 1 , G 12 1 etc.) 11 1 and G 12 1 For example, one of the first-level sub-data streams (such as: G 11 1 ) as the input of the first-stage first delay processing, through which the sub-data stream G is processed 11 1 Delay processing is performed to output a first-level sixth data stream (for example: J1 1 ). Then, the first-level sixth data stream J1 1 and another first-level sub-data stream G 12 1 As the input of the first-stage first multiplexing process, the first-stage sixth data stream J1 is processed by the first-stage first multiplexing process. 1 and another data stream G 12 1 After multiplexing, the first-level output data stream (for example, P1 1 ). It should be noted that the G 11 1 It can be understood as the first sub-data stream described above, the G 12 1It can be understood as the second sub-data stream described above.

[0116] Then, the first-level output data stream P1 1 Continue to serve as the input of the first-level round-robin distribution process, and continue to process the first-level output data stream P1 through the first-level round-robin distribution process. 1 Perform round-robin distribution processing to obtain at least two second-level sub-data streams (for example: G 11 2 , G 12 2 etc.) 11 2 and G 12 2 For example, one of the sub-data streams (such as: G 11 2 ) continues to be used as the input of the first stage first delay processing, and the first stage first delay processing is used to process the sub-data stream G 11 2 Delay processing is performed to obtain a second-level sixth data stream (for example: J1 2 ). At this time, the second level sixth data stream J1 2 and another second-level sub-data stream G 12 2 Continue to serve as the input of the first-level second multiplexing process, and through the multiplexing process of the first-level second multiplexing process, a second-level output data stream (for example: P1 2 ).

[0117] And so on, until the Q-1 level output data stream (for example: P1 Q-1 ) performs the Q-th level round-robin distribution processing, and the Q-th level can obtain at least two Q-th level sub-data streams (for example: G 11 Q , G 12 Q etc.) 11 Q and G 12 Q For example, one of the Q-level sub-data streams (such as: G 11 Q ) continues to be used as the input of the first-stage first delay processing, and the Q-th-stage sub-data stream G is processed by the first-stage first delay processing. 11 Q Delay processing is performed to output a sixth data stream of the Qth level (for example: J1 Q Then, the Qth level sixth data stream J1 Q and another Q-level sub-data stream G 12 QAs the input of the first-stage first multiplexing process, the Q-stage sixth data stream J1 is processed by the first-stage first multiplexing process. Q and another Q-level sub-data stream G 12 Q By performing multiplexing processing, a second data stream (eg, F1) can be obtained.

[0118] Similarly, for the fifth data streams of the remaining paths (eg, G2, ... G z ), or through the corresponding Q-level iterative processing, thereby obtaining the corresponding second data stream. The specific processing process can be understood by referring to the processing process of the fifth data stream G1, which will not be described here.

[0119] Then, in the inner code sublayer, the obtained z-way second data streams are respectively and independently subjected to inner code encoding processing to obtain the corresponding z-way third data streams. The specific contents described in the subsequent step 303 can be understood, and no further description is given here. Then, the z-way third data streams are multiplexed to obtain the n-way fourth data streams, and the specific contents described in the subsequent step 304 can be understood, and no further description is given here.

[0120] It should be noted that the bit length of the sixth data stream obtained in the Q-level iterative processing can also be understood by referring to the bit length of the sixth data stream obtained in the aforementioned Q-level cascade processing, which will not be elaborated here.

[0121] (3) Multiplexing the data streams obtained from different RS encoding processes to obtain z second data streams.

[0122] In some optional examples, the encoding method may also include: obtaining m-way seventh data streams through m-way first input channels; demultiplexing the m-way seventh data streams according to a second ratio to obtain z-way eighth data streams; processing the m-way first data streams to obtain z-way second data streams, including: multiplexing the z-way second data streams and the z-way eighth data streams to obtain the multiplexed z-way second data streams.

[0123] In this example, the m-way seventh data stream is obtained by multiplexing the z-way data stream after RS ​​encoding at the first ratio, which can be understood by referring to the m-way first data stream in the aforementioned step 301, and will not be described here. The data stream obtained from the MAC module is divided into two data streams of the same number at the PCS layer. For each part of the z-way data stream, the PCS layer sequentially completes 64B / 66B encoding, 256B / 257B transcoding, alignment mark AM insertion, and RS encoding on the z-way data stream. Then, the two parts of the z-way data stream obtained after RS ​​encoding are multiplexed according to the first ratio to obtain the m-way first data stream and the m-way seventh data stream. Then, the PCS layer transmits the m-way first data stream to the PMA layer through the m-way output channel, and transmits the m-way seventh data stream to the PMA layer through the m-way first output channel. In this way, after receiving the m first data streams sent by the PCS layer through the m input channels, the PMA layer demultiplexes the m first data streams according to the second ratio to obtain z second data streams. Figure 4A Moreover, after receiving the m-way seventh data stream through the m-way first input channel, the PMA layer also demultiplexes the m-way seventh data stream according to the second ratio to obtain the B-way eighth data stream. For details, please refer to the aforementioned Figure 4A Then, the PMA layer can multiplex the z-way second data stream and the z-way eighth data stream to obtain the multiplexed z-way second data stream.

[0124] For example, Figure 4F Another schematic diagram of data stream transmission provided by an embodiment of the present application is shown. Figure 4F It can be seen that in the above Figure 4A Based on the structure shown in FIG. 1 , in the PMA layer, the m-way seventh data stream is first subjected to a second demultiplexing process according to a second ratio to obtain z-way eighth data stream. Then, in the inner code sublayer of the PMA layer, the z-way second data stream and the z-way eighth data stream are subjected to a second multiplexing process to obtain z-way second data streams after multiplexing. For example, taking z=16 as an example, the 16-way second data streams are respectively represented as F1, F2, ..., F 16 The 16 eighth data streams are represented as W1, W2, ..., W 16. The second data stream F1 and the eighth data stream W1 can be subjected to a second multiplexing process to obtain a second data stream after processing. Similarly, the second data stream F2 and the eighth data stream W2 can also be subjected to a second multiplexing process to obtain another second data stream after processing. By analogy, 16 multiplexed second data streams can be obtained. Then, the z multiplexed second data streams are subjected to inner code encoding. The details can be understood by referring to the contents described in the subsequent step 303, which will not be described here.

[0125] In some possible examples, after multiplexing the z-way second data stream and the z-way eighth data stream to obtain the z-way second data stream after multiplexing, the encoding method may also include: independently performing Q-level processing on each of the z-way second data streams after the multiplexing process to obtain z-way twelfth data streams; wherein each level of processing in the Q-level processing includes performing round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, and delaying the fifth sub-data stream to obtain the thirteenth data stream, and multiplexing the sixth sub-data stream and the thirteenth data stream to obtain the output data stream after processing at this level, the fifth sub-data stream is at least one of the at least two sub-data streams, the sixth sub-data stream is one of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the multiplexed second data stream is a Q-level processed data stream; each of the z-way twelfth data streams is independently encoded to obtain z-way third data streams.

[0126] It should be noted that, here, each of the z-channel second data streams after the multiplexing process is independently subjected to Q-level processing, and the process of the Q-level processing can be specifically understood by referring to the content described in (2) above, which will not be described in detail here. In addition, each of the z-channel twelfth data streams is independently subjected to encoding processing, and the specific process can also be understood by referring to the content described in the subsequent step 303, which will not be described in detail here.

[0127] The bit length of the thirteenth data stream mentioned above is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of sub-data streams. The specific details can also be understood by referring to the sixth data stream described in (2) above, which will not be elaborated here.

[0128] It should be noted that the obtained z-way second data stream can be understood as a data stream that has not been processed by data alignment, de-skew or reordering. In the embodiment of the present application, in addition to using any of the above methods (1) to (3) to process the m-way first data stream to obtain the z-way second data stream, in actual applications, there may be other methods for processing, which are not limited here.

[0129] 303. Perform encoding processing on each of the z second data streams independently to obtain z third data streams.

[0130] In this example, C inner code sublayers are instantiated in the PMA layer according to the integer multiples of the number of physical coding sublayer channels, that is, C is an integer multiple of B. In this way, after the PMA layer obtains z second data streams, for each second data stream, C / z inner code sublayers can be formed into a one-to-one correspondence with one second data stream, and then C / z inner code sublayers are used separately to perform inner code encoding processing on the corresponding second data stream to generate a corresponding data stream after inner code encoding processing, that is, a third data stream.

[0131] It should be understood that after the inner code encoding process, the z-way third data stream is obtained, which can also be understood as each encoded data stream includes FEC codewords. In some possible examples, the inner code sublayer of the present application can also be called an inner code forward error correction code (inner-forward error correction, Inner-FEC) coding sublayer. In practical applications, other names can also be used, which are not specifically limited in this application. In addition, the inner code encoding process described can be understood as the second encoding in the cascade code, which constitutes a cascade code with the RS encoding described in the aforementioned step 301.

[0132] For example, if the processed second data stream is 16 channels, namely F1, F2, ..., F 16 At this time, in the inner code sublayer of the PMA layer, 16 inner code encoding processing operations are performed respectively, namely H1, H2, ... H 16 Then, the data stream F1 is processed by the inner coding operation H1, the data stream F2 is processed by the inner coding operation H2, and so on. 16 This inner code encoding operation is performed on the data stream F 16 In other examples, 32 inner code encoding operations may be performed in the inner code sublayer, namely H1, H2, H3, H4, ... H 31 , H 32 , and perform inner code encoding processing on data stream F1 through the two inner code encoding processing operations H1 and H2, and perform inner code encoding processing on data stream F2 through the two inner code encoding processing operations H3 and H4, and so on. 31 and H 32 These two inner code encoding operations have an effect on the data stream F 16Inner code encoding is performed. It should be noted that only 16 inner code encoding operations and 32 inner code encoding operations are used as examples for description. In practical applications, for 16 second data streams, 64 inner code encoding operations can also be performed in the inner code sublayer, and inner code encoding can be performed on each second data stream through 4 different inner code encoding operations. 128 inner code encoding operations can also be performed, as long as C satisfies an integer multiple of z, and no limitation is given here.

[0133] Alternatively, if the processed second data stream is 32 channels, namely F1, F2, ..., F 16 ,……,F 31 、F 32 At this time, in the inner code sublayer of the PMA layer, 32 inner code encoding processing operations are performed, namely H1, H2, ... H 32 Then, the data stream F1 is processed by the inner coding operation H1, and the data stream F2 is processed by the inner coding operation H2, and so on. 16 This inner code encoding operation is performed on the data stream F 16 Perform internal coding, ... and so on, through H 32 This inner code encoding operation is performed on the data stream F 32 In other examples, 64 inner code encoding operations may also be performed in the inner code sublayer, namely H1, H2, H3, H4, ... H 31 , H 64 , and the data stream F1 is processed by the two inner code sublayers H1 and H2, and the data stream F2 is processed by the two inner code sublayers H3 and H4, and so on. 63 and H 64 These two inner code encoding operations have an effect on the data stream F 32 Inner code encoding is performed. It should be noted that here only 32 inner code encoding operations and 64 inner code encoding operations are performed in the inner code sublayer as an example for description. In actual applications, 128 inner code encoding operations may be performed for 32 second data streams, and inner code encoding is performed on each second data stream through 4 different inner code encoding operations, etc., which is not limited here.

[0134] It should be noted that the above description only takes 16 second data streams and 32 second data streams as examples. In practical applications, other z second data streams may also be included, and the value of z depends on the requirements and is not limited here.

[0135] In some possible examples, since the inner code encoding process can actually be understood as inner code encoding of the data block to be encoded in the second data stream, and in order to enable the decoding sublayer to directly clarify the boundary position of each codeword in the subsequent decoding process to improve the decoding accuracy, different methods can be used for inner code encoding in different scenarios. Exemplarily, it can be understood by referring to the following two methods:

[0136] 1) Encoding a first data block to obtain an FEC codeword, wherein the first data block corresponds to at least C / z consecutive data blocks to be encoded in the second data stream, where C is a positive integer and C is an integer multiple of z; inserting a first identifier at a codeword boundary position of any FEC codeword in the FEC codeword, wherein the first identifier is used to identify the codeword boundary of the FEC codeword, and a throughput rate or a baud rate of the FEC codeword after inserting the first identifier is an integer multiple of a reference clock.

[0137] In this example, the first data block is at least C / z consecutive data blocks to be encoded in the corresponding second data stream, or can be understood as being composed of C / z consecutive data blocks to be encoded. Moreover, the length of the first data block is the sum of the lengths of the C / z consecutive data blocks to be encoded. For example, for each second data stream, a total of Y data blocks to be encoded are included, namely I1, I2, ..., I Y If the data blocks to be encoded are I1, I2, ..., I Y The length of each is k. Then, when the first data block is I1, the length of the corresponding first data block is k. Similarly, when the first data block is composed of I1 and I2, the length of the corresponding first data block is 2k. Y The lengths of each block are all k, and in practical applications, the length of each data block to be encoded may also be different, which is not limited here.

[0138] In addition, the number of obtained FEC codewords is related to the number of to-be-encoded data blocks constituting the first data block.

[0139] For example, if the processed second data stream is 16 channels, namely F1, F2, ..., F 16 Then, for the second data stream F1, there are a total of Y data blocks to be encoded, namely I1, I2, ..., I Y If 16 inner code encoding operations are performed in the inner code sublayer, namely H1, H2, ... H 16 , then the first data block can be understood as I1, I2, ..., I YOne of the Y data blocks to be encoded. In this way, each inner code encoding operation can be performed on one of the first data blocks to obtain a corresponding FEC codeword. At this time, the FEC codeword obtained by each inner code encoding operation is one. For example, Figure 5A Schematic diagram of performing inner code encoding processing operation in the embodiment of the present application. Figure 5A It can be seen that the inner code encoding processing operation H1 can be performed on the data block I1 to be encoded (for example, k bits) in the second data stream F1, and at this time, one FEC codeword (for example, FEC codeword 1) can be obtained; the inner code encoding processing operation H2 can be performed on the data block I2 to be encoded in the second data stream F2, and at this time, one FEC codeword can be obtained; ... and so on, the inner code encoding processing operation H1 can be performed on the data block I2 to be encoded in the second data stream F2, and at this time, one FEC codeword can be obtained. 16 The second data stream F 16 The data block to be encoded in I 16 Inner code encoding is performed, and 1 FEC codeword can be obtained at this time. It should be noted that in this application, only the inner code encoding operation H1 is used to perform inner code encoding on the coded data block I1 as an example. In actual applications, the inner code encoding operation H1 can also perform inner code encoding on the coded data block I2 or I3, etc., which is not limited here. In addition, the remaining inner code encoding operations can also be understood with reference to the inner code encoding operation H1, which is not repeated here. In addition, the remaining second data streams F2, ..., F 16 In fact, it can also be understood by referring to the second data stream F1, which will not be elaborated here.

[0140] Alternatively, if the processed second data stream is still 16-channel, but 32 inner code encoding processing operations are performed in the inner code sublayer. Then, the first data block can be understood as I1, I2, ..., I Y At least two consecutive data blocks to be encoded among the Y data blocks to be encoded. For example, the first data block can be composed of I1 and I2, or I3 and I4, etc., which is not limited here. Figure 5B FIG. 2 is another schematic diagram of performing an inner code encoding process in an embodiment of the present application. Figure 5B It can be seen that the inner code encoding processing operations H1 and H2 can be performed on the first data block (for example, k+k bits) composed of I1 and I2 in the second data stream F1, and two FEC code words (for example, FEC code word 1 and FEC code word 2) can be obtained; the inner code encoding processing operations H3 and H4 can be performed on the first data block composed of I3 and I4 in the second data stream F2, and two FEC code words can be obtained; and so on, the inner code encoding processing operations H3 and H4 can be performed on the first data block composed of I3 and I4 in the second data stream F2, and two FEC code words can be obtained. 31 and H32 The second data stream F 16 In, by I 31 and I 32 It should be noted that in this application, only the inner coding operation H1 is used to perform inner coding on the first data block composed of I1 and I2. In actual applications, the inner coding operations H1 and H2 can also be performed on the first data block composed of I3 and I4 in the second data stream F1, or on the first data block composed of I3 and I4 in the second data stream F1. 31 and I 32 The first data block composed of the inner code encoding process is processed, which is not limited here. In addition, the remaining inner code encoding process operations can also be understood by referring to the inner code encoding process operation H1, which is not repeated here. In addition, the remaining second data streams F2, ..., F 16 In fact, it can also be understood by referring to the second data stream F1, which will not be elaborated here.

[0141] Alternatively, if the processed second data stream is still 16-channel, 64 inner code encoding processing operations can also be performed in the inner code sublayer, and the first data block can be understood as I1, I2, ..., I Y Four consecutive data blocks to be encoded among the Y data blocks to be encoded. For example, the first data block can be composed of I1, I2, I3 and I4, or I5, I6, I7 and I8, and so on, which is not limited here. At this time, the inner code encoding processing operations H1 to H4 can be performed on the first data block (for example, k+k+k+k bits) composed of I1, I2, I3 and I4 in the second data stream F1 to perform inner code encoding processing, and four FEC code words can be obtained. The inner code encoding processing operations H5 to H8 can be performed on the first data block composed of I5, I6, I7 and I8 in the second data stream F2 to perform inner code encoding processing, and four FEC code words can be obtained; ... and so on, the inner code encoding processing operations H1 to H4 can be performed on the first data block (for example, k+k+k+k bits) composed of I1, I2, I3 and I4 in the second data stream F1 to perform inner code encoding processing, and four FEC code words can be obtained; ... and so on, the inner code encoding processing operations H5 to H8 can be performed on the first data block (for example, k+k+k+k bits) composed of I5, I6, I7 and I8 in the second data stream F2 to perform inner code encoding processing, and four FEC code words can be obtained; and so on, the inner code encoding processing operations H 61 To H 64 The second data stream F 16 In, by I 61 ,I 62 ,I 63 and I 64It should be noted that in this application, only the inner code encoding operations H1 to H4 are used to perform inner code encoding on the first data block composed of I1, I2, I3 and I4 in the second data stream F1. In actual applications, the inner code encoding operations H1 to H4 can also be performed on the first data block composed of I5, I6, I7 and I8 in the second data stream F1, or the first data block composed of I 61 ,I 62 ,I 63 and I 64 The first data block composed of the inner code encoding process is processed, which is not limited here. In addition, the remaining inner code encoding process operations can also be understood by referring to the inner code encoding process operation H1, which is not repeated here. In addition, the remaining second data streams F2, ..., F 16 In fact, it can also be understood by referring to the second data stream F1, which will not be elaborated here.

[0142] It should be noted that the above only takes B=16 as an example. In actual applications, it can also be 32 second data streams, 64 second data streams, etc. The specific details can be understood by referring to the content of the aforementioned 16 second data streams, which will not be repeated here.

[0143] In this way, after obtaining the FEC codeword, the first identifier can be inserted into the codeword boundary position of any FEC codeword in the FEC codeword. Figure 5A As shown, the first marker may be inserted into the codeword boundary position of the FEC codeword (eg, FEC codeword 1) obtained by performing the inner code encoding operation H1. Figure 5B As shown, the first identifier can also be inserted at the codeword boundary position of any one of the two FEC codewords (such as FEC codeword 1 and FEC codeword 2) obtained by performing the inner code encoding processing operation H1. For example, the first identifier is inserted at the codeword boundary position of FEC codeword 1, or the first identifier is inserted at the codeword boundary position of FEC codeword 2, etc., which is not limited here. It should be noted that inserting the first identifier at the codeword boundary position of any one of the FEC codewords can also be understood as inserting a first identifier every C / z FEC codewords.

[0144] It should be noted that the throughput or baud rate of the FEC codeword after the first identifier is inserted is an integer multiple of the reference clock. For example, if the data transmission rate is expressed in terms of throughput, assuming that the throughput of the data stream in the PCS layer is 850Gbps, then the throughput of the FEC codeword after the first identifier is inserted can be 910Gbps. Or when the data transmission rate is expressed in terms of baud rate, the baud rate of each physical coding sublayer channel in the PCS layer is 26.5625Gbaud. After the inner code encoding process, the total length of the FEC codeword is 180 bits. After the first identifier is inserted, the total length of the FEC codeword after the first identifier is inserted can become 182 bits. At this time, the baud rate of each corresponding physical coding sublayer channel becomes 28.4375Gbaud. For another example, assuming that the throughput of the data stream in the PCS layer is 850Gbps, then the throughput of the FEC codeword after the first identifier is inserted can be 900Gbps. Or when the data transmission rate is expressed in baud rate, the baud rate of each physical coding sublayer channel in the PCS layer is 26.5625 Gbaud. After the inner code encoding process, the total length of the FEC codeword is 179 bits. After the first identifier is inserted, the total length of the FEC codeword after the first identifier is inserted can become 180 bits. At this time, the baud rate of each corresponding physical coding sublayer channel becomes 28.125 Gbaud.

[0145] Here, only the throughput rate of 850Gbps and the baud rate of 26.5625Gbaud are used as examples for illustration. In practical applications, the transmission rate of the data stream in the PCS layer should be related to the load of the RS codeword. In addition, here, only the throughput rate of the FEC codeword after inserting the first identifier is 910Gbps and 900Gbps as examples, and only the baud rate of each physical coding sublayer channel is changed to 26.5625Gbaud and 28.125Gbaud as examples for illustration. This application does not make specific limitations. The reference clock described can be understood as 156.25 megahertz (MHz), and in practical applications, it may also be other values, which are not limited here.

[0146] The reference clock above indicates the frequency of data stream transmission, that is, the number of times it can be transmitted per second. Both baud rate and throughput rate can indicate the transmission rate of data stream, where throughput rate indicates the number of bits transmitted per second and baud rate indicates the number of symbols transmitted per second. For example, 5 symbols can be transmitted each time, and 10 times per second, so a total of 50 symbols can be transmitted per second.

[0147] In addition, the codeword boundary position can be understood as the codeword beginning and / or codeword end, which is not limited here. The codeword boundary of the FEC codeword is identified by the first identifier, so that the first identifier can be directly identified in the subsequent decoding process, and the boundary position of each FEC codeword can be clearly identified, avoiding the failure of inner code decoding in the case of delay skew and unknown data starting position.

[0148] It should be understood that the first identifier mentioned above may be a preset identifier sequence, or may be obtained according to the bit value of the first data block.

[0149] ①The first identifier is a preset identifier sequence.

[0150] In this example, the first identifier may be a sequence of "1" and "0" or other known sequences, which are not limited here. Fig. 6A FIG. 1 is a schematic diagram of inserting a first identifier provided in an embodiment of the present application. Fig. 6A As shown, the first identifier, i.e., a sequence of "1" and "0", is added at the beginning of the codeword in the FEC codeword, and the first identifier occupies two bits. Therefore, after adding the first identifier at the codeword boundary position of the FEC codeword, the total length of the codeword changes from n bits to n+2 bits. For example, if the length of the first data block is 170, after the inner code encoding process, the total length of the FEC codeword is 180. Now after inserting the first identifier, the length of the entire FEC codeword after inserting the first identifier becomes 182 bits.

[0151] It should be noted that, when the first identifier is a preset identifier sequence, the first identifier may also be selected as a sequence such as "101010", "1010", etc., which is not limited here.

[0152] ② The first identifier is obtained according to the bit value of the first data block.

[0153] In this example, different first identifiers may be obtained for different bit values ​​in the first data block. Specifically, the first identifiers may be determined in the following two ways, namely:

[0154] The first way: the first identifier is obtained according to the value of the first bit of the first data block. It should be noted that the first bit is any one of the at least one bit in the first data block.

[0155] For example, Figure 6B A schematic diagram showing a method for obtaining a value of a first identifier provided in an embodiment of the present application is shown. Figure 6BIt can be seen that the first bit can be the 0th bit in the first data block. If the value of the 0th bit is "0", the first identifier, that is, "1", can be obtained by directly negating the value of the 0th bit. Alternatively, if the value of the 0th bit is "1", the first identifier, that is, "0", can be obtained by directly negating the value of the 0th bit. The specifics are not limited here. In addition, Figure 6B Only the 0th bit is used as the first bit for illustration. In practical applications, the first bit may also be the 1st bit, the 2nd bit, etc. in the first data block, which is not limited here. For example, if the length of the first data block is 180 bits, the last bit can be selected to be inverted, that is, the value of the 179th bit is directly inverted to obtain the first identifier. The first identifier is obtained by inverting the bit at the very beginning or the very end of the first data block, which helps the PMA layer at the receiving end to quickly determine the codeword boundary.

[0156] The second method: the first identifier is obtained based on the bit values ​​of at least L second bits in the first data block, wherein there are s bits between each two adjacent second bits of the L second bits, L≥2, s≥0, and L and s are integers.

[0157] In this example, in the first data block, a second bit is selected every s bits, and a total of L second bits are selected. In this way, the L second bits are processed by an XOR operation, an OR operation, or an AND operation to obtain the first identifier.

[0158] For example, Figure 6C A schematic diagram showing another method for obtaining a value of the first identifier provided in an embodiment of the present application is shown. Figure 6C It can be seen that when L=4, s=2, the four second bits selected from the first data block are bit 0, bit 2, bit 4, and bit 6. In this way, the bit values ​​corresponding to bit 0, bit 2, bit 4, and bit 6 are processed by XOR operation, and the result of the processing can be used as the first identifier. It should be noted that in some examples, the four second bits selected may also be bit 1, bit 3, bit 5, bit 7, etc., which is not limited here.

[0159] Need to explain, Figure 6C The example of L being 4 and s being 2 is used for illustration. In practical applications, L may also be 8 and s may be 3, or L may be 6 and s may be 4, etc. The present application does not limit the value of L or the value of s.

[0160] In addition, in addition to the above-mentioned ① and ② to determine the first identifier, there may be other ways to clarify the first identifier in practical applications, which are not specifically limited in this application.

[0161] The above 1) mainly describes a scheme in which the first data block is firstly encoded with an inner code and then the first identifier is inserted. The following describes a scheme in which the first identifier is also involved in the inner code encoding. The details are as follows:

[0162] 2) inserting a first identifier into each data block to be encoded in the first data block to obtain a second data block, wherein the first data block is C / z consecutive data blocks to be encoded, C is a positive integer, and C is an integer multiple of z; performing inner code encoding on the second data block to obtain an FEC codeword. It should be noted that the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock.

[0163] In this example, the second data block can be understood as consisting of the first data block and the first identifier, and the length of the second data block is the sum of the length of the first data block and the bits occupied by the first identifier. In this way, the first identifier is inserted into each data block to be encoded in the first data block. For example, Figure 5B When the first data block shown is composed of the to-be-encoded data blocks I1 and I2, the first identifier can be inserted at the codeword boundary position of the to-be-encoded data block I1, and the first identifier can be inserted at the codeword boundary position of the to-be-encoded data block I2. If the length of the first data block is k (i.e., the first data block occupies k bits) and the first identifier occupies 1 bit, then the length of the second data block is k+2 bits.

[0164] For the second data block in each second data stream, the second data block can be processed by inner code encoding, which can be understood by referring to the process of inner code encoding of the first data block in the above 1), which will not be described in detail here. In addition, the first data block can be understood by referring to the content in the above 1), which will not be described in detail here. In addition, the first identifier can also be understood by referring to the content described in the above ① and ②, which will not be described in detail here.

[0165] In some other possible examples, the described encoding method may further include: identifying an alignment mark in each second data stream, the alignment mark being used to identify a symbol boundary in the corresponding second data stream; and determining a symbol boundary in the corresponding second data stream based on the alignment mark.

[0166] In this example, the PCS layer adds a common alignment marker of the AM alignment block to each of the m first data streams. After the m first data streams are mapped to obtain the z second data streams, each second data stream includes a corresponding alignment marker, which identifies the symbol boundary in each second data stream. Therefore, after the PMA layer passes through the aforementioned 4A to 4FAfter processing the m first data streams in any possible way to obtain the z second data streams, the alignment marker included in each second data stream can also be identified. After identifying the corresponding alignment marker, the alignment marker is locked to determine the symbol boundary in the corresponding second data stream. For example, a 120-bit AM alignment block with a known sequence is added to each first data stream, and in this 120-bit AM alignment block with a known sequence, there is a 48-bit common alignment marker. Then in the operation that only requires the symbol boundary of the RS code word, the alignment can be locked by identifying the 48-bit common alignment marker.

[0167] Then, the z second data streams are respectively and independently subjected to inner code encoding processing. Please refer to the contents described in the aforementioned step 303 for details, which will not be described in detail here.

[0168] For example, Figure 7 Another schematic diagram of data stream transmission provided in the embodiment of the present application is shown in FIG. Figure 7 As shown in the aforementioned Figure 4A-4F Based on any of the described embodiments, in the inner code sublayer of the PMA layer, the z second data streams may be aligned respectively, and then independently inner code encoded.

[0169] 304. Multiplex the z third data streams to obtain n fourth data streams, where n is a positive integer.

[0170] In this example, after the PMA layer obtains z third data streams, if it wants to send them to the receiving end through n output channels, the PMA layer still needs to multiplex the z third data streams to obtain n fourth data streams, and then transmit the n fourth data streams to the PMA layer at the receiving end through the n output channels.

[0171] Exemplarily, the PMA layer multiplexes the z-channel third data stream according to the third ratio (i.e., z / n) to obtain n-channel fourth data streams. Alternatively, the PMA layer may first multiplex the z-channel third data stream according to the fourth ratio (i.e., z / m) to obtain m-channel data streams, and then multiplex and process the m-channel data streams according to the fifth ratio (i.e., m / n) to obtain n-channel fourth data streams. The specific method is not limited in this application. It should be noted that the described n can take values ​​of 4, 8, 16, etc., which are not limited here.

[0172] For example, Figure 8 Figure 1 is a schematic diagram of the overall transmission of data streams in the PMA layer. Figure 8As shown, the first data stream of z channels is obtained through m input channels, and the first demultiplexing processing is performed on the first data stream of m channels according to the ratio of m / z, thereby obtaining the PCS lane data stream of z channels, i.e., the second data stream of z channels. Then, C inner code encoding processing operations in the inner code sublayer are executed to realize the independent encoding processing of the PCS lane data stream of z channels, and obtain the third data stream of z channels. The inner code encoding processing of each PCS lane data stream is realized by C / z inner code encoding processing operations. Then, the third data stream of z channels is multiplexed according to z / n, and the fourth data stream of n channels is obtained, and is transmitted through the n output channels.

[0173] Above Figure 3-Figure 8 The encoding method provided by the embodiment of the present application is mainly described. The decoding method provided by the embodiment of the present application will be described below. Fig. 9 A flowchart of a decoding method provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the decoding method may include the following steps:

[0174] 901. Obtain n fourth data streams through n input channels.

[0175] In this example, after the PMA layer at the transmitting end obtains n fourth data streams, it can send these n fourth data streams to the PMD layer. After the n fourth data streams are processed by the PMD layer such as photoelectric conversion, the signals can be transmitted to the PMD layer at the receiving end through the transmission medium. Then, at the receiving end, the PMD layer converts the signals received from the transmission medium to obtain n fourth data streams. Then, the PMD layer can transmit these n fourth data streams to the PMA layer at the receiving end through n output channels. In this way, the PMA layer can obtain n fourth data streams through n input channels.

[0176] 902. Demultiplex n fourth data streams to obtain z third data streams.

[0177] After the PMA layer obtains n fourth data streams, the n fourth data streams can be demultiplexed according to the inverse of the third ratio to obtain z third data streams. The third ratio described can refer to the aforementioned Figure 3 The step 304 in FIG. 1 is understood and will not be described in detail here.

[0178] 903. Decode each of the z third data streams independently to obtain z second data streams.

[0179] In this example, the decoding process is as follows: Figure 3For the z third data streams, C inner code decoding processing operations can also be performed in the inner code sublayer, so that the inner code decoding processing can be performed independently on the third data stream by performing different C / z inner code decoding processing operations.

[0180] In some other possible examples, the decoding method may further include: identifying a codeword boundary of the encoded FEC according to the first identifier and / or a decoding flag bit, where the decoding flag bit is used to indicate whether the inner code decoding process is successful.

[0181] Since the corresponding first identifier is included in each of the z third data streams. In the process of decoding the corresponding third data stream, by identifying the first identifier and / or the decoding flag, the codeword boundary position of the FEC codeword in each third data stream can be known, further improving the decoding efficiency and decoding accuracy. For example, when the PMA layer recognizes that each identifier value in the first identifier is correct, it can further determine whether the inner code decoding process is successful through the decoding flag. And when the decoding flag indicates that the inner code decoding process is successful, the codeword boundary of the FEC codeword is identified based on the first identifier, and then the encoded FEC codeword is decoded.

[0182] It should be noted that the identification of the codeword boundary of the encoded FEC according to the first identifier and / or the decoding flag can be understood in three cases. That is, ① the codeword boundary of the encoded FEC can be identified according to the first identifier; ② the codeword boundary of the encoded FEC can be identified according to the decoding flag; ③ the codeword boundary of the encoded FEC can be identified according to the first identifier and the decoding flag. This application does not limit which method is used. In addition, the above-mentioned decoding flag can be fed back during the decoding process, or it can not be fed back, which is not limited here.

[0183] 904. Multiplex the z second data streams according to the first ratio to obtain m first data streams.

[0184] In this example, after obtaining z second data streams, the PMA layer multiplexes the z second data streams according to a first ratio to obtain m first data streams. Exemplarily, when z=16, the first ratio may be 16:4, and 4 first data streams are obtained through multiplexing.

[0185] See also Fig. 10A , is a transmission diagram of a data stream in the decoding process provided by an embodiment of the present application. Fig. 10A It can be seen that the n fourth data streams are first demultiplexed to obtain z third data streams. Then, the z third data streams are respectively inner-coded and decoded in the inner-code sublayer to obtain z second data streams. Finally, the z second data streams are processed.

[0186] In some other optional examples, since an electrical signal is obtained after the photoelectric conversion of the PMD layer, the electrical signal first needs to pass through the CDR unit for data and clock recovery operations. The shorter the time required for the CDR unit to recover the clock and data, the more beneficial it is to the system. Based on this, the decoding method may also include: before identifying the codeword boundary of the FEC codeword according to the first identifier and / or the decoding flag bit, generating a first signal according to the first identifier and / or the decoding flag bit, and the first signal is used to determine the data clock information.

[0187] Fig. 10B Another transmission schematic diagram of data stream in the decoding process provided by the embodiment of the present application is shown. Fig. 10B It can be seen that in the above Fig. 10A On the basis of the figure, before the z-channel third data stream obtained by demultiplexing, the n-channel fourth data stream is first subjected to clock data recovery processing. Then the n-channel fourth data stream after clock recovery processing is demultiplexed to obtain the z-channel third data stream, and then the z-channel third data stream is independently subjected to inner code decoding processing. It should be noted that the CDR unit is uniquely corresponding to the data stream transmitted in the input channel. Since each input channel has a unique corresponding relationship with the physical coding sublayer channel, and each physical coding sublayer channel corresponds to C / z inner code decoding processing operations. Therefore, the decoding unit connected to each CDR unit is also fixed and can be connected by a connection. For example, the PMD layer has 4 input channels and the PMA layer has 16 physical coding sublayer channels. If 32 inner code decoding processing operations can be performed in the inner code sublayer, then each physical coding sublayer channel is correspondingly connected to 2 decoding units. In the process of recovering data and clock through the CDR unit, the first identifier and / or decoding flag bit can be detected by the inner code sublayer first, and then a feedback signal, i.e., a first signal, is generated. At this time, when the CDR unit receives the first signal, it can speed up the data and clock recovery process of the CDR unit, determine the data clock information in advance, and reduce the time required for system locking. In addition, since the first identifier of the present application is designed to generate a sequence, it not only takes into account the autocorrelation characteristics of the sequence corresponding to the first identifier, which helps the first identifier to be detected more quickly, but also takes into account that the first identifier contains a fixed 0,1 jump characteristic, which improves the convergence speed of the data clock recovery of the CDR unit.

[0188] In addition, if the CDR unit receives its own feedback signal for normal data and clock recovery before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal data and clock recovery to complete the data and clock recovery operation.

[0189] In other examples, after obtaining m-channel first data streams, the PMA layer can also send the m-channel first data streams to the PCS layer through m-channel output channels. In this way, after the PCS layer obtains the m-channel first data streams through m-channel input channels, it demultiplexes the m-channel first data streams according to the second ratio, thereby obtaining z-channel eleventh data streams. It should be noted that the z-channel eleventh data stream described corresponds to the z-channel data stream obtained after RS ​​encoding processing. The PCS layer can also further process the z-channel eleventh data streams in sequence through RS decoding processing, 256B / 257B transcoding processing, and 64B / 66B encoding processing. For details, please refer to the aforementioned Figure 1A To understand.

[0190] Compared to Figure 1A-1B The existing scheme shown, in the embodiment of the present application, each of the z second data streams is independently processed with inner code in the PMA layer to obtain z third data streams; and the FEC codewords in each encoded third data stream contain boundary identifiers, which not only ensures the decoupling of the inner code encoding from the data encoded by the upper PCS layer, but also ensures the transmission decoupling of the inner code encoding from the lower PMD layer, which can save the delay of processing delay skew and disorder, making the inner code encoding and decoding of the present application suitable for scenarios sensitive to transmission delay. In addition, it is only necessary to identify the boundary identifier in each third data stream to clarify the codeword boundary of each third data stream, and realize the independent inner code decoding processing of each third data stream in the z third data streams, without the need to perform de-skew, reordering and other operations on the data stream, reducing the operation complexity and delay.

[0191] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. It can be understood that in order to realize the above functions, the above-mentioned PMA layer includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the functions described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0192] Described from the perspective of a physical device, the above-mentioned PMA layer can be specifically implemented by a physical device, such as an optical module, or other encoding devices, decoding devices, etc., or it can be implemented by multiple physical devices together, or it can be a logical functional unit within a physical device. The embodiments of the present application do not make specific limitations on this.

[0193] For example, the above-mentioned PMA layer can be composed of Fig.11This is achieved by the communication equipment in the system. Fig.11 The hardware structure diagram of the communication device provided in the embodiment of the present application is as follows. The communication device includes at least one processor 1101, a memory 1102 and a transceiver 1103.

[0194] The processor 1101 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (application-specific integrated circuit), or one or more integrated circuits for controlling the execution of the program of the present application. The processor 1101 can perform operations such as judgment, analysis, and calculation, including processing m first data streams to obtain z second data streams; and independently performing inner code encoding processing on each second data stream in the z second data streams to obtain z third data streams, etc.

[0195] The transceiver 1103 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc. The transceiver 1103 can be connected to the processor 1101. The transceiver 1103 can obtain m first data streams, etc.

[0196] The memory 1102 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1102 may exist independently or be connected to the processor 1101. The memory 1102 may also be integrated with the processor 1101.

[0197] The memory 1102 is used to store computer-executable instructions for executing the solution of the present application, and the execution is controlled by the processor 1101. The processor 1101 is used to execute the computer-executable instructions stored in the memory 1102, thereby implementing the encoding method and decoding method provided by the above method embodiment of the present application.

[0198] In a possible implementation manner, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0199] In a specific implementation, as an embodiment, the processor 1101 may include one or more CPUs, such as Fig.11 CPU0 and CPU1 in.

[0200] From the perspective of functional units, the present application can divide the PMA layer into functional units according to the above method embodiments. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one functional unit. The above integrated functional unit can be implemented in the form of hardware or software functional units.

[0201] For example, when each functional unit is divided in an integrated manner, Fig.12 FIG. 1 is a schematic diagram showing the structure of a coding device provided in an embodiment of the present application. Fig.12 As shown, an embodiment of the encoding device of the present application may include: a first acquisition unit 1201 and a first processing unit 1202.

[0202] The first acquisition unit 1201 is used to acquire m first data streams through m input channels, where m is a positive integer. Figure 3 The content of step 301 in FIG. 1 can be understood through the above, and will not be repeated here.

[0203] The first processing unit 1202 is used to process the m first data streams to obtain z second data streams, and independently encode each of the z second data streams to obtain z third data streams; multiplex the z third data streams to obtain n fourth data streams, where n and z are both positive integers. Figure 3 The contents of steps 302-304 in FIG. 1 can be understood through the description of FIG.

[0204] In some possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit 1202 is used to: encode the first data block to obtain an FEC codeword, the first data block corresponds to at least C / z consecutive data blocks to be encoded in the second data stream, C is a positive integer, and C is an integer multiple of z; insert a first identifier at the codeword boundary position of any FEC codeword in the FEC codeword, the first identifier is used to identify the codeword boundary of the FEC codeword, and the throughput rate or baud rate of the FEC codeword after inserting the first identifier is an integer multiple of the reference clock. For details, please refer to the aforementioned Figure 3 The content of step 303 in FIG. 1 can be understood through the above, and will not be repeated here.

[0205] In some possible implementations, each of the z second data streams includes a data block to be encoded; the first processing unit 1202 is used to: insert a first identifier into each data block to be encoded in the first data block to obtain a second data block, the first data block is C / z consecutive data blocks to be encoded, C is a positive integer, and C is an integer multiple of z; encode the second data block to obtain an FEC codeword, the throughput rate or baud rate of the FEC codeword is an integer multiple of the reference clock. For details, please refer to the aforementioned Figure 3 The content of step 303 in FIG. 1 can be understood through the above, and will not be repeated here.

[0206] In some possible implementations, the first identifier is a preset identifier sequence. Figure 3 The content of step 303 in FIG. 1 can be understood through the above, and will not be repeated here.

[0207] In some possible implementations, the first identifier is obtained based on the value of the first bit of the first data block, where the first bit is any one of at least one bit in the first data block; or, the first identifier is obtained based on the bit values ​​of at least L second bits in the first data block, where there are s bits between each two adjacent second bits of the L second bits, L≥2, s≥0, and L and s are integers. For details, please refer to the aforementioned Figure 3 The content of step 303 in FIG. 1 can be understood through the above, and will not be repeated here.

[0208] In some possible implementations, the first processing unit 1202 is configured to perform demultiplexing processing on m first data streams according to a second ratio to obtain z second data streams, where the second ratio is a ratio of m to z.

[0209] In some possible implementations, the first processing unit 1202 is used to: demultiplex the m first data streams according to the second ratio to obtain z fifth data streams; independently perform Q-level processing on each of the z fifth data streams to obtain z second data streams; wherein each level of processing in the Q-level processing includes round-robin distribution processing on the data stream obtained at the previous level to obtain at least two sub-data streams, and delay processing on the first sub-data stream to obtain a sixth data stream, and multiplex processing on the second sub-data stream and the sixth data stream to obtain an output data stream after processing at this level, the first sub-data stream is at least one sub-data stream of the at least two sub-data streams, the second sub-data stream is one sub-data stream of the at least two sub-data streams that has not been delayed, Q is a positive integer, and the second data stream is a data stream after Q-level processing.

[0210] In some possible implementations, the bit length of the sixth data stream is at least (N×codeword length of RS codeword) / (z×i) bits, where N is a positive integer and i is the number of the sub-data streams.

[0211] In some possible implementations, the first acquisition unit 1201 is further configured to acquire m seventh data streams through the m input channels. The first processing unit 1202 is configured to demultiplex the m seventh data streams according to the second ratio to obtain z eighth data streams; and multiplex the z second data streams and the z eighth data streams to obtain z second data streams after multiplexing.

[0212] In some possible implementations, the first processing unit 1202 is further used to: identify an alignment mark in each second data stream, the alignment mark being used to identify a symbol boundary in the corresponding second data stream; and determine a symbol boundary in the corresponding second data stream based on the alignment mark.

[0213] In some possible implementations, the m-channel first data streams are obtained by multiplexing z-channel data streams that are Reed-Solomon (RS) encoded at a first ratio.

[0214] The encoding device provided in the embodiment of the present application is used to perform Figure 3 The encoding method in the corresponding method embodiment, so the embodiment of this application can refer to Figure 3 The relevant parts of the corresponding method embodiments are understood.

[0215] The above mainly describes the encoding device provided by the embodiment of the present application from the perspective of functional modules. The following will describe the decoding device provided by the embodiment of the present application from the perspective of functional modules. Fig.13 FIG. 2 shows a schematic diagram of the structure of a decoding device provided in an embodiment of the present application. Fig.13As shown, an embodiment of the decoding device of the present application may include: a second acquisition unit 1301 and a second processing unit 1302.

[0216] The second acquisition unit 1301 is used to acquire n fourth data streams through n input channels. Fig. 9 The content of step 901 in FIG. 1 can be understood through the above, and will not be repeated here.

[0217] The second processing unit 1302 is used to: demultiplex the n fourth data streams to obtain z third data streams; independently decode each of the z third data streams to obtain the z second data streams; multiplex the z second data streams according to the first ratio to obtain the m first data streams, wherein the first ratio and the second ratio are reciprocal. Fig. 9 The contents of steps 902-904 in FIG. 1 can be understood through the description of FIG.

[0218] In some possible implementations, the z-path third data stream includes a first identifier, and the first identifier is used to identify the codeword boundary of the FEC codeword; the second processing unit 1302 is also used to: identify the codeword boundary of the FEC codeword according to the first identifier and / or the decoding flag bit, and the decoding flag bit is used to indicate whether the decoding process is successful.

[0219] In some other possible implementations, the second processing unit 1302 is also used to generate a first signal according to the first identifier and / or the decoding flag bit before identifying the codeword boundary of the FEC codeword according to the first identifier and / or the decoding flag bit, and the first signal is used to determine the data clock information. It should be noted that the data clock information can be determined by the first signal, so that the CDR unit accelerates the data and clock recovery process, determines the data clock information in advance, reduces the time required for system locking, and is conducive to determining the frequency of system transmission in advance. In addition, since the first identifier of the present application is designed in a sequence generation method, it is helpful for the first identifier to be detected more quickly; and it is considered that the first identifier contains a fixed 0,1 jump characteristic, which improves the convergence speed of the data clock recovery of the CDR unit. It should be noted that if the CDR unit receives a signal for normal recovery of data and clock fed back by itself before receiving the first signal, the CDR unit can enter a locked state based on the signal for normal recovery of data and clock, thereby completing the data and clock recovery operation.

[0220] The decoding device provided in the embodiment of the present application is used to perform Fig. 9 The decoding method in the corresponding method embodiment in the present application can be referred to Fig. 9 The relevant parts of the corresponding method embodiments are understood.

[0221] In the embodiment of the present application, the encoding device and the decoding device are presented in the form of dividing each functional unit in an integrated manner. The "functional unit" here may refer to an application-specific integrated circuit (ASIC), a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions. In a simple embodiment, a person skilled in the art can imagine that the encoding device and the decoding device can be used Fig.11 The form shown.

[0222] for example, Fig.11 The processor 1101 can call the computer execution instruction stored in the memory 1102 to make the encoding device execute Figure 3 The encoding method performed by the PMA layer in the corresponding method embodiment. Fig.11 The processor 1101 can call the computer execution instruction stored in the memory 1102 to make the decoding device execute Figure 8 The decoding method performed by the PMA layer in the corresponding method embodiment.

[0223] Specifically, Fig.12 The first processing unit 1202 in Fig.13 The function / implementation process of the second processing unit 1302 can be achieved by Fig.11 The processor 1101 in the embodiment mobilizes the computer execution instructions stored in the memory 1102 to achieve the above. Fig.12 The first acquisition unit 1201 in Fig.13 The function / implementation process of the second acquisition unit 1301 in Fig.11 This is achieved by the transceiver 1103 in .

[0224] In this application Fig.11The components in the device are communicated and connected, that is, the processing unit (or processor), the storage unit (or memory) and the transceiver unit (transceiver) communicate with each other through the internal connection path to transmit control and / or data signals. The above method embodiments of the present application can be applied to the processor, or the steps of the above method embodiments can be implemented by the processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method embodiments can be completed by the hardware integrated logic circuit in the processor or the instructions in the form of software. The above processor can be a central processing unit (CPU), a network processor (NP) or a combination of CPU and NP, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in this application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware. Although only one processor is shown in the figure, the device may include multiple processors or the processor may include multiple processing units. Specifically, the processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.

[0225] The memory is used to store computer instructions executed by the processor. The memory can be a storage circuit or a memory. The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, or a flash memory. The volatile memory can be a random access memory, which is used as an external cache. The memory can be independent of the processor or can be a storage unit in the processor, which is not limited here. Although only one memory is shown in the figure, the device can also include multiple memories or the memory includes multiple storage units.

[0226] The transceiver is used to implement content interaction between the processor and other units or network elements. Specifically, the transceiver can be a communication interface of the device, or a transceiver circuit or a communication unit, or a transceiver. The transceiver can also be a communication interface or a transceiver circuit of the processor. Optionally, the transceiver can be a transceiver chip. The transceiver can also include a sending unit and / or a receiving unit. In one possible implementation, the transceiver can include at least one communication interface. In another possible implementation, the transceiver can also be a unit implemented in software form. In various embodiments of the present application, the processor can interact with other units or network elements through the transceiver. For example: the processor obtains or receives content from other network elements through the transceiver. If the processor and the transceiver are two physically separated components, the processor can interact with other units of the device without going through the transceiver.

[0227] In one possible implementation, the processor, memory, and transceiver may be interconnected via a bus. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, and the like.

[0228] In the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0229] In the various embodiments of the present application, a variety of examples are provided for ease of understanding, however, these examples are merely examples and do not necessarily represent the best implementation of the present application.

[0230] The above embodiments may be implemented in whole or in part through software, hardware, firmware or any combination thereof. When implemented by software, they may be implemented in whole or in part in the form of a computer program product.

[0231] The computer program product includes one or more computer instructions. When the computer execution instruction is loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instruction can be stored in a computer-readable storage medium, or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instruction can be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server, a data center, etc. that includes one or more available media integration. Available media can be magnetic media, (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state hard disk Solid State Disk (SSD)), etc.

[0232] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the transmitting optical module, receiving optical module, unit and module described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0233] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A coding method, characterized in that: include: Obtain m first data streams through m input channels, where m is a positive integer; Processing the m first data streams to obtain z second data streams, where z is a positive integer; Independently encode each of the z second data streams to obtain z third data streams; The z third data streams are multiplexed to obtain n fourth data streams, where n is a positive integer.

2. The encoding method according to claim 1, characterized in that Each of the z second data streams includes a data block to be encoded; and the encoding process is performed independently on each of the z second data streams, including: Encoding the first data block to obtain a forward error correction code FEC codeword, wherein the first data block corresponds to at least C / z consecutive data blocks to be encoded in the second data stream, where C is a positive integer and C is an integer multiple of z; The encoding method further comprises: A first marker is inserted into a codeword boundary position of one of the FEC codewords.

3. The encoding method according to claim 1 or 2, characterized in that: The first identifier includes a preset identifier sequence.

4. The encoding method according to any one of claims 1 to 3, characterized in that: Processing the m first data streams to obtain z second data streams includes: The m first data streams are demultiplexed according to a second ratio to obtain z second data streams, where the second ratio is a ratio of m to z.

5. The encoding method according to claim 4, characterized in that: The demultiplexing process is performed on the m first data streams according to the second ratio to obtain z second data streams, including: Demultiplexing the m first data streams according to the second ratio to obtain z fifth data streams; Each of the z fifth data streams is independently subjected to Q-level processing to obtain z second data streams; wherein each level of processing in the Q-level processing includes: Perform round-robin distribution processing on the data stream obtained at the previous stage to obtain at least two sub-data streams; Delaying the first sub-data stream to obtain a sixth data stream; Multiplexing the second sub-data stream and the sixth data stream to obtain an output data stream after processing at this stage; The first sub-data stream is at least one of the at least two sub-data streams, the second sub-data stream is one of the at least two sub-data streams that has not been delayed, and the second data stream is a data stream output after Q-level processing, where Q is a positive integer.

6. The encoding method according to any one of claims 1 to 4, characterized in that: The encoding method further comprises: Acquire m seventh data streams through the m first input channels; Demultiplexing the m seventh data streams according to the second ratio to obtain z eighth data streams; Processing the m first data streams to obtain z second data streams includes: The z-way second data stream and the z-way eighth data stream are multiplexed to obtain z-way second data stream after multiplexing.

7. The encoding method according to any one of claims 1 to 6, characterized in that: The encoding method further comprises: An alignment mark in each of the second data streams is identified, where the alignment mark is used to identify a symbol boundary in the corresponding second data stream.

8. The encoding method according to claim 7, characterized in that: The alignment marker is an alignment block including a 120-bit sequence, and the alignment block includes a 48-bit common alignment marker.

9. The encoding method according to any one of claims 1 to 8, characterized in that: The m-channel first data streams are obtained by multiplexing the z-channel data streams after Reed-Solomon (RS) encoding at a first ratio.

10. The encoding method according to any one of claims 2 to 9, characterized in that: The throughput rate or baud rate of the data after the first identifier is inserted is an integer multiple of the reference clock.

11. The encoding method according to any one of claims 1 to 10, characterized in that: m=4,z=32,n=4.

12. The encoding method according to any one of claims 1 to 4, before independently encoding each of the z second data streams, the method further comprises: Delay processing is performed on the z-path second data streams.

13. The method according to claim 12, characterized in that The method further comprises: The sub-data streams that have been delayed and the sub-data streams that have not been delayed are multiplexed.

14. The encoding method according to any one of claims 5 to 13, characterized in that: The Q=1.

15. A decoding method, characterized in that: The decoding method comprises: Obtain n fourth data streams through n input channels; Demultiplexing the n fourth data streams to obtain z third data streams; Decoding each of the z third data streams independently to obtain the z second data streams; The z second data streams are multiplexed according to a first ratio to obtain the m first data streams, where the first ratio is a ratio of z to m.

16. The decoding method according to claim 15, characterized in that: The z-path third data stream includes a first identifier, and the first identifier is a preset identifier sequence.

17. A coding device, characterized in that: The encoding device is used to execute the method according to any one of claims 1 to 13.

18. A decoding device, characterized in that: The decoding device is used to execute the method described in any one of claims 14 or 15.

19. A computer-readable storage medium, characterized in that: When the instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 16.

20. A chip system, which may include a processor, wherein the processor is used to execute the method according to any one of claims 1-16.

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