Decoding method and device, electronic equipment and computer program product

Abstract

The invention relates to a decoding method and device, electronic equipment and a computer program product, and belongs to the technical field of computers. The method comprises the following steps: inputting each decoding frame to be decoded into a decoder in sequence; for each input decoding frame, acquiring a decoding reference relationship of the decoding frame through a main thread, and judging whether the decoding frame meets a decoding condition or not according to the decoding reference relationship; and if the decoded frame satisfies the decoding condition, sending a decoding task corresponding to the decoded frame to a sub-thread so as to decode the decoded frame through the sub-thread. The decoding reference relation of the decoding frame is acquired and analyzed through the main thread, the decoding frame meeting the decoding condition is sent to the branch threads for decoding, the upper limit of the decoding parallelism degree can be improved, and the decoding speed is increased.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a decoding method, a decoding device, an electronic device, and a computer program product. Background Art

[0002] In video transmission, the process of converting video code stream into images requires the use of a decoder. The decoder can decode the code stream into images and output them to users for consumption.

[0003] A video is composed of multiple frames. In the implementation of a decoder, it is generally decoded frame by frame, that is, a frame of code stream is input, the current frame is decoded immediately, and then the next frame is input for decoding. Therefore, the decoding speed is slow.

[0004] In view of this, there is an urgent need in the art for a decoding method that can speed up the decoding speed.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide a decoding method, a decoding device, an electronic device and a computer program product, thereby accelerating the decoding speed at least to a certain extent.

[0007] According to a first aspect of the present disclosure, there is provided a decoding method, comprising:

[0008] Input each decoding frame to be decoded into the decoder in sequence;

[0009] For each of the input decoded frames, a decoding reference relationship of the decoded frame is obtained through a main thread, and whether the decoded frame meets a decoding condition is determined according to the decoding reference relationship;

[0010] If the decoded frame meets the decoding condition, the decoding task corresponding to the decoded frame is sent to the sub-thread, so that the decoded frame is decoded by the sub-thread.

[0011] In an exemplary embodiment of the present disclosure, the method further includes:

[0012] If the decoded frame does not meet the decoding condition, the decoded frame is stored in a frame queue until the decoded frame meets the decoding condition, and then the decoding task corresponding to the decoded frame is sent to a sub-thread for decoding.

[0013] In an exemplary embodiment of the present disclosure, the method further includes:

[0014] When each of the decoded frames enters the frame queue, the main thread determines whether other decoded frames in the frame queue meet the decoding condition.

[0015] In an exemplary embodiment of the present disclosure, the method further includes:

[0016] When each of the decoded frames is decoded, the main thread determines whether other decoded frames in the frame queue meet the decoding conditions.

[0017] In an exemplary embodiment of the present disclosure, the obtaining, through the main thread, the decoding reference relationship of the decoded frame includes:

[0018] The header information of the decoded frame is decoded by the main thread to obtain a decoding reference relationship of the decoded frame.

[0019] In an exemplary embodiment of the present disclosure, the decoding reference relationship of the decoded frame includes a reference relationship between the decoded frame and a reference frame corresponding to the decoded frame.

[0020] In an exemplary embodiment of the present disclosure, judging whether the decoded frame meets the decoding condition according to the decoding reference relationship includes:

[0021] It is determined whether the reference frame corresponding to the decoded frame has been decoded according to the decoding reference relationship. If the reference frame has been decoded, it is determined that the decoded frame meets the decoding condition.

[0022] In an exemplary embodiment of the present disclosure, sending the decoding task corresponding to the decoded frame to a sub-thread includes:

[0023] A corresponding decoding frame memory is provided for each of the decoding frames, and a decoding task corresponding to the decoding frame is sent to a sub-thread through the decoding frame memory corresponding to the decoding frame.

[0024] According to a second aspect of the present disclosure, a decoding device is provided, including:

[0025] A decoded frame input module is configured to input each decoded frame to be decoded into the decoder in sequence;

[0026] A reference relationship acquisition module is configured to execute, for each of the input decoded frames, to acquire a decoding reference relationship of the decoded frame through a main thread, and determine whether the decoded frame meets a decoding condition according to the decoding reference relationship;

[0027] The decoding task sending module is configured to send the decoding task corresponding to the decoded frame to the sub-thread if the decoded frame meets the decoding condition, so as to decode the decoded frame through the sub-thread.

[0028] In an exemplary embodiment of the present disclosure, the decoding device further includes:

[0029] The decoding queue storage module is configured to execute if the decoded frame does not meet the decoding condition, then store the decoded frame in the frame queue until the decoded frame meets the decoding condition, and then send the decoding task corresponding to the decoded frame to the sub-thread for decoding.

[0030] In an exemplary embodiment of the present disclosure, the decoding queue storage module includes:

[0031] The frame queue decoding condition judgment unit is configured to execute, when each decoded frame enters the frame queue, judging through the main thread whether other decoded frames in the frame queue meet the decoding condition.

[0032] The frame queue decoding condition judgment unit is further configured to execute, when each of the decoded frames is decoded, to judge, through the main thread, whether other decoded frames in the frame queue meet the decoding condition.

[0033] In an exemplary embodiment of the present disclosure, the reference relationship acquisition module includes:

[0034] The header information decoding unit is configured to perform decoding of the header information of the decoded frame through the main thread to obtain a decoding reference relationship of the decoded frame.

[0035] In an exemplary embodiment of the present disclosure, the reference relationship acquisition module further includes:

[0036] The reference frame decoding judgment unit is configured to judge whether the reference frame corresponding to the decoded frame has been decoded according to the decoding reference relationship, and if the reference frame has been decoded, determine that the decoded frame meets the decoding condition.

[0037] In an exemplary embodiment of the present disclosure, the decoding task sending module includes:

[0038] The decoded frame memory sending unit is configured to provide a corresponding decoded frame memory for each of the decoded frames, and send the decoding task corresponding to the decoded frame to the sub-thread through the decoded frame memory corresponding to the decoded frame.

[0039] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement any one of the decoding methods described above.

[0040] According to a fourth aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the decoding method described in any one of the above is implemented.

[0041] The exemplary embodiments of the present disclosure may have the following beneficial effects:

[0042] In the decoding method of the example implementation of the present disclosure, the decoding reference relationship of the decoded frame is obtained by the main thread, and whether the decoded frame meets the decoding condition is determined according to the decoding reference relationship, and the decoded frame that meets the decoding condition is sent to the sub-thread for direct decoding. The decoding method of the example implementation of the present disclosure performs reference relationship analysis on the input code stream by the main thread, completes the decoding task of the decoded frame by the sub-thread, and the main thread changes the order of frame decoding according to the reference relationship, so that the sub-thread in the decoder can decode multiple frame sequences at the same time, effectively improving the upper limit of parallelism and accelerating the decoding speed.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0045] Figure 1 A schematic diagram of a decoder structure for parallel decoding in a related embodiment of the present disclosure is shown;

[0046] Figure 2 A schematic flow chart showing a decoding method according to an exemplary embodiment of the present disclosure;

[0047] Figure 3 A schematic diagram schematically shows a decoding reference relationship in a specific implementation of the present disclosure;

[0048] Figure 4 A schematic diagram of a decoder structure in a specific embodiment of the present disclosure is shown;

[0049] Figure 5 A block diagram showing a decoding device according to an exemplary embodiment of the present disclosure is shown;

[0050] Figure 6 A schematic diagram of the structure of a computer system suitable for implementing the electronic device of the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0051] In order to enable ordinary persons in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein.

[0053] The following example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0054] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0055] The decoder speed can be increased by using multi-threaded parallelism. However, if only one frame of the code stream is decoded at a time, only parallel decoding within the frame can be performed. Therefore, there is an upper limit to the degree of parallelism, and the improvement in decoding speed is also limited.

[0056] In some related embodiments, a decoder can be developed to decode multiple frames in parallel to improve the parallelism of multi-threaded decoding. Figure 1 The decoding parallel structure shown includes a parser (data parsing) and a decoder (decoder). The parser and decoder rely on the same memory. The decoder implements inter-frame serial decoding, and the decoding process is CTU (Coding Tree Unit) level intra-frame parallel.

[0057] In the frame sequence with large computational load, the decoding speed of multithreading is not slow. However, in the faster sequence, the more threads there are, the slower the decoding speed is, because the number of tasks is insufficient and waiting occurs, resulting in limited parallelism.

[0058] Based on the above problems, this exemplary embodiment first provides a decoding method. Figure 2 As shown, the above decoding method may include the following steps:

[0059] Step S210: Input each decoding frame to be decoded into the decoder in sequence.

[0060] Step S220: For each input decoded frame, a decoding reference relationship of the decoded frame is obtained through the main thread, and whether the decoded frame meets the decoding condition is determined according to the decoding reference relationship.

[0061] Step S230: If the decoded frame meets the decoding condition, the decoding task corresponding to the decoded frame is sent to the sub-thread, so as to decode the decoded frame through the sub-thread.

[0062] In the decoding method of the example implementation of the present disclosure, the decoding reference relationship of the decoded frame is obtained by the main thread, and whether the decoded frame meets the decoding condition is determined according to the decoding reference relationship, and the decoded frame that meets the decoding condition is sent to the sub-thread for direct decoding. The decoding method of the example implementation of the present disclosure performs reference relationship analysis on the input code stream by the main thread, completes the decoding task of the decoded frame by the sub-thread, and the main thread changes the order of frame decoding according to the reference relationship, so that the sub-thread in the decoder can decode multiple frame sequences at the same time, effectively improving the upper limit of parallelism and accelerating the decoding speed.

[0063] Next, combine Figure 3 to Figure 4 The above steps of this exemplary embodiment are described in more detail.

[0064] In step S210, each decoding frame to be decoded is sequentially input into the decoder.

[0065] In the transmission of video, the code stream has a predetermined original decoding order, and the frames to be decoded can be input into the decoder in sequence according to the preset original decoding order. The original decoding order here is the decoding order corresponding to the frame-by-frame decoding process. The decoding order can be adjusted through the subsequent analysis of the reference relationship of each frame.

[0066] In step S220, for each input decoded frame, a decoding reference relationship of the decoded frame is obtained through the main thread, and it is determined whether the decoded frame meets the decoding condition according to the decoding reference relationship.

[0067] In the implementation of codec, in order to improve the compression rate, references between frames will be implemented. For example, the second frame will refer to the image of the first frame for prediction. Therefore, in the decoding process, the first frame needs to be decoded before the second frame can be decoded. In this case, the first and second frames cannot be decoded at the same time. If the frame-by-frame decoding method is used, one frame is input and decoded one frame at a time. When each frame is input, the previous frame has been decoded, so it can be guaranteed that the reference frame of the current input frame has been decoded.

[0068] When implementing multi-frame and multi-parallel decoding of the decoder, it is necessary to input multiple frame code streams into the decoder for decoding at the same time. However, there is a reference dependency between frames. Therefore, it is necessary to consider the reference relationship between frames during the decoding process to adjust the decoding order.

[0069] In the process of encoding video, multiple frames are generally divided into a group (GOP, Group of Pictures), such as Figure 3 The following is a typical group structure. In this group, frame 0 is decoded first. After frame 0 is decoded, it becomes the reference frame for subsequent frames. The second frame that needs to be decoded in the code stream is frame 16. When decoding frame 16, its reference frame is frame 0. Then frame 8 is decoded. The reference frames of frame 8 are frames 0 and 16. Then frames 4 and 12 are decoded. Each decoded frame needs to refer to several frames before it in the decoding order. For example, when decoding frame 2, the possible reference frames are 0, 16, 8, 4, and 12.

[0070] In this example implementation, the main thread can decode the header information of the decoded frame to obtain the decoding reference relationship of the decoded frame. The decoding reference relationship of the decoded frame includes a reference relationship between the decoded frame and a reference frame corresponding to the decoded frame, and the original decoding order of the reference frame is before the decoded frame.

[0071] Each time a decoding frame is input, the decoder will first decode the header information of the frame and obtain the decoding reference relationship of the frame from the header information. After obtaining the decoding reference relationship, it can be determined whether the reference frame corresponding to the decoding frame has been decoded according to the decoding reference relationship. If the reference frame has been decoded, it is determined that the decoding frame meets the decoding conditions.

[0072] In step S230, if the decoded frame meets the decoding condition, the decoding task corresponding to the decoded frame is sent to the sub-thread, so that the decoded frame is decoded by the sub-thread.

[0073] If the currently input decoding frame meets the decoding condition, that is, all reference frames of the currently decoded frame have been decoded, the decoding task of the currently decoded frame is directly sent out, and the currently decoded frame is decoded through a separate thread.

[0074] In this example implementation, a corresponding decoding frame memory may be provided for each decoding frame, and a decoding task corresponding to the decoding frame may be sent to a sub-thread through the decoding frame memory corresponding to the decoding frame.

[0075] By providing multiple decoding frame memories, for frames that meet the decoding conditions, a corresponding decoding frame memory can be obtained, and the extracted frames can be split into tasks and sent out using the decoding frame memory. These tasks will be executed by multiple threads.

[0076] There are multiple decoders that perform decoding tasks. The job of each decoder is to split a frame of decoding task into multiple parallel tasks within the frame after receiving it, and put it into the thread pool to wait for the child thread to take the task for decoding.

[0077] In this example implementation, if the decoded frame does not meet the decoding condition, the decoded frame is stored in the frame queue until the decoded frame meets the decoding condition, and the decoding task corresponding to the decoded frame is sent to the sub-thread for decoding.

[0078] If the currently input decoded frame does not meet the decoding conditions, that is, there are undecoded reference frames of the currently decoded frame, it will be put into the frame queue to wait. The frame queue for storing decoded frames is used to wait for the reference frame to be decoded and then send out the frames that meet the decoding conditions in the queue. Each time a frame header is decoded, it will check whether the frames waiting in the frame queue meet the decoding conditions.

[0079] In this example implementation, when each decoded frame is decoded, or when each decoded frame enters the frame queue, or at other appropriate judgment times, the main thread can determine whether other decoded frames in the frame queue meet the decoding conditions. If there are frames in the frame queue that meet the decoding conditions, the corresponding decoding task is sent to the sub-thread and decoding is performed.

[0080] When each frame is decoded, all the code streams in the frame queue can be checked to see whether the reference frame with which it has a reference has been decoded. If so, the code stream of the frame is sent out for decoding.

[0081] In this example implementation, the decoding task corresponding to the decoded frame can be sent to the sub-thread, and the decoded frame is decoded by the sub-thread. In addition, the main thread can also perform the corresponding decoding task when idle, which is not specifically limited in this example implementation.

[0082] In this example implementation, the decoding process mainly includes the following operations: input code stream, analysis of reference relationship, checking frame queue and frame decoding. Among them, the main thread can be used to read header information, analyze reference relationship, manage frame queue, take out frame tasks that meet decoding conditions and decoder memory of a single frame, split into intra-frame parallel tasks and send them out. In fact, the frame decoding task is calculated in the sub-thread, and the sub-thread can execute the above-mentioned intra-frame parallel tasks in the thread pool to obtain the decoding result of each frame. The main thread only needs to hand over the decoding task to the sub-thread, and then it can immediately take the code stream of the next frame for processing. Therefore, the task of the main thread is lightweight and can quickly read several code streams to fill the frame queue.

[0083] like Figure 4 The figure shows a schematic diagram of the decoder structure in a specific embodiment of the present disclosure, which is an example of the above steps in this example embodiment. Parser can decode the header information of the video sequence frame, obtain the decoding reference relationship of each frame, and determine whether the decoding condition is met. If the decoding condition is not met, it is placed in the frame queue to wait. For frames that meet the decoding conditions, a corresponding decoding frame memory can be obtained, and the decoding frame memory can be used to split the taken frames into tasks and send them out. These tasks will be executed by multiple sub-threads in the thread pool. The sub-threads obtain the decoding results of each frame by executing parallel tasks within the frame.

[0084] by Figure 3 Taking the frame structure shown in the figure as an example, the input order of the code stream is 0, 16, 8, 4, 2, 1, 3, 4, 6, 5, 7, 12, 10, 9, 11, 14, 13, 15. If frame-by-frame decoding is used, the decoding order is still 0, 16, 8, 4, 2, 1, 3, 4, 6, 5, 7, 12, 10, 9, 11, 14, 13, 15.

[0085] If the multi-frame parallel decoding method in this example implementation is used, the reference relationship of each frame is first analyzed. For example, for frames 2 and 6, possible reference frames are frames 0, 16, 8, 4, and 12. Therefore, after the decoding of the previous frames is completed, frames 2 and 6 can be decoded at the same time.

[0086] In the process of implementing multi-frame decoding, assuming that the frame queue is large and all frames have entered the frame queue, you only need to decode frames 0, 16, and 8 in sequence, and then you can start decoding frames 4 and 12 immediately. After decoding frame 4, you can immediately decode frames 2 and 6. After decoding frame 2, you can immediately start decoding frames 1 and 3. After decoding frame 12, you can immediately decode frames 10 and 14, and so on. Finally, all odd frames can be decoded at the same time. In this way, most frames in the entire group can be decoded in parallel, which improves the parallelism and decoding speed.

[0087] In actual operation, the decoding speed based on the master (a multi-decoder architecture using a shared encoder) is 164.93FPS (frames per second), while the 4-thread multi-frame parallel decoding speed optimized by the decoding method in this example implementation is 572.87FPS (frames per second). It can be seen that the optimized online code stream 4-thread speed is 3.47 times that of the master, and the multi-thread decoding speed is significantly improved compared with the master.

[0088] It should be noted that although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0089] Furthermore, the present disclosure also provides a decoding device. Figure 5 As shown, the decoding device may include a decoding frame input module 510, a reference relationship acquisition module 520, and a decoding task sending module 530. Among them:

[0090] The decoded frame input module 510 is configured to sequentially input each decoded frame to be decoded into the decoder;

[0091] The reference relationship acquisition module 520 is configured to acquire the decoding reference relationship of the decoded frame through the main thread for each input decoded frame, and determine whether the decoded frame meets the decoding condition according to the decoding reference relationship;

[0092] The decoding task sending module 530 is configured to send the decoding task corresponding to the decoded frame to the sub-thread if the decoded frame meets the decoding condition, so as to decode the decoded frame through the sub-thread. In some exemplary embodiments of the present disclosure, a decoding device provided by the present disclosure may also include a decoding queue storage module, which is configured to store the decoded frame in the frame queue if the decoded frame does not meet the decoding condition, until the decoded frame meets the decoding condition, and then send the decoding task corresponding to the decoded frame to the sub-thread for decoding.

[0093] In some exemplary embodiments of the present disclosure, the decoding queue storage module may include a frame queue decoding condition judgment unit, which is configured to judge whether other decoded frames in the frame queue meet the decoding conditions through the main thread when each decoded frame enters the frame queue.

[0094] In some exemplary embodiments of the present disclosure, the frame queue decoding condition judgment unit is further configured to judge, through the main thread, whether other decoded frames in the frame queue meet the decoding conditions when each decoded frame completes decoding.

[0095] In some exemplary embodiments of the present disclosure, the reference relationship acquisition module 520 may include a header information decoding unit configured to decode header information of a decoded frame through a main thread to acquire a decoding reference relationship of the decoded frame.

[0096] In some exemplary embodiments of the present disclosure, the decoding reference relationship of the decoded frame includes a reference relationship between the decoded frame and a reference frame corresponding to the decoded frame.

[0097] In some exemplary embodiments of the present disclosure, the reference relationship acquisition module 520 may further include a reference frame decoding judgment unit, which is configured to judge whether the reference frame corresponding to the decoded frame has been decoded according to the decoding reference relationship. If the reference frame is decoded, it is determined that the decoded frame meets the decoding conditions.

[0098] In some exemplary embodiments of the present disclosure, the decoding task sending module 530 may include a decoding frame memory sending unit, which is configured to provide a corresponding decoding frame memory for each decoding frame, and send the decoding task corresponding to the decoding frame to the sub-thread through the decoding frame memory corresponding to the decoding frame.

[0099] The specific details of each module / unit in the above decoding device have been described in detail in the corresponding method embodiment part and will not be repeated here.

[0100] Figure 6 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present disclosure is shown.

[0101] It should be noted that Figure 6 The computer system 600 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0102] like Figure 6 As shown, computer system 600 includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage part 608 into a random access memory (RAM) 603. Various programs and data required for system operation are also stored in RAM 603. CPU 601, ROM 602 and RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0103] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed, so that a computer program read therefrom is installed into the storage section 608 as needed.

[0104] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 609, and / or installed from a removable medium 611. When the computer program is executed by a central processing unit (CPU) 601, various functions defined in the system of the present disclosure are executed.

[0105] The exemplary embodiment of the present disclosure also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the information prompt method for reward redemption is implemented.

[0106] In one embodiment, the computer program product may be a tangible product containing a computer program, such as a computer-readable storage medium storing a computer program. The readable storage medium may be a storage medium based on electrical, magnetic, optical, electromagnetic, infrared, or other signals, including but not limited to: random access memory (RAM), read-only memory (ROM), magnetic tape, floppy disk, flash memory (Flash), mechanical hard disk (HDD), solid-state drive (SSD), and the like. Exemplarily, the computer program product may be implemented as a non-volatile storage medium storing a computer program, such as a read-only memory, a NAND flash memory, and the like.

[0107] In one embodiment, the computer program product may be an intangible product including a computer program. Exemplarily, the computer program product may be implemented as a virtual digital product, such as a digital file storing an executable file, an installation package, etc. of the computer program.

[0108] The code of the computer program can be written in one or more programming languages. Programming languages ​​such as C language, Java, C++, etc. The program code can be executed entirely on the user computing device, or partially on the user computing device, or as a separate software package, or partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, such as a local area network (LAN), a wide area network (WAN), etc., or can be connected to an external computing device (e.g., an Internet connection provided by an operator).

[0109] The computer program may be carried or transmitted via electrical, magnetic, optical, electromagnetic, infrared, or other signals. The electronic device may convert the signal carrying the computer program into a digital signal, thereby running the computer program. When the computer program is run on the electronic device, its code is used to enable the electronic device to execute (more specifically, the processor of the electronic device may execute) the method steps of various exemplary embodiments of the present disclosure, such as the information prompt method for reward redemption described above.

[0110] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0111] It should be noted that, although several modules of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules described above can be concretized in one module. Conversely, the features and functions of one module described above can be further divided into multiple modules to be concretized.

[0112] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure.

[0113] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A decoding method, characterized in that: include: Input each decoding frame to be decoded into the decoder in sequence; For each of the input decoded frames, a decoding reference relationship of the decoded frame is obtained through a main thread, and whether the decoded frame meets a decoding condition is determined according to the decoding reference relationship; If the decoded frame meets the decoding condition, the decoding task corresponding to the decoded frame is sent to the sub-thread, so that the decoded frame is decoded by the sub-thread.

2. The decoding method according to claim 1, characterized in that: The method further comprises: If the decoded frame does not meet the decoding condition, the decoded frame is stored in a frame queue until the decoded frame meets the decoding condition, and then the decoding task corresponding to the decoded frame is sent to a sub-thread for decoding.

3. The decoding method according to claim 2, characterized in that: The method further comprises: When each of the decoded frames enters the frame queue, the main thread determines whether other decoded frames in the frame queue meet the decoding condition.

4. The decoding method according to claim 2, characterized in that: The method further comprises: When each of the decoded frames is decoded, the main thread determines whether other decoded frames in the frame queue meet the decoding conditions.

5. The decoding method according to claim 1, characterized in that: The obtaining the decoding reference relationship of the decoded frame through the main thread includes: The header information of the decoded frame is decoded by the main thread to obtain a decoding reference relationship of the decoded frame.

6. The decoding method according to claim 1, characterized in that: The decoding reference relationship of the decoded frame includes a reference relationship between the decoded frame and a reference frame corresponding to the decoded frame.

7. The decoding method according to claim 6, characterized in that: The determining whether the decoded frame satisfies a decoding condition according to the decoding reference relationship includes: It is determined whether the reference frame corresponding to the decoded frame has been decoded according to the decoding reference relationship. If the reference frame has been decoded, it is determined that the decoded frame meets the decoding condition.

8. The decoding method according to claim 1, characterized in that: The step of sending the decoding task corresponding to the decoded frame to a sub-thread includes: A corresponding decoding frame memory is provided for each of the decoding frames, and a decoding task corresponding to the decoding frame is sent to a sub-thread through the decoding frame memory corresponding to the decoding frame.

9. A decoding device, characterized in that: include: A decoded frame input module is configured to input each decoded frame to be decoded into the decoder in sequence; A reference relationship acquisition module is configured to execute, for each of the input decoded frames, to acquire a decoding reference relationship of the decoded frame through a main thread, and determine whether the decoded frame meets a decoding condition according to the decoding reference relationship; The decoding task sending module is configured to send the decoding task corresponding to the decoded frame to the sub-thread if the decoded frame meets the decoding condition, so as to decode the decoded frame through the sub-thread.

10. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the decoding method according to any one of claims 1 to 8.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the decoding method according to any one of claims 1 to 8 is implemented.

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