Link bandwidth adjusting method, core particle and chip system

Abstract

The embodiment of the invention provides a link bandwidth adjustment method, a core particle and a chip system, and the method comprises the steps: obtaining link bandwidth demand evaluation information of the chip system, which is determined based on the current demand bandwidth of each link, so as to indicate a load scene and a link bandwidth distribution mode of the chip system; when the scene is determined to be the first load scene, determining the effective bandwidth of each link by using a corresponding link bandwidth allocation mode, so that the sum of the effective bandwidths of the links in the first load scene is smaller than or equal to the available bandwidth; adjusting the current required bandwidth into an effective bandwidth to serve as the actual bandwidth of the link; the current required bandwidth is the working bandwidth allocated by a link request when the chip system runs, and the sum of the current required bandwidths in the first load scene is greater than the available bandwidth. According to the technical scheme provided by the embodiment of the invention, the communication power consumption of the link can be reduced on the basis of ensuring the performance of the chip system.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a link bandwidth adjustment method, a core particle, and a chip system. Background Art

[0002] Links are used to achieve interconnection between cores or chips, also known as interconnection links. With the increasing demand for chip computing power and storage, and the limitation of single core area, more and more technical solutions are implemented by multi-core or even multi-chip. As a result, the bandwidth demand for interconnection links between cores and chips is also increasing. Link bandwidth is positively correlated with the power consumption (communication power consumption) consumed by the link for communication.

[0003] Therefore, in this context, how to provide a technical solution to reduce the communication power consumption of the link while ensuring the performance of the chip system has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a link bandwidth adjustment method, a core particle, and a chip system to reduce the communication power consumption of the link while ensuring the performance of the chip system.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a link bandwidth adjustment method, including:

[0007] Acquire link bandwidth requirement assessment information of the chip system, where the link bandwidth requirement assessment information is determined based on the current required bandwidth of each link of the chip system and is used to indicate a load scenario of the chip system and a link bandwidth allocation method under the corresponding load scenario;

[0008] When it is determined that the load scenario indicated by the link bandwidth requirement assessment information is the first load scenario, the effective bandwidth of each link is determined using the link bandwidth allocation method corresponding to the first load scenario, so that the sum of the effective bandwidths of each link under the first load scenario is equal to the bandwidth that can be provided by the chip system;

[0009] Adjust the current required bandwidth to the effective bandwidth as the actual bandwidth of the link;

[0010] The currently required bandwidth is: the working bandwidth allocated by the chip system when the chip system is running and the link requests the chip system to allocate, and the sum of the currently required bandwidths in the first load scenario is greater than the available bandwidth.

[0011] In a second aspect, an embodiment of the present invention provides a core particle, including a system management unit and a link for data communication with other core particles, wherein the system management unit includes:

[0012] An evaluation information acquisition module, used to acquire link bandwidth requirement evaluation information of a chip system, wherein the link bandwidth requirement evaluation information is determined based on the current required bandwidth of each link of the chip system, and is used to indicate a load scenario of the chip system, and a link bandwidth allocation method under the corresponding load scenario;

[0013] A first effective bandwidth determination module is used to determine the effective bandwidth of each link by using the link bandwidth allocation method corresponding to the first load scenario when determining that the load scenario indicated by the link bandwidth demand evaluation information is the first load scenario, so that the sum of the effective bandwidths of each link under the first load scenario is equal to the bandwidth that can be provided by the chip system;

[0014] The bandwidth adjustment module is used to adjust the current required bandwidth to the effective bandwidth as the actual bandwidth of the link;

[0015] The currently required bandwidth is: the working bandwidth allocated by the chip system when the chip system is running and the link requests the chip system to allocate, and the sum of the currently required bandwidths in the first load scenario is greater than the available bandwidth.

[0016] In a third aspect, an embodiment of the present invention provides a chip system, comprising at least one core particle as described in the second aspect.

[0017] A link bandwidth adjustment method provided by an embodiment of the present invention includes: obtaining link bandwidth demand evaluation information of a chip system, wherein the link bandwidth demand evaluation information is determined based on the current demand bandwidth of each link of the chip system and is used to indicate the load scenario of the chip system and the link bandwidth allocation method under the corresponding load scenario; when it is determined that the load scenario indicated by the link bandwidth demand evaluation information is a first load scenario, using the link bandwidth allocation method corresponding to the first load scenario to determine the effective bandwidth of each link, so that the sum of the effective bandwidths of each link under the first load scenario is equal to the available bandwidth of the chip system; adjusting the current demand bandwidth to the effective bandwidth as the actual bandwidth of the link; the current demand bandwidth is: the working bandwidth allocated by the link requesting the chip system when the chip system is running, and the sum of the current demand bandwidths in the first load scenario is greater than the available bandwidth.

[0018] It can be seen that the technical solution provided by the embodiment of the present invention is that the link bandwidth demand evaluation information is determined based on the current demand bandwidth of each link, and the current demand bandwidth is: when the chip system (the chip system where each link is located) is running, the link requests the chip system to allocate a working bandwidth for it; that is, when the chip system is running, before the link performs data communication based on the actual bandwidth, the link bandwidth demand evaluation information is first determined according to the current demand bandwidth of the link to determine the load scenario of the chip system at this time, and the link bandwidth allocation method under the corresponding load scenario; thereby facilitating the real-time clarification of the working status of the chip system (that is, the load scenario); and when it is determined that the load scenario is the first load scenario, the corresponding bandwidth allocation method can be used to obtain the effective bandwidth of each link under this load scenario, thereby adjusting the current demand bandwidth to the effective bandwidth; the current demand bandwidth in the first load scenario is greater than the bandwidth that the chip system can provide, that is, in the first load scenario, the chip system needs to process a large amount of data at this time; because the chip system processes a large amount of data mainly based on the bandwidth it can provide for data calculation and processing. Therefore, in the first load scenario, if each link is allocated directly according to the current required bandwidth of the link, on the one hand, since the sum of the current required bandwidths of the links is greater than the bandwidth available of the chip system, the part of the sum of the current required bandwidths that exceeds the available bandwidth will cause a waste of resources; on the other hand, the part of the sum of the current required bandwidths that is too large (mainly the part that exceeds the available bandwidth) will increase the communication power consumption of the link; therefore, in the embodiment of the present invention, when it is determined that the chip system is in the first load scenario, the current required bandwidth of each link is adjusted to the effective bandwidth, so that the sum of the effective bandwidths of each link after adjustment is equal to the available bandwidth, so that the adjusted effective bandwidth can be less than the current required bandwidth, that is, the current required bandwidth is reduced, so that the chip system can normally process (process data according to the available bandwidth) the data transmitted by the link, and reduce the communication bandwidth of each link, so as to achieve the effect of reducing the communication power consumption of the link on the basis of ensuring the performance of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0020] Figure 1 is a schematic structural diagram of a chip system including two core particles provided by an embodiment of the present invention;

[0021] Figure 2is a schematic diagram of a structure of a link in a core particle provided by an embodiment of the present invention;

[0022] Figure 3 It is a flow chart of a link bandwidth adjustment method provided by an embodiment of the present invention;

[0023] Figure 4 is another flow chart of the link bandwidth adjustment method provided by an embodiment of the present invention;

[0024] Figure 5 is a schematic structural diagram of a chip system including four core particles provided in an embodiment of the present invention;

[0025] Figure 6 is an example diagram of a bandwidth bottleneck provided by an embodiment of the present invention;

[0026] Figure 7 A schematic diagram of allocating available bandwidth when level values ​​are the same in a first load scenario provided by an embodiment of the present invention;

[0027] Figure 8 A schematic diagram of allocating available bandwidth when different level values ​​are used in a first load scenario provided by an embodiment of the present invention;

[0028] Fig. 9 is a schematic structural diagram of a core particle provided by an embodiment of the present invention;

[0029] Fig.10 It is a structural diagram of a chip system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] Due to the limitations of chip system (or chiplet) manufacturing process and chip system (or chiplet) yield, only limited logic units can be integrated on a single chiplet. Therefore, in order to achieve higher computing power and more functions, two or more chiplets are usually interconnected through interconnected links to form a larger chip system. Please refer to Figure 1 , Figure 1 It is a schematic structural diagram of a chip system including two core particles provided in an embodiment of the present invention.

[0032] like Figure 1As shown, data communication is performed between two core particles 1 in the chip system via a link 11 to meet the functional requirements of the chip system.

[0033] With the increasing demand for computing power and storage of chip systems and the limitation of the area of ​​a single chip, the number of chiplets integrated on a chip system is increasing. As a result, the bandwidth demand for the link used to connect the chiplets and realize data communication is also increasing. In order to use the link to realize the interconnection between the chiplets, a set of multi-layer protocols usually needs to be implemented on the link to ensure the smooth progress of data communication.

[0034] To understand the structure of the link in the core particle, please refer to Figure 2 , Figure 2 It is a structural schematic diagram of a link in a core particle provided by an embodiment of the present invention.

[0035] like Figure 2 As shown, the core particle 1 includes a link 11 for data communication, a system management unit 12 for managing the actual bandwidth of the link 11, that is, the real bandwidth (effective bandwidth) during operation, and a clock module 13 for receiving the main frequency information configured by the system management unit 12; the bus 14 is used to realize information transmission among the system management unit 12, the clock module 13, and the link 11.

[0036] The link 11 may generally be composed of three parts: a transport layer 111 , a data link layer 112 and a physical layer 113 .

[0037] The transport layer 111 usually implements a bus protocol, which may be a data bus protocol for internal data communication, a management bus protocol for internal management control, or a protocol that combines both data communication and management communication functions. The protocol content of the bus protocol may be a custom protocol or a standard protocol, such as the AXI protocol. At the same time, the transport layer 111 is generally also responsible for organizing the internal bus information into a form suitable for link transmission, such as a data frame format.

[0038] The data link layer 112 is usually used to realize a stable transmission link, and generally realizes functions including link establishment, management, exception handling, link layer data packaging and transmission. At the same time, in order to ensure the reliability of the link 11, the data link layer 112 also realizes functions such as error detection, error correction and retransmission of data. The clock of the transport layer 111 and the data link layer 112 (contained in the main frequency information) is provided by the clock module 13, and the system management unit 12 configures the clock module 13. The physical layer 113 mainly realizes the serial-to-parallel conversion of data and the high-speed transmission of data between core particles 1. The system management unit 12 can configure and manage the transport layer 111, data link layer 112 and physical layer 113 of the link 11 through the bus 14.

[0039] Since data communication corresponds to the computing power requirements of the chip system, as the amount of data processing involved in data communication increases, the bandwidth of the link also increases, resulting in the continuous increase in the communication power consumption of the link. Especially the physical layer in the link, the physical layer is usually implemented by analog circuits, and its communication power consumption decreases relatively slowly with the evolution of the process, that is, for analog circuits, the speed of reduction of communication power consumption is relatively slow. This is because the performance of analog circuits is more affected by physical limitations, such as signal amplification, filtering and other processes, which often require a certain amount of energy consumption, and these energy consumptions are not easy to significantly reduce with the reduction of the process; As a result, the communication power consumption of the link has always accounted for a high proportion of the total power consumption of the chip system. Therefore, it is very necessary to reduce the communication power consumption of the link.

[0040] To solve the above problems, an embodiment of the present invention provides a link bandwidth adjustment method, which reduces the communication power consumption of the link while ensuring the performance of the chip system.

[0041] Please refer to Figure 3 , Figure 3 The present invention is a flowchart of a link bandwidth adjustment method provided by an embodiment of the present invention.

[0042] like Figure 3 As shown, the method includes:

[0043] Step S100: obtaining link bandwidth requirement evaluation information of the chip system.

[0044] The link bandwidth requirement evaluation information is determined based on the current required bandwidth of each link of the chip system, and is used to indicate the load scenario of the chip system and the link bandwidth allocation method under the corresponding load scenario.

[0045] The currently required bandwidth is: the working bandwidth allocated by the chip system when the chip system is running and the link requests the chip system.

[0046] The link requests the chip system to obtain the corresponding bandwidth as the current required bandwidth according to the computing requirements of the chip system. For example, the link may request the system management unit to allocate the corresponding bandwidth to it.

[0047] The link bandwidth requirement assessment information can clarify the working status of the chip system according to the current required bandwidth being requested by each link at this time. For example, when the sum of the current required bandwidths is very large, it means that the chip system is in a busy working state, that is, the chip system needs to process a large amount of data; when the sum of the current required bandwidths is very small, it means that the chip system is not busy working, and the amount of data that the chip system needs to process is small or there is no data to be processed. It should be noted that the "very large" and "very small" mentioned here are the results when the sum of the current required bandwidths is compared with the available bandwidth.

[0048] Step S101: when it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the effective bandwidth of each link is determined using the link bandwidth allocation method corresponding to the first load scenario.

[0049] So that the sum of the effective bandwidths of each link in the first load scenario is equal to the bandwidth that can be provided by the chip system.

[0050] The sum of currently required bandwidths in the first load scenario is greater than the available bandwidth.

[0051] The link transmits data based on the allocated current demand bandwidth so that the chip system can process the data transmitted by the link accordingly. When each chip in the chip system performs data processing tasks, the transmission of data mainly relies on the processing of the functional unit in the chip system that can realize data interaction. For example, when the chip system needs to perform data calculations, each chip that performs calculations (such as computing chips) needs to obtain data from the memory from the IO chip (input and output interface chip) through the link, as well as the storage of subsequent calculation results. At this time, the functional unit can be a memory controller, where the memory controller can be located in the IO chip to facilitate access to the memory to obtain the data required for data calculations. The data processing capability of the functional unit is determined by the bandwidth that the functional unit can provide (the bandwidth that the chip system can provide).

[0052] Therefore, when the chip system needs to process a large amount of data at the current moment, the current required bandwidth that the link needs to request will increase accordingly. When the sum of the current required bandwidths is greater than the available bandwidth, that is, when the load scenario corresponding to the chip system is the first load scenario, since the bandwidth that can be provided by the functional unit is fixed, if the corresponding current required bandwidth is allocated to the link at this time, and since the bandwidth that can be provided by the functional unit is less than the current required bandwidth, the functional unit cannot quickly process the large amount of data transmitted by the link; this causes data processing congestion in the chip system, affecting the performance of the chip system. At the same time, the link configures the actual bandwidth of the link based on the current required bandwidth for data transmission, which will increase the communication power consumption of the link and have a greater impact on the overall performance of the chip system.

[0053] Therefore, in the embodiment of the present invention, when the chip system is in the first load scenario according to the link bandwidth demand evaluation information, the bandwidth is no longer allocated to the link based on the current demand bandwidth, but each link is allocated based on the available bandwidth, that is, the link bandwidth allocation method corresponding to the first load scenario is used to determine the effective bandwidth of each link, so that the sum of the effective bandwidth is equal to the available bandwidth. This avoids the problem that when the chip system is in a busy working state, the link transmits data according to the current demand bandwidth, thereby causing data processing congestion in the chip system and increasing the link communication power consumption.

[0054] Since the sum of the effective bandwidths of the links is equal to the available bandwidth, and the available bandwidth is smaller than the sum of the current required bandwidths of the links in the first load scenario, the adjusted effective bandwidth is smaller than the current required bandwidth.

[0055] The link uses the adjusted effective bandwidth to gradually transmit the data that needs to be processed, so that the sum of the data transmitted by each core particle per unit time meets the data that can be processed by the available bandwidth. Therefore, it will not affect the working performance of the chip system in the first load scenario. Moreover, since the current required bandwidth is reduced to the effective bandwidth, the communication power consumption of the link can be reduced.

[0056] Step S102: Adjust the current required bandwidth to the effective bandwidth as the actual bandwidth of the link.

[0057] When adjusting the current required bandwidth to the effective bandwidth, a commonly used link low power consumption method can be used.

[0058] Since the communication power consumption of the link is generally related to the data transmission capacity of the link and the actual amount of data transmitted, and the data transmission capacity of the link and the actual amount of data transmitted can reflect the bandwidth of the data transmission of the link. Therefore, in order to enable the link to have a higher data transmission capacity, the transport layer and data link layer of the link will design a higher bus operating frequency and a wider bus data bit width. The bus operating frequency and bus data bit width are parameters used by the data link layer and the transport layer to adjust the bandwidth of data transmission, that is, the bandwidth of data transmission ≤ bus operating frequency * bus data bit width. The physical layer needs to achieve a higher baud rate or use a wider physical link to match the bandwidth requirements of data transmission. The baud rate and physical link width are parameters used by the physical layer to adjust the bandwidth of data transmission.

[0059] Since the physical layer is usually designed with analog circuits, with the advancement of technology, the power consumption of digital design has dropped much more than that of analog circuit design, resulting in an increasing proportion of the communication power consumption of the physical layer in the total link power consumption in advanced process design. Therefore, the low-power design scheme of the link is more focused on reducing the power consumption of the data link layer and the physical layer design.

[0060] From the above analysis, it can be seen that the communication power consumption of the link is generally positively correlated with the maximum data transmission capacity of the link (the bandwidth of data transmission). Therefore, in the commonly used link low power consumption method, the purpose of reducing the communication power consumption of the link is achieved by adjusting (dynamically reducing) the parameters that affect the bandwidth of data transmission. For example, the bus operating frequency and baud rate can be reduced to reduce the bandwidth of data transmission of the link, thereby reducing the communication power consumption; or the bus data bit width and link bit width can be reduced to reduce the communication power consumption.

[0061] It can be seen that the technical solution provided by the embodiment of the present invention is that the link bandwidth demand evaluation information is determined based on the current demand bandwidth of each link, and the current demand bandwidth is: when the chip system (the chip system where each link is located) is running, the link requests the chip system to allocate a working bandwidth for it; that is, when the chip system is running, before the link performs data communication based on the actual bandwidth, the link bandwidth demand evaluation information is first determined according to the current demand bandwidth of the link to determine the load scenario of the chip system at this time, and the link bandwidth allocation method under the corresponding load scenario; thereby facilitating the real-time clarification of the working status of the chip system (that is, the load scenario); and when it is determined that the load scenario is the first load scenario, the corresponding bandwidth allocation method can be used to obtain the effective bandwidth of each link under this load scenario, thereby adjusting the current demand bandwidth to the effective bandwidth; the current demand bandwidth in the first load scenario is greater than the bandwidth that the chip system can provide, that is, in the first load scenario, the chip system needs to process a large amount of data at this time; because the chip system processes a large amount of data mainly based on the bandwidth it can provide for data calculation and processing. Therefore, in the first load scenario, if each link is allocated directly according to the current required bandwidth of the link, on the one hand, since the sum of the current required bandwidths of the links is greater than the bandwidth available of the chip system, the part of the sum of the current required bandwidths that exceeds the available bandwidth will cause a waste of resources; on the other hand, the part of the sum of the current required bandwidths that is too large (mainly the part that exceeds the available bandwidth) will increase the communication power consumption of the link; therefore, in the embodiment of the present invention, when it is determined that the chip system is in the first load scenario, the current required bandwidth of each link is adjusted to the effective bandwidth, so that the sum of the effective bandwidths of each link after adjustment is equal to the available bandwidth, so that the adjusted effective bandwidth can be less than the current required bandwidth, that is, the current required bandwidth is reduced, so that the chip system can normally process (process data according to the available bandwidth) the data transmitted by the link, and reduce the communication bandwidth of each link, so as to achieve the effect of reducing the communication power consumption of the link on the basis of ensuring the performance of the chip system.

[0062] In order to accurately obtain link bandwidth requirement assessment information, the chip system can monitor the current required bandwidth of each link. Figure 4 , Figure 4 It is another flowchart of the link bandwidth adjustment method provided by an embodiment of the present invention.

[0063] like Figure 4 As shown, the method includes:

[0064] Step S201, obtaining the current required bandwidth of each link in the chip system.

[0065] When the chip system is running, it will receive different data processing tasks based on different computing requirements. The number of data processing tasks that need to be processed is also different. The core particles in the chip system will execute the received data processing tasks, such as the computing core particles mentioned above. When each computing core particle performs data processing, the data transmission is realized using a link. Therefore, when the chip system is running, the bandwidth requested by each link, that is, the current required bandwidth, can be obtained, which facilitates accurate and real-time acquisition of link bandwidth demand assessment information.

[0066] Step S202, based on the sum of the current required bandwidths of each link, determine the load scenario of the chip system, and obtain the link bandwidth allocation method defined corresponding to the determined load scenario to form link bandwidth requirement evaluation information.

[0067] When the chip system allocates bandwidth to each link, it allocates it based on the available bandwidth, and the available bandwidth is the bandwidth that the functional unit can provide. Therefore, by calculating the sum of the current required bandwidths of each link, the load scenario of the chip system at this time can be determined.

[0068] Since the load scenarios of the chip system can be predetermined based on the design and usage scenarios of the chip system, the designer can define the corresponding link bandwidth allocation method based on some load scenarios of the chip system.

[0069] Therefore, after obtaining the current required bandwidth, the load scenario of the chip system can be directly determined according to the sum of the current required bandwidths, and the link bandwidth allocation method defined under the load scenario can be obtained.

[0070] For example, the load scenarios of the chip system can be divided into heavy load scenarios, light load scenarios, and no load scenarios.

[0071] Among them, the current total required bandwidth in the heavy load scenario is greater than the available bandwidth, that is, the heavy load scenario is the first load scenario. At this time, in the embodiment of the present invention, the current required bandwidth can be reduced so that the sum of the effective bandwidths of each link after the reduction is equal to the available bandwidth.

[0072] In light load scenarios and no load scenarios (the second load scenario described later), the current total required bandwidth is less than or equal to the available bandwidth; if it is a light load scenario, the bandwidth can be directly allocated according to the current demand; if it is a no load scenario, bandwidth allocation for the link can be stopped.

[0073] Step S203: obtaining link bandwidth requirement evaluation information of the chip system.

[0074] In order to accurately define the bandwidth allocation method under different load scenarios, in one implementation, it can be defined according to the actual configuration in the chip system.

[0075] Please continue to refer to Figure 4 ,like Figure 4 As shown, the method may also include:

[0076] Step S2001, obtaining the available bandwidth of the chip system and obtaining the link bandwidth threshold that each link can provide.

[0077] The available bandwidth may be the bandwidth provided by the functional unit in the chip system that can provide a basis for data interaction for each core particle. For example, if the functional unit is a memory controller, the available bandwidth is the bandwidth provided by the memory controller. Since the available bandwidth is provided by the functional unit in the chip system that provides data interaction for each core particle, that is, the functional unit can serve each core particle, the available bandwidth of the functional unit can also be called the public bandwidth.

[0078] The link bandwidth threshold is the highest bandwidth that each link can provide, that is, the highest bandwidth that each link can transmit data, and the current required bandwidth is less than or equal to the link bandwidth threshold.

[0079] Step S2002 , defining a load scenario of the chip system based on the available bandwidth and the sum of bandwidth thresholds of each link.

[0080] The load scenario can reflect the working status of the chip system, which is related to the available bandwidth of the chip system and the current required bandwidth of each link.

[0081] Step S2003: for each load scenario, determine the bandwidth bottleneck of the corresponding chip system, and define the corresponding link bandwidth allocation method based on the determined bandwidth bottleneck.

[0082] Bandwidth bottleneck refers to the phenomenon that the overall transmission rate of the chip system decreases due to the bandwidth limitation of a certain component or assembly during the data transmission process (the working process of the chip system). For example, when the sum of the link bandwidth thresholds is greater than the available storage bandwidth, if the link bandwidth is allocated according to the link bandwidth threshold, the bandwidth available to the functional unit is fixed and limited. Even if the link transmits data according to the link bandwidth threshold, the functional unit cannot synchronously process the amount of data transmitted according to the available bandwidth, resulting in data processing congestion and affecting the data task processing capability of the chip system; therefore, the bandwidth bottleneck at this time is the first bandwidth bottleneck.

[0083] Correspondingly, when the sum of the current required bandwidth is less than or equal to the available bandwidth, there is a surplus of available bandwidth at this time. Therefore, the bandwidth bottleneck is to allocate bandwidth to each link according to the sum of the maximum bandwidth that can be provided by the link (link bandwidth threshold), and the allocated bandwidth is less than or equal to the available bandwidth. In other words, the maximum allocable bandwidth of the available bandwidth is: the bandwidth allocated according to the sum of the link bandwidth thresholds (the bandwidth bottleneck at this time).

[0084] Since the current required bandwidth is less than or equal to the link bandwidth threshold, the sum of the current required bandwidths is less than or equal to the sum of the link bandwidth thresholds. Then when it is determined that the available bandwidth is less than or equal to the minimum value of the link bandwidth (the sum of the current required bandwidths), the available bandwidth must be sufficient for the chip system to process data tasks normally without congestion. Therefore, in the embodiment of the present invention, the bandwidth bottleneck when the sum of the current required bandwidths is less than or equal to the available bandwidth is determined as the link bandwidth. After determining the bandwidth bottleneck, the corresponding link bandwidth allocation method can be defined under each bandwidth bottleneck; thereby, the current required bandwidth of the link can be flexibly adjusted, and the effective bandwidth of the link can be reasonably allocated.

[0085] In one implementation, step S2002 may include:

[0086] The bandwidth between the available bandwidth and the sum of the bandwidth thresholds of each link forms a first bandwidth range, and the scenario corresponding to the first bandwidth range is defined as a first load scenario; the bandwidth between the first value and the available bandwidth forms a second bandwidth range, and the scenario corresponding to the second bandwidth range is defined as a second load scenario.

[0087] Since the bandwidth that the chip system can provide is fixed and known, and the available bandwidth is the bandwidth used for allocation when the chip system performs data processing tasks, and the link bandwidth threshold is the maximum bandwidth that each link can provide when the chip system is running. At the same time, during operation, the chip system is faced with the execution of data processing tasks with different amounts of data, which makes the sum of the current required bandwidths constantly changing. Therefore, in order to ensure the accuracy and reliability of judging the load scenarios of the chip system under different current required bandwidths, different load scenarios are defined in advance based on the sum of the available bandwidth and the link bandwidth threshold.

[0088] Subsequently, the current required bandwidth obtained in real time can be compared with the available bandwidth to determine the bandwidth range and the corresponding load scenario at this time.

[0089] After different bandwidth bottlenecks are determined, load scenarios and bandwidth allocation methods may be defined accordingly. In one implementation, step S2002 may include:

[0090] The bandwidth bottleneck under the first load scenario is defined as the first bandwidth bottleneck, and the link bandwidth allocation method when in the first bandwidth bottleneck is defined as: allocating the available bandwidth according to the priority of each link in the chip system; the bandwidth bottleneck under the second load scenario is defined as the second bandwidth bottleneck, and the link bandwidth allocation method when in the second bandwidth bottleneck is defined as: allocating according to the current demand bandwidth.

[0091] Bandwidth bottleneck may refer to the phenomenon that the overall transmission rate of the chip system decreases due to the bandwidth limitation of a certain part or component during the data transmission process (the working process of the chip system). The first bandwidth bottleneck may refer to the phenomenon that the overall transmission rate of the chip system is limited due to the limitation of the available bandwidth (such as the bandwidth provided by the memory controller) when the chip system is in a busy working state. Therefore, the link bandwidth allocation method when in the first bandwidth bottleneck is defined as: the available bandwidth is allocated according to the priority of each link in the chip system, so that the normal operation of the chip system can be met and the bandwidth of the link can be reduced.

[0092] The second bandwidth bottleneck may refer to the phenomenon that the overall transmission rate of the chip system is limited due to the link bandwidth limitation of the available bandwidth allocated to each link when the chip system is in a non-busy working state (i.e., there is a surplus of available bandwidth at this time). Therefore, the link bandwidth allocation method when in the second bandwidth bottleneck is defined as: allocating according to the current required bandwidth, thereby reducing the communication power consumption at this time.

[0093] After completing the definition information corresponding to each bandwidth bottleneck (defined load scenario and bandwidth allocation method), the defined information can be obtained according to the current required bandwidth obtained in real time to form link bandwidth requirement evaluation information. Therefore, in one embodiment, step S203 may include:

[0094] Based on the comparison result of the sum of the current required bandwidth and the available bandwidth, the load scenario of the chip system is determined, and the bandwidth bottleneck and link bandwidth allocation method corresponding to the determined load scenario are obtained.

[0095] The bandwidth bottleneck is related to the sum of the link bandwidth thresholds and the available bandwidth. The available bandwidth is the bandwidth used to allocate links in the chip system, and the link bandwidth threshold must be greater than or equal to the current required bandwidth. Therefore, in actual use, the sum of the current required bandwidth obtained in real time can be used to compare only with the available bandwidth to quickly determine the load scenario of the chip system at this time.

[0096] In one embodiment, the determining the load scenario of the chip system based on the comparison result of the sum of the currently required bandwidth and the available bandwidth, and obtaining the bandwidth bottleneck and link bandwidth allocation method corresponding to the determined load scenario, include:

[0097] When the sum of the currently required bandwidths is greater than the available bandwidth, the currently required bandwidth is within the first bandwidth range, and the load scenario of the chip system is determined to be the first load scenario; and the bandwidth bottleneck corresponding to the first load scenario is obtained: the available bandwidth, and when the bandwidth bottleneck is the first bandwidth bottleneck, the corresponding link bandwidth allocation method is defined: the public bandwidth is allocated according to the priority of each link in the chip system;

[0098] When it is determined that the sum of the currently required bandwidths is less than or equal to the available bandwidth, the currently required bandwidth is within the second bandwidth range, and the load scenario of the chip system is determined to be the second load scenario; and the corresponding bandwidth bottleneck defined under the second load scenario is obtained: the link bandwidth, and when the bandwidth bottleneck is the second bandwidth bottleneck, the corresponding link bandwidth allocation method is defined: allocation according to the currently required bandwidth.

[0099] Please continue to refer to Figure 4 , the method further comprises:

[0100] Step S204: when it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the available bandwidth is allocated according to the priority of each link in the chip system.

[0101] The bandwidth bottleneck defined in the first load scenario is the available bandwidth, and the available bandwidth can be allocated to each link according to the priority of each link.

[0102] In order to enhance the flexibility of defining the bandwidth allocation method, in one implementation, when the bandwidth bottleneck is determined as the first bandwidth bottleneck based on the sum of the current required bandwidths, the priority level values ​​of the various links may be the same;

[0103] At this time, step S204 may include:

[0104] When it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the public bandwidth is evenly distributed according to the number of links so that the effective bandwidth of each link is equal.

[0105] Or, the priority level values ​​of the links are different, in which case step S205 may include:

[0106] When it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the available bandwidth is allocated according to the corresponding level value so that the effective bandwidths of the links are not equal.

[0107] When the priority level values ​​are set to the same value, it means that the priorities of the links are the same, so the effective bandwidth of each link is determined by evenly allocating the available bandwidth.

[0108] When the priority level is set to different values, it is allocated according to the specific level setting. The higher the level, the more bandwidth is allocated, and the lower the level, the less bandwidth is allocated, so that the final effective bandwidth of each link is equal to the available bandwidth.

[0109] For example, the chip system can provide a bandwidth of 200GBps, the chip system includes 4 links, the link bandwidth threshold of each link is 100GBps, and the current total required bandwidth is: the current required bandwidth of the first link + the current required bandwidth of the second link + the current required bandwidth of the third link + the current required bandwidth of the fourth link = 400GBps.

[0110] It can be seen that the sum of the current required bandwidths is equal to the sum of the link bandwidth thresholds of each link, and the sum of the current required bandwidths is greater than the available bandwidth. It can be determined that the bandwidth bottleneck of the chip system at this time is the first bandwidth bottleneck.

[0111] Therefore, the bandwidth is allocated according to the priority of each link. If the priority level values ​​of each link are the same, for example, 1, the 200 GBps public bandwidth is evenly allocated, and the effective bandwidth of each link is 200 GBps / 4=50 GBps.

[0112] If the priority level values ​​of the links are different, for example, the first link and the second link have a level value of 1, and the third link and the fourth link have a level value of 2, then the 200GBps public bandwidth is allocated accordingly according to the priority level value. The effective bandwidth allocated to the first link and the second link with a level value of 1 may be 80GBps, and the effective bandwidth allocated to the third link and the fourth link with a level value of 2 may be (200GBps-2*80GBps) / 2=20GBps.

[0113] Please continue to refer to Figure 4 In one embodiment, the method may further include:

[0114] Step S205, when it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the second load scenario, the link bandwidth allocation method corresponding to the second load scenario is used to determine the current required bandwidth of the link as the effective link bandwidth as the actual bandwidth of the link.

[0115] So that the sum of the effective bandwidths of each link in the second load scenario is less than or equal to the bandwidth that can be provided by the chip system.

[0116] The bandwidth bottleneck defined in the second load scenario is the second bandwidth bottleneck, which can be directly allocated according to the current required bandwidth.

[0117] To understand the complete implementation of the link bandwidth adjustment method, please refer to Figure 5 , Figure 5 It is a schematic structural diagram of a chip system including four core particles provided in an embodiment of the present invention.

[0118] like Figure 5 As shown, a chip system for computing consists of four computing cores (51-A, 51-B, 51-C, 51-D) and one IO core 52. Each computing core 51 is connected to the IO core 52 through a link 11, and there is no interconnection between the computing cores. The computing unit is implemented on the computing core to provide computing power. The system management unit 12 and the memory controller 53 (functional unit) are implemented on the IO core 52, wherein the system management unit 12 can read the working status of each component (each computing core and IO core 52) in the chip system and predict the subsequent working status of the component. At the same time, the system management unit 12 can also independently change the effective bandwidth configuration of each link.

[0119] Figure 5 In the chip system shown, it is assumed that the memory controller 53 on the IO core 52 includes two memory controllers: a first memory controller and a second memory controller, wherein the first memory controller and the second memory controller can each provide 100GBps bandwidth, and the memory controller 53 can provide 200GBps bandwidth (i.e., the available bandwidth of the chip system). The link between each computing core and the IO core 52 can provide a maximum bandwidth of 100GBps (i.e., the link bandwidth threshold).

[0120] When obtaining link bandwidth requirement evaluation information:

[0121] The first step is to obtain the available bandwidth within the chip system. Figure 5 The chip system shown can provide a storage bandwidth (i.e., a total bandwidth provided by a memory controller): 200 GBps, so that four computing cores can perform data processing tasks.

[0122] The second step is to determine the load scenario of the chip system based on the sum of the available bandwidth, the bandwidth thresholds of each link, and the sum of the current required bandwidth, and obtain the bandwidth bottleneck defined under the determined load scenario and the link bandwidth allocation method defined for each bandwidth bottleneck.

[0123] Since the storage bandwidth of 200 GBps is less than the total link bandwidth of 400 GBps (4*100 GBps) connecting the four computing cores 51 and the IO core 52, that is, the public bandwidth is less than the sum of the bandwidth thresholds of each link. Therefore, the bandwidth bottleneck at this time is determined to be the storage bandwidth, and the scenario at this time is defined as the first load scenario of multiple computing cores accessing memory together intensively.

[0124] The above bandwidth bottleneck determination is explained by taking the current required bandwidth as the maximum value (link bandwidth threshold) as an example. In other implementations, it can also be determined according to the actual current required bandwidth. When it is determined that the sum of the current required bandwidths is greater than the available bandwidth, it can be determined that the chip system is in the first load scenario, and the bandwidth bottleneck of the chip system defined in the first load scenario is obtained: the available bandwidth.

[0125] If only a single computing core 51-A is used in the chip system for data processing, the storage bandwidth of 200GBps is greater than the link bandwidth threshold of 100GBps corresponding to the link between the computing core 51-A and the IO core 52, that is, the public bandwidth is greater than the sum of the link bandwidth thresholds (the bandwidth of the link between other computing cores and the IO core is 0 at this time). Therefore, it is determined that the load scenario of the chip system at this time is the second load scenario of intensive memory access by a single computing core, and the bandwidth bottleneck defined by the second load scenario is obtained: link bandwidth.

[0126] Of course, the second load scenario can also be to use two computing cores for data processing, in which case the storage bandwidth 200 GBps is equal to the sum of the link bandwidth thresholds 200 GBps corresponding to the links between the computing core and the IO core 52. As long as the sum of the maximum bandwidths of each link (the sum of the link bandwidth thresholds) does not exceed the storage bandwidth, it belongs to the second load scenario.

[0127] To facilitate understanding of the analysis and determination of bandwidth bottlenecks, the memory controller 53 on the IO core 52 includes two memory controllers: a first memory controller and a second memory controller, wherein the first memory controller and the second memory controller can each provide 100GBps bandwidth, and the memory controller 53 can provide 200GBps bandwidth (i.e., the bandwidth that the chip system can provide) as an example for explanation. Please refer to Figure 6 , Figure 6 This is an example diagram of a bandwidth bottleneck provided by an embodiment of the present invention.

[0128] like Figure 6As shown, when the link bandwidth threshold of 100GBps corresponding to the link 11 between one computing core 51-A and the IO core 52 is fully used, the total bandwidth allocated to the memory controller 53 on the IO core 52 is 100GBps, then the first memory controller 530 allocates 50GBps of storage bandwidth, and the second memory controller 531 allocates 50GBps of storage bandwidth, which is lower than the maximum available bandwidth of 100GBps of the first memory controller 530 and the second memory controller 531 respectively; therefore, at this time (the chip system is in the second load scenario), the bandwidth bottleneck is the second bandwidth bottleneck, and the bandwidth allocation method is to allocate according to the current required bandwidth.

[0129] Please continue to refer to Figure 5 , the step of obtaining link bandwidth evaluation information also includes:

[0130] The third step is to obtain the corresponding defined bandwidth bottleneck when it is determined that the load scenario of the chip is the first load scenario: the available bandwidth, and the link bandwidth allocation method defined when the bandwidth bottleneck is the first bandwidth bottleneck: the available bandwidth is allocated according to the priority of each link in the chip system.

[0131] In the first load scenario, the chip system will allocate the available bandwidth according to the priority of each link in the chip system. When the priority level values ​​are the same, the chip system can evenly allocate the available bandwidth; when the level values ​​are different, the chip system can allocate the available bandwidth based on different priority level values.

[0132] Please refer to Figure 7 , Figure 7 A schematic diagram of allocating available bandwidth when level values ​​are the same in a first load scenario provided by an embodiment of the present invention.

[0133] When the bandwidth bottleneck is determined to be the first bandwidth bottleneck, for example, the current total required bandwidth is greater than 180 GBps: 180 GBps can be set according to the storage bandwidth, and when the level values ​​are the same, the available bandwidth can be evenly distributed. Figure 7 As shown, according to the number of links, the storage bandwidth is evenly divided into 50 GBps as the effective bandwidth of each link.

[0134] Please refer to Figure 8 , Figure 8 A schematic diagram of allocating available bandwidth when level values ​​are different in a first load scenario provided by an embodiment of the present invention.

[0135] When the bandwidth bottleneck is determined to be the first bandwidth bottleneck, for example, the current total required bandwidth <= 180GBps, and when the level values ​​are different, for example Figure 8As shown, according to the specific level value, the storage bandwidth of 200 GBps can be allocated to the link effective bandwidth of 20 GBps of computing cores 51-B and 51-A, and to the link effective bandwidth of 80 GBps of computing cores 51-C and 51-D.

[0136] In the fourth step, when the chip system is running, the system management unit 12 of the IO chip 52 dynamically determines the current working status of the chip system, that is, based on the current required bandwidth of each link collected in real time, determines the load scenario of the chip system at this time, so as to obtain the bandwidth bottleneck and link bandwidth allocation method defined by the load scenario, and form link bandwidth demand evaluation information.

[0137] For example, the current working status may be determined based on the internal status of each computing core and the IO core 52 and the memory bandwidth usage.

[0138] Exemplarily, the internal states of the computing cores 51 and IO cores 52 can be determined by monitoring the Load Store state of the computing cores of the computing cores, the Cache state, the effective bus bandwidth monitoring inside the computing cores and IO cores, etc. The storage bandwidth usage can be monitored by counting the effective storage bandwidth of the memory controller, the internal cache occupancy rate of the memory controller, etc.

[0139] For example, if the current total required bandwidth obtained by monitoring the internal states of each computing core and the IO core 52 is ≤ a threshold value of 180GBps set based on the storage bandwidth, the bandwidth capacity of the link is configured according to the actual memory access bandwidth demand (current required bandwidth) of each computing core; if the current total required bandwidth obtained by monitoring the internal states of each computing core and the IO core 52 is greater than a threshold value of 180GBps set based on the storage bandwidth, the bandwidth capacity of each link is configured according to a predetermined allocation method (for example, allocating the available bandwidth according to the priority of each link in the chip system).

[0140] The threshold of 180GBps is set based on storage bandwidth because although the chip system can theoretically provide a bandwidth of 200GBps, this may change in actual use, so it can be specifically set by the designer.

[0141] That is to say, the bandwidth that can be provided in the embodiment of the present invention may be a design value determined when the chip system is designed, or may be a value defined by the designer based on the design value according to the actual usage of the chip system.

[0142] After obtaining the link bandwidth requirement assessment information, it can be used to indicate the load scenario of the chip system corresponding to each link and the link bandwidth allocation method under the corresponding load scenario to determine the effective bandwidth of each link.

[0143] Please continue to refer to Figure 5 The system management unit 12 of the IO core particle 52 calculates the bus operating frequency and physical layer baud rate of the transport layer and the data link layer according to the obtained link bandwidth demand assessment information, and configures the main frequency configuration information to the clock module and the transport layer and data link layer of the link, and configures the baud rate to the physical layer to achieve bandwidth capacity adjustment of the link.

[0144] The embodiment of the present invention further provides a core particle, which is used to implement the link bandwidth adjustment method described in the above embodiment.

[0145] Please refer to Fig. 9 , Fig. 9 It is a schematic diagram of the structure of the core particle provided by an embodiment of the present invention.

[0146] like Fig. 9 As shown, the core particle 1 includes:

[0147] A system management unit 12 and a link 11 for data communication with other core particles 1, the system management unit 12 comprising:

[0148] An evaluation information acquisition module 121 is used to acquire link bandwidth requirement evaluation information of a chip system, wherein the link bandwidth requirement evaluation information is determined based on the current required bandwidth of each link of the chip system, and is used to indicate a load scenario of the chip system and a link bandwidth allocation method under the corresponding load scenario;

[0149] A first effective bandwidth determination module 122 is used to determine the effective bandwidth of each link by using the link bandwidth allocation method corresponding to the first load scenario when determining that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, so that the sum of the effective bandwidths of each link under the first load scenario is equal to the bandwidth that can be provided by the chip system;

[0150] The bandwidth adjustment module 123 is used to adjust the current required bandwidth to the effective bandwidth as the actual bandwidth of the link;

[0151] The currently required bandwidth is: the working bandwidth allocated by the chip system when the chip system is running and the link requests the chip system to allocate, and the sum of the currently required bandwidths in the first load scenario is greater than the available bandwidth.

[0152] Optionally, the system management unit 12 further includes:

[0153] The link required bandwidth acquisition module 124 is used to obtain the current required bandwidth of each link in the chip system;

[0154] The evaluation information forming module 125 is used to determine the load scenario of the chip system based on the sum of the current required bandwidths of each link, and obtain the link bandwidth allocation method defined corresponding to the determined load scenario to form link bandwidth requirement evaluation information.

[0155] Optionally, the system management unit 12 further includes:

[0156] The bandwidth acquisition module 126 is used to acquire the available bandwidth of the chip system and the link bandwidth threshold that can be provided by each link, and the current required bandwidth is less than or equal to the link bandwidth threshold;

[0157] A load scenario determination module 127, configured to define a load scenario of the chip system based on the available bandwidth, the sum of the currently required bandwidth, and the sum of the bandwidth thresholds of each link;

[0158] The definition module 128 is used to determine the bandwidth bottleneck of the corresponding chip system in each load scenario, and define the corresponding link bandwidth allocation method based on the determined bandwidth bottleneck.

[0159] Optionally, the load scenario determination module 127 is used to define the load scenario of the chip system based on the available bandwidth, the sum of the current required bandwidth, and the sum of the bandwidth thresholds of each link, including:

[0160] A scenario where the sum of the current required bandwidth is greater than the available bandwidth and less than or equal to the sum of the bandwidth thresholds of each link is defined as the first load scenario;

[0161] A scenario in which the sum of the currently required bandwidths is less than or equal to the available bandwidth is defined as the second load scenario.

[0162] Optionally, the definition module 128 is used to determine the bandwidth bottleneck of the corresponding chip system in each load scenario, and define a corresponding link bandwidth allocation method based on the determined bandwidth bottleneck, including:

[0163] The bandwidth bottleneck in the first load scenario is defined as a first bandwidth bottleneck, and the link bandwidth allocation method in the first bandwidth bottleneck is defined as: allocating the available bandwidth according to the priority of each link in the chip system;

[0164] The bandwidth bottleneck in the second load scenario is defined as a second bandwidth bottleneck, and the link bandwidth allocation method when in the second bandwidth bottleneck is defined as: allocating according to the current required bandwidth.

[0165] Optionally, the first effective bandwidth determination module 122 is configured to determine the effective bandwidth of each link by using the link bandwidth allocation method corresponding to the first load scenario when determining that the load scenario indicated by the link bandwidth demand evaluation information is the first load scenario, including:

[0166] When it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the available bandwidth is allocated according to the priority of each link in the chip system.

[0167] Optionally, the system management unit 12 further includes:

[0168] The second effective bandwidth determination module 120 is used to determine the current required bandwidth of the link as the link effective bandwidth as the actual bandwidth of the link when it is determined that the load scenario indicated by the link bandwidth requirement assessment information is the second load scenario, using the link bandwidth allocation method corresponding to the second load scenario, so that the sum of the effective bandwidths of each link under the second load scenario is less than or equal to the bandwidth that can be provided by the chip system.

[0169] Optionally, the core particle is an IO core particle, and a memory controller is disposed inside the IO core particle; the available bandwidth is a bandwidth provided by the memory controller.

[0170] Optionally, the core particle 1 is an IO core particle, and a memory controller is disposed inside the IO core particle; the available bandwidth is the bandwidth provided by the memory controller.

[0171] It can be seen that the technical solution provided by the embodiment of the present invention is that the link bandwidth demand evaluation information is determined based on the current demand bandwidth of each link, and the current demand bandwidth is: when the chip system (the chip system where each link is located) is running, the link requests the chip system to allocate a working bandwidth for it; that is, when the chip system is running, before the link performs data communication based on the actual bandwidth, the link bandwidth demand evaluation information is first determined according to the current demand bandwidth of the link to determine the load scenario of the chip system at this time, and the link bandwidth allocation method under the corresponding load scenario; thereby facilitating the real-time clarification of the working status of the chip system (that is, the load scenario); and when it is determined that the load scenario is the first load scenario, the corresponding bandwidth allocation method can be used to obtain the effective bandwidth of each link under this load scenario, thereby adjusting the current demand bandwidth to the effective bandwidth; the current demand bandwidth in the first load scenario is greater than the bandwidth that the chip system can provide, that is, in the first load scenario, the chip system needs to process a large amount of data at this time; because the chip system processes a large amount of data mainly based on the bandwidth it can provide for data calculation and processing. Therefore, in the first load scenario, if each link is allocated directly according to the current required bandwidth of the link, on the one hand, since the sum of the current required bandwidths of the links is greater than the bandwidth available of the chip system, the part of the sum of the current required bandwidths that exceeds the available bandwidth will cause a waste of resources; on the other hand, the part of the sum of the current required bandwidths that is too large (mainly the part that exceeds the available bandwidth) will increase the communication power consumption of the link; therefore, in the embodiment of the present invention, when it is determined that the chip system is in the first load scenario, the current required bandwidth of each link is adjusted to the effective bandwidth, so that the sum of the effective bandwidths of each link after adjustment is equal to the available bandwidth, so that the adjusted effective bandwidth can be less than the current required bandwidth, that is, the current required bandwidth is reduced, so that the chip system can normally process (process data according to the available bandwidth) the data transmitted by the link, and reduce the communication bandwidth of each link, so as to achieve the effect of reducing the communication power consumption of the link on the basis of ensuring the performance of the chip system.

[0172] The present invention also provides a chip system, please refer to Fig.10 , Fig.10 It is a structural diagram of a chip system provided by an embodiment of the present invention.

[0173] like Fig.10 As shown, the chip system includes at least one core particle 1 as described in any of the aforementioned embodiments.

[0174] It can be seen that the chip system provided by the embodiment of the present invention can adjust the current required bandwidth to the effective bandwidth when it determines that the chip system is in the first load scenario, so that the sum of the effective bandwidths of each link is equal to the available bandwidth. This can reduce the current required bandwidth of each link while ensuring that the chip system can normally process the data transmitted by the link, and use the effective bandwidth for data communication, thereby reducing the communication power consumption of the link while ensuring the performance of the chip system.

[0175] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0176] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A link bandwidth adjustment method, characterized in that: include: Acquire link bandwidth requirement assessment information of the chip system, where the link bandwidth requirement assessment information is determined based on the current required bandwidth of each link of the chip system and is used to indicate a load scenario of the chip system and a link bandwidth allocation method under the corresponding load scenario; When it is determined that the load scenario indicated by the link bandwidth requirement assessment information is the first load scenario, the effective bandwidth of each link is determined using the link bandwidth allocation method corresponding to the first load scenario, so that the sum of the effective bandwidths of each link under the first load scenario is equal to the bandwidth that can be provided by the chip system; Adjust the current required bandwidth to the effective bandwidth as the actual bandwidth of the link; The currently required bandwidth is: the working bandwidth allocated by the chip system when the chip system is running and the link requests the chip system to allocate, and the sum of the currently required bandwidths in the first load scenario is greater than the available bandwidth.

2. The link bandwidth adjustment method according to claim 1, characterized in that: Before the step of obtaining the bandwidth requirement assessment information of the link, the method further includes: Obtain the current required bandwidth of each link in the chip system; Based on the sum of the current required bandwidths of each link, the load scenario of the chip system is determined, and the link bandwidth allocation method corresponding to the determined load scenario is obtained to form link bandwidth requirement evaluation information.

3. The link bandwidth adjustment method according to claim 2, characterized in that: Before the step of obtaining the current required bandwidth of each link in the chip system, the method further includes: Acquire the available bandwidth of the chip system and the link bandwidth threshold that each link can provide, wherein the current required bandwidth is less than or equal to the link bandwidth threshold; Defining a load scenario of the chip system based on the available bandwidth and the sum of the bandwidth thresholds of each link; For each load scenario, the bandwidth bottleneck of the corresponding chip system is determined, and the corresponding link bandwidth allocation method is defined based on the determined bandwidth bottleneck.

4. The link bandwidth adjustment method according to claim 3, characterized in that: Defining the load scenario of the chip system based on the available bandwidth and the sum of each link bandwidth threshold includes: The bandwidth between the available bandwidth and the sum of the bandwidth thresholds of each link forms a first bandwidth range, and the scenario corresponding to the first bandwidth range is defined as a first load scenario; A bandwidth between the first value and the available bandwidth forms a second bandwidth range, and a scenario corresponding to the second bandwidth range is defined as a second load scenario.

5. The link bandwidth adjustment method according to claim 4, characterized in that: The method of determining the bandwidth bottleneck of the corresponding chip system in each load scenario, and defining the corresponding link bandwidth allocation method based on the determined bandwidth bottleneck, includes: The bandwidth bottleneck in the first load scenario is defined as a first bandwidth bottleneck; and the link bandwidth allocation method in the first bandwidth bottleneck is defined as: allocating the available bandwidth according to the priority of each link in the chip system; The bandwidth bottleneck in the second load scenario is defined as a second bandwidth bottleneck, and the link bandwidth allocation method when in the second bandwidth bottleneck is defined as: allocating according to the current required bandwidth.

6. The link bandwidth adjustment method according to claim 5, characterized in that: The determining of the load scenario of the chip system based on the sum of the current required bandwidths of each link, and obtaining the corresponding defined link bandwidth allocation method under the determined load scenario, includes: Based on the comparison result of the sum of the current required bandwidth and the available bandwidth, the load scenario of the chip system is determined, and the bandwidth bottleneck and link bandwidth allocation method corresponding to the determined load scenario are obtained.

7. The link bandwidth adjustment method according to claim 6, characterized in that: The determining of the load scenario of the chip system based on the comparison result of the sum of the currently required bandwidth and the available bandwidth, and obtaining the bandwidth bottleneck and link bandwidth allocation method correspondingly defined under the determined load scenario, includes: When the sum of the currently required bandwidths is greater than the available bandwidth, the currently required bandwidth is within the first bandwidth range, and the load scenario of the chip system is determined to be the first load scenario; and the bandwidth bottleneck corresponding to the first load scenario is obtained: the available bandwidth, and when the bandwidth bottleneck is the first bandwidth bottleneck, the corresponding link bandwidth allocation method is defined: the public bandwidth is allocated according to the priority of each link in the chip system; When it is determined that the sum of the currently required bandwidths is less than or equal to the available bandwidth, the currently required bandwidth is within the second bandwidth range, and the load scenario of the chip system is determined to be the second load scenario; and the corresponding bandwidth bottleneck defined under the second load scenario is obtained: the link bandwidth, and when the bandwidth bottleneck is the second bandwidth bottleneck, the corresponding link bandwidth allocation method is defined: allocation according to the currently required bandwidth.

8. The link bandwidth adjustment method according to claim 7, characterized in that: When determining that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, determining the effective bandwidth of each link by using the link bandwidth allocation method corresponding to the first load scenario includes: When it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the available bandwidth is allocated according to the priority of each link in the chip system.

9. The link bandwidth adjustment method according to claim 8, characterized in that: The priority level values ​​of the links are the same, and when it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the available bandwidth is allocated according to the priority of each link in the chip system, including: The available bandwidth is evenly distributed according to the number of links so that the effective bandwidth of each link is equal.

10. The link bandwidth adjustment method according to claim 8, characterized in that: The priority level values ​​of each link are different. When determining that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, allocating the available bandwidth according to the priority of each link in the chip system includes: The available bandwidth is allocated according to the corresponding level value so that the effective bandwidth of each link is not equal.

11. The link bandwidth adjustment method according to any one of claims 1 to 10, characterized in that: Also includes: When it is determined that the load scenario indicated by the link bandwidth requirement assessment information is the second load scenario, the link bandwidth allocation method corresponding to the second load scenario is used to determine the current required bandwidth of the link as the effective bandwidth of the link as the actual bandwidth of the link, so that the sum of the effective bandwidths of each link under the second load scenario is less than or equal to the bandwidth that can be provided by the chip system.

12. A core particle, characterized in that: It includes a system management unit and a link for data communication with other core particles, and the system management unit includes: An evaluation information acquisition module, used to acquire link bandwidth requirement evaluation information of a chip system, wherein the link bandwidth requirement evaluation information is determined based on the current required bandwidth of each link of the chip system, and is used to indicate a load scenario of the chip system, and a link bandwidth allocation method under the corresponding load scenario; A first effective bandwidth determination module is used to determine the effective bandwidth of each link by using the link bandwidth allocation method corresponding to the first load scenario when determining that the load scenario indicated by the link bandwidth demand evaluation information is the first load scenario, so that the sum of the effective bandwidths of each link under the first load scenario is equal to the bandwidth that can be provided by the chip system; The bandwidth adjustment module is used to adjust the current required bandwidth to the effective bandwidth as the actual bandwidth of the link; The currently required bandwidth is: the working bandwidth allocated by the chip system when the chip system is running and the link requests the chip system to allocate, and the sum of the currently required bandwidths in the first load scenario is greater than the available bandwidth.

13. The core particle according to claim 12, characterized in that The system management unit also includes: A link required bandwidth acquisition module is used to obtain the current required bandwidth of each link in the chip system; The evaluation information forming module is used to determine the load scenario of the chip system based on the sum of the current required bandwidths of each link, and obtain the link bandwidth allocation method defined corresponding to the determined load scenario to form link bandwidth requirement evaluation information.

14. The core particle according to claim 13, characterized in that The system management unit also includes: A bandwidth acquisition module, used to acquire the available bandwidth of the chip system and the link bandwidth threshold that can be provided by each link, wherein the currently required bandwidth is less than or equal to the link bandwidth threshold; A load scenario determination module, used to define a load scenario of the chip system based on the available bandwidth and the sum of each link bandwidth threshold; The definition module is used to determine the bandwidth bottleneck of the corresponding chip system in each load scenario, and define the corresponding link bandwidth allocation method based on the determined bandwidth bottleneck.

15. The core particle according to claim 14, characterized in that The load scenario determination module is used to define the load scenario of the chip system based on the available bandwidth and the sum of each link bandwidth threshold, including: The bandwidth between the available bandwidth and the sum of the bandwidth thresholds of each link forms a first bandwidth range, and the scenario corresponding to the first bandwidth range is defined as a first load scenario; A bandwidth between the first value and the available bandwidth forms a second bandwidth range, and a scenario corresponding to the second bandwidth range is defined as a second load scenario.

16. The core particle according to claim 15, characterized in that The definition module is used to determine the bandwidth bottleneck of the corresponding chip system in each load scenario, and define the corresponding link bandwidth allocation method based on the determined bandwidth bottleneck, including: The bandwidth bottleneck in the first load scenario is defined as a first bandwidth bottleneck; and the link bandwidth allocation method in the first bandwidth bottleneck is defined as: allocating the available bandwidth according to the priority of each link in the chip system; The bandwidth bottleneck in the second load scenario is defined as a second bandwidth bottleneck, and the link bandwidth allocation method when in the second bandwidth bottleneck is defined as: allocating according to the current required bandwidth.

17. The core particle according to claim 16, characterized in that The first effective bandwidth determination module is used to determine the effective bandwidth of each link by using the link bandwidth allocation method corresponding to the first load scenario when determining that the load scenario indicated by the link bandwidth demand evaluation information is the first load scenario, including: When it is determined that the load scenario indicated by the link bandwidth requirement evaluation information is the first load scenario, the available bandwidth is allocated according to the priority of each link in the chip system.

18. The core particle according to any one of claims 12 to 17, characterized in that: The system management unit also includes: The second effective bandwidth determination module is used to determine the current required bandwidth of the link as the effective bandwidth of the link when it is determined that the load scenario indicated by the link bandwidth requirement assessment information is the second load scenario, using the link bandwidth allocation method corresponding to the second load scenario, as the actual bandwidth of the link, so that the sum of the effective bandwidths of each link under the second load scenario is less than or equal to the bandwidth that can be provided by the chip system.

19. The core particle according to claim 18, characterized in that The core particle is an IO core particle, and a memory controller is arranged inside the IO core particle; the available bandwidth is the bandwidth provided by the memory controller.

20. A chip system, characterized in that: Comprising at least one core particle according to any one of claims 12 to 19.

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