Message transmission method and device

Abstract

The invention provides a message transmission method and device, and the method comprises the steps: sequentially traversing each first serial port for a data writing process, and reading M first data blocks of the first serial ports from an external storage medium, M being the number of time slots occupied by the first serial ports; for each first data block, selecting a basic storage unit of the first data block from the internal storage medium, storing the first data block through the basic storage unit, and recording an offset position of the basic storage unit in the internal storage medium in a mapping table; aiming at a data sending process, traversing each second serial port in sequence, aiming at each second data block of the second serial port, acquiring an offset position of a basic storage unit where the second data block is located from the mapping table, and reading the second data block from the basic storage unit of the internal storage medium based on the offset position; and sending each second data block of the second serial port in the time slot occupied by the second serial port. By means of the scheme, more serial ports are achieved, and the utilization rate of internal storage media is increased.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a message transmission method and device. Background Art

[0002] In the field of voice communication, CPOS (Channelized Packet over SONET) interface is widely used for the aggregation and forwarding of E1 interface and T1 interface.

[0003] The CPOS interface allows multiple independent logical channels to be divided on a physical POS interface. These logical channels are called serial ports. For example, a CPOS interface with a rate of 155.520Mbps is split into 63 E1 interfaces. Each E1 interface can be divided into 32 time slots, and each time slot transmits 1 byte of data. Based on this, the E1 interface is further configured as a channel, and the E1 interface is divided into multiple serial ports (such as 1-31 serial ports). In this way, the 63 E1 interfaces of the CPOS interface can be split into a maximum of 1953 serial ports.

[0004] When the CPOS interface is divided into multiple serial ports, there is no effective way to efficiently transmit the data of these serial ports, resulting in poor data transmission efficiency and other issues. In addition, although the CPOS interface can be split into a maximum of 1953 serial ports, the number of available serial ports is limited due to limited cache space. Summary of the invention

[0005] The present application provides a message transmission method, which is applied to a processing device, wherein a target interface corresponding to the processing device is divided into a plurality of wide area network interfaces, each wide area network interface is divided into a plurality of serial ports, each wide area network interface corresponds to a plurality of time slots, and a serial port occupies at least one time slot, and the method comprises:

[0006] For the data writing process, traverse each first serial port in turn, and read M first data blocks of the first serial port from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port;

[0007] For each first data block, selecting a basic storage unit of the first data block from an internal storage medium of the processing device, storing the first data block through the basic storage unit, and recording an offset position of the basic storage unit in the internal storage medium in a mapping table;

[0008] In the data sending process, traverse each second serial port in turn, and for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position;

[0009] Each second data block of the second serial port is sent in the time slot occupied by the second serial port.

[0010] The present application provides a message transmission device, which is applied to a processing device, wherein a target interface corresponding to the processing device is divided into a plurality of wide area network interfaces, each wide area network interface is divided into a plurality of serial ports, each wide area network interface corresponds to a plurality of time slots, and a serial port occupies at least one time slot, and the device comprises:

[0011] A message buffer module, used for traversing each first serial port in turn, and reading M first data blocks of the first serial port from an external storage medium of the processing device, where M is the number of time slots occupied by the first serial port;

[0012] For each first data block, select a basic storage unit of the first data block from an internal storage medium of a processing device, store the first data block through the basic storage unit, and record an offset position of the basic storage unit in the internal storage medium in a mapping table;

[0013] a framing module, configured to traverse each second serial port in sequence, obtain, for each second data block of the second serial port, an offset position of a basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position;

[0014] The interface sending module is used to send each second data block of the second serial port in the time slot occupied by the second serial port after the framing module reads the second data block.

[0015] It can be seen from the above technical solutions that in the embodiment of the present application, the mutually exclusive characteristics of serial port binding time slots of the same wide area network interface under the CPOS interface are utilized to optimize the performance of multiple serial port sending cache polling under the CPOS interface, and reliably realize more serial ports under similar logical cache resource conditions, solve the problem of limited total number of serial ports, and more fully release the performance of the CPOS interface to meet user needs. The total amount of cache of the internal storage medium is determined by the number of time slots, and the linked list technology is used to realize dynamic allocation and polling scheduling of multiple serial ports, thereby dynamically allocating the cache resources of the internal storage medium, dynamically adjusting the number of bytes of each serial port polling read message, improving the utilization rate and scheduling efficiency of the internal storage medium, and saving storage resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of uplink forwarding processing of a CPOS interface in one embodiment of the present application;

[0017] Figure 2 It is a schematic diagram of downlink forwarding processing of a CPOS interface in one implementation manner of the present application;

[0018] Figure 3 It is a schematic diagram of downlink forwarding processing of a CPOS interface in one implementation manner of the present application;

[0019] Figure 4 It is a schematic diagram of the correspondence between the E1 interface and the serial port in one implementation of the present application;

[0020] Figure 5 It is a schematic diagram of the corresponding relationship between the local cache RAM and the serial port in one embodiment of the present application;

[0021] Figure 6 It is a schematic diagram of dynamic management of the BM linked list RAM of the serial port in one implementation mode of the present application;

[0022] Figure 7 It is a schematic diagram of an address queue and a BM linked list RAM in one embodiment of the present application;

[0023] Figure 8 It is a flowchart of a message transmission method in one embodiment of the present application;

[0024] Fig. 9 It is a scheduling diagram of a serial port polling FIFO in one implementation of the present application;

[0025] Fig.10 It is a schematic diagram of the update process of the address linked list in one implementation mode of the present application;

[0026] Fig.11 It is a flowchart of a message transmission method in one embodiment of the present application;

[0027] Fig.12 It is a structural schematic diagram of a message transmission device in one implementation of the present application. DETAILED DESCRIPTION

[0028] In the communication field such as voice calls, CPOS interface is widely used for the convergence and forwarding of E1 interface and T1 interface. CPOS interface is a channelized interface that uses SONET (Synchronous Optical Network) to transmit data packets, or CPOS interface is a channelized interface that uses SDH (Synchronous Digital Hierarchy) to transmit data packets. Among them, E1 interface is a digital communication interface, which is widely used in digital communication systems that transmit voice and data. The transmission rate of E1 interface is 2.048Mbps, which can be divided into 32 time slots (1 time slot is used for frame synchronization, and other time slots are used to transmit voice or data information). T1 interface is a digital transmission standard interface used to transmit data and audio signals in telephone networks. The transmission rate is 1.544Mbps, which can be divided into 24 time slots (1 time slot is used for frame synchronization, and other time slots are used to transmit voice or data information). For the convenience of description, the E1 interface will be used as an example for explanation.

[0029] The CPOS interface allows multiple independent logical channels to be divided on a physical POS interface. These logical channels are called serial ports (Serial Port, which is an interface for data communication between a computer and an external device). For example, a CPOS interface with a rate of 155.520Mbps is split into 63 E1 interfaces (or 84 T1 interfaces). Each E1 interface can be divided into 32 time slots, and each time slot transmits 1 byte of data. Based on this, the E1 interface is further configured as a channel, and the E1 interface is divided into multiple serial ports (such as 1-31 serial ports, that is, at least 1 serial port is divided, 1 serial port is bound to 31 time slots, and at most 31 serial ports are divided, each serial port is bound to 1 time slot. Obviously, a serial port is bound to at least one time slot, and time slot 0 is used to transmit the E1 frame header and cannot be bound). Taking each E1 interface divided into 31 serial ports as an example, the 63 E1 interfaces of the CPOS interface can be split into a maximum of 1953 serial ports.

[0030] See also Figure 1 The figure shows the schematic diagram of the uplink forwarding processing (message receiving direction) of the CPOS interface of a network device (such as a router, switch, etc.). The network message is sent to the interface processing module through the CPOS interface. The interface processing module can perform CPOS frame parsing, E1 frame parsing, HDLC (High-level Data Link Control Protocol) frame parsing, message buffering, etc. on the network message, and finally sends the serial port message to the protocol controller (such as CPU) for processing.

[0031] See also Figure 2The figure shows a schematic diagram of the downlink forwarding processing (message sending direction) of the CPOS interface of the network device. After receiving the network message for the CPOS interface, the protocol controller (such as the CPU) sends the serial port message to the interface processing module. The interface processing module performs message buffering, HDLC protocol framing (for adding HDLC header information), E1 protocol framing (for adding E1 header information), CPOS protocol framing (for adding CPOS header information) and other processing on the serial port message, and sends the message through the CPOS interface.

[0032] In the message sending direction, since the protocol controller sends network messages to the interface processing module in the form of "packets", a communication packet can be any 4-9600 bytes, and the CPOS interface has the characteristics of a large number of serial ports and a small communication bandwidth (such as the downstream bandwidth of each serial port of the E1 interface is between 64Kbps-2.048Mbps), that is, the inlet message traffic has a high burst flow, while the outlet bandwidth is small. Therefore, the interface processing module needs to cache the message in a whole packet, but the outlet is sent by bytes. Therefore, the interface processing module usually needs to cache a large number of messages, and needs to cache them separately according to the serial port number, which requires a high cache space.

[0033] The interface processing module can be implemented using a processing device, and the processing device can include but is not limited to a processing protocol chip or a programmable logic device (such as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc.). Since the number of serial ports split out of the CPOS interface is relatively large (such as 128-2000), and each serial port needs to store multiple messages. Therefore, for the processing device, there is usually not enough cache to store messages, and the external DDR (Double Data Rate) memory is selected to store the messages.

[0034] See also Figure 3 The figure shows a schematic diagram of the downlink forwarding processing (message sending direction) of the CPOS interface of the network device. After receiving the network message for the CPOS interface, the protocol controller (such as the CPU) sends the serial port message to the interface processing module. The message write cache module stores the serial port message in the DDR memory outside the processing device (also called the external storage medium of the processing device).

[0035] The message write cache module transmits storage information to the downlink cache polling scheduling module. The downlink cache polling scheduling module reads the message from the DDR memory and stores the message in the corresponding local cache, that is, the downlink cache polling scheduling module reads the message of each serial port from the DDR memory according to the downlink rate of each serial port, and stores it in the local cache of the processing device (also called the internal storage medium of the processing device).

[0036] For example, local cache 1 corresponds to serial port 1, and the message of serial port 1 is stored in local cache 1; local cache 2 corresponds to serial port 2, and the message of serial port 2 is stored in local cache 2, and so on.

[0037] The serial port framing module (i.e., HDLC framing module) can read messages from the local cache and perform framing operations on the messages, that is, add serial port information to the messages. For example, for serial port 1, the serial port framing module reads messages from local cache 1 and adds serial port information to the messages. For serial port 2, the serial port framing module reads messages from local cache 2 and adds serial port information to the messages, and so on.

[0038] The E1 framing module can perform framing operations on messages, that is, add E1 header information to the messages. For serial port 1, the serial port framing module sends the message with the serial head information added to the E1 framing module, and the E1 framing module adds the E1 header information to the message. For serial port 2, the serial port framing module sends the message with the serial head information added to the E1 framing module, and the E1 framing module adds the E1 header information to the message, and so on.

[0039] The CPOS framing module can perform framing operations on messages, that is, add CPOS header information to the messages. For serial port 1, the E1 framing module sends the message with the E1 header information added to it to the CPOS framing module. The CPOS framing module adds the CPOS header information to the message and sends the message through the CPOS interface. For serial port 2, the E1 framing module sends the message with the E1 header information added to it to the CPOS framing module. The CPOS framing module adds the CPOS header information to the message and sends the message through the CPOS interface, and so on.

[0040] Since the serial port downstream rate of the CPOS interface is relatively slow (64Kbps-2.048Mbps), and the reading speed of the DDR memory is fast (such as 800Mbps, 16BIT-width DDR3 memory, the interface bandwidth is 0.5Gbps-10Gbps, which varies according to the number of bytes read each time. The more bytes read at one time, the larger the available bandwidth), the "local cache" corresponding to each serial port only needs a small cache of 8-100 bytes. The downstream cache polling scheduling module must ensure that the local cache corresponding to the serial port is not empty, and timely fetch the corresponding serial port message from the DDR memory and put it into the local cache (to ensure that the serial port sends the whole packet continuously and reaches the maximum speed limit at the same time), but it cannot fetch too many messages at one time, resulting in the local cache being unable to fit.

[0041] Based on this, under the condition of limited local cache, the scheduling method of multiple serial port downstream cache directly affects the number of serial ports that can be realized (performance index). Under the same logical resource conditions, proper scheduling of multiple serial port downstream cache can maximize the number of serial ports and better meet the aggregation and forwarding requirements of CPOS interface.

[0042] Based on the above findings, a method for optimizing the sending cache and scheduling of multiple serial ports under the CPOS interface is proposed in an embodiment of the present application. By utilizing the mutually exclusive characteristics of the serial port binding time slots of the same E1 interface under the CPOS interface, the total amount of local cache can be determined based on the number of time slots used by the E1 interface, and the linked list technology is used to realize the dynamic allocation and polling scheduling of multiple serial ports of the local cache, thereby optimizing the polling performance of the sending cache of multiple serial ports under the CPOS interface, and reliably realizing more serial ports under similar logical cache resource conditions.

[0043] In an example, the interface processing module of the CPOS interface can be implemented by a processing device (such as FPGA, etc.), but the processing device usually does not have a large amount of cache for storing messages, that is, the internal storage medium (such as local cache) of the processing device is limited. Therefore, an external DDR memory can be selected to store messages. The DDR memory is the external storage medium of the processing device. Figure 3 As shown in the figure, the serial port message of the protocol controller is first stored in the DDR memory, and then, after the downstream cache polling scheduling module, the message of each serial port is polled from the DDR memory in units of bytes according to the downstream rate of each serial port, and stored in the internal storage medium (local cache) of the processing device. The serial port framing module then takes the message from the internal storage medium, frames it, and sends it to the E1 framing module, and finally frames it and outputs it from the CPOS interface.

[0044] Since different users have different bandwidths and numbers of serial ports supported by CPOS interfaces, the relationship between serial ports and E1 interfaces can have the following characteristics: 1) A serial port must belong to a certain E1 interface and can be bound to one or more time slots in all time slots of the E1 interface, that is, a serial port can be bound to one time slot, or a serial port can be bound to multiple time slots. For example, an E1 interface can have 32 time slots, and except for time slot 0 which only supports unframed mode, other time slots can be bound to any serial port.

[0045] 2) Under one user configuration, one time slot of the E1 interface belongs to only one serial port (that is, multiple serial ports cannot correspond to the same time slot at the same time). The time slots bound to all serial ports are mutually exclusive. Under the same E1 interface, the sum of the bandwidths of the serial ports will not exceed the total bandwidth of the E1 interface, such as the total bandwidth of 2.048Mbps.

[0046] Take the serial port generated by E1 interface as an example, see Figure 4The figure below is a schematic diagram of the correspondence between the E1 interface and the serial port under the CPOS interface. Serial ports 0 to 31 correspond to the E1-1 interface, serial ports 32 to 63 correspond to the E1-2 interface, and so on. The 32 serial ports 0 to 31 correspond to the 32 time slots of the E1-1 interface. Here, one serial port corresponds to one time slot as an example, that is, 32 serial ports correspond to 32 time slots. One serial port can also correspond to multiple time slots, and fewer serial ports (such as serial ports 1 to 6) correspond to 32 time slots of the E1-1 interface. The 32 serial ports 32 to 63 correspond to the 32 time slots of the E1-2 interface. Here, one serial port corresponds to one time slot as an example, one serial port can correspond to multiple time slots, that is, fewer serial ports correspond to 32 time slots of the E1-2 interface, and so on.

[0047] Users can use any serial port corresponding to any E1 interface. Any serial port can be bound to one or more time slots of the E1 interface according to different user configurations. The speed of all serial ports is configurable, ranging from 64Kbps to 2.048Mbps. For example, user 1 can use serial port 1 of the E1-1 interface, and serial port 1 is bound to one or more time slots. User 2 can use serial port 2 of the E1-1 interface, and serial port 2 is bound to one or more time slots. And so on. The speed of each serial port is 64Kbps. For another example, users can use serial port 32 of the E1-2 interface to bind it into one unframed serial port (including all time slots of the E1-2 interface), and the speed is 2.048Mbps. Users can also use serial port 65 corresponding to the E1-3 interface, and bind four time slots of the E1-3 interface, namely, time slots 1, 3, 4, and 30, and the speed is 256Kbps.

[0048] In an example, each serial port corresponds to a local cache RAM (Random Access Memory) inside the processing device, and the local cache RAMs corresponding to all serial ports constitute the internal storage medium of the processing device, that is, the internal storage medium includes the local cache RAM corresponding to each serial port.

[0049] See also Figure 5 As shown, it is a schematic diagram of the correspondence between the local cache RAM and the serial port, serial port 0 corresponds to local cache RAM0, serial port 1 corresponds to local cache RAM1, serial port 2 corresponds to local cache RAM2, and so on, serial port 2015 corresponds to local cache RAM2015. Obviously, each serial port corresponds to a local cache RAM. In addition, the internal storage medium may include these 2016 local cache RAMs.

[0050] See also Figure 5As shown in the figure, if the method of polling each serial port at the same speed is adopted, the same bytes are read in each polling and placed in the local cache RAM of the serial port, regardless of the speed of the serial port. Therefore, the polling scheduling efficiency is low, which leads to a large usage of the local cache RAM and a small number of serial ports that can be operated at the same time. The reason is that when the number of serial ports reaches a certain number, due to the difference in speed of different serial ports, the time spent on polling all serial ports cannot guarantee the continuity of the message sent by the serial port with a fast speed. If the continuity of the message sent by the serial port cannot be guaranteed, it will cause error packets or fail to reach the speed limit performance of the interface.

[0051] In the embodiment of the present application, according to the mutually exclusive characteristics of the time slots of the E1 interface bound between the serial ports, a method of dynamically adjusting the local RAM cache using a linked list is proposed, dynamically allocating the local cache RAM according to the serial port rate configuration, and dynamically adjusting the number of bytes of each serial port polling read message, thereby solving the problem of low utilization of the local cache RAM and limited total number of serial ports, and more fully releasing the performance of the CPOS interface.

[0052] In one example, a local cache RAM may be allocated in the internal storage medium of the processing device, and the local cache RAM is shared by all serial ports, instead of allocating a local cache RAM for each serial port.

[0053] The local cache RAM may be divided into a plurality of basic memory units (Basic Memory, BM for short). The size of the basic memory unit is a fixed value, which may be 4 bytes, 16 bytes, etc., and there is no restriction on this.

[0054] In one example, a storage area can be divided in the internal storage medium of the processing device (the storage area is recorded as a BM linked list RAM), and a mapping table can be stored through the BM linked list RAM. The mapping table may include a fixed relationship table and an address linked list. The fixed relationship table may include data table items corresponding to each serial port one by one (the items in the fixed relationship table are recorded as data table items), and the address linked list (such as the BM linked list) may include multiple linked list items shared by all serial ports (the items in the address linked list are recorded as linked list items).

[0055] For example, for each serial port, if the serial port corresponds to multiple time slots, multiple data blocks of the serial port are read from the DDR memory, and if the serial port corresponds to one time slot, one data block of the serial port is read from the DDR memory. The size of the data block can be the same as the size of the basic storage unit, or the size of the data block can be smaller than the size of the basic storage unit. For each data block, a basic storage unit can be selected from the local cache RAM for the data block, and the data block can be stored in the basic storage unit.

[0056] When selecting a basic storage unit from the local cache RAM, the basic storage unit may be selected randomly, or a certain strategy may be adopted to select the basic storage unit, and there is no restriction on this selection method.

[0057] For the multiple data blocks of the serial port, the addresses of the basic storage units of different data blocks may be discontinuous, that is, the multiple data blocks of the serial port are not stored continuously in the local cache RAM.

[0058] On this basis, for the first data block of the serial port, the offset position of the basic storage unit where the data block is located is recorded in the fixed relationship table (the offset position represents the starting address of the basic storage unit in the local cache RAM, and the basic storage unit can be found based on the offset position and the size of the basic storage unit).

[0059] For example, the fixed relationship table may include a data table entry corresponding to each serial port. For the first serial port, the offset position of the basic storage unit where the data block is located may be recorded in the first data table entry of the fixed relationship table. For the second serial port, the offset position of the basic storage unit where the data block is located may be recorded in the second data table entry of the fixed relationship table, and so on. In addition, the offset address corresponding to the linked list item of the next data block in the address linked list may also be recorded in the data table entry of the fixed relationship table.

[0060] For the non-first data block of the serial port, the offset position of the basic storage unit where the data block is located is recorded in the address linked list (the offset position represents the first address of the basic storage unit in the local cache RAM, and the basic storage unit can be found based on the offset position and the size of the basic storage unit).

[0061] For example, the address linked list may include multiple linked list items, and a linked list item (i.e., an unused linked list item) may be selected for the data block from the multiple linked list items of the address linked list, and the offset position of the basic storage unit where the data block is located may be recorded in the selected linked list item. In addition, the offset address corresponding to the linked list item of the next data block in the address linked list may also be recorded in the linked list item of the address linked list.

[0062] For example, assume that data block 1 of serial port 1 is stored in basic storage unit a1, data block 2 of serial port 1 is stored in basic storage unit a2, data block 3 of serial port 1 is stored in basic storage unit a3, and the addresses of basic storage unit a1, basic storage unit a2 and basic storage unit a3 are not continuous.

[0063] Then, the offset position of the basic storage unit a1 can be recorded in the first data table item of the fixed relationship table (the data table item corresponding to serial port 1). The offset position of the basic storage unit a2 can be recorded in the link list item b1 of the address link list, and the link list item b1 is any unused link list item in the address link list. The offset position of the basic storage unit a3 can be recorded in the link list item b2 of the address link list, and the link list item b2 is any unused link list item in the address link list, and the address of the link list item b2 is not continuous with that of the link list item b1.

[0064] On this basis, the offset address corresponding to the linked list item b1 (i.e., the linked list item of the data block after the current data block) in the address linked list can also be recorded in the first data table item of the fixed relationship table. The offset address indicates the first address of the linked list item b1 in the address linked list, and the linked list item b1 can be found from the address linked list based on the offset address. In addition, the offset address corresponding to the linked list item b2 (i.e., the linked list item of the data block after the current data block) in the address linked list can also be recorded in the linked list item b1. The offset address indicates the first address of the linked list item b2 in the address linked list. Similarly, the offset address corresponding to the next linked list item in the address linked list can be recorded in each linked list item until the last linked list item. For the last linked list item, an end mark can be recorded in the linked list item to indicate that there are no other linked list items behind it.

[0065] For the reading process of serial port 1, the offset position of basic storage unit a1 and the offset address of linked list item b1 can be read from the first data table item of the fixed relationship table. Based on the offset address of linked list item b1, linked list item b1 can be found from the address linked list, and the offset position of basic storage unit a2 and the offset address of linked list item b2 can be read from linked list item b1. Based on the offset address of linked list item b2, linked list item b2 can be found from the address linked list, and the offset position of basic storage unit a3 can be read from linked list item b2, and so on, until the last linked list item. Since the last linked list item includes an end mark, no more linked list items are read.

[0066] In summary, the offset position of the basic storage unit a1, the offset position of the basic storage unit a2, and the offset position of the basic storage unit a3 can be read. Based on the offset position of the basic storage unit a1, data block 1 can be read from the basic storage unit a1 of the local cache RAM, based on the offset position of the basic storage unit a2, data block 2 can be read from the basic storage unit a2 of the local cache RAM, and based on the offset position of the basic storage unit a3, data block 3 can be read from the basic storage unit a3 of the local cache RAM.

[0067] See also Figure 6As shown, it is a schematic diagram of the dynamic management of the BM linked list RAM of the serial port. The mapping table can be stored through the BM linked list RAM, and the mapping table can include a fixed relationship table and an address linked list. The local cache RAM can include multiple basic storage units (Basic Memory). By configuring fixed relationship tables and address linked lists for these basic storage units, the dynamic management of the basic storage units is realized. Among them, the linked list RAM is a linked list data structure implemented using a random access memory (RAM) for dynamically managing data in memory. The linked list consists of a series of nodes, each of which contains data and one or more pointers to other nodes. It has the characteristics of dynamic memory allocation, flexible size, and high efficiency of insertion and deletion operations.

[0068] Each time a message is written, the address of the basic storage unit used last time by the same serial port is used as the address, and the address of the basic storage unit written this time is used as the data, and the address chain table is written to create a link relationship between two consecutive basic storage units of the same serial port. That is, as long as the address of the initial basic storage unit of a serial port is recorded (located in the fixed relationship table), all messages of the serial port can be found according to the address chain table.

[0069] See also Figure 6 As shown, when each serial port reads a message, it needs to first find the address of the basic storage unit according to the fixed relationship table and the address linked list, and then read the message from the address space of the local cache RAM.

[0070] In one example, a storage area can be divided in the internal storage medium of the processing device, and an address queue can be stored in the storage area. The address queue can be called a FIFO (First In First Out) of the basic storage unit address (i.e., BM address), and the address queue is used to record the offset position of the unoccupied basic storage unit (the first address of the basic storage unit in the local cache RAM).

[0071] In the initial case, all basic storage units are not occupied, and the address queue is used to record the offset positions of all basic storage units. During the writing process of the data block, the offset position of the basic storage unit can be selected from the address queue, and the data block is stored in the basic storage unit based on the offset position. In this way, the offset position needs to be deleted from the address queue, and so on, the offset position of the occupied basic storage unit is continuously deleted from the address queue. In addition, during the reading process of the data block, the data block is also read from the basic storage unit, so that the basic storage unit is called an unoccupied basic storage unit again, and then the offset position of the basic storage unit is re-recorded to the address queue, and so on, the offset position of the basic storage unit where the data is released is continuously added to the address queue.

[0072] In summary, the offset positions of the basic storage units (also called the addresses of the basic storage units, which are also the pointers of the address linked list) are all placed in the address queue. When a data block needs to be written in the basic storage unit, the offset position of a basic storage unit is read from the address queue (such as reading the offset position in a FIFO manner), and the message content is written into the basic storage unit corresponding to the offset position. After reading the content in the basic storage unit, the offset position of the basic storage unit can be recycled and written into the address queue (such as writing the offset position in a FIFO manner), so as to be recycled.

[0073] See also Figure 7 As shown, it is a schematic diagram of the local cache RAM, address queue and BM linked list RAM. The address queue (referred to as BM address FIFO) can record the offset positions of all unoccupied basic storage units, and the offset positions of these basic storage units are called BM Addr (ie, BM address).

[0074] In an example, the cache space of the internal storage medium, that is, the size of the local cache RAM, can be determined based on the number of WAN interfaces (such as E1 interfaces or T1 interfaces) divided by the CPOS interface, the number of time slots corresponding to each WAN interface, and the number of bytes sent in each time slot; wherein the cache space can be greater than or equal to K*P*U, that is, the size of the local cache RAM can be greater than or equal to K*P*U.

[0075] For example, K may represent the number of WAN interfaces divided by the CPOS interface, P may represent the number of time slots corresponding to each WAN interface, and U may represent the number of bytes sent in each time slot.

[0076] For example, the total size of the buffer space is determined according to the total number of E1 time slots. Assuming that each time slot is U bytes, that is, U bytes of data are sent in each time slot, the CPOS interface is divided into 32 E1 interfaces, and each E1 interface contains 32 time slots, then the total size of the buffer space can be U*32*32, that is, 1024*U bytes.

[0077] As long as U bytes satisfy the even scheduling of messages by 1024 serial ports with a rate of 64 Kbps, the continuity of scheduling U*N byte messages by the serial port containing N time slots can be guaranteed.

[0078] In an example, the size of the RAM space temporarily used for the serial port can be determined according to the number of time slots configured for the serial port. For example, if the serial port occupies 1 time slot, it is converted to use 2 basic storage units, and if it occupies 32 time slots, 64 basic storage units can be used. Since the time slots bound to different serial ports are mutually exclusive, it is guaranteed that the sum of the cache dynamically allocated by all serial ports will not exceed the total RAM space, that is, the RAM space is always sufficient. Due to the high-speed serial port, the local cache can also be multiplied accordingly. Therefore, in one scheduling, multiple messages can be read into the local cache, which is equivalent to caching the message reading of multiple single-time slot 64Kbps serial ports in one time. Even if polling is performed according to the average probability, polling for one week can ensure the continuity of the high-speed serial port messages, and there will be no abnormal reading of the local cache and discontinuity. In addition, for the read operation of DDR memory, the more bytes read in one time, the higher the read efficiency. Therefore, reading U*N bytes in one time is usually more efficient than reading N times, reading U bytes each time. Reading messages of multiple basic storage unit sizes at one time further shortens the time required for polling all serial ports once, thus improving efficiency.

[0079] In one example, the serial port message adopts the principle of "entering the queue when there is a message, and leaving the queue when there is no message to send" to perform polling, thereby reducing the "idle" situation of the empty serial port with no message to send, and further improving the efficiency of polling scheduling.

[0080] In an example, a local cache RAM with a basic storage unit as the basic unit and dynamic management using a linked list can be set, and the local cache RAM, address queue and BM linked list RAM are used together, see Figure 7 The size of the local cache RAM (i.e. the size and number of basic storage units) is set as follows:

[0081] Assuming that the processing device uses L E1 interfaces, polling scheduling of all serial ports under L E1 interfaces can be implemented. When each E1 interface configures the serial port according to "1 serial port binds 1 available time slot", 31*L serial ports will be generated to complete the continuous scheduling of this number of serial port messages. The minimum cache space required for each serial port is J bytes (it can be calculated based on the actual DDR memory scheduling efficiency, or confirmed by actual debugging, and there is no limit on the value of J). Based on this, the size of the local cache RAM can be set to 32*L*J. For the convenience of scheduling, the number of bytes scheduled each time is J / 2, that is, the size of each basic storage unit is defined as J / 2, and the number of BMs of the local cache RAM is equal to (64*L).

[0082] In an embodiment of the present application, a message transmission method is proposed, which can be applied to a processing device (such as an FPGA), the processing device can be an interface processing module of a target interface, and the target interface can include a channelized POS interface, i.e., a CPOS interface. The CPOS interface is divided into a plurality of WAN interfaces (the WAN interface can include but is not limited to an E1 interface or a T1 interface, etc.), each WAN interface is divided into a plurality of serial ports, each WAN interface corresponds to a plurality of time slots, and a serial port occupies at least one time slot.

[0083] See also Figure 8 FIG. 1 is a flow chart of a message transmission method, which may include:

[0084] Step 801: After receiving a serial port message, store the serial port message in an external storage medium of the processing device. For example, the processing device includes a message write cache module, and after receiving the serial port message, the message write cache module stores the serial port message in a DDR memory, which is an external storage medium.

[0085] Step 802: traverse each first serial port in turn, and read M first data blocks of the first serial port from an external storage medium of the processing device, where M may be the number of time slots occupied by the first serial port.

[0086] For example, the processing device may include a downlink cache polling scheduling module, and the downlink cache polling scheduling module traverses each serial port (each serial port is called a first serial port) in sequence. For example, first traverse the first serial port 1. If the first serial port 1 occupies 3 time slots, then read the 3 first data blocks of the first serial port 1 from the external storage medium (each data block is called a first data block). The size of the first data block can be the same as the size of the basic storage unit, and the size of the first data block can also be smaller than the size of the basic storage unit. Then, traverse the first serial port 2. If the first serial port 2 occupies 6 time slots, then read the 6 first data blocks of the first serial port 2 from the external storage medium, and so on. It is necessary to poll and traverse the first data blocks of each first serial port.

[0087] In one example, the processing device may set a serial port polling FIFO, and the serial port polling FIFO may record the serial port to be scheduled (i.e., the first serial port traversed above, i.e., traversing each first serial port in the serial port polling FIFO in turn). Fig. 9 The figure shows the scheduling diagram of the serial port polling FIFO. In the initialization state, the serial port polling FIFO is empty. When a message of a serial port S is stored in the DDR memory and the message needs to be scheduled and output to the local cache RAM, the information of the serial port S is added to the serial port polling FIFO.

[0088] When a certain serial port is read out from the serial port polling FIFO (i.e., traversed to the serial port) and the scheduling is completed, the M first data blocks of the serial port have been read from the DDR memory. Then, it is determined whether the message of the serial port is read empty, that is, whether the serial port has messages to be read. If the message is read empty from the DDR memory, the serial port will not re-polling the serial port FIFO after reading it out from the serial port polling FIFO. Otherwise, the serial port re-polling the serial port FIFO and continues to participate in the polling scheduling.

[0089] In an example, the length of each message from the DDR memory to the local cache RAM (i.e., the length of the M first data blocks) can be set according to the rate of the serial port, i.e., the number of bound time slots. Assuming that the cache space corresponding to each time slot is 2 basic storage units, each basic storage unit corresponds to C bytes, then for a serial port bound to M time slots (such as a serial port of an E1 interface with a rate of (64*T) Kbps), the number of bytes scheduled each time is M*C, i.e., M first data blocks, each of which has a size of C bytes, and the data block in this embodiment represents C bytes of data.

[0090] In an example, for each serial port, taking serial port S as an example, the method for determining the local cache margin set for serial port S can be: record the number of messages of serial port S output from the local cache RAM as Dout (with the basic storage unit cache byte as the basic counting unit), and record the number of messages dispatched from the DDR memory by serial port S as Din (with the basic storage unit cache byte as the basic counting unit). Assuming that the serial port contains M time slots, the total cache is 2M basic storage units. Based on this, the local cache margin Dfree can be expressed by the following formula: Dfree = 2M + Dout - Din.

[0091] Step 803: for each first data block of the first serial port, select a basic storage unit of the first data block from the internal storage medium of the processing device, and store the first data block in the basic storage unit.

[0092] For example, a local cache RAM can be divided in the internal storage medium, the local cache RAM is shared by all serial ports, and the local cache RAM includes multiple basic storage units. On this basis, after the downlink cache polling scheduling module reads the first data block of the first serial port from the DDR memory, it selects a basic storage unit from all the basic storage units and stores the first data block through the selected basic storage unit.

[0093] In one example, an address queue may be pre-stored, and the address queue is used to record the offset position of an unoccupied basic storage unit. Based on this, when selecting a basic storage unit of the first data block, the offset position of the basic storage unit may be selected from the address queue, such as by reading the first offset position in the address queue in a FIFO manner, determining the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and deleting the offset position from the address queue (i.e., the basic storage unit corresponding to the offset position is occupied). In this way, the first data block may be stored by the basic storage unit.

[0094] In an example, the processing method of the address queue can be: remove the basic storage unit with address 0 (as an invalid basic storage unit, initialize the write address list and the initial value of the unused serial port buffer address), and write the offset positions of the remaining basic storage units into the address queue in sequence. When there is a demand for writing a data block, read the offset position of a basic storage unit from the address queue. When the content of the data block stored in the basic storage unit is read empty, the offset position of the basic storage unit is recovered and written into the address queue.

[0095] Step 804: for each first data block of the first serial port, after the first data block is stored in the basic storage unit, the offset position of the basic storage unit in the internal storage medium is recorded in the mapping table.

[0096] For example, the mapping table may include a fixed relationship table and an address chain table, the fixed relationship table includes a data table entry corresponding to each serial port, and the address chain table (such as a BM chain table) includes a plurality of chain table entries shared by all serial ports. Based on this, for the first first data block of the first serial port, the downlink cache polling scheduling module determines the target data table entry corresponding to the first serial port from the fixed relationship table, records the offset position of the basic storage unit where the first data block is located in the target data table entry, and records the offset address corresponding to the target chain table entry of the first data block after the first data block in the address chain table in the target data table entry.

[0097] For the non-first first data block of the first serial port, the downlink cache polling scheduling module can select an unused linked list item for the first data block from multiple linked list items in the address linked list, and use this unused linked list item as the target linked list item corresponding to the first data block, record the offset position of the basic storage unit where the first data block is located in the target linked list item, and record the offset address corresponding to the target linked list item of the next first data block after the first data block in the address linked list in the target linked list item.

[0098] For an example, see Fig.10 The figure shows a schematic diagram of the update process of the address linked list.

[0099] Step 1001, in the initial state, determine whether the address list is initialized to 0. If yes, execute step 1002. If not, continue to wait and return to step 1001. For example, initializing the address list to 0 means initializing the address list to an invalid value (invalid basic storage unit space).

[0100] Step 1002: Enter the address linked list continuous update state.

[0101] Step 1003: When a message is to be written into the local cache RAM by the serial port (assuming the serial port number is S), the offset position of the last basic storage unit of the serial port S corresponding to the message is queried and recorded as ADDR_OLD.

[0102] Step 1004: determine whether ADDR_OLD is equal to 0 (0 indicates invalid).

[0103] If yes, step 1005 may be executed, and if no, step 1006 may be executed.

[0104] Step 1005: If ADDR_OLD is equal to 0, it means that the serial port S is caching a message for the first time, therefore, the offset address ADDR_NEW of one basic storage unit is read from the address queue, and the offset address ADDR_NEW is written into the address linked list as both the address and the content.

[0105] Step 1006: If ADDR_OLD is not equal to 0, it means that the serial port S is not caching the message for the first time. Therefore, the offset address ADDR_NEW of one basic storage unit is read from the address queue, and the offset position ADDR_OLD is used as the address and the offset address ADDR_NEW is written into the address linked list as the content.

[0106] After step 1005 , return to step 1002 , and after step 1006 , return to step 1002 .

[0107] At this point, the update process of the address list is completed and you can continue to execute subsequent steps.

[0108] Step 805, traverse each second serial port in turn, for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position.

[0109] For example, the processing device may include a serial port framing module, and the serial port framing module traverses each serial port in turn (each serial port is referred to as a second serial port). For example, first traverse the second serial port 1, if the second serial port 1 corresponds to 3 second data blocks (each data block is referred to as a second data block), then obtain the offset position of the basic storage unit where the second data block 1 is located from the mapping table, and read the second data block 1 from the basic storage unit corresponding to the offset position. Obtain the offset position of the basic storage unit where the second data block 2 is located from the mapping table, and read the second data block 2 from the basic storage unit corresponding to the offset position, and so on.

[0110] In one example, the processing device can set a serial port polling FIFO, and the serial port polling FIFO can record the serial port to be scheduled. Based on this, the downlink cache polling scheduling module traverses each first serial port in turn from the serial port polling FIFO, and executes step 802 for each first serial port. The serial port framing module traverses each second serial port in turn from the serial port polling FIFO, and executes step 805 for each second serial port.

[0111] For the second serial port currently traversed, first determine the data table entry corresponding to the second serial port from the fixed relationship table (such as the first second serial port corresponds to the first data table entry, and so on), obtain the offset position of the basic storage unit where the second data block 1 (that is, the first second data block of the second serial port) is located from the data table entry, and obtain the offset address corresponding to the second data block 2 following the second data block 1 from the data table entry (the offset address represents the offset address corresponding to the linked list entry of the second data block 2 in the address linked list. Then, the offset position and offset address recorded in the data table entry can also be deleted.

[0112] Based on the offset address corresponding to the second data block 2, a linked list item of the second data block 2 is determined from the address linked list; the offset position of the basic storage unit where the second data block 2 is located is obtained from the linked list item, and the offset address corresponding to the next second data block 3 after the second data block 2 is obtained from the linked list item. Then, the offset position and the offset address recorded in the linked list item can also be deleted.

[0113] Based on the offset address corresponding to the second data block 3, determine the linked list item of the second data block 3 from the address linked list; obtain the offset position of the basic storage unit where the second data block 3 is located from the linked list item, and so on, repeat the above process until the offset position of the basic storage unit where the last second data block is located is obtained.

[0114] Step 806: for each second data block of the second serial port, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, record the offset position of the basic storage unit where the second data block is located into the address queue, that is, recycle the offset position in the address queue.

[0115] Step 807: for each second data block of the second serial port, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, perform a framing operation on the second data block.

[0116] For example, the processing device may include a serial port framing module, which performs a serial port framing operation on the message after reading the second data block from the basic storage unit, that is, adding serial port information to the message. The processing device may include an E1 framing module, which obtains the message after the serial port framing operation from the serial port framing module, and performs an E1 interface framing operation on the message, that is, adding E1 header information to the message. The processing device may include a CPOS framing module, which obtains the message after the E1 interface framing operation from the E1 framing module, and performs a CPOS framing operation on the message, that is, adding CPOS header information to the message.

[0117] Step 808: Send each second data block of the second serial port in the time slot occupied by the second serial port.

[0118] For example, for the second serial port currently traversed, assuming that the second serial port occupies 3 time slots, the second data block 1 is sent in the first time slot occupied by the second serial port, such as sending the message after the framing operation. The second data block 2 is sent in the second time slot occupied by the second serial port. The second data block 3 is sent in the third time slot occupied by the second serial port. So far, each second data block of the second serial port can be sent.

[0119] In an example, taking serial port S as an example, the number of messages Dwr written to the local cache RAM can be recorded. The number of messages Dwr represents the total number of data blocks stored for serial port S through the internal storage medium, which is subsequently recorded as the second number. The second number represents the total number of data blocks, and can also represent the total number of bytes of all data blocks (in BYTE), and record the Head Address of the address list of the written message.

[0120] After each time a second data block (i.e., the second data block of the serial port S) is read from the basic storage unit, the number of messages Drd of the second data block read (read out) from the internal storage medium can also be determined. The number of messages Drd represents the total number of data blocks read out from the local cache RAM for the serial port S, which is subsequently recorded as the first number. The first number can represent the total number of data blocks or the total number of bytes of all data blocks (in BYTE), and the Tail Address of the read address linked list is recorded.

[0121] On this basis, the remaining readable number can be determined based on the first number and the second number. For example, the remaining readable number Dram can be determined using the following formula: Dram=Dwr-Drd.

[0122] If the remaining number of readable data is greater than 0, it is determined that the data reading for the second serial port has not been completed and data reading needs to continue. For example, the offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position. For example, the serial port framing module can use Tail Address to find the message of the address in the local cache RAM and the linked list address of the next basic storage unit to be read (that is, the offset address corresponding to the linked list item in the address linked list). Alternatively, if the remaining number of readable data is equal to 0, it is determined that the data reading for the second serial port has been completed, that is, the data of the second serial port does not exist in the local cache RAM, and the serial port framing module does not read the message from the local cache RAM, but directly fills the IDLE code into the line, and there is no restriction on this.

[0123] For example, FPGA and other processing devices can be used to implement this process, record the above information in each clock cycle, and detect in real time whether the output conditions are met (when the data reading for the second serial port is not completed, it means that the conditions are met, and when the data reading for the second serial port is completed, it means that the conditions are not met), thereby realizing the write scheduling and read scheduling of the message in the local cache RAM.

[0124] In an example, when the user needs to release a serial port (such as serial port S), the cache information of serial port S can be cleared to deregister the serial port. For example, the following clearing operations can be performed. Clear the number of messages Dwr of serial port S written to the local cache RAM. Clear the Head Address of the address list of the written message. Clear the number of messages Drd read out. Clear the Tail Address of the read address list. Release the address list finally occupied by the serial port S to the address queue for the clock of other serial ports. When the serial port framing module corresponding to serial port S requests a message from the local RAM, it sees that the address list is 0, and returns no message to send. The serial port framing module continues to send IDLE code to the line.

[0125] It can be seen from the above technical solutions that in the embodiment of the present application, the mutually exclusive characteristics of serial port binding time slots of the same wide area network interface under the CPOS interface are utilized to optimize the performance of multiple serial port sending cache polling under the CPOS interface. Under similar logical cache resource conditions, more serial ports can be reliably realized, the problem of limited total number of serial ports can be solved, and the performance of the CPOS interface can be more fully released to meet user needs. The total amount of cache of the internal storage medium is determined by the number of time slots, and the dynamic allocation and polling scheduling of multiple serial ports are realized by using the linked list technology, so as to dynamically allocate the cache resources of the internal storage medium, dynamically adjust the number of bytes of each serial port polling read message, improve the utilization rate and scheduling efficiency of the internal storage medium, and save storage resources. The size of the local cache RAM is dynamically adjusted according to the serial port rate, the utilization rate of the local cache RAM and the efficiency of DDR scheduling are improved, and the continuity of serial port sending is better guaranteed. A serial port scheduling scheme is proposed in which there are messages in the queue and the messages are sent out of the queue, so as to reduce the idling of the serial port without messages and improve the efficiency of polling scheduling. The size of the local cache RAM is set according to the number of time slots included in all E1 interfaces, that is, to meet the minimum cache required to ensure that all available serial ports contain 1 time slot (at the minimum rate) and evenly schedule to ensure the continuity of messages. Set the serial port polling entry and exit mechanism. When serial port S has a message stored in DDR and needs to be scheduled to be output to the local cache RAM, the information of serial port S is added to the polling FIFO; when the serial port reads out from the polling FIFO and completes the scheduling and the serial port message is read empty, it will not be re-queued. Set the clear register to clear the number of messages written to the local cache RAM by the serial port, the head address of the address linked list, and the number of messages read and the tail address of the address linked list to release the serial port cache, solving the problem of temporarily using 1 time slot cache for serial port cancellation.

[0126] In the embodiment of the present application, a message transmission method is proposed, which is applied to a processing device, wherein the target interface corresponding to the processing device is divided into multiple WAN interfaces, each WAN interface is divided into multiple serial ports, each WAN interface corresponds to multiple time slots, and a serial port occupies at least one time slot, and the target interface includes a channelized POS interface. Fig.11 FIG. 1 is a flow chart of the method, which may include:

[0127] Step 1101 , for a data writing process, traverse each first serial port in turn, and read M first data blocks of the first serial port from an external storage medium of a processing device, where M is the number of time slots occupied by the first serial port.

[0128] Step 1102: for each first data block, select a basic storage unit of the first data block from the internal storage medium of the processing device, store the first data block through the basic storage unit, and record the offset position of the basic storage unit in the internal storage medium in a mapping table.

[0129] Step 1103: for the data sending process, traverse each second serial port in turn, and for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position.

[0130] Step 1104: Send each second data block of the second serial port in the time slot occupied by the second serial port.

[0131] In one example, selecting a basic storage unit of a first data block from an internal storage medium of a processing device may include: selecting an offset position of a basic storage unit from an address queue, determining the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and deleting the offset position from the address queue; wherein the address queue is used to record the offset position of unoccupied basic storage units.

[0132] In one example, after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, the offset position of the basic storage unit where the second data block is located can also be determined, and the offset position of the basic storage unit can be recorded in the address queue.

[0133] In one example, the mapping table may include a fixed relationship table and an address linked list, the fixed relationship table may include a data table item corresponding to each serial port one by one, and the address linked list may include multiple linked list items shared by all serial ports. Based on this, recording the offset position of the basic storage unit in the internal storage medium in the mapping table may include: for the first first data block of the first serial port, determining the target data table item corresponding to the first serial port from the fixed relationship table, recording the offset position of the basic storage unit where the first data block is located in the target data table item, and recording the offset address corresponding to the target linked list item of the next first data block of the first data block in the address linked list in the target data table item; for the non-first first data block of the first serial port, selecting the target linked list item corresponding to the first data block from the address linked list, recording the offset position of the basic storage unit where the first data block is located in the target linked list item, and recording the offset address corresponding to the target linked list item of the next first data block of the first data block in the address linked list in the target linked list item.

[0134] In one example, obtaining the offset position of the basic storage unit where the second data block is located from a mapping table may include: for the first second data block of the second serial port, determining the data table item corresponding to the second serial port from the fixed relationship table, obtaining the offset position of the basic storage unit where the second data block is located from the data table item, and obtaining the offset address corresponding to the next second data block of the second data block from the data table item; wherein the offset address represents the offset address corresponding to the linked list item in the address linked list; for the non-first second data block of the second serial port, determining the linked list item of the second data block from the address linked list based on the offset address corresponding to the second data block; obtaining the offset position of the basic storage unit where the second data block is located from the linked list item, and obtaining the offset address corresponding to the next second data block of the second data block from the linked list item.

[0135] In one example, after obtaining the offset position of the basic storage unit where the second data block is located from the data table entry and obtaining the offset address corresponding to the next second data block after the second data block from the data table entry, the offset position and offset address recorded in the data table entry can also be deleted.

[0136] In one example, after obtaining the offset position of the basic storage unit where the second data block is located from the linked list item and obtaining the offset address corresponding to the next second data block after the second data block from the linked list item, the offset position and offset address recorded in the linked list item can also be deleted.

[0137] In an example, after each time a second data block is read from a basic storage unit of an internal storage medium, a first number of second data blocks read from the internal storage medium is determined; a remaining readable number is determined based on the first number and the second number, the second number representing the total number of data blocks stored for the second serial port through the internal storage medium; if the remaining readable number is greater than 0, it is determined that data reading for the second serial port is not completed, the offset position of the basic storage unit where the next second data block is located is obtained from a mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position; if the remaining readable number is equal to 0, it is determined that data reading for the second serial port is completed.

[0138] In one example, the cache space of the internal storage medium may also be determined based on the number of WAN interfaces divided by the target interface, the number of time slots corresponding to each WAN interface, and the number of bytes sent in each time slot; wherein the cache space may be greater than or equal to K*P*U;

[0139] Wherein, K represents the number of WAN interfaces divided by the target interface, P represents the number of time slots corresponding to each WAN interface, and U represents the number of bytes sent in each time slot.

[0140] It can be seen from the above technical solutions that in the embodiment of the present application, the mutually exclusive characteristics of serial port binding time slots of the same wide area network interface under the CPOS interface are utilized to optimize the performance of multiple serial port sending cache polling under the CPOS interface, and reliably realize more serial ports under similar logical cache resource conditions, solve the problem of limited total number of serial ports, and more fully release the performance of the CPOS interface to meet user needs. The total amount of cache of the internal storage medium is determined by the number of time slots, and the linked list technology is used to realize dynamic allocation and polling scheduling of multiple serial ports, thereby dynamically allocating the cache resources of the internal storage medium, dynamically adjusting the number of bytes of each serial port polling read message, improving the utilization rate and scheduling efficiency of the internal storage medium, and saving storage resources.

[0141] Based on the same application concept as the above method, a message transmission device is proposed in the embodiment of the present application, which is applied to a processing device, wherein the target interface corresponding to the processing device is divided into a plurality of wide area network interfaces, each wide area network interface is divided into a plurality of serial ports, each wide area network interface corresponds to a plurality of time slots, and a serial port occupies at least one time slot, see Fig.12 FIG. 1 is a schematic diagram of the structure of the device, and the device may include:

[0142] The message buffer module 1201 is used to traverse each first serial port in turn and read M first data blocks of the first serial port from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port;

[0143] For each first data block, select a basic storage unit of the first data block from an internal storage medium of a processing device, store the first data block through the basic storage unit, and record an offset position of the basic storage unit in the internal storage medium in a mapping table;

[0144] The framing module 1202 is configured to sequentially traverse each second serial port, obtain, for each second data block of the second serial port, an offset position of a basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position;

[0145] The interface sending module 1203 is configured to send each second data block of the second serial port in the time slot occupied by the second serial port after the framing module reads the second data block.

[0146] In one example, the message buffer module 1201 selects the basic storage unit of the first data block from the internal storage medium of the processing device, specifically for:

[0147] Selecting an offset position of a basic storage unit from the address queue, determining the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and deleting the offset position from the address queue; wherein the address queue is used to record the offset position of the basic storage unit that is not occupied;

[0148] The framing module 1202 is further configured to determine the offset position of the basic storage unit where the second data block is located after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, and record the offset position of the basic storage unit into the address queue.

[0149] In one example, the mapping table includes a fixed relationship table and an address linked list, the fixed relationship table includes a data table entry corresponding to each serial port one by one, and the address linked list includes multiple linked list entries shared by all serial ports; when the message cache module 1201 records the offset position of the basic storage unit in the internal storage medium in the mapping table, it is specifically used to: for the first first data block of the first serial port, determine the target data table entry corresponding to the first serial port from the fixed relationship table, record the offset position of the basic storage unit where the first data block is located in the target data table entry, and record the offset address of the target linked list entry of the next first data block of the first data block in the target data table entry in the address linked list; for the non-first first data block of the first serial port, select the target linked list entry corresponding to the first data block from the address linked list, record the offset position of the basic storage unit where the first data block is located in the target linked list entry, and record the offset address of the target linked list entry of the next first data block of the first data block in the address linked list in the target linked list entry.

[0150] In one example, when the framing module 1202 obtains the offset position of the basic storage unit where the second data block is located from the mapping table, it is specifically used to:

[0151] For the first second data block of the second serial port, determine the data table item corresponding to the second serial port from the fixed relationship table, obtain the offset position of the basic storage unit where the second data block is located from the data table item, and obtain the offset address corresponding to the next second data block after the second data block from the data table item; wherein the offset address represents the offset address corresponding to the linked list item in the address linked list;

[0152] For the non-first second data block of the second serial port, based on the offset address corresponding to the second data block, determine the linked list item of the second data block from the address linked list;

[0153] The offset position of the basic storage unit where the second data block is located is obtained from the linked list item, and the offset address corresponding to the next second data block after the second data block is obtained from the linked list item.

[0154] In one example, the framing module 1202 is further used to delete the offset position and offset address recorded in the data table entry after obtaining the offset position of the basic storage unit where the second data block is located from the data table entry and obtaining the offset address corresponding to the next second data block after the second data block from the data table entry; the framing module 1202 is further used to delete the offset position and offset address recorded in the linked list entry after obtaining the offset position of the basic storage unit where the second data block is located from the linked list entry and obtaining the offset address corresponding to the next second data block after the second data block from the linked list entry.

[0155] In one example, the framing module 1202 obtains the offset position of the basic storage unit where the second data block is located from the mapping table, and reads the second data block from the basic storage unit of the internal storage medium based on the offset position, specifically for:

[0156] After each reading of a second data block from a basic storage unit of the internal storage medium, determining a first number of second data blocks read from the internal storage medium;

[0157] determining a remaining readable quantity based on the first quantity and a second quantity, the second quantity representing a total quantity of data blocks stored for the second serial port via the internal storage medium;

[0158] If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port is not completed, the offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position;

[0159] If the remaining readable quantity is equal to 0, it is determined that the data reading for the second serial port has been completed.

[0160] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0161] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A message transmission method, characterized in that: Applied to a processing device, the target interface corresponding to the processing device is divided into a plurality of wide area network interfaces, each wide area network interface is divided into a plurality of serial ports, each wide area network interface corresponds to a plurality of time slots, and a serial port occupies at least one time slot, the method comprising: For the data writing process, traverse each first serial port in turn, and read M first data blocks of the first serial port from the external storage medium of the processing device, where M is the number of time slots occupied by the first serial port; For each first data block, selecting a basic storage unit of the first data block from an internal storage medium of the processing device, storing the first data block through the basic storage unit, and recording an offset position of the basic storage unit in the internal storage medium in a mapping table; In the data sending process, traverse each second serial port in turn, and for each second data block of the second serial port, obtain the offset position of the basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position; Each second data block of the second serial port is sent in the time slot occupied by the second serial port.

2. The method according to claim 1, characterized in that The step of selecting a basic storage unit of the first data block from an internal storage medium of the processing device comprises: Selecting an offset position of a basic storage unit from the address queue, determining the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and deleting the offset position from the address queue; wherein the address queue is used to record the offset position of an unoccupied basic storage unit; After reading the second data block from the basic storage unit of the internal storage medium based on the offset position, the method further includes: determining the offset position of the basic storage unit where the second data block is located, and recording the offset position of the basic storage unit into the address queue.

3. The method according to claim 1, characterized in that The mapping table includes a fixed relationship table and an address chain table, the fixed relationship table includes a data table entry corresponding to each serial port one by one, and the address chain table includes a plurality of chain table entries shared by all serial ports; The recording in the mapping table the offset position of the basic storage unit in the internal storage medium comprises: For the first first data block of the first serial port, determine the target data table entry corresponding to the first serial port from the fixed relationship table, record the offset position of the basic storage unit where the first data block is located in the target data table entry, and record the offset address of the target linked list entry of the first data block after the first data block in the address linked list in the target data table entry; For the non-first first data block of the first serial port, a target linked list item corresponding to the first data block is selected from the address linked list, the offset position of the basic storage unit where the first data block is located is recorded in the target linked list item, and the offset address corresponding to the target linked list item of the next first data block after the first data block in the address linked list is recorded in the target linked list item.

4. The method according to claim 3, characterized in that The obtaining the offset position of the basic storage unit where the second data block is located from the mapping table includes: For the first second data block of the second serial port, determine the data table item corresponding to the second serial port from the fixed relationship table, obtain the offset position of the basic storage unit where the second data block is located from the data table item, and obtain the offset address corresponding to the next second data block after the second data block from the data table item; wherein the offset address represents the offset address corresponding to the linked list item in the address linked list; For the non-first second data block of the second serial port, based on the offset address corresponding to the second data block, determine the linked list item of the second data block from the address linked list; The offset position of the basic storage unit where the second data block is located is obtained from the linked list item, and the offset address corresponding to the next second data block after the second data block is obtained from the linked list item.

5. The method according to claim 4, characterized in that After obtaining the offset position of the basic storage unit where the second data block is located from the data table entry, and obtaining the offset address corresponding to the next second data block after the second data block from the data table entry, the method further includes: deleting the offset position and the offset address recorded in the data table entry; After obtaining the offset position of the basic storage unit where the second data block is located from the linked list item and obtaining the offset address corresponding to the next second data block after the second data block from the linked list item, the method further includes: deleting the offset position and offset address recorded in the linked list item.

6. The method according to claim 1, characterized in that The acquiring the offset position of the basic storage unit where the second data block is located from the mapping table, and reading the second data block from the basic storage unit of the internal storage medium based on the offset position, comprises: After each reading of a second data block from a basic storage unit of the internal storage medium, determining a first number of second data blocks read from the internal storage medium; determining a remaining readable quantity based on the first quantity and a second quantity, the second quantity representing a total quantity of data blocks stored for the second serial port via the internal storage medium; If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port is not completed, the offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position; If the remaining readable quantity is equal to 0, it is determined that the data reading for the second serial port has been completed.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Determining the cache space of the internal storage medium based on the number of wide area network interfaces divided by the target interface, the number of time slots corresponding to each wide area network interface, and the number of bytes sent in each time slot; Wherein, the cache space is greater than or equal to K*P*U; Wherein, K represents the number of WAN interfaces divided by the target interface, P represents the number of time slots corresponding to each WAN interface, and U represents the number of bytes sent in each time slot; The target interface includes a channelized POS interface.

8. A message transmission device, characterized in that: Applied to a processing device, the target interface corresponding to the processing device is divided into a plurality of wide area network interfaces, each wide area network interface is divided into a plurality of serial ports, each wide area network interface corresponds to a plurality of time slots, and a serial port occupies at least one time slot, the device comprises: A message buffer module, used for traversing each first serial port in turn, and reading M first data blocks of the first serial port from an external storage medium of the processing device, where M is the number of time slots occupied by the first serial port; For each first data block, select a basic storage unit of the first data block from an internal storage medium of a processing device, store the first data block through the basic storage unit, and record an offset position of the basic storage unit in the internal storage medium in a mapping table; a framing module, configured to traverse each second serial port in sequence, obtain, for each second data block of the second serial port, an offset position of a basic storage unit where the second data block is located from the mapping table, and read the second data block from the basic storage unit of the internal storage medium based on the offset position; The interface sending module is used to send each second data block of the second serial port in the time slot occupied by the second serial port after the framing module reads the second data block.

9. The device according to claim 8, characterized in that The message buffer module selects the basic storage unit of the first data block from the internal storage medium of the processing device specifically for: Selecting an offset position of a basic storage unit from the address queue, determining the basic storage unit corresponding to the offset position as the basic storage unit of the first data block, and deleting the offset position from the address queue; wherein the address queue is used to record the offset position of the basic storage unit that is not occupied; The framing module is further configured to determine the offset position of the basic storage unit where the second data block is located after reading the second data block from the basic storage unit of the internal storage medium based on the offset position, and record the offset position of the basic storage unit into the address queue.

10. The device according to claim 8, characterized in that The mapping table includes a fixed relationship table and an address chain table, the fixed relationship table includes a data table entry corresponding to each serial port one by one, and the address chain table includes a plurality of chain table entries shared by all serial ports; When the message cache module records the offset position of the basic storage unit in the internal storage medium in the mapping table, it is specifically used to: determine the target data table item corresponding to the first serial port from the fixed relationship table for the first first data block of the first serial port, record the offset position of the basic storage unit where the first data block is located in the target data table item, and record the offset address corresponding to the target linked list item of the first data block after the first data block in the address linked list in the target data table item; For the non-first first data block of the first serial port, a target linked list item corresponding to the first data block is selected from the address linked list, the offset position of the basic storage unit where the first data block is located is recorded in the target linked list item, and the offset address corresponding to the target linked list item of the next first data block after the first data block in the address linked list is recorded in the target linked list item.

11. The device according to claim 10, characterized in that When the framing module obtains the offset position of the basic storage unit where the second data block is located from the mapping table, it is specifically used to: For the first second data block of the second serial port, determine the data table item corresponding to the second serial port from the fixed relationship table, obtain the offset position of the basic storage unit where the second data block is located from the data table item, and obtain the offset address corresponding to the next second data block after the second data block from the data table item; wherein the offset address represents the offset address corresponding to the linked list item in the address linked list; For the non-first second data block of the second serial port, based on the offset address corresponding to the second data block, determine the linked list item of the second data block from the address linked list; The offset position of the basic storage unit where the second data block is located is obtained from the linked list item, and the offset address corresponding to the next second data block after the second data block is obtained from the linked list item.

12. The device according to claim 11, characterized in that The framing module is further configured to delete the offset position and the offset address recorded in the data table entry after obtaining the offset position of the basic storage unit where the second data block is located from the data table entry and obtaining the offset address corresponding to the next second data block after the second data block from the data table entry; The framing module is further configured to delete the offset position and offset address recorded in the linked list item after obtaining the offset position of the basic storage unit where the second data block is located from the linked list item and obtaining the offset address corresponding to the next second data block after the second data block from the linked list item.

13. The device according to claim 8, characterized in that The framing module obtains the offset position of the basic storage unit where the second data block is located from the mapping table, and reads the second data block from the basic storage unit of the internal storage medium based on the offset position, specifically for: After each reading of a second data block from a basic storage unit of the internal storage medium, determining a first number of second data blocks read from the internal storage medium; determining a remaining readable quantity based on the first quantity and a second quantity, the second quantity representing a total quantity of data blocks stored for the second serial port via the internal storage medium; If the remaining readable quantity is greater than 0, it is determined that the data reading for the second serial port is not completed, the offset position of the basic storage unit where the next second data block is located is obtained from the mapping table, and the second data block is read from the basic storage unit of the internal storage medium based on the offset position; If the remaining readable quantity is equal to 0, it is determined that the data reading for the second serial port has been completed.

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