Compound dielectric gate dual transistor readout method for variable slope based hdr

Abstract

The application discloses a composite dielectric gate dual transistor reading method based on variable slope to realize HDR and belongs to the field of integrated circuits. By adding a specific nonlinear slope voltage (the slope voltage is small in the front section, large in the middle section, and small again in the rear section) to the gate of a composite dielectric gate dual transistor photosensitive detector, the comparator flip time of pixel points in the low brightness and high brightness intervals is lengthened, that is, the gray value range of the two intervals is enlarged, but the pixel in the middle gray value is not enlarged, so that the imaging effect of HDR is achieved at the circuit end, the problems of large power consumption and high complexity caused by processing at the algorithm end are avoided, the scheme of the application does not need to pass through multiple exposure imaging and additional algorithm processing, and the implementation method is simple.

Description

TECHNICAL FIELD

[0001] The application relates to a composite medium gate dual transistor readout method based on a variable slope for realizing HDR. BACKGROUND

[0002] An image sensor is a device for imaging by using a photoelectric device, converting a light signal on a photosensitive surface into an electric signal in a corresponding proportional relationship with the light signal, and then quantizing the changed analog signal into a digital signal through a designed circuit to realize imaging. In existing image sensors, CCD and CMOS-APS have been widely used. A composite medium gate dual transistor photosensitive detector is disclosed in Chinese Patent Publication No. CN102938409A. The photosensitive detector has a dual transistor structure, and is provided with a photosensitive transistor and a reading transistor for respectively realizing photosensitive function and reading function. The composite structure makes the photosensitive transistor part not need to be made into a source-drain. Compared with a traditional photoelectric detector, the photosensitive detector has the advantages of low dark current, no interference between photosensitive units, high quantum efficiency and the like. When the composite medium gate dual transistor photosensitive detector is read out, different light responses will make the threshold voltage of the reading transistor different, and therefore the light signal can be read out through a fixed gate voltage quantization drain current or a fixed current quantization gate voltage and the like.

[0003] The quantization mode of a traditional readout circuit is linear quantization, that is, the light response intensity and the converted electric signal are linearly corresponding. For the readout of the composite medium gate dual transistor, Chinese Patent Publication No. CN111147078A proposes an analog-to-digital conversion circuit based on the composite medium gate dual transistor photosensitive detector. Through an off-chip slope voltage source, the device light response can be converted into digital readout. In addition, Chinese Patent Publication Nos. CN116017184A and CN117135478A respectively propose a composite medium gate dual transistor pixel readout circuit based on an inverter chain transimpedance amplifier and a composite medium gate transistor pixel readout circuit based on a double transimpedance amplifier. The former adopts a mode of applying a slope voltage to the gate of the composite medium gate dual transistor for readout, and the latter adopts a mode of a slope current source plus a cross-group amplifier for readout. In the above schemes, whether it is a slope voltage source or a slope current source, a fixed slope slope signal is adopted, and the light responses of all pixels are linearly quantized. Therefore, for an image with a large range of brightness, if the exposure time is short, the dark pixel points cannot obtain good imaging effect; if the exposure time is long, the bright pixel points cannot obtain good imaging effect.

[0004] In order to improve the imaging effect of the image with large light and dark range, high dynamic range imaging technology (High Dynamic Range Imaging, HDR) can be used to make the range of highlights and shadows in the image wider by improving the image brightness range, so that the image details are more full and correctly represent the brightness range from direct sunlight to the darkest shadow in the real world. The traditional method to realize HDR is to use time domain multi-frame synthesis method, that is, to shoot multiple images (for example, to shoot three frames, short exposure time frame, medium exposure time frame and long exposure time frame) with different exposure times, and then to synthesize, which usually needs to be processed at the algorithm end, resulting in large power consumption and higher complexity. SUMMARY

[0005] In order to improve the imaging effect of the image with large light and dark range without increasing power consumption and complexity, the application provides a composite medium gate dual transistor readout circuit and readout method based on variable slope to realize HDR, which is improved on the basis of the readout circuit framework provided in the Chinese invention patent with publication number CN111147078A, and realizes HDR imaging at the circuit end without multiple exposure imaging and additional algorithm processing, so that the method is simple and does not bring additional power consumption.

[0006] A composite medium gate dual transistor readout method based on variable slope to realize HDR, which non-linearly reads out the threshold voltage of the composite medium gate dual transistor by applying a slope voltage with variable slope to the gate of the composite medium gate dual transistor; the slope of the slope voltage is small at both ends and large in the middle.

[0007] Optionally, the method is realized by a composite medium gate dual transistor readout circuit based on variable slope to realize HDR, which includes a composite medium gate dual transistor photosensitive detector, a slope controllable slope generation circuit, a clamping circuit, an integration capacitor, a comparator circuit and a counter; wherein the slope controllable slope generation circuit is connected to the gate of the composite medium gate dual transistor photosensitive detector, the source of the composite medium gate dual transistor photosensitive detector is grounded, and the drain is connected to the output of the clamping circuit to keep the drain voltage constant; the drain of the composite medium gate dual transistor photosensitive detector is also connected to the integration capacitor to convert the current signal into a voltage signal connected to the positive input terminal of the comparator circuit, the negative input terminal of the comparator circuit is connected to the reference voltage Vrefcomp; the counter is connected to the output terminal of the comparator circuit.

[0008] Optionally, the slope-controllable ramp generator circuit comprises a transconductance operational amplifier, an integration capacitor and a current mirror circuit, the upper and lower plates of the integration capacitor are connected to the negative input terminal and the output terminal of the transconductance operational amplifier respectively, and the positive input terminal of the transconductance operational amplifier is connected to a reference voltage Vhold; the current mirror circuit is used to generate an integration current, and the current mirror circuit is connected to the negative input terminal of the transconductance operational amplifier through a switch.

[0009] Optionally, the current mirror circuit comprises N current mirrors, and each current mirror is connected to a switch, and the switch is controlled by a digital circuit to adjust the size of the integration current.

[0010] Optionally, the N current mirrors generate currents with sizes of 2 0 I, 2 1 I, 2 2 I, …, 2 N-1 I, I represents a unit current.

[0011] Optionally, the three slopes of the ramp voltage are denoted as k1, k2 and k1 respectively, and k1 < k2; the lowest and highest voltages of the ramp voltage are denoted as VL and VH respectively, and the ramp voltages at the slope transition points are denoted as V1 and V2 respectively.

[0012] For a pixel point with a threshold voltage in the range of VL to V1, the time of comparator flip is equal to The count value is

[0013]

[0014] For a pixel point with a threshold voltage in the range of V1 to V2, the time of comparator flip is equal to The count value is

[0015] For a pixel point with a threshold voltage in the range of V2 to VH, the time of comparator flip is equal to The count value is

[0016] VTH is the threshold voltage of the composite gate double transistor.

[0017] Optionally, the method comprises:

[0018] Step 1: controlling the size of the integration current by a digital circuit to apply a slope-controllable ramp voltage to the gate of the composite gate double transistor;

[0019] Step 2: when the size of the ramp voltage reaches the threshold value of the composite gate double transistor, the drain current of the composite gate double transistor charges the integration capacitor to the reference voltage Vrefcomp of the comparator, and the comparator flips.

[0020] Step 3, the counter starts to count from the beginning to the time when the comparator flips, and the final count value is the quantization of the threshold voltage of the composite medium gate dual transistor;

[0021] Step 4, the quantization of the threshold voltage of the composite medium gate dual transistor is obtained according to the final count value of the counter, and the gray value of each pixel is read according to the quantization value.

[0022] The application also provides a composite medium gate dual transistor readout circuit for realizing HDR based on a variable slope, which comprises a composite medium gate dual transistor photosensitive detector, a slope-controllable slope generation circuit, a clamping circuit, an integration capacitor, a comparator circuit and a counter; wherein the slope-controllable slope generation circuit is connected to the gate of the composite medium gate dual transistor photosensitive detector, the source of the composite medium gate dual transistor photosensitive detector is grounded, and the drain is connected to the output of the clamping circuit to keep the voltage at the drain end constant; the drain of the composite medium gate dual transistor photosensitive detector is also connected to the integration capacitor to convert the current signal into a voltage signal and connected to the positive input end of the comparator circuit, the negative input end of the comparator circuit is connected to a reference voltage Vrefcomp; and the counter is connected to the output end of the comparator circuit.

[0023] Optionally, the slope-controllable slope generation circuit comprises a transconductance operational amplifier, an integration capacitor and a current mirror circuit, the upper and lower plates of the integration capacitor are respectively connected to the negative input end and the output end of the transconductance operational amplifier, and the positive input end of the transconductance operational amplifier is connected to a reference voltage Vhold; the current mirror circuit is used to generate an integration current, and the current mirror circuit is connected to the negative input end of the transconductance operational amplifier through a switch.

[0024] Optionally, the current mirror circuit comprises N current mirrors, each current mirror is connected to a switch, and the size of the integration current is adjusted by the digital circuit controlling the switch; the currents generated by the N current mirrors are 2 0 I, 2 1 I, 2 2 I, …, 2 N-1 I, I represents a unit current.

[0025] The application has the following beneficial effects:

[0026] By adding a specific nonlinear slope voltage (the slope voltage is small in the front section, large in the middle section, and small again in the rear section) to the gate of the composite dielectric gate dual transistor photosensitive detector, the comparator flip time of the pixel points in the low brightness and high brightness intervals is lengthened, that is, the gray value range of the two intervals is enlarged, but the pixel in the middle gray value is not enlarged, so that the imaging effect of HDR is achieved at the circuit end, and the problems of high power consumption and high complexity caused by processing at the algorithm end are avoided, and the present application does not need to be exposed to multiple imaging and additional algorithm processing, and the method is simple. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Figure 1 is a schematic diagram of the variable slope voltage used in the present application.

[0029] Figure 2 is a readout circuit structure diagram used in the present application.

[0030] Figure 3 is a slope generator circuit diagram used in the present application to generate the slope voltage.

[0031] Figure 4 is an effect comparison diagram of the present application for processing underexposed pictures.

[0032] Figure 5 is an effect comparison diagram of the present application for processing overexposed pictures. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0034] Embodiment one

[0035] The present embodiment provides a composite dielectric gate dual transistor readout circuit for realizing HDR based on variable slope, and the slope voltage used is as shown in Figure 1 The slope voltage has the characteristics of small front section slope, large middle section slope, and small rear section slope. The slope voltage is added to the gate of the composite dielectric gate dual transistor, and the drain current of the composite dielectric gate dual transistor is read out, that is, the gray value corresponding to each pixel point. The image obtained by quantizing the slope voltage with the illustrated nonlinear slope has a high dynamic range, and has a better display effect for darker and brighter pixel points.

[0036] The architecture of the composite medium gate dual transistor readout circuit based on variable slope to realize HDR provided by the embodiment is as shown in Figure 2 The readout structure includes a composite medium gate dual transistor photosensitive detector, a slope-controllable slope generator, a clamping circuit, an integration capacitor, a comparator circuit, and a counter.

[0037] The source end of the composite medium gate dual transistor photosensitive detector is connected to ground, the drain end is connected to the output of the clamping circuit to keep the drain-off voltage constant, the gate end is connected to the slope voltage output by the slope generator, and the drain end current is connected to the integration capacitor to convert into a voltage signal, which is then converted into a digital quantity by the subsequent comparator and counter.

[0038] The slope voltage in Figure 1 is applied to the gate end of the composite medium gate dual transistor. When the slope voltage reaches the threshold voltage (VTH) of the composite medium gate dual transistor, the charging of the capacitor by the drain end current reaches the reference voltage Vrefcomp of the comparator of the readout circuit, and the comparator flips. The output of the comparator is connected to the counter, and the time from the start to the flip of the comparator is recorded. The final count value is the quantization of the threshold voltage of the composite medium gate dual transistor.

[0039] Since the composite medium gate dual transistor photosensitive detector can convert light intensity into transistor threshold voltage, the gray value of the pixel point can be obtained by quantizing the threshold voltage of the composite medium gate dual transistor, that is, the gray value of each pixel is read out by the count value.

[0040] To generate a slope voltage with characteristics as shown in Figure 1 , a slope generator with adjustable slope is designed, as shown in Figure 3 . The designed slope generator is composed of a transconductance operational amplifier, an integration capacitor, and a current mirror circuit. The upper and lower plates of the integration capacitor are respectively connected to the negative input end and the output end of the transconductance operational amplifier, and the positive input end of the transconductance operational amplifier is connected to the reference voltage Vhold. The integration current is generated by the current mirror circuit, and the size of the generated current is adjustable. The method is to add a switch under each current mirror, and the switch can be controlled by a digital circuit. If a 4-bit control switch is used, the sizes of the 4 currents are respectively I, 2I, 4I, and 8I, so the range of the generated current size is 0-15I.

[0041] According to the principle of constant current charging of the capacitor, the slope of the rising slope voltage is proportional to the size of the charging current, that is, the adjustable range of the slope is 0-15I / C. Therefore, the slope voltage with adjustable slope, for example, can be generated by inputting a 4-bit current control code to the digital end in sequence with 1, 4, and 1. The slopes of the three segments are respectively I / C, 4I / C, and I / C.

[0042] In order to control the rising and falling of the slope, a switching switch is needed to control the charging and discharging of the capacitor. For example,Figure 3 In the middle, a switch S1 is added between the capacitor and the charging current, and a switch S2 is added between the capacitor. When S1 is closed and S2 is open, the current charges the capacitor, and thus the output voltage is a linearly rising ramp voltage; when S1 is open and S2 is closed, the output voltage rapidly declines and remains stable when it drops to the size of the reference voltage Vhold.

[0043] Embodiment two

[0044] The embodiment provides a composite medium gate dual transistor readout method based on a variable slope to realize HDR. The method is realized based on the circuit provided in the embodiment one. The method is different from the method of conventional linear slope quantization. Different quantization coefficients are set for pixel points in different brightness ranges through a nonlinear slope, so that the imaging effect of high dynamic range is achieved.

[0045] A composite medium gate dual transistor readout method based on a variable slope to realize HDR, comprising:

[0046] Step 1: A variable slope voltage is applied to the gate of the composite medium gate dual transistor by controlling the size of the integral current through a digital circuit.

[0047] Step 2: When the size of the slope voltage reaches the threshold voltage of the composite medium gate dual transistor, the drain current of the composite medium gate dual transistor charges the integral capacitor to reach the reference voltage Vrefcomp of the comparator, and the comparator flips.

[0048] Step 3: The counter starts counting from the time of the start to the flip, and the final count value is the quantization of the threshold voltage of the composite medium gate dual transistor.

[0049] Step 4: The quantization of the threshold voltage of the composite medium gate dual transistor is obtained according to the final count value of the counter, and the gray value of each pixel is read out according to the quantization value.

[0050] The specific quantization method is as follows:

[0051] If the three slopes of the slope voltage are k1, k2 and k1 (where k1 < k2), the lowest and highest voltages of the slope voltage are VL and VH, the slope voltages at the slope turning points are V1 and V2, and the clock frequency of the counter is f.

[0052] For the pixel points with threshold voltages in the range of VL to V1, the time of the comparator flip is equal to The count value is For the pixel points with threshold voltages in the range of V1 to V2, the time of the comparator flip is equal to The count value is For the pixel points with threshold voltages in the range of V2 to VH, the time of the comparator flip is equal to The count value is

[0053] For the method of fixed slope ramp voltage quantization, if the slope voltage slope is fixed as k2, then for each pixel point, the time of comparator flip is equal to The count value range is The accuracy is low, and the dynamic range is small; if the slope voltage slope is fixed as k1, then for each pixel point, the time of comparator flip is equal to (wherein k1<k2), the count value range is The accuracy is high, but a higher bit counter is required, and the contrast of the darker and brighter regions cannot be improved.

[0054] Therefore, as can be seen, the slope voltage of the segmented slope lengthens the comparator flip time of the pixel points in the low brightness and high brightness intervals, that is, the gray value range of the two intervals is enlarged, but the pixels in the middle gray value are not enlarged, thereby achieving the imaging effect of HDR.

[0055] A underexposed picture is processed by using the above variable slope segmented slope quantization method:

[0056] As shown in the left picture of FIG. 1, it is an underexposed Lena picture, the whole picture is dark, and some black details are difficult to distinguish. Figure 4 The segmented slope mapping shown in FIG. 2 is performed on the picture, and the result shown in the right picture of FIG. 2 is obtained. Figure 1 As shown in the left picture of FIG. 3, it is an overexposed Lena picture, the whole picture is bright, and the details of the bright part are submerged. Figure 4 The segmented slope mapping shown in FIG. 4 is performed on the picture, and the result shown in the right picture of FIG. 4 is obtained.

[0057] A underexposed picture is processed by using the above variable slope segmented slope quantization method:

[0058] As shown in the left picture of FIG. 1, it is an underexposed Lena picture, the whole picture is dark, and some black details are difficult to distinguish. Figure 5 The segmented slope mapping shown in FIG. 2 is performed on the picture, and the result shown in the right picture of FIG. 2 is obtained. Figure 1 As shown in the left picture of FIG. 3, it is an overexposed Lena picture, the whole picture is bright, and the details of the bright part are submerged. Figure 5 The segmented slope mapping shown in FIG. 4 is performed on the picture, and the result shown in the right picture of FIG. 4 is obtained.

[0059] Some steps in the embodiments of the present application can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0060] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A compound diegate readout method for implementing HDR based on variable ramping, characterized in that, The method reads out the threshold voltage of the composite dielectric gate double crystal by applying a slope voltage with variable slope to the gate of the composite dielectric gate double crystal; the slope of the slope voltage is small at both ends and large in the middle; The method is realized by the readout circuit of the composite dielectric gate double transistor for HDR based on variable slope, which comprises a composite dielectric gate double transistor photosensitive detector, a slope-controllable slope generation circuit, a clamping circuit, an integration capacitor, a comparator circuit and a counter; wherein the slope-controllable slope generation circuit is connected to the gate of the composite dielectric gate double transistor photosensitive detector, the source of the composite dielectric gate double transistor photosensitive detector is grounded, and the drain is connected to the output of the clamping circuit to keep the drain voltage constant; the drain of the composite dielectric gate double transistor photosensitive detector is also connected to the integration capacitor to convert the current signal into a voltage signal and connected to the positive input terminal of the comparator circuit, the negative input terminal of the comparator circuit is connected to the reference voltage Vrefcomp; the counter is connected to the output terminal of the comparator circuit; The slope-controllable slope generation circuit comprises a transconductance operational amplifier, an integration capacitor and a current mirror circuit, the upper and lower plates of the integration capacitor are respectively connected to the negative input terminal and the output terminal of the transconductance operational amplifier, and the positive input terminal of the transconductance operational amplifier is connected to the reference voltage Vhold; the current mirror circuit is used to generate an integration current, and the current mirror circuit is connected to the negative input terminal of the transconductance operational amplifier through a switch; The current mirror circuit comprises N current mirrors, and each current mirror is connected to a switch, and the size of the integration current is adjusted by the digital circuit.

2. The method of claim 1, wherein, The N-way current mirror generates currents of 2 0 ×I, 2 1 ×I, 2 2 ×I, …, 2 N-1 ×I, I represents a unit current.

3. The method of claim 2, wherein, The three slopes of the slope voltage are respectively denoted as k1, k2 and k1, and k1 < k2; the lowest and highest voltages of the slope voltage are respectively denoted as VL and VH, and the slope voltages at the slope turning points are respectively denoted as V1 and V2; For the pixel point with threshold voltage range in VL~V1, the time of comparator flip is equal to , and the count value is ; For the pixel point with threshold voltage range of V1~V2, the time of comparator flip is equal to , and the count value is ; For the pixel point with threshold voltage range of V2~VH, the time of comparator flip is equal to , and the count value is ; VTH is the threshold voltage of the composite dielectric gate double transistor.

4. The method of claim 3, wherein, The method comprises: Step 1: controlling the size of the integration current by the digital circuit to apply a slope voltage with variable slope to the gate of the composite dielectric gate double transistor; Step 2: when the size of the slope voltage reaches the threshold value of the composite dielectric gate double transistor, the drain current of the composite dielectric gate double transistor charges the integration capacitor to reach the reference voltage Vrefcomp of the comparator, and the comparator flips; Step 3: the counter starts counting from the time when the comparator flips, and the final count value is the quantization of the threshold voltage of the composite dielectric gate double transistor; Step 4: the quantization of the threshold voltage of the composite dielectric gate double transistor is obtained according to the final count value of the counter, and the gray value of each pixel is read according to the quantization value.

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