Memory device and method of manufacturing the same

Abstract

The invention provides a memory device and a method of manufacturing the same. The memory device includes first and second vertical structures spaced apart from each other and a connection structure contacting a bottom portion of the first vertical structure and a bottom portion of the second vertical structure. The memory device also includes a first gate layer disposed between the first and second vertical structures and a second gate layer surrounding the first and second vertical structures and the connection structure. The memory device also includes a global line disposed on the first vertical structure and a local line disposed on the second vertical structure.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a memory device and a method of manufacturing the same, and more particularly, to a memory device including a memory block having a three-dimensional (3D) structure and a method of manufacturing the same. Background Art

[0002] The memory device may include a nonvolatile memory device in which stored data can be retained even when power is interrupted. The nonvolatile memory device may be classified into a two-dimensional (2D) structure and a three-dimensional (3D) structure according to the structure in which the memory cells are arranged. The memory cells of the nonvolatile memory device having a 2D structure may be arranged in a single layer on a substrate, and the memory cells of the nonvolatile memory device having a 3D structure may be vertically stacked on the substrate. Because the integration of the nonvolatile memory device having a 3D structure is higher than that of the nonvolatile memory device having a 2D structure, the number of electronic devices using the nonvolatile memory device having a 3D structure has recently increased. Summary of the invention

[0003] One embodiment of the present disclosure relates to a memory device. The memory device may include: a first vertical structure and a second vertical structure, the first vertical structure and the second vertical structure are spaced apart from each other; a connecting structure, the connecting structure contacts the bottom of the first vertical structure and the bottom of the second vertical structure; a first gate layer, the first gate layer is disposed between the first vertical structure and the second vertical structure; a second gate layer, the second gate layer surrounds the first vertical structure and the second vertical structure and the connecting structure; a global line, the global line is disposed on the first vertical structure; and a local line, the local line is disposed on the second vertical structure.

[0004] One embodiment of the present disclosure relates to a method for manufacturing a memory device. The method may include the following steps: forming a first material layer on a substrate; forming a groove in the first material layer; forming a sacrificial layer in the groove; forming a second material layer on the first material layer and the sacrificial layer; forming a hole through the second material layer to expose a portion of the sacrificial layer; removing the sacrificial layer exposed by the hole; and forming a channel layer along an inner wall of the groove and an inner wall of the hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0006] Figure 2 is a diagram illustrating in detail global lines and local lines according to one embodiment of the present disclosure.

[0007] Figure 3is a diagram illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0008] 4A to 4D is a diagram illustrating a structure of a row decoder according to one embodiment of the present disclosure.

[0009] FIG. 5A to FIG. 9B is a diagram illustrating a method of manufacturing a row decoder according to one embodiment of the present disclosure.

[0010] Fig.10 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0011] Fig.11 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0012] The specific structural description or functional description in the embodiments according to the concept of the present disclosure introduced in this specification or this application is only used for the description of the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0013] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which embodiments of the present disclosure are shown so that those skilled in the art to which the present disclosure belongs can practice the technical idea of ​​the present disclosure.

[0014] Some embodiments of the present disclosure relate to a memory device in which an area of ​​a peripheral circuit is reduced and a method of manufacturing the memory device.

[0015] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0016] Reference Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0017] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a plurality of memory cells capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly coupled to the first to i-th memory blocks BLK1 to BLKi.

[0018] Each of the first to i-th memory blocks BLK1 to BLKi may be formed to have a three-dimensional (3D) structure. Each memory block having the 3D structure may include memory cells stacked on a substrate in a vertical direction.

[0019] According to the programming scheme, each memory cell can store 1 bit of data or 2 or more bits of data. For example, the scheme for storing 1 bit of data in one memory cell is called a single-level cell (SLC) scheme, and the scheme for storing 2 bits of data in one memory cell is called a multi-level cell (MLC) scheme. The scheme for storing 3 bits of data in one memory cell is called a three-level cell (TLC) scheme, and the scheme for storing 4 bits of data in one memory cell is called a quad-level cell (QLC) scheme. In addition, 5 or more bits of data can be stored in one memory cell.

[0020] The peripheral circuit 170 may perform a program operation of storing data in the memory cell array 110, a read operation of outputting data stored in the memory cell array 110, and an erase operation of erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0021] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erasing voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0022] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell coupled to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used to determine whether the threshold voltage of a selected memory cell has increased to a verification operation of a target level. The verification voltage may be set to various levels according to a target level, and may be applied to a selected word line.

[0023] The read voltage may be applied to the selected word line during a read operation performed on the selected memory cell. For example, the read voltage may be set to various levels according to the programming scheme for the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among the word lines WL during a programming or read operation, and may be used to turn on the memory cells connected to the unselected word lines. The erase voltage may be used during an erase operation to erase the memory cells included in the selected memory block, and may be applied to the source line SL.

[0024] The row decoder 130 may transmit an operation voltage Vop to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL connected to a memory block selected according to a row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through a global line, and may be connected to the first memory block BLK1 to the i-th memory block BLKi through a local line (e.g., a drain select line DSL, a word line WL, a source select line SSL, and a source line SL). This will be referred to later. Figure 2 Describe global and local lines in detail.

[0025] The page buffer group 140 may include page buffers (not illustrated) respectively coupled to the first to i-th storage blocks BLK1 to BLKi. The page buffers (not illustrated) may be coupled to the first to i-th storage blocks BLK1 to BLKi through the bit lines BL. During a read operation, the page buffers (not illustrated) may sense a current or voltage of a bit line that varies with a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and may temporarily store the sensed data.

[0026] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL, and may send an enable signal through the column line CL. A page buffer (not illustrated) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0027] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and may send data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0028] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 so that a program operation is performed on a storage block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 so that a read operation is performed on a storage block selected by the address and the read data is output. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 so that an erase operation is performed on a selected storage block.

[0029] Figure 2 is a diagram illustrating in detail global lines and local lines according to one embodiment of the present disclosure.

[0030] Reference Figure 2 The row decoder 130 may include first to i-th pass switch groups PSG1 to PSGi corresponding to the first to i-th memory blocks BLK1 to BLKi, respectively. Figure 2 The configuration of the i-th pass switch group PSGi is described below, but the description of the i-th pass switch group PSGi can also be applied to the remaining pass switch groups.

[0031] The i-th pass switch group PSGi may include a decoder DEC, a block word line BWL, and a pass transistor group PTRG. The pass transistor group PTRG may include a plurality of pass transistors PTR.

[0032] A plurality of pass transistors PTR included in the pass transistor group PTRG may be coupled to the voltage generator 120 through a global line GL, and may be coupled to the i-th memory block BLKi through a local line LL. The local line LL may include a drain select line DSL, a word line WL, a source select line SSL, and a source line SL. The global line GL may include a global drain select line G_DSL, a global word line G_WL, a global source select line G_SSL, and a global source line G_SL.

[0033] The row decoder 130 may connect the global line GL to the local line LL connected to the memory block selected according to the row address RADD among the first to i-th memory blocks BLK1 to BLKi. In addition, the row decoder 130 may not connect the global line GL to the local line LL connected to the memory block not selected according to the row address RADD among the first to i-th memory blocks BLK1 to BLKi.

[0034] The decoder DEC may turn on or off the pass transistor PTR by applying a block control signal to the block word line BWL according to the received row address RADD. In one example, when the decoder DEC receives the row address RADD for activating the i-th pass switch group PSGi, the decoder DEC may turn on the pass transistor PTR included in the i-th pass switch group PSGi by applying a block control signal having a high voltage to the block word line BWL. In one example, when the decoder DEC receives the row address RADD for deactivating the i-th pass switch group PSGi, the decoder DEC may turn off the pass transistor PTR included in the i-th pass switch group PSGi by deactivating the block control signal. For example, the deactivation block control signal may have a cutoff voltage.

[0035] When the pass transistor PTR of the i-th pass switch group PSGi is turned on, the global drain selection lines G_DSL and the drain selection lines DSL, the global word lines G_WL and the word lines WL, the global source selection lines G_SSL and the source selection lines SSL, and the global source lines G_SL and the source lines SL may be electrically connected to each other through the corresponding pass transistors PTR. When the pass transistors PTR are turned on, the operating voltage (e.g., Figure 1 Vop) can be sent to the i-th storage block BLKi through the global line GL, the transistor PTR and the local line LL.

[0036] When the pass transistor PTR of the i-th pass switch group PSGi is turned off, the global drain select line G_DSL and the drain select line DSL, the global word line G_WL and the word line WL, the global source select line G_SSL and the source select line SSL, and the global source line G_SL and the source line SL may be electrically disconnected from each other through the corresponding pass transistor PTR. When the pass transistor PTR is turned off, the operating voltage Vop generated by the voltage generator 120 and applied to the global line GL may not be transmitted to the i-th memory block BLKi.

[0037] Figure 3 is a diagram illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0038] Reference Figure 3 , the memory device 100 may include a cell array CA and a peripheral circuit PC. In one embodiment, the cell array CA and the peripheral circuit PC may be included in the same wafer, and the cell array CA may be stacked on the peripheral circuit PC. In one embodiment, the cell array CA and the peripheral circuit PC may be included in different wafers, and the memory device 100 may have a structure in which at least two wafers are bonded to each other.

[0039] The memory device 100 may include a block word line BWL, a pass transistor PTR, a local pad LP, and a global line GL. The memory device 100 may also include a substrate 10, a gate structure GST, a cell plug CP, a source line SL, a bit line BL, a first interlayer insulating layer IIL1, a second interlayer insulating layer IIL2, a third interlayer insulating layer IIL3, a fourth interlayer insulating layer IIL4, a first interconnection structure IC1, a second interconnection structure IC2, a third interconnection structure IC3, or at least one of a fourth interconnection structure IC4.

[0040] The cell array CA may include at least one of a source line SL, a cell plug CP, a gate structure GST, a via 27, or a bit line BL. The gate structure GST may be disposed between the source line SL and the bit line BL.

[0041] The gate structure GST may include a cell region CR and a contact region CTR. The gate structure GST may include stacked gate lines 21. For example, the gate structure GST may include alternately stacked gate lines 21 and insulating layers 22. Among the gate lines 21 included in the gate structure GST, the uppermost gate line may be a drain select line DSL, the lowermost gate line may be a source select line SSL, and the remaining gate lines may be word lines WL.

[0042] In the contact region CTR of the gate structure GST, the gate line 21 may be exposed separately. In one example, the contact region CTR of the gate structure GST may have a step shape. The third interconnect structure IC3 may be formed in the contact region CTR of the gate structure GST. The third interconnect structure IC3 may transmit a bias to the gate line 21. The third interconnect structure IC3 may include one or more contact plugs 28A and 28C and one or more lines 28B.

[0043] Referenced above Figure 2 The local line LL described may include Figure 3 At least one of the local pad LP, the third interconnect structure IC3, or the gate line 21 illustrated in FIG. Figure 3 In and subsequent figures, the local line LL may indicate each of the local pad LP, the third interconnection structure IC3, or the gate line 21, or a combination of two or more thereof.

[0044] The cell plug CP may be located in the cell region CR of the gate structure GST. The cell plug CP may pass through the gate line 21. In the region where the cell plug CP and the gate line 21 intersect each other, a memory cell or a selection transistor may be formed. The cell plug CP may be disposed between the source line SL and the bit line BL. The cell plug CP and the bit line BL may be coupled to each other through a through hole 27. The fourth interconnection structure IC4 may be coupled to the bit line BL. The fourth interconnection structure IC4 may include at least some of one or more contact plugs 29A or one or more lines 29B.

[0045] Each of the cell plugs CP may include a channel layer 23, a memory layer 24, an insulating pillar 25, and a capping layer 26. The memory layer 24 may surround the sidewalls of the channel layer 23. The memory layer 24 may include at least one of a tunneling layer, a data storage layer, or a barrier layer. The insulating pillar 25 may be formed in a cylindrical shape in a region surrounded by the channel layer 23. The insulating pillar 25 may be formed of an oxide, a nitride, or an air gap. The capping layer 26 may be disposed on the insulating pillar 25 and may be directly coupled to the channel layer 23. The capping layer 26 may include a junction doped with impurities.

[0046] The peripheral circuit PC may include a first peripheral circuit PC1 and a second peripheral circuit PC2. The first peripheral circuit PC1 may be disposed below the contact region CTR. The first peripheral circuit PC1 may include a row decoder 130. The first peripheral circuit PC1 may include a block word line BWL and a pass transistor PTR. The pass transistor PTR may be coupled to a global line GL and a local pad.

[0047] The block word lines BWL may be formed by depositing a conductive layer on the substrate 10. In one example, the block word lines BWL may be formed by depositing polysilicon on the substrate 10. In one example, the block word lines BWL may be formed by doping the substrate 10 with impurities. The impurities may include arsenic (As) or phosphorus (P).

[0048] The global line GL and the local line (eg, the local pad LP) may be connected to each other by the pass transistor PTR. The pass transistor PTR may be a switch for controlling the connection between the global line GL and the local line LL.

[0049] Each pass transistor PTR may include a channel layer CH disposed in a block word line BWL. The pass transistor PTR may be formed in a portion where the block word line BWL and the channel layer CH intersect. The block word line BWL surrounding the channel layer CH may be a gate electrode of the pass transistor PTR. For example, the pass transistor PTR may be a high-voltage NMOS transistor. The channel layer CH of each pass transistor PTR may include a tube structure. Figure 4B The detailed shape of the pass transistor PTR is described in detail.

[0050] The corresponding pass transistor PTR can be turned on or off in response to the block control signal applied to the block word line BWL. When the pass transistor PTR is turned on, the global line GL can be connected to the local line LL, and the operation voltage Vop can be transmitted from the global line GL to the local line LL. When the pass transistor PTR is turned off, the global line GL and the local line LL can be disconnected from each other.

[0051] Each pass transistor PTR may further include a gate insulating layer GIL, an insulating column CO, and a pad PD. The gate insulating layer GIL may be disposed between the channel layer CH and the block word line BWL. The gate insulating layer GIL may be formed to surround the sidewall of the channel layer CH. The gate insulating layer GIL may extend to an upper insulating layer UIL formed along the upper surface of the block word line BWL. Each of the gate insulating layer GIL and the upper insulating layer UIL may include an oxide layer, which may be formed using a deposition method or an oxidation method. The insulating column CO may be disposed in a space surrounded by the channel layer CH. The insulating column CO may be formed of an oxide, a nitride, or an air gap.

[0052] The pad PD may be disposed on the insulating column CO, or may be coupled to the channel layer CH. For example, the pad PD may be formed to be surrounded by the channel layer CH. The pad PD may be disposed above the block word line BWL. For example, the pad PD may be formed to protrude from the upper surface of the block word line BWL. The pad PD and the block word line BWL may be insulated from each other by the upper insulating layer UIL and the gate insulating layer GIL. The pad PD may be a source pad including a source region or a drain pad including a drain region. Reference will be made later to Figure 4A and Figure 4B The source pad and the drain pad are described in detail.

[0053] The first interconnect structure IC1 may be coupled to the first peripheral circuit PC1. For example, the first interconnect structure IC1 may be coupled to the pad PD of each pass transistor PTR. The first interconnect structure IC1 may be disposed in the first interlayer insulating layer IIL1. The first interconnect structure IC1 may include one or more contact plugs 17A and one or more lines 17B. The pass transistor PTR may be coupled to the local line LL and the global line GL through the first interconnect structure IC1. For example, among the contact plugs 17A, the contact plug 17A disposed under the line 17B may be coupled to the pad PD, and the contact plug 17A disposed on the line 17B may be coupled to the corresponding local pad LP or the global line GL.

[0054] The gate line 21 may be coupled to the local pad LP through the third interconnect structure IC3. The contact plug 28A may extend in a direction passing through the gate line 21 to electrically connect the local pad LP to the line 28B, respectively. In addition, the contact plug 28C may extend in a direction passing through the gate line 21 to electrically connect the line 28B to the gate line 21, respectively. For example, the contact plug 28A may pass through the third interlayer insulating layer IIL3, the gate structure GST, and the second interlayer insulating layer IIL2, or may pass through the third interlayer insulating layer IIL3 and the second interlayer insulating layer IIL2. In addition, the contact plug 28C may pass through the third interlayer insulating layer IIL3. Therefore, the local pad LP may be coupled to the gate line 21, respectively, through the contact plugs 28A and 28C and the line 28B. In addition, it can be understood that the local pad LP, the third interconnect structure IC3, and the gate line 21 connected to each other are components included in the local line LL.

[0055] The second peripheral circuit PC2 may be disposed under the cell region CR. The second peripheral circuit PC2 may include transistors TRS disposed on the substrate 10. Each of the transistors TRS may include a gate insulating layer 11 and a gate electrode 12 disposed on the substrate 10. The transistor TRS may be a planar transistor. The second peripheral circuit PC2 may include a page buffer included in the page buffer group 140.

[0056] The second interconnect structure IC2 may be coupled to the second peripheral circuit PC2. The second interconnect structure IC2 may include one or more contact plugs 18A and one or more lines 18B. A portion of the second interconnect structure IC2 may be arranged in the first interlayer insulating layer IIL1, and the remainder of the second interconnect structure IC2 may be arranged in the fourth interlayer insulating layer IIL4. The fourth interlayer insulating layer IIL4 may extend to a portion below the block word line BWL.

[0057] according to Figure 3 In the structure illustrated in FIG. 1 , the pass transistor PTR can be arranged in the block word line BWL. Because the channel layer CH of each pass transistor PTR includes a tube structure, the area where the channel layer CH intersects with the block word line BWL can be increased while the volume occupied by the pass transistor PTR is reduced. In addition, according to the present disclosure, the size of the pass transistor PTR can be reduced compared to the conventional scheme, and as a result, the area of ​​the contact region CTR of the gate structure GST can be reduced. As the area of ​​the contact region CTR is reduced, the volume of the third interlayer insulating layer IIL3 can also be reduced, and therefore, wafer warpage can be prevented or minimized.

[0058] 4A to 4D is a diagram illustrating a structure of a row decoder according to one embodiment of the present disclosure.

[0059] Figure 4A It can be illustrated along the lines of Figure 3 Layout of the cross section taken along line AA'. Figure 4B It is along Figure 4A A cross-sectional view taken along line BB'. Figure 4C It is along Figure 4A A cross-sectional view taken along line CC'. Figure 4D It is along Figure 4A Hereinafter, description of the same configuration as that described above will be omitted or will be briefly made.

[0060] Reference Figure 4A , the memory device 100 may include a block word line BWL, a first pass transistor PTR1 and a second pass transistor PTR2. Figure 4A , the memory device 100 may further include an isolation structure for separating the block word lines BWL.

[0061] The block word line BWL may extend in the X direction. The additional block word line may be disposed in the Y direction of the block word line BWL. The block word line BWL and the additional block word line may be insulated from each other by an isolation structure IS. Each isolation structure IS may extend in the X direction.

[0062] In the block word line BWL, a first pass transistor PTR1 and a second pass transistor PTR2 may be formed. The first pass transistor PTR1 may be arranged adjacent to each other along the X direction, and the second pass transistor PTR2 may also be arranged adjacent to each other along the X direction. The first pass transistor PTR1 and the second pass transistor PTR2 may be arranged so that the central axes (e.g., axes parallel to the Y direction) of the first pass transistor PTR1 and the second pass transistor PTR2 are offset from each other. Figure 4AUnlike the structure illustrated in FIG. 1 , the first pass transistor PTR1 and the second pass transistor PTR2 may be arranged such that center axes of the first pass transistor PTR1 and the second pass transistor PTR2 overlap with each other.

[0063] Each of the first pass transistors PTR1 may include a first source pad SPD1, a first drain pad DPD1, and a channel layer CH. Each of the second pass transistors PTR2 may include a second source pad SPD2, a second drain pad DPD2, and a channel layer CH. Figure 4A The following embodiment is shown, in which, among the pads PD included in the first pass transistor PTR1 and the second pass transistor PTR2, the pad closer to the isolation structure IS is a drain pad (e.g., a first drain pad DPD1 and a second drain pad DPD2), and the corresponding source pads of the pass transistors PTR1 and PTR2 (e.g., a first source pad SPD1 and a second source pad SPD2) are adjacent to each other. However, this is only one embodiment, and various embodiments can be implemented in addition to the above-mentioned embodiments. For example, the first source pad SPD1 of the first pass transistor PTR1 and the second drain pad DPD2 of the second pass transistor PTR2 can be formed adjacent to each other. Alternatively, the first drain pad DPD1 of the first pass transistor PTR1 and the second source pad SPD2 of the second pass transistor PTR2 can be formed adjacent to each other. Alternatively, the first drain pad DPD1 of the first pass transistor PTR1 and the second drain pad DPD2 of the second pass transistor PTR2 can be formed adjacent to each other.

[0064] The first drain pad DPD1, the first source pad SPD1, the second source pad SPD2, and the second drain pad DPD2 may be surrounded by the corresponding channel layer CH. In addition, the first drain pad DPD1, the first source pad SPD1, the second source pad SPD2, and the second drain pad DPD2 may protrude from the upper insulating layer UIL formed on the upper surface of the block word line BWL in the Z direction.

[0065] exist Figure 4A In the description, the pass transistor PTR is separated into a first pass transistor PTR1 and a second pass transistor PTR2. Figure 3 , but there may be no difference between the actual configurations of the first pass transistor PTR1 and the second pass transistor PTR2. Therefore, hereinafter, description will be made based only on the pass transistor PTR without distinguishing the first pass transistor PTR1 from the second pass transistor PTR2.

[0066] Figure 4B Examples along Figure 4A The cross section is taken along the line BB'. Figure 4A and Figure 4B , the pass transistor PTR may include a first vertical structure VS1, a second vertical structure VS2, and a connecting structure CS. The first vertical structure VS1 and the second vertical structure VS2 may be spaced apart from each other in the Y direction. The connecting structure CS may contact the bottoms of the first vertical structure VS1 and the second vertical structure VS2. The connecting structure CS may have a tube structure extending along the Y direction. In the present disclosure, the tube structure may refer to a structure in which both ends of the connecting structure CS contact the bottom of the first vertical structure VS1 and the bottom of the second vertical structure VS2. For example, the first vertical structure VS1 and the second vertical structure VS2 may be connected to each other through the connecting structure CS.

[0067] Each of the first vertical structure VS1 and the second vertical structure VS2 may include a vertical channel layer V_CH, a vertical insulating column V_CO surrounded by the vertical channel layer V_CH, and a pad (e.g., a source pad SPD or a drain pad DPD) on the vertical insulating column V_CO. The first vertical structure VS1 may include a source pad SPD, and the second vertical structure VS2 may include a drain pad DPD. The vertical channel layer V_CH may surround the source pad SPD and the drain pad DPD, respectively.

[0068] The connection structure CS may include a horizontal channel layer H_CH and a horizontal insulating pillar H_CO surrounded by the horizontal channel layer H_CH. The horizontal channel layer H_CH may extend to the vertical channel layer V_CH. Furthermore, the horizontal insulating pillar H_CO may extend to the vertical insulating pillar V_CO.

[0069] In the present disclosure, the channel layer CH may include a horizontal channel layer H_CH and a vertical channel layer V_CH extending to each other. Therefore, the channel layer CH may be coupled to the source pad SPD and the drain pad DPD. In addition, in the present disclosure, the insulating column CO may include a horizontal insulating column H_CO and a vertical insulating column V_CO extending to each other.

[0070] Reference Figure 4B , the block word line BWL may include a first gate layer GT1 and a second gate layer GT2. The first gate layer GT1 may be disposed between the first vertical structure VS1 and the second vertical structure VS2. The first gate layer GT1 may be disposed on the connection structure CS. The second gate layer GT2 may surround the first vertical structure VS1, the second vertical structure VS2, and the connection structure CS. Figure 4A and Figure 4B , the first gate layer GT1 and the second gate layer GT2 may extend to each other to surround the first vertical structure VS1, the second vertical structure VS2 and the connection structure CS. That is, Figure 4BThe illustration that the first gate layer GT1 and the second gate layer GT2 are separated from each other is made only for convenience of description. For one embodiment, the gate layers GT1 and GT2 may be components that are not physically separated from each other.

[0071] The block word line BWL surrounding the channel layer CH may be used as a gate electrode of the pass transistor PTR. Since the pass transistor PTR according to the present disclosure includes a connection structure CS and a first vertical structure VS1 and a second vertical structure VS2 spaced apart from each other, the area of ​​the gate electrode adjacent to the channel layer CH may be increased compared to the existing structure. Therefore, the area of ​​the block word line BWL contacting the channel layer CH may be increased compared to the volume occupied by the pass transistor PTR within the block word line BWL. Therefore, according to the present disclosure, the volume occupied by the pass transistor PTR in the memory device 100 may be reduced.

[0072] Reference Figure 4B , the memory device 100 may further include a gate insulating layer GIL disposed between the first vertical structure VS1 and the second vertical structure VS2 and the first gate layer GT1 and the second gate layer GT2, and between the connection structure CS and the first gate layer GT1 and the second gate layer GT2. The gate insulating layer GIL may be formed to surround the sidewall of the channel layer CH. The gate insulating layer GIL may be disposed between the vertical channel layer V_CH and the block word line BWL and between the horizontal channel layer H_CH and the block word line BWL.

[0073] The gate insulating layer GIL may extend to an upper insulating layer UIL formed along an upper surface of the block word line BWL. The insulating layer IL may include a gate insulating layer GIL and an upper insulating layer UIL. The source pad SPD and the drain pad DPD may protrude higher than the upper insulating layer UIL in the Z direction. The channel layer CH (e.g., a vertical channel layer V_CH) surrounding the source pad SPD and the drain pad DPD may protrude higher than the upper insulating layer UIL in the Z direction. Because the source pad SPD and the drain pad DPD are individually surrounded by the channel layer CH, they may not directly contact the upper insulating layer UIL.

[0074] The memory device 100 may include a global line GL on a first vertical structure VS1 and a local pad LP on a second vertical structure VS2. The local pad LP may be understood as a component included in the local line LL. The pass transistor PTR may be coupled to the local pad LP via a drain pad DPD and may be coupled to the global line GL via a source pad SPD.

[0075] The memory device 100 may further include a first interconnect structure IC1 that connects the source pad SPD to the global line GL and the drain pad DPD to the local pad LP. The first interconnect structure IC1 may include one or more contact plugs 17A and one or more lines 17B. The first interconnect structure IC1 may be disposed in the first interlayer insulating layer IIL1.

[0076] Figure 4C Examples along Figure 4A The cross section is taken along the line C-C', and Figure 4D Examples along Figure 4A The cross section is taken along the line D-D'. Figure 4C and Figure 4D Relatedly, the comparison will be omitted or simply performed Figure 3 , Figure 4A and Figure 4B The configuration is the same as the configuration described in the description of the configuration.

[0077] Reference Figure 4C , the local pads LP may be disposed above the block word lines BWL. The local pads LP may be arranged along the X direction. The local pads LP may be respectively coupled to the drain pads DPD of the pass transistors PTR. The first interconnect structure IC1 may respectively connect the drain pads DPD to the local pads LP.

[0078] Reference Figure 4D , the global lines GL may be disposed above the block word lines BWL. The global lines GL may be arranged along the X direction. The global lines GL may be respectively coupled to the source pads SPD of the pass transistors PTR. The first interconnect structure IC1 may respectively connect the source pads SPD to the global lines GL.

[0079] The pass transistor PTR can be turned on or off according to the voltage applied to the block word line BWL. For example, when the pass transistor PTR is turned on, Figure 4D The global lines GL can be electrically connected to Figure 4C In addition, when the pass transistor PTR is turned off, Figure 4D The global line GL can be connected to the Figure 4C The local pad LP is electrically disconnected.

[0080] FIG. 5A to FIG. 9B is a diagram illustrating a method of manufacturing a row decoder according to an embodiment of the present disclosure. The diagram corresponding to "A" in the corresponding figure can illustrate the method of manufacturing a row decoder according to an embodiment of the present disclosure. Figure 3 The layout of the cross section taken along the line AA' of the corresponding figure, and the figure corresponding to "B" may be a cross-sectional view taken along the line BB' of the corresponding figure "A".

[0081] Reference Figure 5A and Figure 5B , the first material layer PO1 may be formed on a substrate (not illustrated). The first material layer PO1 may be a conductive layer, for example, a polysilicon layer. In one embodiment, before forming the first material layer PO1, an insulating layer (not illustrated) may be formed, and the first material layer PO1 may be formed on the insulating layer.

[0082] The trench TR may be formed in the first material layer PO1. A cross section of the trench TR may have a major axis in the Y direction and a minor axis in the X direction.

[0083] A sacrificial layer SF may be formed in the trench TR. The sacrificial layer SF may be formed of a material having an etch selectivity with respect to the first material layer PO1 (eg, a nitride layer).

[0084] Reference Fig. 6A and Figure 6B , a second material layer PO2 may be formed on the first material layer PO1 and the sacrificial layer SF. The second material layer PO2 may be formed of the same material (eg, polysilicon) as the first material layer PO1.

[0085] A slit trench ST1 may be formed passing through the first material layer PO1 and the second material layer PO2. The slit trench ST1 may extend in the X direction.

[0086] Reference Fig. 7A and Figure 7B , a hole HL may be formed through the second material layer PO2 to expose a portion of the sacrificial layer SF. In one embodiment, a first insulating layer IL1 may be formed on the second material layer PO2, and a hole HL may be formed through the second material layer PO2 and the first insulating layer IL1. The hole HL may be formed to overlap with the trench TR. For example, the hole HL may be formed on the trench TR so that two holes HL overlap with one trench TR.

[0087] The sacrificial layer SF exposed through the hole HL may be removed. As the sacrificial layer SF is removed, an opening in which the hole HL and the trench TR are coupled to each other may be formed.

[0088] In one embodiment, an etching process for opening may also be performed. In one example, a portion of the first material layer PO1 exposed by the trench TR may be etched, so that the size of the trench TR may be expanded. In one example, a portion of the second material layer PO2 exposed by the hole HL may be etched, so that the size of the hole HL may be expanded. Through the etching process, the inner wall of the trench TR and the inner wall of the hole HL may be flattened. The etching process may be performed as a high temperature wet etching process.

[0089] Reference Fig. 8A and Figure 8BThe channel layer CH may be formed along the inner wall of the trench TR and the inner wall of the hole HL. The channel layer CH may also be formed on the first insulating layer IL1 and the inner wall of the trench TR and the inner wall of the hole HL together.

[0090] In one implementation, the second insulating layer IL2 may be formed along inner walls of the trench TR and the hole HL, and the channel layer CH may be formed on the inner wall of the second insulating layer IL2. The second insulating layer IL2 may be an oxide layer formed using an oxidation method or a deposition method.

[0091] Reference Fig. 9A and Fig. 9B , the insulating column CO may be formed in the trench TR and the hole HL along which the channel layer CH is formed. Pads (e.g., source pads SPD and drain pads DPD) may be formed on the insulating column CO exposed by the hole HL. For example, when a portion of the insulating column CO formed in the hole HL is removed, a source region may be formed in a first hole among the holes HL, and a drain region may be formed in the remaining holes (that is, second holes) among the holes HL. The source region and the drain region may be filled with a conductive layer (e.g., polysilicon). The conductive layer filling the source region of the first hole may be a source pad SPD, and the conductive layer filling the drain region of the second hole may be a drain pad DPD. Each of the source pad SPD and the drain pad DPD may be surrounded by the channel layer CH.

[0092] Next, an etching process for removing a portion of the channel layer CH formed on a plane between the source pad SPD and the drain pad DPD may be performed. When the portion of the channel layer CH on the plane is removed, a portion of the first insulating layer IL1 formed between the source pad SPD and the drain pad DPD may be exposed, and the exposed portion of the first insulating layer IL1 may be etched. As a portion of the first insulating layer IL1 is etched and the thickness of the first insulating layer IL1 is reduced, a portion of the channel layer CH, the source pad SPD, and the drain pad DPD may protrude higher than the first insulating layer IL1 in the Z direction.

[0093] Reference Fig. 9B and Figure 4B , the global line GL may be formed on the source pad SPD, and the local pad LP may be formed on the drain pad DPD. Fig. 9B and Figure 3 , the gate line 21 stacked on the local pad LP may be formed. In addition, a third interconnection structure IC3 electrically connecting the corresponding gate line 21 to the local pad LP may be formed.

[0094] exist FIG. 5B to FIG. 9B The first material layer PO1 and the second material layer PO2 illustrated in the example may be formed Figure 4AFor example, a portion of the second material layer PO2 may correspond to the first gate layer GT1 and the remaining portion of the second material layer PO2 and the first material layer PO1 may correspond to the second gate layer GT2.

[0095] In addition, FIG. 7B to FIG. 9B The first insulating layer IL1 and the second insulating layer IL2 illustrated in the figure may be respectively Figure 4B The upper insulating layer UIL corresponds to the gate insulating layer GIL.

[0096] Fig.10 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0097] Reference Fig.10 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0098] The controller 3100 may be coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a programming operation, a read operation, or an erase operation of the memory device 3200, or may control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In one example, the controller 3100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0099] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. In one embodiment, the controller 3100 can communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCI-E), an advanced technology attachment (ATA) protocol, a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), Firewire, a universal flash storage (UFS), WiFi, Bluetooth (Bluetooth) and a high-speed non-volatile memory (NVMe). In one embodiment, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0100] The memory device 3200 may include a plurality of memory cells and may be Figure 1 The memory device 100 illustrated in FIG.

[0101] The controller 3100 and the memory device 3200 may be integrated into a single memory device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single memory device, and then a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), or a Universal Flash Storage (UFS) may be formed.

[0102] Fig.11 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0103] Reference Fig.11 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0104] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. In one embodiment, the received signal may be a signal based on an interface of the host 4100 and the SSD 4200. For example, the signal may be defined by at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCI-E), an advanced technology attachment (ATA) protocol, a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WiFi, Bluetooth, and a high-speed non-volatile memory (NVMe).

[0105] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Figure 1The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0106] The auxiliary power supply 4230 may be coupled to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may be supplied with a power supply voltage from the host 4100 and may be charged. When the supply of power from the host 4100 is not performed smoothly, the auxiliary power supply 4230 may provide a power supply voltage of the SSD 4200. In one embodiment, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located in a mainboard and may provide auxiliary power to the SSD 4200.

[0107] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, and a low power DDR (LPDDR) SDRAM, or a nonvolatile memory such as a ferroelectric RAM (FRAM), a resistive RAM (ReRAM), a spin transfer torque magnetic RAM (STT-MRAM), and a phase change RAM (PRAM).

[0108] The present disclosure can provide a memory device including a peripheral circuit with a reduced area.

[0109] CROSS-REFERENCE TO RELATED APPLICATIONS

[0110] This application claims the priority of Korean Patent Application No. 10-2023-0080364 filed in the Korean Intellectual Property Office on June 22, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a first vertical structure and a second vertical structure, the first vertical structure and the second vertical structure being spaced apart from each other; a connecting structure contacting a bottom of the first vertical structure and a bottom of the second vertical structure; a first gate layer, the first gate layer being disposed between the first vertical structure and the second vertical structure; a second gate layer, the second gate layer surrounding the first vertical structure, the second vertical structure and the connecting structure; a global line, the global line being disposed on the first vertical structure; as well as A local line is arranged on the second vertical structure.

2. The memory device according to claim 1, wherein: Each of the first vertical structure and the second vertical structure comprises: vertical channel layer; a vertical insulating column, the vertical insulating column being surrounded by the vertical channel layer; and A pad is disposed on the vertical insulating column.

3. The memory device according to claim 2, wherein: The pad is surrounded by the vertical channel layer.

4. The memory device according to claim 2, wherein: The pad comprises: a source pad included in the first vertical structure; and A drain pad is included in the second vertical structure.

5. The memory device according to claim 4, further comprising: A first interconnect structure connects the source pad to the global line and the drain pad to the local line.

6. The memory device according to claim 2, wherein: The connection structure comprises: a horizontal channel layer; and A horizontal insulating column is surrounded by the horizontal channel layer.

7. The memory device according to claim 6, wherein: The vertical channel layer and the horizontal channel layer extend to each other, and The vertical insulating pillars and the horizontal insulating pillars extend to each other.

8. The memory device according to claim 1, wherein: The first gate layer and the second gate layer extend to each other to surround the first and second vertical structures and the connection structure.

9. The memory device according to claim 1, wherein: The first gate layer is disposed on the connection structure.

10. The memory device of claim 1, further comprising: A gate insulating layer is disposed between the first vertical structure, the second vertical structure and the first gate layer, the second gate layer, and between the connection structure and the first gate layer, the second gate layer.

11. The memory device according to claim 1, wherein: The local lines include: A local pad, wherein the local pad is disposed on the second vertical structure; a gate line, the gate line being stacked on the local pad; and A second interconnect structure connects the local pad to the gate line.

12. The memory device according to claim 1, wherein: The first and second vertical structures and the connection structure are implemented as pass transistors that electrically connect or disconnect the global line and the local line to each other.

13. A method of manufacturing a memory device, the method comprising the steps of: forming a first material layer on a substrate; forming a groove in the first material layer; forming a sacrificial layer in the trench; forming a second material layer on the first material layer and the sacrificial layer; forming a hole through the second material layer to expose a portion of the sacrificial layer; removing the sacrificial layer exposed through the hole; as well as A channel layer is formed along an inner wall of the trench and an inner wall of the hole.

14. The method according to claim 13, wherein: The steps of forming the hole include: forming a first insulating layer on the second material layer; and The hole is formed through the second material layer and the first insulating layer.

15. The method according to claim 13, wherein: Each of the first material layer and the second material layer includes polysilicon.

16. The method according to claim 13, before the step of forming the channel layer, the method further comprises the following steps: A portion of the first material layer exposed by the trench and a portion of the second material layer exposed by the hole are etched to expand sizes of the trench and the hole.

17. The method according to claim 13, wherein: The step of forming the channel layer includes: forming a second insulating layer along inner walls of the trench and inner walls of the hole; and The channel layer is formed along an inner wall of the second insulating layer.

18. The method according to claim 13, after the step of forming the channel layer, the method further comprises the following steps: forming an insulating column in the trench and the hole in which the channel layer is formed; as well as A pad is formed on the insulating pillar exposed through the hole.

19. The method according to claim 18, wherein: The steps of forming the pad include: forming a source region in a first hole among the holes and forming a drain region in a remaining second hole among the holes by removing a portion of the insulating pillar formed in the holes; and A source pad is formed in the first hole and a drain pad is formed in the second hole by filling the source region and the drain region with a conductive layer.

20. The method according to claim 19, further comprising the steps of: A global line is formed on the source pad and a local pad is formed on the drain pad.

21. The method according to claim 20, further comprising the steps of: forming a gate line, the gate line being stacked on the local pad; and An interconnect structure is formed that electrically connects the gate line to the local pad.

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