An ultrasonic transducer based on a piezoelectric MEMS chip and its fabrication method

Abstract

The application relates to the technical field of semiconductor process technology and ultrasonic transducer manufacturing technology, and particularly relates to an ultrasonic transducer based on a piezoelectric MEMS chip and a preparation method thereof, which comprises a substrate, a piezoelectric layer is formed on the front surface of the substrate, a through back cavity is formed in the substrate, a structure layer is formed on the surface of the piezoelectric layer, the thickness of the structure layer is greater than the thickness of a piezoelectric thin film in the piezoelectric layer, and a neutral plane is located in the lateral projection area range of the structure layer; a gap is formed in the diaphragm area penetrating through the structure layer and the piezoelectric layer, and a plurality of vibration structures are connected through a central structure formed due to the gap. The preparation method comprises the following steps: growing the piezoelectric layer, etching the piezoelectric layer, forming the gap, growing the structure layer, etching the structure layer, and etching the substrate. In the application, silicon oxide is used as the structure layer, the process stress is low, the resonant frequency can be effectively reduced, the gap is etched through, the sensitivity of the chip is improved, the stress effect is reduced, the central part is provided with a connecting part due to etching, sound leakage is avoided, and multiple resonant frequencies are also avoided.

Description

Technical Field

[0001] This invention relates to the field of ultrasonic transducer manufacturing technology based on piezoelectric MEMS chip semiconductor technology, and particularly to an ultrasonic transducer based on a piezoelectric MEMS chip and its fabrication method. Background Technology

[0002] A piezoelectric ultrasonic transducer is a sensor that converts ultrasonic signals into other energy signals. Ultrasonic waves are mechanical waves with vibration frequencies higher than 20 kHz. They are characterized by high frequency, short wavelength, minimal diffraction, and, most importantly, good directionality, enabling them to propagate directionally as rays. Ultrasonic waves have a strong penetrating ability in liquids and solids, especially in solids that are opaque to sunlight. When ultrasonic waves encounter impurities or interfaces, they produce significant reflections, forming reflected echoes. When they encounter moving objects, they exhibit the Doppler effect. Ultrasonic sensors are widely used in industry, defense, and biomedicine.

[0003] In existing technologies, low-frequency ultrasonic sensors are required for long-distance measurement, monitoring, and information transmission using ultrasound. Therefore, low-frequency MEMS chip devices have a large market. However, traditional piezoelectric MEMS chips consist of a stacked SOI substrate with a back cavity and a piezoelectric layer. The top silicon in the SOI substrate acts as a structural layer, serving as the neutral plane. Silicon has a high Young's modulus and high process stress, which leads to a high resonant frequency, which is not conducive to the production design and manufacturing of low-frequency devices. In order to reduce the stress on the device and improve its sensitivity, gaps are made in the chip. The opening of gaps can cause the device to leak sound and have multiple resonant frequencies.

[0004] Patent document with application number 202323565644.9 discloses a piezoelectric micromechanical ultrasonic transducer chip structure and an ultrasonic transducer array structure. The chip structure of this application includes an SOI wafer substrate and a chip sensitive layer. The SOI wafer substrate includes a substrate layer, a buried oxide layer and a device layer stacked from bottom to top. A hexagonal opening is formed in the substrate layer through its upper and lower end faces. The chip sensitive layer includes a lower electrode layer, a first piezoelectric layer and an upper electrode layer stacked from bottom to top. The lower electrode layer is stacked on top of the device layer. The upper electrode layer has a hexagonal electrode structure and is located directly above the hexagonal opening. A plurality of first recesses are formed on the buried oxide layer, the device layer, the lower electrode layer and the first piezoelectric layer. The plurality of first recesses are distributed in a hexagonal outline on the outer periphery of the upper electrode layer. The hexagonal outline is close to or located at the edge of the hexagonal opening.

[0005] This proposed solution improves the effective vibration displacement of the chip's sensitive layer, thereby enhancing the chip's performance as both a driver and a sensor. However, the solution also has drawbacks: its structure is a traditional one, with the top silicon layer in the SOI substrate serving as the neutral plane, which presents challenges for the design and manufacturing of low-frequency devices.

[0006] In summary, this application proposes an ultrasonic transducer based on a piezoelectric MEMS chip and its fabrication method to solve the aforementioned problems. Summary of the Invention

[0007] To address the aforementioned problems, this invention proposes an ultrasonic transducer based on a piezoelectric MEMS chip and its fabrication method. A structural layer is used instead of the traditional top silicon. Silicon oxide / silicon nitride has a low Young's modulus and low process stress, which can effectively reduce the resonant frequency. On this basis, through-etched gaps are used to improve the chip's sensitivity and reduce stress. At the same time, the central part has a connection part due to etching, which avoids sound leakage and also avoids the generation of multiple resonant frequencies.

[0008] The objective of this invention can be achieved through the following technical solution: an ultrasonic transducer based on a piezoelectric MEMS chip:

[0009] Includes a substrate having a front side and a back side, a piezoelectric layer is formed on the front side of the substrate, a back cavity extending through the piezoelectric layer is formed on the back side of the substrate, a structural layer is formed on the surface of the piezoelectric layer, the piezoelectric layer and the structural layer within the longitudinal projection area of ​​the back cavity are diaphragms, the thickness of the structural layer is greater than the thickness of the piezoelectric film in the piezoelectric layer, so that the neutral plane is located within the lateral projection area of ​​the structural layer;

[0010] The diaphragm region forms a gap that penetrates the structural layer and the piezoelectric layer, and the gap is used to reduce stress.

[0011] As a further embodiment of the present invention, the diaphragm region is divided into several vibration structures due to the gaps, and the several vibration structures are connected by a central structure formed by the gaps.

[0012] As a further embodiment of the present invention, the slits are provided in four or six groups and arranged in a ring array around the central structure of the diaphragm.

[0013] As a further embodiment of the present invention, the central structure is provided with V-shaped grooves, the same number as the gaps, which are not connected to the gaps, and the V-shaped grooves are arranged in a ring array around the center of the diaphragm.

[0014] As a further embodiment of the present invention, the V-groove is axially symmetrical about its inflection point.

[0015] As a further embodiment of the present invention, the material of the structural layer is silicon oxide.

[0016] As a further embodiment of the present invention, the structural layer is a two-layer structure or a three-layer structure in which silicon nitride and silicon oxide are alternately stacked.

[0017] A method for fabricating the above-mentioned piezoelectric ultrasonic transducer, the method comprising the following steps:

[0018] S1. Prepare a substrate with a front side and a back side. Grow a piezoelectric layer on the front side of the substrate.

[0019] S2. Etch the piezoelectric layer to pattern it. The piezoelectric layer forms through gaps due to etching. The diaphragm is divided into several vibration structures due to the etched gaps. The several vibration structures are connected through the central structure formed by the etched gaps.

[0020] S3. Grow a structural layer on the surface of the patterned piezoelectric layer;

[0021] S4. Etch the structural layer to pattern the structural layer, so that the diaphragm area of ​​the structural layer forms a pattern consistent with the diaphragm area of ​​the piezoelectric layer due to etching.

[0022] S5. Etch through the substrate to form a back cavity;

[0023] The thickness of the structural layer is greater than the thickness of the piezoelectric film in the piezoelectric layer, so that the neutral surface is located within the lateral projected area of ​​the structural layer.

[0024] As a further embodiment of the present invention, in step S2, when the piezoelectric layer is patterned, V-shaped grooves are etched on the central structure, which are the same number as the gaps and are not connected to the gaps.

[0025] As a further embodiment of the present invention, forming a back cavity through etching the substrate specifically includes:

[0026] First, a dry process is used to etch part of the substrate from the back side, and then a wet process is used to etch through the back cavity of the substrate.

[0027] The beneficial effects of this invention are:

[0028] 1. The piezoelectric ultrasonic transducer and its fabrication method of the present invention use silicon oxide / silicon nitride as the structural layer, and the neutral plane is raised to the structural layer to replace the traditional top silicon. Silicon oxide / silicon nitride has low Young's modulus and low process stress, which can effectively reduce the resonant frequency and is beneficial to the design and manufacturing of low frequency devices.

[0029] 2. This invention creates gaps in the diaphragm area to reduce stress, while using a central structure to integrate the various vibration modules into a whole, avoiding sound leakage and the occurrence of multiple resonant frequencies. The central structure can enhance the mechanical stability of the chip, enabling it to maintain good performance under vibration and shock environments.

[0030] 3. The present invention etches V-shaped grooves on the central structure, the same number as the gaps, which are not connected to the gaps. The V-shaped grooves make the central structure form a V-shaped beam structure. The V-shaped beam can keep the diaphragm highly stable. The characteristics of the V-shaped structure allow the load to be transmitted along the axial direction of the V-shaped beam, thereby reducing the possibility of bending and twisting.

[0031] 4. The fabrication method of the piezoelectric ultrasonic transducer based on MEMS chip proposed in this invention, compared with the traditional fabrication process, first grows a piezoelectric layer and patterns it, then grows a structural layer on the surface of the piezoelectric layer, and then patterns the structural layer. The patterning steps of the piezoelectric layer and the structural layer are independent and do not interfere with each other. The piezoelectric layer does not need to generate unnecessary cutouts due to the patterning of the structural layer, thus ensuring the integrity of the piezoelectric layer to the greatest extent. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the ultrasonic transducer based on a piezoelectric MEMS chip proposed in an embodiment of the present invention;

[0033] Figure 2 for Figure 1 Exploded view of the structure;

[0034] Figure 3 This is an exploded view of the structural layers;

[0035] Figure 4 for Figure 1 Top view;

[0036] Figure 5 A schematic diagram of the structure for creating the gap;

[0037] Figure 6 for Figure 5 A magnified view of a section at point A in the middle;

[0038] Figures 7-11 This is a schematic flowchart of the fabrication method of ultrasonic transducer based on piezoelectric MEMS chip proposed in an embodiment of the present invention.

[0039] In the attached diagram:

[0040] 1. Substrate;

[0041] 2. Piezoelectric layer; 21. Bottom electrode; 22. Piezoelectric thin film; 23. Top electrode;

[0042] 3. Structural layer; 31. First structural layer; 32. Second structural layer; 33. Third structural layer; 3a. Gap; 3b. Vibration structure; 3c. Central structure; 3d. V-groove. Detailed Implementation

[0043] Embodiments of the present invention are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] Example 1:

[0045] Please see Figures 1-2 The ultrasonic transducer based on a piezoelectric MEMS chip proposed in this embodiment of the invention includes a substrate 1, a piezoelectric layer 2 and a structural layer 3 stacked sequentially.

[0046] The substrate 1 has a front side and a back side. A back cavity is formed through the back side of the substrate 1. The piezoelectric layer 2 and the structural layer 3 within the longitudinal projection range of the back cavity form the diaphragm region. The back cavity provides space for the diaphragm to vibrate.

[0047] Optionally, substrate 1 is a silicon wafer substrate 1, which reduces costs by replacing SOI substrate 1 with silicon wafer substrate 1.

[0048] The piezoelectric layer 2 includes a bottom electrode 21, a piezoelectric film 22 and a top electrode 23 sequentially stacked on the surface of the substrate 1. The thickness of the structural layer 3 is greater than the thickness of the piezoelectric film 22, so that the neutral plane is located within the lateral projection area of ​​the structural layer 3.

[0049] Optionally, the material of structural layer 3 is silicon oxide / silicon nitride, and the Young's modulus of silicon oxide / silicon nitride is lower than that of silicon.

[0050] An optional structure of the structural layer 3 is as follows: the structural layer 3 includes a first structural layer 31 and a second structural layer 32, the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31, the material of the first structural layer 31 is silicon nitride (Si3N4), and the material of the second structural layer 32 is silicon oxide (SiO2), forming a silicon nitride-silicon oxide bilayer structure.

[0051] An optional structure of the structural layer 3 is as follows: the structural layer 3 includes a first structural layer 31 and a second structural layer 32, the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31, the material of the first structural layer 31 is silicon oxide (SiO2), and the material of the second structural layer 32 is silicon nitride (Si3N4), forming a silicon oxide-silicon nitride bilayer structure.

[0052] In the two structures described above, the second structural layer 32 serves as the main structural layer. The thickness of the entire structural layer 3 is greater than the thickness of the piezoelectric thin film 22 in the piezoelectric layer 2, so that the neutral plane is located within the lateral projection area of ​​the structural layer 3. The second structural layer 32 mainly undertakes the function of adjusting the neutral plane of the chip, and the device performance is mainly determined by the material and thickness of the second structural layer 32.

[0053] Another alternative structure with three layers is, for example... Figure 3 As shown, structural layer 3 includes a first structural layer 31, a second structural layer 32, and a third structural layer 33; wherein the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31 and / or the third structural layer 33. The first structural layer 31 is made of silicon nitride (Si3N4), the second structural layer 32 is made of silicon oxide (SiO2), and the third structural layer 33 is made of silicon nitride (Si3N4), forming a three-layer structure of silicon nitride-silicon oxide-silicon nitride.

[0054] Another alternative structure with three layers is, for example... Figure 3 As shown, structural layer 3 includes a first structural layer 31, a second structural layer 32, and a third structural layer 33; wherein the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31 and / or the third structural layer 33. The first structural layer 31 is made of silicon oxide (SiO2), the second structural layer 32 is made of silicon nitride (Si3N4), and the third structural layer 33 is made of silicon oxide (SiO2), forming a three-layer structure of silicon oxide-silicon nitride-silicon oxide.

[0055] In the two three-layer structures described above, the second structural layer 32 serves as the main structural layer 3. The second structural layer 32 mainly functions to adjust the neutral plane of the chip, and the device performance is mainly determined by the material and thickness of the second structural layer 32. The first structural layer 31 mainly improves the adhesion of the intermediate layer and enhances the film quality. The third structural layer 33 mainly enhances the tensile strength of the intermediate layer and improves the stability of the structural layer 3. By adopting the above three-layer structure, the structural layer 3 is more stable, more reliable, and more conducive to improving the yield rate.

[0056] The piezoelectric PMUT based on MEMS chip proposed in this embodiment uses silicon oxide / silicon nitride instead of silicon as the material of structural layer 3. Through the above two or three-layer structure, the thickness of the entire structural layer 3 is greater than the thickness of the piezoelectric thin film 22 in the piezoelectric layer 2, so that the neutral plane is located within the lateral projection area of ​​structural layer 3. By setting structural layer 3, the position of the neutral plane is moved up to structural layer 3. Utilizing the low Young's modulus and low process stress of silicon oxide / silicon nitride, the resonant frequency can be effectively reduced, which is beneficial to the design and manufacturing of low-frequency devices.

[0057] Furthermore, such as Figure 4As shown, a gap 3a is formed in the diaphragm region by creating a through-structure layer 3 and a piezoelectric layer 2. Creating a gap 3a can reduce stress and improve the sensitivity of the chip.

[0058] The diaphragm region is divided into several vibration structures 3b by the gap 3a. The vibration structures 3b are connected by the central structure 3c formed by the gap 3a. The vibration structures 3b are connected by the connecting structure at the center position to avoid sound leakage and the generation of multiple resonant frequencies.

[0059] Example 2:

[0060] Based on Example 1, please refer to Figure 5 a and 5b, the diaphragm area has four or six sets of slits 3a.

[0061] like Figure 6 As shown in 6a and 6b, the diaphragm region is divided into four or six vibration structures 3b by the gap 3a, and the vibration structures 3b are interconnected by the connecting structure at the center position.

[0062] Optionally, the central structure 3c has the same number of V-shaped grooves 3d as the slits 3a, and is not connected to the slits 3a. The V-shaped grooves 3d are arranged in a ring array around the center of the diaphragm.

[0063] Optionally, the V-groove 3d is axially symmetric around its inflection point.

[0064] The ultrasonic transducer based on a piezoelectric MEMS chip proposed in this embodiment has a V-groove 3d on the central structure 3c of the chip. The V-groove 3d forms a V-beam structure on the central structure 3c. The V-beam can maintain the high stability of the diaphragm. At the same time, the characteristics of the V-shaped structure allow the load to be transmitted along the axial direction of the V-beam, thereby reducing the possibility of bending and twisting.

[0065] Example 3:

[0066] The present invention also discloses a method for preparing the ultrasonic transducer for Embodiment 1 or 2, comprising the following steps:

[0067] S1, please refer to Figure 7 Prepare substrate 1, which can be a silicon wafer substrate. Substrate 1 has a front side and a back side. Grow a piezoelectric layer 2 on the front side of substrate 1, specifically including:

[0068] S1-1, a bottom electrode 21 is sputtered and grown on the front side of substrate 1;

[0069] S1-2, a piezoelectric thin film 22 is sputtered and grown on the surface of the bottom electrode 21;

[0070] S1-3, top electrode 23 is sputtered and grown on the surface of piezoelectric thin film 22.

[0071] S2, please refer to Figure 8 The piezoelectric layer 2 is etched to create a pattern. The etching process creates a through-slit 3a in the piezoelectric layer 2. The diaphragm is divided into several vibration structures 3b by the etched slit 3a. These vibration structures 3b are connected by a central structure 3c formed by the etched slit 3a. Specifically, the diaphragm includes:

[0072] S2-1, The top electrode 23 is patterned by etching the top electrode 23 using the IBE dry etching method;

[0073] S2-2, wet etching is used to pattern the piezoelectric thin film 22;

[0074] S2-3, IBE dry etching is used to pattern the bottom electrode 21.

[0075] When patterning the piezoelectric layer 2, V-shaped grooves 3d, which are the same number as the gaps 3a and not connected to the gaps 3a, are etched on the central structure 3c.

[0076] S3, please refer to Figure 9 The structural layer 3 is deposited on the surface of the piezoelectric layer 2 using the PECVD process. The thickness of the structural layer 3 is greater than the thickness of the piezoelectric film 22, so that the neutral plane is located within the lateral projection area of ​​the structural layer 3.

[0077] S4, please refer to Figure 10 The structural layer 3 is etched to pattern it, and the diaphragm region of the structural layer 3 forms a pattern consistent with the diaphragm region of the piezoelectric layer 2 due to the etching.

[0078] S5, please refer to Figure 11 The back cavity is formed by etching through the back of the substrate 1. The piezoelectric layer 2 and structural layer 3 within the longitudinal projection area of ​​the back cavity serve as the diaphragm, and the back cavity provides space for the diaphragm to vibrate.

[0079] The piezoelectric PMUT fabrication method based on MEMS chips proposed in this embodiment, compared with the traditional fabrication process, first grows a piezoelectric layer 2 and patterns it, then grows a structural layer 3 on the surface of the piezoelectric layer 2, and then patterns the structural layer 3. Therefore, the patterning steps of the piezoelectric layer 2 and the structural layer 3 are independent and do not interfere with each other. The piezoelectric layer 2 does not need to generate unnecessary cutouts due to the patterning of the structural layer 3, thus ensuring the integrity of the piezoelectric layer 2 to the greatest extent.

[0080] Example 4:

[0081] As a preferred embodiment of Example 3, when etching the structural layer 3 in step S4, the structural layer 3 is patterned. The diaphragm region of the structural layer 3 forms a pattern consistent with the diaphragm region of the piezoelectric layer 2 due to etching. The structural layer 3 is a double-layer structure or a triple-layer structure in which silicon nitride and silicon oxide are alternately stacked.

[0082] Optionally, the structural layer 3 includes a first structural layer 31, a second structural layer 32 and a third structural layer 33. The first structural layer 31 and the third structural layer 33 are made of silicon nitride, the second structural layer 32 is made of silicon oxide, and the thickness of the second structural layer 32 is much greater than the thickness of the first structural layer 31 and / or the third structural layer 33.

[0083] Optionally, when performing the back cavity process in step S5, such as Figure 11 As shown, a portion of substrate 1 can be etched from the back side of substrate 1 using a dry etching process, followed by a wet etching process to etch through the back cavity of substrate 1. Specifically, this includes:

[0084] S5-1, The back side of substrate 1 is etched by DRIE dry etching process. The substrate 1 will not be etched through, because DRIE etching will damage the piezoelectric layer 2. Therefore, substrate 1 will have a thickness of 5-15% remaining after DRIE etching.

[0085] S5-2, the back side of substrate 1 is etched by wet etching process, completely penetrating the remaining 5-15% thickness of substrate 1 to form a U-shaped support structure and a back cavity.

[0086] Using the above method, since the buried oxide layer serves as a cutoff line during the etching of SOI substrate 1, a back cavity can be formed by penetrating the buried oxide layer. Pure dry etching may damage the piezoelectric layer 2. In order to improve the yield, dry etching is used to partially etch the silicon wafer substrate 1, and then wet etching is used to penetrate the remaining part. The wet process will not affect the piezoelectric layer 2.

[0087] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

[0088] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

Claims

1. An ultrasonic transducer based on a piezoelectric MEMS chip, comprising a substrate (1) having opposite front and back surfaces, a piezoelectric layer (2) being formed on the front surface of the substrate (1), characterized in that: a back cavity is formed on the back surface of the substrate (1) and extends to the piezoelectric layer (2), a structure layer (3) is formed on the surface of the piezoelectric layer (2), the piezoelectric layer (2) and the structure layer (3) within the longitudinal projection area of the back cavity are a diaphragm, the thickness of the structure layer (3) is greater than the thickness of a piezoelectric film (22) in the piezoelectric layer (2), so that a neutral plane is located within the lateral projection area of the structure layer (3); wherein the diaphragm region forms a slit (3a) extending through the structure layer (3) and the piezoelectric layer (2), the slit (3a) is used to reduce stress effect; the diaphragm region is divided into a plurality of vibration structures (3b) due to the slit (3a), and the plurality of vibration structures (3b) are connected through a central structure (3c) formed due to the slit (3a); the central structure (3c) is provided with V-shaped grooves (3d) which are the same in number as the slit (3a) and are not communicated with the slit (3a), and the V-shaped grooves (3d) are arranged in a ring array around the center of the diaphragm. The slit (3a) is provided with four groups or six groups and is arranged in a ring array around the central structure (3c) of the diaphragm. The V-shaped grooves (3d) are axisymmetric along the inflection points thereof. The material of the structure layer (3) is silicon oxide. The structure layer (3) is a double-layer structure or a three-layer structure in which silicon nitride and silicon oxide are alternately stacked.

2. The piezoelectric MEMS chip-based ultrasonic transducer of claim 1, wherein, The preparation method comprises the following steps:

3. The piezoelectric MEMS chip-based ultrasonic transducer of claim 1, wherein, S1, preparing a substrate (1) having opposite front and back surfaces, and growing a piezoelectric layer (2) on the front surface of the substrate (1); 4. The piezoelectric MEMS chip-based ultrasonic transducer of claim 1, wherein, S2, etching the piezoelectric layer (2) to pattern the piezoelectric layer (2), the piezoelectric layer (2) forms a through slit (3a) due to etching, the diaphragm is divided into a plurality of vibration structures (3b) due to the slit (3a), and the plurality of vibration structures (3b) are connected through a central structure (3c) formed due to the etched slit (3a); 5. The piezoelectric MEMS chip-based ultrasonic transducer of claim 1, wherein, S3, growing a structure layer (3) on the surface of the patterned piezoelectric layer (2); 6. A method of manufacturing an ultrasonic transducer applied to the piezoelectric MEMS chip according to any one of claims 1 to 5, characterized in that, S4, etching the structure layer (3) to pattern the structure layer (3), so that the diaphragm region of the structure layer (3) forms a pattern consistent with the diaphragm region of the piezoelectric layer (2) due to etching; S5, etching through the substrate (1) to form a back cavity; The thickness of the structure layer (3) is greater than the thickness of the piezoelectric film (22) in the piezoelectric layer (2), so that the neutral plane is located within the lateral projection area of the structure layer (3). In S2, when the piezoelectric layer (2) is patterned, V-shaped grooves (3d) which are the same in number as the slit (3a) and are not communicated with the slit (3a) are etched on the central structure (3c). Etching through the substrate (1) to form a back cavity specifically comprises: First, etching part of the substrate (1) from the back surface of the substrate (1) by dry process, and then etching the back cavity through the substrate (1) by wet process. ​ 7. The preparation method according to claim 6, characterized in that, ​ 8. The preparation method according to claim 7, characterized in that, ​ ​

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