Fault current loop circuit, multi-source oscillation experimental loop circuit and control method thereof

Abstract

The present application proposes a fault current loop, a multi-source oscillation experimental loop and its control method, an electronic device, and a non-transient computer-readable storage medium. The fault current loop circuit includes at least one fault current branch, and the at least one fault current branch includes a discharge end, both connected to the first common end; a charging end, both connected to the second common end; a grounding end, both connected to the third common end; the fault current branch includes a fault current energy storage branch, the negative end of the fault current energy storage branch is electrically connected to the third common end, wherein the fault current energy storage branch includes an energy storage capacitor; and an energy storage capacitor flipping branch, connected in parallel with the energy storage capacitor, for performing voltage reversal on the energy storage capacitor. According to an embodiment of the present application, the energy storage capacitor is subjected to multiple voltage reversals by the energy storage capacitor flipping branch until the energy of the energy storage capacitor is completely consumed, which can solve the problem of LC oscillation branch reuse in the fault current loop circuit, thereby saving costs.

Description

Technical Field

[0001] The present application relates to the technical field of high-voltage direct current transmission, and in particular to a fault current loop, a multi-source oscillation experimental loop and a control method thereof, an electronic device, and a non-transient computer-readable storage medium. Background Art

[0002] In order to solve the problem of commutation failure on the receiving side of the HVDC transmission system, some scholars have proposed in recent years to use a converter valve with controllable shutdown capability on the receiving system side. That is, to add a controllable shutdown device to the original converter valve bridge arm to achieve forced commutation, thereby effectively avoiding the occurrence of commutation failure.

[0003] To verify the converter valve's ability to forcibly shut off high currents in the laboratory, a fault current loop is required to simulate the multi-cycle fault current generated by a short-circuit fault in the AC system. Currently, there are two common types of short-circuit current generation systems: one uses a generator, but this solution is costly and requires a large footprint; the other uses a capacitor-inductor oscillation (LC oscillation) circuit, which is low-cost and requires a small footprint, making it a relatively economical solution. However, each LC oscillation circuit requires an LC oscillation branch. Existing test systems typically only have three oscillation branches to meet the requirements of a three-cycle fault current. For fault currents exceeding three cycles, configuring multiple LC oscillation branches would incur significant construction costs.

[0004] Therefore, it is necessary to propose a multi-source oscillation test circuit and its control method and control device to solve the problem of multiplexing of LC oscillation branches in the current fault current system, save equipment costs, and be more in line with the characteristics of short-circuit current oscillation attenuation during actual faults. Summary of the Invention

[0005] The present application aims to propose a fault current loop, a multi-source oscillation experimental loop and its control method, an electronic device, and a non-transient computer-readable storage medium to solve the problem of multiplexing LC oscillation branches in a fault current loop circuit.

[0006] According to one aspect of the present application, a fault current loop circuit is provided, comprising at least one fault current branch, wherein the at least one fault current branch comprises: a discharge terminal, each connected to a first common terminal; a charging terminal, each connected to a second common terminal; and a ground terminal, each connected to a third common terminal;

[0007] The fault current branch includes a fault current energy storage branch, the negative end of the fault current energy storage branch is electrically connected to the third common end, wherein the fault current energy storage branch includes: an energy storage capacitor; and an energy storage capacitor reversal branch, connected in parallel with the energy storage capacitor, for performing voltage reversal on the energy storage capacitor.

[0008] According to some embodiments, the energy storage capacitor reversal branch includes a fault current voltage reversal inductor; and a fault current voltage reversal valve, which is connected in series with the fault current voltage reversal inductor, and the anode end of the fault current voltage reversal valve is electrically connected to the third common end.

[0009] According to some embodiments, the fault current energy storage branch further includes an energy storage capacitor discharge branch connected in parallel with the energy storage capacitor and configured to discharge the energy storage capacitor.

[0010] According to some embodiments, the energy storage capacitor discharge branch includes a discharge resistor and a grounding isolation switch connected in series.

[0011] According to some embodiments, the fault current branch further includes a fault current discharge branch, the negative terminal of the fault current discharge branch is electrically connected to the first common terminal, and the positive terminal of the fault current discharge branch is electrically connected to the positive terminal of the fault current energy storage branch.

[0012] According to some embodiments, the fault current discharge branch includes a discharge isolation switch; a fault current phase selection valve connected in series with the discharge isolation switch, and a negative terminal of the valve is electrically connected to the first common terminal.

[0013] According to some embodiments, the fault current branch further includes a fault current charging branch, wherein a first end of the fault current charging branch is electrically connected to the positive terminal of the fault current energy storage branch, and a second end of the fault current charging branch is electrically connected to the second common terminal.

[0014] According to some embodiments, the fault current charging branch includes a charging isolation switch.

[0015] According to some embodiments, an oscillating inductor and a fault current isolation valve are further included, wherein the oscillating inductor and the fault current isolation valve are connected in series, one end of the oscillating inductor is electrically connected to the fourth common terminal, and the other end of the oscillating inductor is electrically connected to the first common terminal.

[0016] According to some embodiments, the fault current loop circuit further includes a high-voltage DC power supply, one end of which is electrically connected to the ground terminal of the fault current branch, and the other end of which is electrically connected to the second common terminal.

[0017] According to some embodiments, the fault current isolation valve, the fault current phase selection valve, and the fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor and a reverse-blocking IGCT connected in series and parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode connected in series and parallel.

[0018] According to one aspect of the present application, a multi-source oscillation experimental loop circuit is proposed, which includes a fault current loop circuit as described in any of the previous embodiments, and is characterized in that the multi-source oscillation experimental loop circuit also includes a high-voltage loop circuit, a large current loop circuit and a test valve, wherein: the high-voltage loop circuit, the large current loop circuit, the test valve and the fault current loop circuit are connected in parallel, and one end of each of the high-voltage loop circuit, the large current loop circuit, the fault current loop circuit and the test valve is electrically connected to the fourth common terminal, and the other end is electrically connected to the third common terminal.

[0019] According to one aspect of the present application, a control method for a multi-source oscillation experimental loop circuit as described in any of the previous embodiments is proposed, comprising the following steps:

[0020] S1: Disconnect the grounding isolating switch and the discharging isolating switch in the fault current loop circuit, and close the charging isolating switch in the fault current loop circuit;

[0021] S2: Using a high-voltage DC power supply to charge the energy storage capacitor in the fault current loop circuit;

[0022] S3: Disconnecting the charging isolating switch in the fault current loop circuit and closing the discharging isolating switch in the fault current loop circuit;

[0023] S4: during the test valve opening stage, opening the fault current phase selection valve and the fault current isolation valve in the fault current loop circuit to apply the superposition of the fault current and the high current loop circuit current to the test valve;

[0024] S5: Turn on the fault current voltage reversal valve of the discharged fault current branch to achieve voltage reversal of the energy storage capacitor;

[0025] S6: Determine whether the energy storage capacitor voltage meets a preset trigger condition. If the energy storage capacitor voltage meets the trigger condition, execute step S4 after a preset delay.

[0026] According to some embodiments, the fault current isolation valve is turned on at the same time as any one of the fault current phase selection valves is turned on.

[0027] According to one aspect of the present application, a control device for a multi-source oscillation circuit is provided, characterized in that it is used to execute the control method as described in any of the previous embodiments, and the control device includes:

[0028] A high voltage loop control unit, configured to perform status monitoring, output voltage control, and fault protection on each converter of the high voltage loop circuit;

[0029] A high current loop control unit, used for performing status monitoring, output current control and fault protection on each converter of the high current loop circuit;

[0030] A coordination control unit, configured to coordinate and control the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit;

[0031] A fault current loop control unit is used to monitor the status of the fault current isolation valve, fault current phase selection valve, high-voltage DC power supply, and fault current voltage reversal valve of the fault current loop circuit, trigger conduction, control the charging voltage of the energy storage capacitor, and provide fault protection;

[0032] an input / output unit, configured to exchange data with the high-voltage loop control unit, the high-current loop control unit, the fault current loop control unit, and the coordination control unit, so as to issue trigger pulses to the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit, and receive status information output by the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit;

[0033] The human-machine interface unit is used to perform signal interaction with the input-output unit and the external PC, receive input instructions from the external PC and status information from the input-output unit, and issue control instructions to the input-output unit.

[0034] According to one aspect of the present application, an electronic device is proposed, comprising a processor; and a memory storing a computer program, wherein when the computer program is executed by the processor, the processor executes the control method as described in any of the previous embodiments.

[0035] According to one aspect of the present application, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored. When the instructions are executed by a processor, the processor executes the control method as described in any of the previous embodiments.

[0036] According to an embodiment of the present application, the voltage of the energy storage capacitor is reversed multiple times through the energy storage capacitor flipping branch until the energy of the energy storage capacitor is completely consumed, which can solve the problem of multiplexing of LC oscillation branches in the fault current loop circuit, thereby saving costs.

[0037] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. By describing the exemplary embodiments in detail with reference to the accompanying drawings, the above and other objects, features and advantages of the present application will become more apparent.

[0039] Figure 1 A block diagram of a fault current loop circuit according to an exemplary embodiment of the present application is shown.

[0040] Figure 2 A circuit block diagram of a multi-source oscillation experimental loop according to an exemplary embodiment of the present application is shown.

[0041] Figure 3 A schematic diagram of a multi-source oscillation experimental loop circuit according to an exemplary embodiment of the present application is shown.

[0042] Figure 4 A schematic diagram of a multi-source oscillation experimental loop circuit structure according to an exemplary embodiment of the present application is shown.

[0043] Figure 5 A flow chart of a control method for a multi-source oscillation experimental loop circuit according to an exemplary embodiment of the present application is shown.

[0044] Figure 6 A block diagram of a control device for a multi-source oscillation circuit according to an exemplary embodiment of the present application is shown.

[0045] Figure 7 A triggering timing diagram of each valve group of a multi-source oscillation test circuit according to an exemplary embodiment of the present application is shown.

[0046] Figure 8 An electronic device according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Identical figures in the drawings represent identical or similar parts, and thus repeated description thereof will be omitted.

[0048] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0049] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other modes, components, materials, devices or operations may be employed. In these cases, well-known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0050] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0051] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0052] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] Figure 1 A block diagram of a fault current loop circuit according to an exemplary embodiment of the present application is shown. According to an embodiment of the present application, the fault current loop circuit includes at least one fault current branch. The at least one fault current branch includes a discharge terminal, a charge terminal, and a ground terminal. The discharge terminals are all connected to a first common terminal, the charge terminals are all connected to a second common terminal, and the ground terminals are all connected to a third common terminal.

[0054] In some embodiments, the fault current branch includes a fault current energy storage branch, wherein a negative terminal of the fault current energy storage branch is electrically connected to the third common terminal.

[0055] In a specific embodiment, the fault current energy storage branch includes an energy storage capacitor and an energy storage capacitor reversing branch, wherein the energy storage capacitor reversing branch is connected in parallel with the energy storage capacitor and is used to reverse the voltage of the energy storage capacitor.

[0056] according to Figure 1In the embodiment shown, the voltage of the energy storage capacitor is repeatedly reversed by the energy storage capacitor flipping branch until the energy of the energy storage capacitor is completely consumed, which can solve the problem of multiplexing LC oscillation branches in the fault current loop circuit, thereby saving costs.

[0057] In a specific embodiment, the energy storage capacitor reversal branch includes a fault current voltage reversal inductor and a fault current voltage reversal valve. The fault current voltage reversal valve is connected in series with the fault current voltage reversal inductor, and the anode terminal of the fault current voltage reversal valve is electrically connected to the third common terminal. In this embodiment, the fault current voltage reversal valve is used to achieve positive voltage reversal of the energy storage capacitor, thereby achieving continuous oscillation output of the fault current, solving the problem of multiplexing LC oscillation branches in the fault current loop circuit and saving costs.

[0058] According to an embodiment of the present application, the fault current energy storage branch further includes an energy storage capacitor discharge branch, wherein the energy storage capacitor discharge branch is connected in parallel with the energy storage capacitor for discharging the energy storage capacitor.

[0059] In a specific embodiment, the energy storage capacitor discharge branch includes a discharge resistor and a grounding isolation switch connected in series.

[0060] According to an embodiment of the present application, the fault current branch further includes a fault current discharge branch, wherein the negative terminal of the fault current discharge branch is electrically connected to the first common terminal, and the positive terminal of the fault current discharge branch is electrically connected to the positive terminal of the fault current energy storage branch.

[0061] In a specific embodiment, the fault current discharge branch includes a discharge isolating switch and a fault current phase selection valve, wherein the fault current phase selection valve is connected in series with the discharge isolating switch, and the negative terminal of the valve is electrically connected to the first common terminal.

[0062] According to an embodiment of the present application, the fault current branch further includes a fault current charging branch, wherein a first end of the fault current charging branch is electrically connected to the positive terminal of the fault current energy storage branch, and a second end of the fault current charging branch is electrically connected to the second common terminal.

[0063] In a specific embodiment, the fault current charging branch includes a charging isolation switch.

[0064] According to the embodiments of the present application, Figure 1 The fault current loop circuit shown further includes an oscillating inductor and a fault current isolation valve. The oscillating inductor and the fault current isolation valve are connected in series. One end of the series connection is electrically connected to the fourth common terminal, and the other end is electrically connected to the first common terminal.

[0065] According to the embodiments of the present application, Figure 1The fault current loop circuit shown further includes a high-voltage DC power supply, wherein one end of the high-voltage DC power supply is electrically connected to the ground terminal of the fault current branch, and the other end is electrically connected to the second common terminal.

[0066] In some embodiments, the fault current isolation valve, fault current phase selection valve, and fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor connected in series / parallel, a reverse-blocking IGCT, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode in series / parallel.

[0067] Figure 2 FIG. 1 shows a circuit block diagram of a multi-source oscillation experimental loop according to an exemplary embodiment of the present application. Figure 2 The multi-source oscillation experimental circuit shown includes the following Figure 1 The fault current loop circuit 201, high voltage loop circuit 203, large current loop circuit 205 and sample valve 207 are shown. The high voltage loop circuit 203, large current loop circuit 205, sample valve 207 and fault current loop circuit 201 are connected in parallel, and one end of each of the high voltage loop circuit 203, large current loop circuit 205, sample valve 207 and fault current loop circuit 201 is electrically connected to the fourth common terminal, and the other end is electrically connected to the third common terminal.

[0068] Figure 3 FIG. 1 shows a schematic diagram of a multi-source oscillation experimental circuit according to an exemplary embodiment of the present application. Figure 3 The multi-source oscillation test circuit shown includes a high voltage circuit, a large current circuit, a fault current circuit and a test valve connected in parallel.

[0069] like Figure 3 As shown, one end of the high voltage circuit, the high current circuit, the fault current circuit and the test valve is electrically connected to the common terminal A. The other end of the high voltage circuit, the high current circuit, the fault current circuit and the test valve is electrically connected to the common terminal D.

[0070] exist Figure 3 In the embodiment shown, the fault current loop circuit includes an oscillating inductor L R , Fault current isolation valve V 60 , at least one fault current branch and a high-voltage DC power supply. The discharge terminals of the fault current branches are electrically connected to the common terminal A, the charging terminals of the fault current branches are electrically connected to the common terminal A and the positive terminal of the high-voltage DC power supply, and the ground terminals of the fault current branches are electrically connected to the negative terminal of the high-voltage DC power supply.

[0071] In a specific embodiment, the high voltage circuit is used to apply voltage to the test valve, and the high current circuit and the fault current circuit are used to apply current to the test valve.

[0072] Figure 4 FIG. 1 shows a schematic diagram of a circuit structure of a multi-source oscillation experimental loop according to an exemplary embodiment of the present application. Figure 4 The multi-source oscillation experimental circuit shown includes multiple fault current branches, wherein the fault current branches include a fault current energy storage branch, a fault current discharge branch, and a fault current charging branch.

[0073] like Figure 4 As shown, the negative end of the fault current energy storage branch is electrically connected to the common terminal D, and the negative end of the fault current discharge branch is connected to the common terminal A. One end of the fault current charging branch is electrically connected to the positive end of the fault current discharge branch and the positive end of the fault current energy storage branch, and the other end of the fault current charging branch is electrically connected to the positive end of the high voltage DC voltage at the common terminal B.

[0074] In some embodiments, the fault current energy storage branch includes an energy storage capacitor (ie, C s1 、C s2 , ... or C sn ), an energy storage capacitor discharge branch and an energy storage capacitor voltage reversal branch connected in parallel with the energy storage capacitor.

[0075] like Figure 4 The energy storage capacitor discharge branch includes a discharge resistor (ie, R G1 、R G2 , ... or R Gn ) and grounding disconnector (also known as K G1 , K G2 , ... or K Gn ); The energy storage capacitor voltage reversal branch includes a series-connected fault current voltage reversal inductor (also known as L R1 , L R2 , ... or L Rn ) and the fault current voltage reversal valve (also known as V 611 、V 621 , ... or V 6n1 ), the anode terminal of the fault current voltage reversal valve is electrically connected to the common terminal D.

[0076] According to some embodiments, the fault current discharge branch includes a fault current phase selection valve (ie, V 61 、V 62 , ... or V 6n ) and discharge isolating switch (also known as K F1 , K F2 , ... or K Fn ).

[0077] According to some embodiments, the fault current charging branch includes a charging isolation switch. Figure 4 K shownC1 , K C2 , ... or K Cn .

[0078] According to some embodiments, the fault current isolation valve, the fault current phase selection valve, and the fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor and a reverse-blocking IGCT connected in series and parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode connected in series and parallel.

[0079] Figure 5 A flow chart of a control method for a multi-source oscillation experimental loop circuit according to an exemplary embodiment of the present application is shown below. Figure 5 Taking as an example, a control method for a multi-source oscillation experimental loop circuit in an exemplary embodiment of the present application is described in detail.

[0080] like Figure 5 The control method shown includes steps S1 to S6.

[0081] In step S1, the grounding isolating switch and the discharging isolating switch in the fault current loop circuit are opened, and the charging isolating switch in the fault current loop circuit is closed.

[0082] According to an embodiment of the present application, before step S1 , it is necessary to determine at least one fault current branch according to the number of fault current cycles.

[0083] For example, when the number of fault current cycles is 3, three fault current energy storage branches, fault current discharge branches and fault current charging branches with electrical connection relationships are selected respectively, and multiple non-overlapping current waves applied to the test valve are generated in sequence using the preset delay.

[0084] For another example, when the number of fault current cycles is 3, one fault current energy storage branch, one fault current discharge branch, and one fault current charging branch that are electrically connected are selected respectively, and a preset delay is used to generate multiple non-overlapping current waves applied to the test valve.

[0085] In step S2, a high-voltage DC power supply is used to charge the energy storage capacitor in the selected fault current loop circuit.

[0086] In step S3, the charging isolating switch in the fault current loop circuit is opened, and the discharging isolating switch in the fault current loop circuit is closed.

[0087] In step S4, during the test valve opening stage, the fault current phase selection valve and the fault current isolation valve in the selected fault current loop circuit are opened to apply the superposition of the fault current and the high current loop circuit current to the test valve.

[0088] In step S5, the fault current voltage reversal valve of the discharged fault current branch is turned on to achieve voltage reversal of the energy storage capacitor.

[0089] In step S6, it is determined whether the energy storage capacitor voltage meets the preset triggering condition. If the energy storage capacitor voltage meets the triggering condition, step S4 is executed after a preset delay (for example, 20ms). If the energy storage capacitor voltage does not meet the re-triggering condition, the process ends.

[0090] According to an embodiment of the present application, to prevent the fault current loop current pulses from overlapping, a preset delay is required before the combined fault current and high current loop currents are applied to the test valve. That is, once the energy storage capacitor voltage meets the triggering condition, step S4 is executed after a preset delay (e.g., 20ms).

[0091] In a specific embodiment, the voltage of the energy storage capacitor of the discharged fault current branch will change from positive to negative. When the fault current voltage reversal valve of the branch is turned on, the voltage of the energy storage capacitor will change from negative to positive, and the branch will meet the discharge conditions again.

[0092] For example, Figure 4 As shown, assuming that the energy storage capacitor C S1 When the voltage is positive at the top and negative at the bottom, V 61 、V 60 The conduction condition is met, and the condition for applying fault current to the test valve is met. After the fault current is applied, the energy storage capacitor C S1 The voltage is negative at the top and positive at the bottom. 611 With conduction conditions, V 611 After conduction, the energy storage capacitor C S1 The voltage goes up positive and down negative again, and now it is connected to C S1 Connected fault current branches (including V 61 and K F1 ) The conditions for the test valve to apply a fault current are met again, that is, the triggering conditions are met.

[0093] For example, Figure 4 As shown, assuming that the energy storage capacitor C S1 、C S2 When the voltage is positive at the top and negative at the bottom, V 61 、V 62 The conduction condition is met, and the conditions for applying fault current to the test valve are met. 60 、V 61 、V 62 After the fault current is applied, the voltage of the energy storage capacitor C S1 、C S2 Negative on top and positive on bottom, at this time V 611 and V 621The conduction conditions are met. Give V 611 After the on command is applied, the energy storage capacitor C S1 The voltage goes up positive and down negative again, and now it is connected to C S1 Connected fault current branches (including V 61 and K F1 ) The condition for the test valve to apply fault current is met again, that is, the trigger condition is met. Before the conduction command is applied, the capacitor C S2 The voltage is still negative at the top and positive at the bottom.

[0094] According to the embodiments of the present application, Figure 5 In the embodiment shown, the fault current isolation valve is turned on at the same time as any one of the fault current phase selection valves is turned on.

[0095] Figure 6 A block diagram of a control device for a multi-source oscillation circuit according to an exemplary embodiment of the present application is shown, which is used to perform the following steps: Figure 5 The control method shown.

[0096] like Figure 6 The control device shown includes a high-voltage circuit control unit 1 , a high-current circuit control unit 2 , a coordination control unit 3 , a fault current circuit control unit 4 , an input-output unit 5 and a human-machine interface unit 6 .

[0097] like Figure 6 As shown, the high voltage loop control unit 1 is used to monitor the status of each converter in the high voltage loop circuit, control the output voltage and perform fault protection; the high current loop control unit 2 is used to monitor the status of each converter in the high current loop circuit, control the output current and perform fault protection; the coordination control unit 3 is used to coordinate the control of the high voltage loop circuit, the high current loop circuit, the test valve and the fault current loop circuit; the fault current loop control unit 4 is used to monitor the status of the fault current isolation valve, the fault current phase selection valve, the high voltage DC power supply and the fault current voltage reversal valve in the fault current loop circuit, and trigger the conduction and charging of the energy storage capacitor. voltage control and fault protection; the input and output unit 5 is used to exchange data with the high-voltage loop control unit, the high-current loop control unit, the fault current loop control unit, and the coordination control unit to send trigger pulses to the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit, and receive status information output by the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit; the human-machine interface unit 6 is used to exchange signals with the input and output unit and the external PC, receive input instructions from the external PC and status information from the input and output unit, and send control instructions to the input and output unit.

[0098] like Figure 6The control device shown further includes a power supply unit 7 for providing power to the high voltage circuit control unit 1 , the high current circuit control unit 2 , the coordination control unit 3 , the fault current circuit control unit 4 , the input and output unit 5 and the human-machine interface unit 6 .

[0099] Figure 7 A triggering timing diagram of each valve group of a multi-source oscillation test circuit according to an exemplary embodiment of the present application is shown.

[0100] like Figure 7 As shown, CP Vt is the test valve trigger pulse, CP 60 Trigger pulse for fault current isolation valve, CP 61 、CP 62 ,…,CP 6n They are respectively the fault current phase selection valve trigger pulse, CP 611 、CP 621 ,…,CP 6n1 They are respectively the fault current reversal valve trigger pulses.

[0101] In a specific embodiment, during the test valve opening stage, the fault current phase selection valve and the fault current isolation valve of the fault current are opened, and the fault current and the large current loop current are superimposed and applied to the test valve. When the fault current phase selection valve of any fault current branch is turned on, the fault current isolation valve is turned on at the same time. After the energy storage capacitor is discharged, the fault current voltage reversal valve of the discharged fault current branch is turned on to realize the positive reversal of the energy storage capacitor voltage, and it is judged whether the energy storage capacitor voltage meets the re-triggering conditions. If the re-triggering conditions are met, after a preset delay, the fault current phase selection valve and the isolation valve are opened again to superimpose the fault current and the large current loop current on the test valve again. At this time, due to the existence of loop impedance, the second oscillation current will be lower than the first oscillation current. The fault current voltage reversal valve of the discharged fault current branch is turned on again to realize the positive reversal of the energy storage capacitor voltage, and this cycle is repeated until the energy of the energy storage capacitor is completely consumed.

[0102] like Figure 7 As shown, the interval between the current waves of adjacent fault current loops is 20ms.

[0103] Figure 8 An electronic device according to an exemplary embodiment of the present application is shown. Figure 8 hereinafter, an electronic device 200 according to this embodiment of the present application is described. Figure 8 The electronic device 200 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0104] like Figure 8As shown, electronic device 200 is implemented as a general-purpose computing device. Components of electronic device 200 may include, but are not limited to, at least one processing unit 210, at least one storage unit 220, a bus 230 connecting various system components (including storage unit 220 and processing unit 210), a display unit 240, and the like.

[0105] The storage unit stores program codes, which can be executed by the processing unit 210, so that the processing unit 210 executes the methods described in this specification according to various exemplary embodiments of the present application. For example, the processing unit 210 can execute the following Figure 1 The method shown in .

[0106] The storage unit 220 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 2201 and / or a cache memory unit 2202 , and may further include a read-only memory unit (ROM) 2203 .

[0107] The storage unit 220 may also include a program / utility 2204 having a set (at least one) of program modules 2205, such program modules 2205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0108] Bus 230 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0109] The electronic device 200 can also communicate with one or more external devices 300 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 200, and / or any device that enables the electronic device 200 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 250. Furthermore, the electronic device 200 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 260. The network adapter 260 can communicate with other modules of the electronic device 200 via the bus 230. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device 200, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0110] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described here can be implemented by software or by combining software with necessary hardware. The technical solution according to the embodiment of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiment of the present application.

[0111] The software product can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0112] Computer-readable storage media may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0113] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0114] The computer-readable medium carries one or more programs. When the one or more programs are executed by the device, the computer-readable medium implements the aforementioned functions.

[0115] Those skilled in the art will appreciate that the modules described above can be distributed in the device according to the description of the embodiment, or can be modified accordingly to be used in one or more devices that are different from the embodiment. The modules of the above embodiment can be combined into one module or further divided into multiple submodules.

[0116] According to an embodiment of the present application, a computer program is provided, including a computer program or instructions. When the computer program or instructions are executed by a processor, the method described above can be executed.

[0117] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present application, the specific implementation methods, and the scope of application of the present application, all fall within the scope of protection of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims

1. A fault current loop circuit, characterized in that: The invention comprises at least one fault current branch, wherein the at least one fault current branch comprises: The discharge terminals are connected to the first common terminal; The charging terminals are all connected to the second common terminal; The ground terminals are all connected to the third common terminal; The fault current branch includes a fault current energy storage branch, the negative end of the fault current energy storage branch is electrically connected to the third common terminal, The fault current energy storage branch comprises: Energy storage capacitors; and An energy storage capacitor reversing branch, connected in parallel with the energy storage capacitor, for performing voltage reversal on the energy storage capacitor; The fault current branch also includes a fault current discharge branch, wherein: The negative terminal of the fault current discharge branch is electrically connected to the first common terminal, the positive terminal of the fault current discharge branch is electrically connected to the positive terminal of the fault current energy storage branch, and the fault current discharge branch includes: Discharge isolating switch, A fault current phase selection valve is connected in series with the discharge isolating switch, and a negative terminal thereof is electrically connected to the first common terminal.

2. The fault current loop circuit according to claim 1, characterized in that: The energy storage capacitor flipping branch includes: Fault current voltage reversal inductance; and A fault current and voltage reversal valve is connected in series with the fault current and voltage reversal inductor, and an anode end of the fault current and voltage reversal valve is electrically connected to the third common end.

3. The fault current loop circuit according to claim 1, characterized in that: The fault current energy storage branch further includes: The energy storage capacitor discharge branch is connected in parallel with the energy storage capacitor and is used to discharge the energy storage capacitor.

4. The fault current loop circuit according to claim 3, characterized in that: The energy storage capacitor discharge branch includes a discharge resistor and a grounding isolation switch connected in series.

5. The fault current loop circuit according to claim 2, characterized in that: The fault current branch further includes a fault current charging branch, wherein a first end of the fault current charging branch is electrically connected to the positive terminal of the fault current energy storage branch, and a second end of the fault current charging branch is electrically connected to the second common terminal.

6. The fault current loop circuit according to claim 5, characterized in that: The fault current charging branch includes a charging isolation switch.

7. The fault current loop circuit according to claim 2, characterized in that: Also included are oscillating inductors and fault current isolation valves, where The oscillating inductor and the fault current isolation valve are connected in series, one end of the oscillating inductor is electrically connected to the fourth common terminal, and the other end of the oscillating inductor is electrically connected to the first common terminal.

8. The fault current loop circuit according to claim 7, characterized in that: Also includes: A high-voltage direct current power supply has one end electrically connected to the ground terminal of the fault current branch and the other end electrically connected to the second common terminal.

9. The fault current loop circuit according to claim 7, characterized in that: The fault current isolation valve, the fault current phase selection valve, and the fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor and a reverse-blocking IGCT connected in series and parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode connected in series and parallel.

10. A multi-source oscillation experimental loop circuit comprising the fault current loop circuit according to any one of claims 1 to 9, characterized in that: The multi-source oscillation experimental loop circuit further includes a high voltage loop circuit, a high current loop circuit and a test valve, wherein: The high voltage loop circuit, the high current loop circuit, the test valve and the fault current loop circuit are connected in parallel. One end of each of the high-voltage loop circuit, the high-current loop circuit, the fault current loop circuit, and the sample valve is electrically connected to the fourth common terminal, and the other end is electrically connected to the third common terminal.

11. A control method for a multi-source oscillation experimental loop circuit according to claim 10, characterized in that: The following steps are involved: S1: Disconnect the grounding isolating switch and the discharging isolating switch in the fault current loop circuit, and close the charging isolating switch in the fault current loop circuit; S2: Using a high-voltage DC power supply to charge the energy storage capacitor in the fault current loop circuit; S3: Disconnecting the charging isolating switch in the fault current loop circuit and closing the discharging isolating switch in the fault current loop circuit; S4: during the test valve opening stage, opening the fault current phase selection valve and the fault current isolation valve in the fault current loop circuit to apply the superposition of the fault current and the high current loop circuit current to the test valve; S5: Turn on the fault current voltage reversal valve of the discharged fault current branch to achieve voltage reversal of the energy storage capacitor; S6: Determine whether the energy storage capacitor voltage meets a preset trigger condition. If the energy storage capacitor voltage meets the trigger condition, execute step S4 after a preset delay.

12. The control method according to claim 11, characterized in that: The fault current isolation valve is turned on at the same time as any one of the fault current phase selection valves is turned on.

13. A control device for a multi-source oscillation circuit, characterized in that: For executing the control method according to any one of claims 11 to 12, the control device comprises: A high voltage loop control unit, configured to perform status monitoring, output voltage control, and fault protection on each converter of the high voltage loop circuit; A high current loop control unit, used for status monitoring, output current control and fault protection of each converter of the high current loop circuit; A coordination control unit, configured to coordinate and control the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit; A fault current loop control unit is used to monitor the status of the fault current isolation valve, fault current phase selection valve, high-voltage DC power supply, and fault current voltage reversal valve of the fault current loop circuit, trigger conduction, control the charging voltage of the energy storage capacitor, and provide fault protection; an input / output unit, configured to exchange data with the high-voltage loop control unit, the high-current loop control unit, the fault current loop control unit, and the coordination control unit, so as to issue trigger pulses to the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit, and receive status information output by the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit; The human-machine interface unit is used to perform signal interaction with the input-output unit and the external PC, receive input instructions from the external PC and status information from the input-output unit, and issue control instructions to the input-output unit.

14. An electronic device comprising: processor; as well as A memory storing a computer program, which, when executed by the processor, enables the processor to execute the control method according to any one of claims 11 to 12. 15 . A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by a processor, causes the processor to execute the control method according to claim 11 .

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