Clock calibration method and device and clock source system
Through frequency division processing and count comparison, the calibration value is determined and the clock signal is gradually calibrated, which solves the problem of high synchronization complexity of the clock source system and subsystem, and realizes simple and efficient clock calibration and automatic clock recovery.
Patent Information
- Application Number
- CN202411324701.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-27
AI Technical Summary
The existing clock source system and subsystem have time out-synchronization problems during clock signal synchronization, resulting in the need of complex digital algorithm calculations and multi-resource consumption, making it difficult to achieve simple and efficient clock calibration.
By obtaining the input signal for frequency division processing, recording the actual count value and comparison with the pre-designed value, determining the calibration value for each cycle, gradually calibrating the clock signal until it is synchronized with the target clock, using frequency dividers, frequency error counters, comparators and clocks The calibration module enables clock calibration, simplifying the process and reducing resource usage.
It realizes clock calibration that is simple, resource-consuming and does not affect the efficiency of the microcontroller, and automatically performs clock recovery, simplifies the clock calibration process and reduces complexity and resource consumption.
Smart Images
Figure CN119200747A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of clock signal processing, and in particular to a clock calibration method, device and clock source system. Background Art
[0002] The clock system device includes a clock source system and a subsystem. The clock source system generates a stable and accurate clock signal, and provides a clock signal for each subsystem in the clock system device, so that each subsystem can synchronize time with the clock source system. However, the clock source system and the subsystem often have time asynchronism. In the prior art, both the clock source system and the subsystem require a timer module, and the process of obtaining the deviation of the subsystem to obtain the calibration step requires digital algorithm calculation. The information interaction between the clock source system and the subsystem requires the participation of the communication interface and the task sequence controller task sequence comparator, resulting in high resource consumption, high complexity and difficulty. Summary of the invention
[0003] In view of this, the embodiments of the present application provide a clock calibration method, device and clock source system, which are simple to implement, occupy few resources, do not affect the efficiency of the microcontroller, and are stable and reliable.
[0004] In a first aspect, an embodiment of the present application provides a clock calibration method, which is applied to a clock source system, comprising:
[0005] Acquire an input signal, perform frequency division processing on the input signal, and obtain a synchronization signal;
[0006] Each time the synchronization signal is received, counting is started according to the current clock signal of the clock source system, and the actual count value captured in the current cycle when the next synchronization signal arrives is recorded;
[0007] Comparing the actual count value of each cycle with the pre-designed value to obtain a deviation value of each cycle;
[0008] Determining a calibration value for each cycle according to the deviation value for each cycle;
[0009] The clock signal is calibrated step by step according to the calibration value of each cycle until it is synchronized with the target clock.
[0010] In a first possible embodiment of the first aspect, the stepwise calibrating the clock signal according to the calibration value of each cycle until it is synchronized with the target clock includes:
[0011] If the deviation value of the current cycle is greater than zero, determining that the calibration value of the current cycle is a negative value, and calibrating the clock signal of the current cycle according to the determined calibration value;
[0012] If the deviation value of the current cycle is less than zero, determining the calibration value of the current cycle to be a positive value, and calibrating the clock signal of the current cycle according to the determined calibration value;
[0013] If the deviation value of the current cycle is equal to zero, the clock calibration is stopped.
[0014] In a second possible embodiment of the first aspect, the calibration value is an integer, and the calibration step range corresponding to the calibration value is [-2, +2].
[0015] In a third possible embodiment of the first aspect, the method further includes:
[0016] If the absolute value of the deviation value of the current cycle is greater than a preset threshold, adjusting the calibration step size to -2 or +2 to calibrate the clock signal of the current cycle;
[0017] If the absolute value of the deviation value of the current cycle is smaller than a preset threshold, the calibration step is adjusted to -1 or +1 to calibrate the clock signal of the current cycle.
[0018] In a fourth possible embodiment of the first aspect, the input signal is an external signal or an internal signal of the clock source system.
[0019] In a fifth possible embodiment of the first aspect, the frequency of the synchronization signal is less than a preset multiple of the frequency of the target clock signal, and is less than the product of the frequency of the target clock signal and the maximum value of a frequency error counter.
[0020] In a second aspect, an embodiment of the present application provides a clock source system, including:
[0021] A frequency divider, used for performing frequency division processing on the received input signal to obtain a synchronization signal;
[0022] A frequency error counter connected to the frequency divider and the clock output terminal of the clock source system, for starting counting and recording an actual count value captured in the current cycle when the next synchronization signal arrives according to the current clock signal of the clock source system each time the synchronization signal is received;
[0023] A comparator, connected to the frequency error counter, for comparing the actual count value of each cycle with a pre-designed value to obtain a deviation value of each cycle;
[0024] A clock calibration module is connected to the clock calibration end of the clock source system and is used to determine the calibration value of each cycle according to the deviation value of each cycle, so as to gradually calibrate the clock signal according to the calibration value of each cycle until it is synchronized with the target clock.
[0025] In a first possible embodiment of the second aspect, the clock calibration device further includes a signal selector;
[0026] The signal selector is connected to the external sub-device and the internal reference clock output terminal of the clock source system, and is used to receive external signals and internal signals, and select one of the external signals or the internal signal as the input signal.
[0027] In a second possible embodiment of the second aspect, the clock calibration module includes an adder;
[0028] The adder is connected to the clock calibration terminal of the clock source system, and is used to calibrate the clock signal according to the calibration step length of each cycle, so that the clock signal gradually approaches the target clock.
[0029] In a third aspect, an embodiment of the present application provides a clock source system, comprising the above-mentioned clock calibration device.
[0030] The embodiments of the present application have the following beneficial effects:
[0031] A clock calibration method of this embodiment is applied to a clock source system, including: obtaining an input signal, dividing the input signal to obtain a synchronization signal; each time a synchronization signal is received, starting to count and record the actual count value captured in the current cycle when the next synchronization signal arrives according to the current clock signal of the clock source system; comparing the actual count value of each cycle with the pre-designed value to obtain the deviation value of each cycle; determining the calibration value of each cycle according to the deviation value of each cycle; and calibrating the clock signal step by step according to the calibration value of each cycle until it is synchronized with the target clock. Based on the above scheme, the clock source system calibrates its own clock signal according to the input signal to realize the function of automatic clock recovery. At the same time, during the implementation of the clock calibration method, it occupies less IO and does not require additional communication modules. The implementation method is simple and reliable. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0033] Figure 1 A first schematic diagram of the framework of the clock calibration device according to an embodiment of the present application is shown;
[0034] Figure 2A second schematic diagram of the framework of the clock calibration device according to an embodiment of the present application is shown;
[0035] Figure 3 A first flow chart of the clock calibration method according to an embodiment of the present application is shown;
[0036] Figure 4 A second flow chart of the clock calibration method according to an embodiment of the present application is shown.
[0037] Description of main component symbols:
[0038] 100 - clock calibration device; 110 - frequency divider; 120 - frequency error counter; 130 - comparator; 140 - clock calibration module; 150 - signal selector. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0040] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0041] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.
[0042] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.
[0043] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0044] Typically, the clock source system includes a first timer module and a deviation acquisition module, and the subsystem includes a second timer module and a deviation compensation module, and both also need to contain a communication module to obtain the clock deviation. The first timer module obtains the first clock signal of the clock source system and the second clock signal of the subsystem, and the deviation acquisition module of the clock source system calculates the clock deviation according to the first clock signal and the second clock signal, and sends the clock deviation to the subsystem to instruct the subsystem to calibrate the clock signal. The information exchange between the clock source system and the subsystem causes the clock recovery process to be too costly and too complicated. The present application obtains the calibration step of the clock signal of the clock source system by processing and comparing the input signal accordingly, and continuously calibrates the clock signal according to the calibration step to achieve clock synchronization of the clock source system.
[0045] Before describing the clock calibration method, the clock calibration device 100 is first introduced accordingly.
[0046] Example 1
[0047] Figure 1 A schematic diagram of a framework of a clock calibration device 100 according to an embodiment of the present application is shown. Exemplarily, the clock calibration device 100 is applied to a clock source system, and the clock calibration device 100 includes a frequency divider 110, a frequency error counter 120, a comparator 130, and a clock calibration module 140. Specifically, the clock output end of the clock source system is connected to the frequency error counter 120 to provide an actual clock signal to the frequency error counter 120, and the frequency divider 110, the frequency error counter 120, the comparator 130, and the clock calibration module 140 are connected in sequence to calibrate the clock signal in sequence to achieve clock synchronization. In this embodiment, the frequency divider 110, the frequency error counter 120, the comparator 130, and the clock calibration module 140 also have the following functions.
[0048] The frequency divider 110 is used to perform frequency division processing on the received input signal to obtain a synchronization signal.
[0049] Exemplarily, the clock source system has two input signals, one of which can be flexibly selected according to the application scenario. One of the sources of the input signal is the external signal EXT_IN of the clock source system; the other source of the input signal is other clock signals inside the clock source system.
[0050] For example, in one embodiment, Figure 2As shown, the input signal is one of the external signal EXT_IN or the internal signal INT_IN of the clock source system; the clock calibration device 100 also includes a signal selector 150; the signal selector 150 is connected to the external sub-device of the clock source system and the internal reference clock output terminal, and is used to receive the external signal EXT_IN and the internal signal INT_IN, and select one of the external signal EXT_IN or the internal signal INT_IN as the input signal.
[0051] Specifically, the external signal EXT_IN is a pulse signal with a fixed time interval, which is used to synchronize the clock of the external sub-device; the internal signal INT_IN is a clock signal provided by the internal reference clock output terminal of the clock source system for its own clock recovery. The clock source system can calibrate the clock signal with the help of its own more accurate internal signal INT_IN. When one of the multiple input signals needs to be output, the signal selector 150 can select one of the input signals to output to the output port according to the control signal or logic condition. For example, when the control signal is logic 1, the external signal EXT_IN1 is selected; when the control signal is logic 0, the internal signal INT_IN2 is selected.
[0052] Exemplarily, the clock source system performs synchronous frequency division processing on the input signal through the divider 110 to obtain the divided synchronous signal. The purpose is to solve the problem of poor calibration accuracy of the clock signal of the clock source system due to the excessively high frequency of the input signal. The clock source system expands the frequency range of the input signal through the divider 110.
[0053] Specifically, the frequency divider 110 is used to reduce the frequency of the input signal while keeping the phase of the synchronization signal the same as the input signal, thereby obtaining the synchronization signal after frequency division. The frequency divider 110 can be implemented by a counter. Different frequency division ratios can be achieved by changing the count value of the counter, so that the frequency of the input signal can be reduced. The counter frequency of the counter is provided by the reference clock signal, and its count value is determined by the frequency division ratio. The frequency divider 110 reduces the frequency of the input signal to the original 1 / n (n is the frequency division ratio). In the frequency divider 110, there is an integer multiple relationship between the frequencies of the input signal and the reference clock signal, so their phase synchronization can be maintained. For example, when the reference clock frequency is an integer multiple of the input signal frequency, the counter can complete a certain count in each reference clock cycle so that the output signal has the same phase as the input signal.
[0054] Optionally, the frequency of the synchronization signal is less than a preset multiple of the frequency of the target clock signal, and is less than the product of the frequency of the target clock signal and the maximum value of the frequency error counter 120. The preset multiple can be set according to actual application conditions, for example, the frequency of the synchronization signal is less than 128 times the frequency of the target clock signal.
[0055] The frequency error counter 120 is connected to the frequency divider 110 and the clock output terminal of the clock source system, and is used to start counting and record the actual count value captured in the current cycle when the next synchronization signal arrives according to the current clock signal of the clock source system each time the synchronization signal is received;
[0056] Exemplarily, the clock source system captures the actual count value of the current cycle through the frequency error counter 120. The frequency error counter 120 uses the actual clock signal of the clock source system as a clock to synchronize the count of the frequency error counter 120 to a fixed starting point. When the synchronization signal arrives, the frequency error counter 120 starts counting according to the rising edge or falling edge of the synchronization signal, records the number of rising edges of the synchronization signal, and stops counting after counting to the cycle of the actual clock signal to obtain the actual count value.
[0057] Optionally, when the frequency error counter 120 receives the first synchronization signal, it starts counting down from the overload value, and when it receives the second synchronization signal, it saves the count value to obtain the current captured count value. At the same time, the frequency error counter 120 counts down from the overload value again, and then receives multiple second clock signals in sequence, and repeats this operation to obtain the actual count value.
[0058] The comparator 130 is connected to the frequency error counter 120 and is used to compare the actual count value of each cycle with the pre-designed value to obtain the deviation value of each cycle;
[0059] Exemplarily, the pre-designed value is calculated and optimized by the system designer according to the requirements and characteristics of the clock source system to obtain an optimal pre-designed value to ensure that the clock source system has good performance and stability. The pre-designed value can be the count value captured by the frequency error counter 120 when the clock of the clock source system is synchronized.
[0060] Optionally, the preset count value is that each time a synchronization signal is received, counting is started according to the target clock signal, and the count value captured when the next synchronization signal arrives is recorded.
[0061] The clock calibration module 140 is connected to the clock calibration terminal of the clock source system and is used to determine the calibration value of each cycle according to the deviation value of each cycle, so as to gradually calibrate the clock signal according to the calibration value of each cycle until it is synchronized with the target clock.
[0062] Optionally, the calibration value is an integer, and the calibration step range corresponding to the calibration value is [-2, +2]. It can be understood that if the calibration step range is too large, on the one hand, it will lead to poor accuracy of clock calibration; on the other hand, it will lead to more occupied resources, so after comprehensive consideration, the calibration step can be set to [-2, +2]. When the absolute value of the deviation value is greater than the preset threshold, that is, the frequency of the clock signal differs greatly from the frequency of the target clock signal, the clock calibration module 140 adjusts the calibration step to -2 or +2; when the absolute value of the deviation value is less than the preset threshold, that is, the frequency of the clock signal differs little from the frequency of the target clock signal, the clock calibration module 140 adjusts the calibration step to -1 or +1.
[0063] For example, in one embodiment, if the absolute value of the deviation value of the current cycle is greater than a preset threshold, the clock calibration module 140 adjusts the calibration step to -2 or +2 to calibrate the clock signal of the current cycle; if the absolute value of the deviation value of the current cycle is less than the preset threshold, the clock calibration module 140 adjusts the calibration step to -1 or +1 to calibrate the clock signal of the current cycle.
[0064] Specifically, the value of the preset threshold depends on the specific application scenario and the requirements of the clock source system. In some application scenarios, the floating range of the deviation value is small, and the preset threshold will be relatively small; in other application scenarios, the floating range of the deviation value is large, and the preset threshold is relatively large.
[0065] It can be understood that the clock calibration module 140 adaptively adjusts the calibration step size according to the difference between the frequency of the clock signal and the frequency of the target clock signal, which can simplify the complexity of the clock signal calibration and improve the calibration accuracy of the clock signal.
[0066] In one embodiment, the clock calibration module 140 further includes an adder; the adder is connected to the clock calibration terminal of the clock source system and is used to calibrate the clock signal according to the calibration step of each cycle so that the clock signal gradually approaches the target clock.
[0067] Exemplarily, the clock calibration module 140 adds the calibration step length and the clock signal through an adder to calculate the calibration time and gradually approach the frequency of the clock signal to the target clock signal. Specifically, the adder adds the calibration step length and the period of the current clock signal to obtain a calibrated time value, which is used to adjust the frequency of the clock signal to gradually approach the frequency of the target clock signal.
[0068] It can be understood that the clock output end of the clock source system is used to provide the current actual clock signal to the frequency error counter 120, so that the frequency error counter 120 counts according to the actual clock signal and the synchronization signal to obtain the actual count value, and the comparator 130 obtains the deviation value based on the comparison result between the actual count value and the pre-designed value. The clock calibration module 140 converts the deviation value into a calibration step according to the size of the deviation value, and provides the oscillator with a calibration step for clock calibration. The clock calibration module 140 also calibrates the current actual clock signal according to the calibration step to provide an accurate clock signal, so that the clock source system can achieve clock synchronization.
[0069] The clock calibration method is described below in conjunction with some specific embodiments.
[0070] Example 2
[0071] Figure 3 A flow chart of a clock calibration method according to an embodiment of the present application is shown. Exemplarily, the clock calibration method is applied to a clock source system and includes the following steps:
[0072] S210, acquiring an input signal, performing frequency division processing on the input signal, and obtaining a synchronization signal.
[0073] S220, each time a synchronization signal is received, counting is started according to the current clock signal of the clock source system, and the actual count value captured in the current cycle when the next synchronization signal arrives is recorded.
[0074] S230, comparing the actual count value of each cycle with the pre-designed value to obtain the deviation value of each cycle.
[0075] S240, determining a calibration value for each cycle according to the deviation value for each cycle.
[0076] S250, gradually calibrating the clock signal according to the calibration value of each cycle until it is synchronized with the target clock.
[0077] In one embodiment, if Figure 4 As shown, the clock calibration method gradually calibrates the clock signal according to the calibration value of each cycle until it is synchronized with the target clock, including the following steps:
[0078] S251, if the deviation value of the current cycle is greater than zero, determine that the calibration value of the current cycle is a negative value, and calibrate the clock signal of the current cycle according to the determined calibration value through an adder.
[0079] S252, if the deviation value of the current cycle is less than zero, determine that the calibration value of the current cycle is a positive value, and calibrate the clock signal of the current cycle according to the determined calibration value through an adder.
[0080] S253: If the deviation value of the current cycle is equal to zero, stop clock calibration.
[0081] Specifically, the positive and negative values of the calibration step are determined according to the positive and negative values of the deviation value. If the deviation value is positive, it means that the frequency of the clock signal is too high, and the calibration step needs to be adjusted to a negative value to reduce the frequency; conversely, if the deviation value is negative, it means that the frequency of the clock signal is too low, and the calibration step needs to be adjusted to a positive value to increase the frequency. In this way, the clock source system can accurately adjust the frequency of the clock signal to ensure that it is consistent with the target clock signal.
[0082] It can be understood that the clock calibration method divides the input signal obtained to obtain multiple synchronization signals of the same frequency. The first synchronization signal starts the frequency error counter 120 to count. The frequency error counter 120 serves as the clock source system clock. Then, each time the frequency error counter 120 receives a synchronization signal, it will reload the count. The clock calibration method compares the actual count value of the frequency error counter 120 with the pre-designed value through the comparator 130 to obtain the deviation value. The clock calibration method also outputs a corresponding calibration step according to the deviation value to calibrate the clock source system clock. Each calibration step varies with the last calibration step in the range [-2, +2]. The clock source system counts the error between multiple synchronization signals and the current clock signal to obtain different actual count values, and calibrates the clock signal with different calibration steps, so that the clock signal approaches the target clock signal one by one within a certain deviation range to complete the synchronization with the target clock signal. The clock calibration method makes the process of converting the deviation value into the calibration step extremely simple by making the clock signal approach the target clock signal one by one, and consumes fewer resources at the same time, and only requires one adder to complete.
[0083] It can be understood that the clock calibration method of this embodiment corresponds to the clock calibration device 100 of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.
[0084] The present application also provides a clock source system, which exemplarily includes the above-mentioned clock calibration device 100. Specifically, the clock source system provides a clock signal for each subsystem in the clock system device by providing a stable and accurate clock signal. The clock source system can provide a clock signal for each logic module in a digital circuit such as a microprocessor, a microcontroller, and a digital signal processor to ensure that the clock source system and each subsystem work at a consistent speed and beat.
[0085] Optionally, the clock source system also includes an oscillator connected to the clock output terminal and the clock calibration terminal of the clock source system, for providing an actual clock signal to the clock calibration device 100, and generating a stable, periodic and accurate clock signal according to the calibration result of the clock calibration device 100, so as to provide a time reference for the entire clock source system and each subsystem.
[0086] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.
Claims
1. A clock calibration method, characterized in that: Applicable to clock source systems, including: Acquire an input signal, perform frequency division processing on the input signal, and obtain a synchronization signal; Each time the synchronization signal is received, counting is started according to the current clock signal of the clock source system, and the actual count value captured in the current cycle when the next synchronization signal arrives is recorded; Comparing the actual count value of each cycle with the pre-designed value to obtain a deviation value of each cycle; Determining a calibration value for each cycle according to the deviation value for each cycle; The clock signal is calibrated step by step according to the calibration value of each cycle until it is synchronized with the target clock.
2. The clock calibration method according to claim 1, characterized in that: The step of calibrating the clock signal step by step according to the calibration value of each cycle until it is synchronized with the target clock includes: If the deviation value of the current cycle is greater than zero, determining that the calibration value of the current cycle is a negative value, and calibrating the clock signal of the current cycle according to the determined calibration value; If the deviation value of the current cycle is less than zero, determining the calibration value of the current cycle to be a positive value, and calibrating the clock signal of the current cycle according to the determined calibration value; If the deviation value of the current cycle is equal to zero, the clock calibration is stopped.
3. The clock calibration method according to claim 2, characterized in that: The calibration value is an integer, and the calibration step range corresponding to the calibration value is [-2, +2].
4. The clock calibration method according to claim 3, characterized in that: The method further comprises: If the absolute value of the deviation value of the current cycle is greater than a preset threshold, adjusting the calibration step size to -2 or +2 to calibrate the clock signal of the current cycle; If the absolute value of the deviation value of the current cycle is smaller than a preset threshold, the calibration step is adjusted to -1 or +1 to calibrate the clock signal of the current cycle.
5. The clock calibration method according to claim 1, characterized in that: The input signal is one of an external signal or an internal signal of the clock source system.
6. The clock calibration method according to claim 1, characterized in that: The frequency of the synchronization signal is less than a preset multiple of the frequency of the target clock signal, and is less than a product of the frequency of the target clock signal and a maximum value of a frequency error counter.
7. A clock calibration device, characterized in that: Applicable to clock source systems, including: A frequency divider, used for performing frequency division processing on the received input signal to obtain a synchronization signal; A frequency error counter connected to the frequency divider and the clock output terminal of the clock source system, for starting counting and recording an actual count value captured in the current cycle when the next synchronization signal arrives according to the current clock signal of the clock source system each time the synchronization signal is received; A comparator, connected to the frequency error counter, for comparing the actual count value of each cycle with a pre-designed value to obtain a deviation value of each cycle; A clock calibration module is connected to the clock calibration end of the clock source system and is used to determine the calibration value of each cycle according to the deviation value of each cycle, so as to gradually calibrate the clock signal according to the calibration value of each cycle until it is synchronized with the target clock.
8. The clock calibration device according to claim 7, characterized in that: Also included is a signal selector; The signal selector is connected to the external sub-device and the internal reference clock output terminal of the clock source system, and is used to receive external signals and internal signals, and select one of the external signals or the internal signal as the input signal.
9. The clock calibration device according to claim 7, characterized in that: The clock calibration module includes an adder; The adder is connected to the clock calibration terminal of the clock source system, and is used to calibrate the clock signal according to the calibration step of each cycle, so that the clock signal gradually approaches the target clock.
10. A clock source system, characterized in that: Comprising a clock calibration device as described in any one of claims 7-9.