Information processing apparatus

Abstract

The embodiment of the invention relates to an information processing device, and the device comprises a mainboard which is provided with a first surface, and the first surface is provided with a central processing unit electrically connected with the mainboard; the compression additional memory module is located on one side of the first surface, and at least one surface of the compression additional memory module is provided with a plurality of chips; the external connection structure is located on one side of the first surface and is configured to be electrically connected with the compression additional memory module and the central processing unit, and the central processing unit is configured to read and write data into each chip at least through the external connection structure. The information processing device provided by the embodiment of the invention at least can enhance the heat dissipation function of the mainboard.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an information processing device. Background Art

[0002] CAMM (Compression Attached Memory Module) is a new type of memory module. CAMM connects multiple chips, fixes multiple chips on the motherboard, and electrically connects the motherboard and the chips. The central processing unit electrically connected to the motherboard can write data to the chip or read data from the chip. Compared with traditional memory modules, it is thinner and has better heat dissipation.

[0003] Signal transmission between the chip and the central processing unit is usually achieved through signal lines located in the motherboard. However, as the number of chips connected to the CAMM increases, the number of signal lines in the motherboard increases, which not only increases the thickness of the motherboard and slows down the heat dissipation of the motherboard, but also increases the routing density of the signal lines in the motherboard, resulting in serious crosstalk between signal lines and causing signal distortion. Summary of the invention

[0004] The disclosed embodiment provides an information processing device, which is at least beneficial to enhancing the heat dissipation of a mainboard.

[0005] An embodiment of the present disclosure provides a signal processing device, comprising: a mainboard having a first surface, the first surface having a central processing unit electrically connected to the mainboard; a compressed additional memory module located on one side of the first surface, at least one surface of the compressed additional memory module having a plurality of chips; an external connection structure located on one side of the first surface, configured to electrically connect the compressed additional memory module and the central processing unit, the central processing unit being configured to read and write data to each of the chips at least via the external connection structure.

[0006] In some embodiments, a mainboard has a plurality of signal lines, each of which electrically connects the central processing unit and the compressed additional memory module, and the central processing unit is configured to read and write data to each of the chips via the signal lines and the external connection structure.

[0007] In some embodiments, the external connection structure is located on a side of the compressed additional memory module facing the central processing unit.

[0008] In some embodiments, a height of the CCAM module relative to the motherboard is greater than a height of the CPU relative to the motherboard.

[0009] In some embodiments, the system further includes: a central processing unit connector, the central processing unit connector is located on the first surface, and a height of the central processing unit connector compared to the mainboard is greater than a height of the central processing unit compared to the mainboard.

[0010] In some embodiments, the height of the CPU connector relative to the motherboard is the same as the height of the CCAM module relative to the motherboard.

[0011] In some embodiments, a bottom surface of a CPU connector facing the first surface is electrically connected to the CPU, and a top surface of the CPU connector away from the first surface is electrically connected to the external connection structure.

[0012] In some embodiments, the motherboard is configured to: electrically connect the central processing unit connector and the central processing unit, the central processing unit and the motherboard are electrically connected via a gold finger or a ball grid array; the central processing unit connector and the external connection structure are electrically connected via any one of a ball grid array, a press-type connector or a silicon interposer.

[0013] In some embodiments, it also includes: a first adapter, located between the mainboard and the compressed additional memory module, for electrically connecting the mainboard and the compressed additional memory module, and the first adapter is also used to electrically connect the external connection structure and the compressed additional memory module.

[0014] In some embodiments, the external connection structure is in electrical contact with a surface of the first adapter facing the CAM module.

[0015] In some embodiments, it also includes: a first adapter, located between the mainboard and the compressed additional memory module, used to electrically connect the mainboard and the compressed additional memory module; a second adapter, located on a side of the compressed additional memory module away from the mainboard, the second adapter electrically connecting the external connection structure and the compressed additional memory module.

[0016] In some embodiments, the number of the compressed additional memory modules is two, the two compressed additional memory modules are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules are electrically connected to the central processing unit through the same external connection structure.

[0017] In some embodiments, the first adapter is a silicon interposer or a z-axis compression connector; and the external connection structure is a flexible circuit board.

[0018] In some embodiments, the compressed additional memory module has the multiple chips on one of its surfaces along a direction perpendicular to the first surface; or, the compressed additional memory module has the multiple chips on two opposite surfaces along a direction perpendicular to the first surface.

[0019] In some embodiments, it also includes: a top pad, located on the surface of the compressed additional memory module away from the mainboard, the top pad having at least one mounting hole; a bottom pad, fixed to the first surface, the bottom pad is located on the surface of the compressed additional memory module facing the mainboard, the bottom pad having at least one pin corresponding to the mounting hole; a fastener, matching the pin, the fastener is used to fix the pin after the pin passes through the mounting hole, so that the top pad and the bottom pad clamp and fix the compressed additional memory module.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] In the information processing device provided by the embodiment of the present disclosure, an external connection structure is arranged on one side of the first surface of the mainboard, and is used to electrically connect the compressed additional memory module and the central processing unit. That is, the external connection structure is routed from the outside of the mainboard to connect the compressed additional memory module and the central processing unit. In this way, the number of signal lines in the mainboard for electrically connecting the central processing unit and the compressed additional memory module can be reduced, and even the arrangement of the signal lines in the mainboard can be omitted, thereby greatly reducing the thickness of the mainboard, greatly reducing the heat dissipation path of the mainboard, and facilitating the heat dissipation of the mainboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic cross-sectional structure diagram of a first information processing device provided by an embodiment of the present disclosure;

[0024] Figure 2 A schematic cross-sectional structure diagram of a second information processing device provided by an embodiment of the present disclosure;

[0025] Figure 3A schematic diagram of the three-dimensional structure of an information processing device provided by an embodiment of the present disclosure;

[0026] Figure 4 A schematic cross-sectional structure diagram of a third information processing device provided by an embodiment of the present disclosure;

[0027] Figure 5 A schematic cross-sectional structure diagram of a fourth information processing device provided by an embodiment of the present disclosure;

[0028] Figure 6 A schematic cross-sectional structure diagram of a fifth information processing device provided by an embodiment of the present disclosure;

[0029] Figure 7 A schematic cross-sectional structure diagram of a sixth information processing device provided by an embodiment of the present disclosure;

[0030] Figure 8 A schematic cross-sectional structure diagram of a seventh information processing device provided by an embodiment of the present disclosure;

[0031] Fig. 9 A schematic cross-sectional structure diagram of an eighth information processing device provided by an embodiment of the present disclosure;

[0032] Fig.10 A schematic cross-sectional structure diagram of a ninth information processing device provided by an embodiment of the present disclosure;

[0033] Fig.11 A schematic cross-sectional structure diagram of a tenth information processing device provided by an embodiment of the present disclosure;

[0034] Fig.12 A schematic diagram of the three-dimensional structure of another information processing device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] As can be seen from the background technology, the heat dissipation capacity of the mainboard in the current signal processing device is relatively poor. Analysis shows that one of the reasons for the poor heat dissipation capacity of the mainboard is that there are many signal lines in the mainboard for electrically connecting the central processing unit and the compressed additional memory module. As the number of chips connected to the compressed additional memory module increases, the number of signal lines in the mainboard increases, which in turn leads to an increasing thickness of the mainboard, resulting in a significant reduction in the heat dissipation capacity of the mainboard.

[0036] The disclosed embodiment provides a signal processing device, in which an external connection structure is arranged on one side of the first surface of a mainboard, and is used to electrically connect a compressed additional memory module and a central processing unit. That is, the external connection structure is routed from the outside of the mainboard to connect the compressed additional memory module and the central processing unit. In this way, the number of signal lines in the mainboard for electrically connecting the central processing unit and the compressed additional memory module can be reduced, and even the arrangement of signal lines in the mainboard can be omitted, thereby greatly reducing the thickness of the mainboard and greatly increasing the heat dissipation capacity of the mainboard.

[0037] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0038] Figure 1 A schematic cross-sectional structure diagram of a first information processing device provided in one embodiment of the present disclosure.

[0039] refer to Figures 1 to 3 The signal processing device includes: a mainboard 101 having a first surface, the first surface having a central processing unit 102 electrically connected to the mainboard 101. The signal processing device also includes: a compressed additional memory module 103 located on one side of the first surface, at least one surface of the compressed additional memory module 103 having a plurality of chips 104. The signal processing device also includes: an external connection structure 105 located on one side of the first surface, configured to: electrically connect the compressed additional memory module 103 and the central processing unit 102, and the central processing unit 102 is configured to: read and write data to each chip 104 at least via the external connection structure 105.

[0040] The central processing unit 102, referred to as CPU for short, is the computing and control core of the computer system and is the final execution unit for information processing and program running.

[0041] The mainboard 101 is also called a motherboard, and can be used as a carrier for the central processing unit 102 and the compressed additional memory module 103, and realizes the electrical connection between the central processing unit 102 and the compressed additional memory module 103. In some embodiments, the mainboard 101 can be a system board, a logic board or any other printed circuit board.

[0042] The compression attached memory module 103, namely “Compression Attached Memory Module”, referred to as CAMM, is a new form of notebook memory different from the traditional SO-DIMM. Its structure includes: a PCB circuit board and a chip 104 that can be installed on both sides.

[0043] When the central processing unit 102 writes data to the chip 104, it can send the address information through the address line, then send a memory write command through the control line, select the chip 104, and write data to the selected chip 104 through the external connection structure 105. When the central processing unit 102 reads data from the chip 104, it sends the address information through the address line, then sends a memory read command through the control line, selects the chip 104, and the selected chip 104 sends the data in the chip 104 to the central processing unit 102 through the external connection structure 105.

[0044] In some embodiments, the chip 104 may include any one of DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory) or SDRAM (Synchronous Dynamic Random-Access Memory).

[0045] In a specific example, the chip 104 may be a DRAM, specifically some variant of synchronous DRAM, such as DDR3 (DDR version 3), DDR4 (DDR version 4), DDR5 (DDR version 5), LPDDR3 (low power DDR version 3), LPDDR4 (LPDDR version 4), LPDDR5 (LPDDR version 5), or other or a combination of memory technologies.

[0046] The external connection structure 105 is located on one side of the first surface of the mainboard 101, that is, the external connection structure 105 is arranged outside the mainboard 101 to realize the electrical connection between the central processing unit 102 and the compressed additional memory module 103. Since the chip 104 is electrically connected to the compressed additional memory module 103, the central processing unit 102 can read and write data to the chip 104 through the external connection structure 105 and the compressed additional memory module 103.

[0047] Figure 2 A schematic cross-sectional structure diagram of a second signal processing device provided in an embodiment of the present disclosure, Figure 3 A schematic diagram of the three-dimensional structure of an information processing device provided by an embodiment of the present disclosure.

[0048] refer to Figure 2 as well as Figure 3 In some embodiments, the motherboard 101 has a plurality of signal lines 10, each signal line 10 electrically connects the central processing unit 102 and the compressed additional memory module 103, and the central processing unit 102 is configured to read and write data to each chip 104 via the signal line 10 and the external connection structure 105. That is, the external connection structure 105 and the signal line 10 can both realize signal transmission between the central processing unit 102 and the chip 104, the signal line 10 is located inside the motherboard 101, and the external connection structure 105 is located outside the motherboard 101, so that the number of signal lines 10 in the motherboard 101 can be greatly reduced. On the one hand, the volume occupied by the signal line 10 in the motherboard 101 can be reduced, the thickness of the motherboard 101 can be reduced, and the heat dissipation of the motherboard 101 can be enhanced. On the other hand, the routing density of the signal line 10 in the motherboard 101 is greatly reduced, thereby avoiding the crosstalk problem between the signals transmitted in different signal lines 10 caused by the excessive routing density of the signal line 10, and avoiding the distortion of the transmitted signal in the signal line 10.

[0049] By jointly realizing signal transmission between the central processing unit 102 and the chip 104 through the external connection structure 105 and the signal line 10, the flexibility of the wiring of the external connection structure 105 and the signal line 10 can be enhanced, which can avoid the problem of too dense routing of the external connection structure 105 and the problem of too dense routing of the signal line 10, and greatly reduce the risk of signal distortion caused by excessive routing density.

[0050] refer to Figure 4 In some embodiments, the mainboard 101 further includes a plurality of signal lines 10, and the signal processing device further includes: a first pin 21, located on the first surface, and the central processing unit 102 is electrically connected to the first pin 21 to achieve electrical connection with the mainboard 101. The signal line 10 is electrically connected to a portion of the first pin 21, and further electrically connected to the central processing unit 102 and the compressed additional memory module 103.

[0051] The signal processing device further includes: a second pin 22, located on the first surface, the second pin 22 is electrically connected to the remaining first pin 21, and the second pin 22 is electrically connected to the external connection structure 105, so as to realize the electrical connection between the central processing unit 102 and the external connection structure 105. In some embodiments, the mainboard 101 further includes a first lead 20, the first lead 20 is used to electrically connect the first pin 21 and the second pin 22, so that the second pin 22 can be electrically connected to the central processing unit 102, and then the external connection structure 105 electrically connected to the second pin 22 can be electrically connected to the central processing unit 102.

[0052] In some embodiments, the second pin 22 is located on the first surface between the central processing unit 102 and the compressed additional memory module 103, and is disposed adjacent to the first pin 21, so that the length of the first lead 20 in the mainboard 101 is shorter, reducing the transmission loss of the signal transmitted in the first lead 20. And because the length of the first lead 20 is shorter, the loss of the signal transmitted in the first lead 20 is smaller, therefore, the diameter of the first lead 20 can be set smaller, reducing the volume occupied by the first lead 20 in the mainboard 101, and avoiding the increase in the thickness of the mainboard 101 due to the setting of the first lead 20.

[0053] In some embodiments, the diameter of the first lead 20 may be smaller than the diameter of the signal line 10. In this way, it can be ensured that the provision of the first lead 20 will not cause a further increase in the thickness of the mainboard 101.

[0054] It is understandable that in some embodiments, the signal line 10 may not be provided in the mainboard 101, so that the chip 104 and the central processor 102 transmit signals only through the external connection structure 105. In this way, the thickness of the mainboard 101 can be greatly reduced, and the heat dissipation of the mainboard 101 can be further enhanced.

[0055] In some embodiments, the chip 104 and the central processing unit 102 transmit signals only through the external connection structure 105, and the signal processing device further includes: a first pin located on the first surface, and the central processing unit 102 is electrically connected to the first pin to achieve electrical connection with the mainboard 101.

[0056] The signal processing device further includes: a second pin, located on the first surface, the second pin being electrically connected to the first pin, and the second pin being electrically connected to the external connection structure 105, so as to realize the electrical connection between the central processing unit 102 and the external connection structure 105. In some embodiments, the mainboard 101 further includes a first lead, and the first lead is used to electrically connect the first pin and the second pin.

[0057] In some embodiments, the first pin may be a gold finger or a ball grid array, and the second pin may be a gold finger or a ball grid array.

[0058] The gold finger is a structure composed of multiple golden conductive contacts. It is called a gold finger because its surface is gold-plated and the conductive contacts are arranged like fingers.

[0059] The ball grid array is a spherical contact made in an array on the first surface of the mainboard 101. In some embodiments, the spherical contact can be an array of solder balls.

[0060] Both the gold fingers and the ball grid array can be formed on the first surface in a manner well known to those skilled in the art, and are in electrical contact with the CPU 102 .

[0061] In some embodiments, the first lead 20 may be formed in the mainboard 101 by electroplating. The embodiment of the present disclosure does not limit the specific routing method and shape of the first lead 20 in the mainboard 101, and only needs to satisfy that the first lead 20 can electrically connect the first pin 21 and the second pin 22. The material of the first lead 20 may be a metal material, for example, may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.

[0062] refer to Figures 1 to 3 In some embodiments, the external connection structure 105 is located on the side of the compressed additional memory module 103 facing the central processor 102. The central processor 102 and the compressed additional memory module 103 are both located on the first surface, and the central processor 102 and the compressed additional memory module 103 are arranged opposite to each other. The external connection structure 105 can be located between the central processor 102 and the compressed additional memory module 103. The external connection structure 105 is located on the side of the compressed additional memory module 103 facing the central processor 102, that is, the external connection structure 105 is directly opposite to the compressed additional memory module 103, and the height of the external connection structure 105 compared to the first surface is not higher than the height of the compressed additional memory module 103 compared to the first surface. That is to say, the free space between the compressed additional memory module 103 and the central processing unit 102 can be used to set up the external connection structure 105, and because the height of the external connection structure 105 is not higher than the height of the compressed additional memory module 103, the external connection structure 105 will not occupy too much extra volume, thereby preventing the problem that the thickness of the information processing device cannot be further reduced due to the excessive thickness of the external connection structure 105.

[0063] In some embodiments, the height of the CAM module relative to the motherboard 101 is greater than the height of the CPU 102 relative to the motherboard 101. In other words, the height of the surface of the CAM module 103 away from the motherboard 101 relative to the first surface is greater than the height of the surface of the CPU 102 away from the motherboard 101 relative to the first surface.

[0064] refer to Figure 5 In some embodiments, the signal processing device further includes: a central processing unit connector 106, the central processing unit connector 106 is located on the first surface, and the central processing unit connector 106 is used to electrically connect the external connection structure 105 and the central processing unit 102. The central processing unit connector 106 is located between the central processing unit 102 and the compressed additional memory module 103, and is disposed adjacent to the central processing unit 102, so that the distance between the central processing unit connector 106 and the central processing unit 102 is short, which is conducive to enhancing the electrical transmission performance between the central processing unit 102 and the external connection structure 105.

[0065] In some embodiments, the bottom surface of the CPU connector 106 facing the first surface is electrically connected to the CPU 102, and the top surface of the CPU connector 106 away from the first surface is electrically connected to the external connection structure 105. Then the bottom surface of the CPU connector 106 is in electrical contact with the gold finger or ball grid array located on the first surface, the top surface of the CPU connector 106 has a ball grid array or a press-type connector, and the CPU connector 106 is in electrical contact with the external connection structure 105 through any one of the ball grid array, press-type connector or silicon interposer located on the top surface.

[0066] One end of the external connection structure 105 is electrically connected to the central processing unit 102, and the other end is electrically connected to the compressed additional memory module 103. That is, the external connection structure 105 extends in the direction from the central processing unit 102 to the compressed additional memory module 103. Since the height of the compressed additional memory module 103 relative to the first surface is higher than the height of the central processing unit 102 relative to the first surface, there is a large height difference between the compressed additional memory module 103 and the central processing unit 102. This may cause the heights of the two ends of the external connection structure 105 to be inconsistent, resulting in the problem that the external connection structure 105 is tilted relative to the first surface, and further resulting in a larger space occupied by the external connection structure 105.

[0067] Based on the above considerations, in some embodiments, the height of the CPU connector 106 relative to the motherboard 101 is greater than the height of the CPU 102 relative to the motherboard 101. In other words, the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the motherboard 101 is greater than the height of the surface of the CPU 102 away from the motherboard 101 relative to the motherboard 101. In this way, the height difference between the CPU connector 106 and the compression additional memory module 103 is smaller than the height difference between the CPU 102 and the compression additional memory module 103. Since the external connection structure 105 is electrically connected to the CPU connector 106, compared with being directly connected to the CPU 102, the height difference between the external connection structure 105 and the compression additional memory module 103 is smaller, so that the inclination of the external connection structure 105 relative to the first surface is not too large, thereby improving the problem of the large space occupied by the external connection structure 105.

[0068] refer to Figure 6In some embodiments, the bottom surface of the CPU connector 106 facing the first surface is electrically connected to the CPU 102, and the top surface of the CPU connector 106 away from the first surface is electrically connected to the external connection structure 105. In this way, the height of the external connection structure 105 is higher than the height of the CPU connector 106, which can minimize the height difference between the external connection structure 105 and the compressed additional memory module 103. Since the two ends of the external connection structure 105 are electrically connected to the CPU connector 106 and the compressed additional memory module 103 respectively, reducing the height difference between the external connection structure 105 and the compressed additional memory module 103 can make the height difference between the two ends of the external connection structure 105 smaller, or even zero, so that the external connection structure 105 can be placed horizontally or nearly horizontally, and the horizontal placement referred to here is parallel to the first surface. Compared with the external connection structure 105 being placed obliquely relative to the first surface, the external connection structure 105 is placed horizontally. On the one hand, it is beneficial to maintain the stability of the external connection structure 105. On the other hand, it makes the space occupied by the external connection structure 105 smaller, which can provide more space for the arrangement of other components on the surface of the mainboard 101, which is beneficial to the arrangement of wiring.

[0069] In some embodiments, the height of the central processing connector relative to the mainboard 101 is the same as the height of the compressed additional memory module 103 relative to the mainboard 101. In other words, the height of the surface of the central processing connector 106 away from the mainboard 101 relative to the first surface is the same as the height of the surface of the compressed additional memory module 103 relative to the mainboard 101 relative to the first surface. In this way, the two ends of the external connection structure 105 electrically connecting the central processing connector 106 and the compressed additional memory module 103 are close to each other in height relative to the first surface, so that the height difference between the two ends of the external connection structure 105 is small, or even zero. In this way, the external connection structure 105 can be arranged roughly parallel to the first surface, so that the space occupied by the external connection structure 105 on one side of the first surface is small.

[0070] In some embodiments, the height of the CPU connector 106 relative to the motherboard 101 is the same as the height of the compressed additional memory module 103 relative to the motherboard 101. It may also be that the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface is the same as the height of the surface of the compressed additional memory module 103 facing the motherboard 101 relative to the first surface.

[0071] In some embodiments, the height of the surface of the CPU connector 106 away from the motherboard 101 compared to the first surface may be different from the height of the surface of the compression additional memory module 103 away from the motherboard 101 compared to the first surface. For example, the height of the surface of the CPU connector 106 away from the motherboard 101 compared to the first surface may be slightly higher than the height of the surface of the compression additional memory module 103 away from the motherboard 101 compared to the first surface. Alternatively, the height of the surface of the CPU connector 106 away from the motherboard 101 compared to the first surface may be slightly lower than the height of the surface of the compression additional memory module 103 away from the motherboard 101 compared to the first surface.

[0072] refer to Figure 7 In some embodiments, the motherboard 101 is configured as follows: the CPU connector 106 is electrically connected to the CPU 102, and the CPU 102 is electrically connected to the motherboard 101 through a gold finger or a ball grid array; the CPU connector 106 is electrically connected to the external connection structure 105 through any one of a ball grid array, a press-type connector or a silicon interposer.

[0073] In some embodiments, the first surface is provided with a gold finger or a ball grid array, and the first surface is also provided with a first pin 21, and the first pin 21 is used to electrically connect the central processing unit 102 and the mainboard 101. The mainboard 101 is also provided with a first lead 20, and the first lead 20 is used to lead the signal of the first pin 21 to the gold finger or the ball grid array on the first surface, and further lead it to the central processing unit connector 106 through the gold finger or the ball grid array. In a specific example, the material of the first lead 20 can be a metal material, for example, it can be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.

[0074] In some embodiments, the surface of the CPU connector 106 is provided with a ball grid array, a press-type connector or a silicon interposer, and the CPU 102 is provided with a connection structure inside, which is used to transmit the signal of the CPU 102 to the ball grid array or the press-type connector located on the surface of the CPU connector 106, and then transmit it to the external connection structure 105 via the ball grid array or the press-type connector.

[0075] In some embodiments, a silicon interposer is disposed on the surface of the CPU connector 106, and the silicon interposer includes a through silicon via, which penetrates the silicon interposer along the thickness direction of the silicon interposer. The bottom end of the through silicon via is electrically contacted with the connection structure in the CPU connector 106, and the top end of the through silicon via is electrically connected to the external connection structure 105.

[0076] In some embodiments, the connection structure may be a second lead. The embodiment of the present disclosure does not limit the specific routing method and shape of the second lead in the CPU connector 106. It is only necessary that the second lead can lead the signal from the CPU 102 to any one of the ball grid array, the press-type connector or the silicon interposer located on the surface of the CPU connector 106. The material of the second lead may be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.

[0077] refer to Figure 6 as well as Figure 7 In some embodiments, the signal processing device further includes: a first adapter 107, located between the mainboard 101 and the compressed additional memory module 103, for electrically connecting the mainboard 101 and the compressed additional memory module 103, and the first adapter 107 is also used to electrically connect the external connection structure 105 and the compressed additional memory module 103. In other words, the external connection structure 105 and the mainboard 101 share the same first adapter 107, so that space can be saved.

[0078] In some embodiments, the external connection structure 105 and the mainboard 101 share the same first adapter 107, and the mainboard 101 has a plurality of signal lines 10, each of which is electrically connected to the central processing unit 102 and the compressed additional memory module 103. The signal lines 10 in the mainboard 101 are electrically connected to the first adapter 107, and the external connection structure 105 is electrically connected to the first adapter 107, and both the signal lines 10 and the external connection structure 105 can realize signal transmission between the central processing unit 102 and the chip 104.

[0079] Continue to refer Figure 6 as well as Figure 7 In some embodiments, the external connection structure is in electrical contact with the surface of the first adapter 107 facing the compression additional memory module 103. In a specific example, the signal line 10 is electrically connected to the surface of the first adapter 107 facing the motherboard 101, and the external connection structure 105 is electrically connected to the surface of the first adapter 107 facing the compression additional memory module 103. In other words, the external connection structure 105 and the signal line 10 are respectively located on two opposite surfaces of the first adapter 107, avoiding the signal crosstalk problem between the external connection structure 105 and the signal line 10 due to the external connection structure 105 and the signal line 10 being located on the same surface of the first adapter 107.

[0080] The side of the first adapter 107 facing the compression additional memory module 103 is also electrically connected to the compression additional memory module 103 , so that the signals transmitted in the external connection structure 105 and the signal line 10 can be transmitted to the compression additional memory module 103 .

[0081] In some embodiments, the compressed additional memory module 103 has: a first routing line 41, the first routing line 41 is used to electrically connect the first connecting line and the chip 104, and the first routing line 41 is also used to electrically connect the first adapter 107, that is, the first adapter 107 is electrically connected to the first routing line 41 on the side facing the compressed additional memory module 103, and the first routing line 41 is used to transmit the transmission signal from the first adapter 107 and transmit it to the chip 104, or the signal in the chip 104 can be transmitted to the first adapter 107 through the first routing line 41.

[0082] In some embodiments, the first adapter 107 may be a silicon interposer or a z-axis compression connector. In some embodiments, the external connection structure 105 may be a flexible circuit board.

[0083] In some embodiments, the first adapter 107 is a first silicon interposer, and the first silicon interposer includes a first through silicon via 111, the first through silicon via 111 penetrates the first silicon interposer along the thickness direction of the first silicon interposer, the first silicon interposer exposes the top and bottom ends of the first through silicon via 111, the signal line 10 is electrically connected to the first through silicon via 111 toward the bottom end of the mainboard 101, and the first through silicon via 111 is electrically connected to the first trace 41 away from the top end of the mainboard 101.

[0084] In some embodiments, the surface of the first silicon interposer away from the mainboard may further include: a third pin 31, the third pin 31 is electrically in contact with the top of the first through silicon via 111, and the side of the external connection structure 105 facing the first silicon interposer is electrically connected to the third pin 31. Since the third pin 31 is electrically in contact with the top of the first through silicon via 111, and the bottom of the first through silicon via 111 is electrically connected to the signal line 10, the external connection structure 105 and the signal line can also be electrically connected. In this way, the signal transmitted in the signal line can also be transmitted to the compressed additional memory module 103 via the external connection structure 105. The remaining third pin 31 is in electrical contact with the compressed additional memory module 103, and is used to input the signal transmitted in the signal line in the mainboard into the compressed additional memory module 103.

[0085] In some embodiments, the third pin 31 can be any one of a gold finger or a ball grid array, the electrical connection structure can be a conductive metal wire, and the material of the electrical connection structure can be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.

[0086] The flexible circuit board is a highly reliable and highly flexible printed circuit board made of polyimide or polyester film as a substrate, and has the characteristics of high wiring density, light weight, thin thickness, and good bendability. Using a flexible circuit board as the external connection structure 105 can prevent the problem of failure of the external connection structure 105 caused by bending the external connection structure 105 during the packaging step. In addition, the thickness of the flexible circuit board is relatively thin, which prevents the external connection structure 105 from occupying too much space, making the overall thickness of the signal processing device relatively small. It is conducive to miniaturization of the device and to enhancing the overall heat dissipation capacity of the signal processing device.

[0087] refer to Figures 8 to 10 In some embodiments, the mainboard 101 and the external connection structure 105 may not share the same first adapter 107, and the signal processing device includes: a first adapter 107, located between the mainboard 101 and the compressed additional memory module 103, and used to electrically connect the mainboard 101 and the compressed additional memory module 103; a second adapter 108, located on a side of the compressed additional memory module 103 away from the mainboard 101, and the second adapter 108 electrically connects the external connection structure 105 and the compressed additional memory module 103.

[0088] That is to say, the first adapter 107 and the second adapter 108 are respectively located on opposite sides of the compressed additional memory module 103, the first adapter 107 is only electrically connected to the signal line 10, and the second adapter 108 is only electrically connected to the external connection structure 105, so that the wiring density of the wiring used for signal transmission in the first adapter 107 and the second adapter 108 is relatively small, which can avoid the problem of signal crosstalk caused by excessive wiring density in the first adapter 107 and the second adapter 108.

[0089] In some embodiments, the signal line 10 in the mainboard 101 is electrically connected to a side of the first adapter 107 facing the mainboard 101, and a side of the first adapter 107 away from the mainboard 101 is electrically connected to the compression additional memory module 103. The external connection structure 105 is electrically connected to a side of the second adapter 108 away from the compression additional memory module 103, and a side of the second adapter 108 facing the compression additional memory module 103 is electrically connected to the compression additional memory module 103.

[0090] That is to say, in the first adapter 107, the side that is closer to the compressed additional memory module 103 is electrically connected to the compressed additional memory module 103, and in the second adapter 108, the side that is closer to the compressed additional memory module 103 is electrically connected to the compressed additional memory module 103. In this way, the wiring distance between the first adapter 107 and the compressed additional memory module 103 can be reduced, as well as the wiring distance between the second adapter 108 and the compressed additional memory module 103, which is beneficial to saving wiring length.

[0091] In some embodiments, the first adapter 107 is a first silicon interposer, the first silicon interposer includes a first through silicon via 111, the first through silicon via 111 penetrates the first silicon interposer along the thickness direction of the first silicon interposer, the first silicon interposer exposes the top and bottom of the first through silicon via 111, the signal line 10 is electrically connected to the bottom of the first through silicon via 111 facing the mainboard 101, and the top of the first through silicon via 111 away from the mainboard 101 is electrically connected to the compression additional memory module 103. The second adapter 108 is a second silicon interposer, the second silicon interposer includes a second through silicon via 112, the second through silicon via 112 penetrates the second silicon interposer along the thickness direction of the second silicon interposer, and the second silicon interposer exposes the top and bottom of the second through silicon via 112. The bottom of the second through silicon via 112 is directly opposite to the surface of the compression additional memory module 103 away from the mainboard 101, and is electrically connected to the side of the compression additional memory module 103 away from the mainboard 101. The external connection structure 105 is electrically connected to the top of the second through silicon via 112.

[0092] In some embodiments, the information processing device includes a first adapter 107 and a second adapter 108, and the compressed additional memory module 103 has: a first routing line 41, the first routing line 41 is used to electrically connect the first connecting line and the chip 104, and the first routing line 41 is also used to electrically connect the first adapter 107; a second routing line 42, the second routing line 42 is used to electrically connect the external connection structure 105 and the chip 104, and the second routing line 42 is also used to electrically connect the second adapter 108.

[0093] In some embodiments, the compressed additional memory module 103 includes a third surface and a fourth surface opposite to each other, the fourth surface is directly opposite to the first surface, and the first trace 41 and the second trace 42 are arranged at intervals in a direction parallel to the third surface. In other words, the second trace 42 and the first trace 41 are arranged horizontally, so that the second trace 42 and the first trace 41 do not occupy the space in the thickness direction of the compressed additional memory module 103. Compared with the second trace 42 and the first trace 41 being arranged at intervals in the thickness direction of the compressed additional memory module 103, the second trace 42 and the first trace 41 are arranged at intervals in a direction parallel to the third surface, which greatly reduces the thickness of the compressed additional memory module 103.

[0094] In some embodiments, the top of the first through silicon via 111 is electrically connected to the first routing line 41, and the bottom of the second through silicon via 112 is electrically connected to the second routing line 42, wherein the top of the first through silicon via 111 faces the third surface, and the bottom of the second through silicon via 112 faces the fourth surface.

[0095] refer to Figure 8In some embodiments, the compressed additional memory module has a plurality of chips 104 on one of the surfaces along a direction perpendicular to the first surface. In some embodiments, the compressed additional memory module 103 includes a third surface and a fourth surface opposite to the first surface, and the third surface is directly opposite to the first surface. The plurality of chips 104 may be located only on the third surface or only on the fourth surface. Each chip 104 may be electrically connected to either the external connection structure 105 or the signal line 10, that is, the central processing unit 102 may read and write data to a chip 104 through either the external connection structure 105 or the signal line 10.

[0096] refer to Fig. 9 In some embodiments, the CAM 103 has multiple chips 104 on two opposite surfaces along a direction perpendicular to the first surface. In other words, the third surface and the fourth surface both have multiple chips 104, so that the integration of the chips 104 can be improved.

[0097] refer to Fig. 9 In some embodiments, the signal processing device includes: a first adapter 107 and a second adapter 108, the first adapter 107 is located on one side of the third surface, the second adapter 108 is located on one side of the fourth surface, the external connection structure 105 is electrically connected to the second adapter 108, and the signal line 10 is electrically connected to the first adapter 107. Then the second adapter 108 can be electrically connected to the chip 104 on the fourth surface, that is, the central processing unit 102 reads and writes data to the chip 104 on the fourth surface through the external connection structure 105. The first adapter 107 can be electrically connected to the chip 104 on the third surface, and the central processing unit 102 can read and write data to the chip 104 on the third surface through the signal line 10 in the motherboard 101. In this way, the wiring length can be saved and the wiring can be simplified.

[0098] refer to Figure 8 In some embodiments, each of the plurality of chips 104 located on the third surface may also be electrically connected to the external connection structure 105 or the signal line 10. Each of the plurality of chips 104 located on the fourth surface may also be electrically connected to the external connection structure 105 or the signal line 10.

[0099] refer to Fig.11In some embodiments, the number of the compressed additional memory modules is two, the two compressed additional memory modules 103 are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules 103 are electrically connected to the central processing unit 102 through the same external connection structure 105. At least one surface of each of the two compressed additional memory modules 103 has a plurality of chips 104, and through the same external connection structure 105, the central processing unit 102 can read and write data to the chip 104 located on the surface of any compressed additional memory module 103. While ensuring that the number of external connection structures 105 does not increase, the number of chips 104 electrically connected to the central processing unit 102 is increased, thereby improving the integration of the chips 104.

[0100] Since the external connection structure 105 is arranged outside the mainboard 101, the number of signal lines 10 in the mainboard 101 can be reduced, or even the arrangement of the signal lines 10 in the mainboard 101 can be omitted. Thus, while improving the integration of the chip 104, the heat dissipation capacity of the mainboard 101 can be enhanced, which is beneficial to ensuring the excellent performance of the mainboard 101 and ensuring that the information processing device has a higher operating speed.

[0101] In some embodiments, the two compressed additional memory modules 103 are respectively recorded as: a first compressed additional memory module 121 and a second compressed additional memory module 122, the first compressed additional memory module 121 is adjacent to the first surface, and the second compressed additional memory module 122 is located on a side of the first compressed additional memory module 121 away from the motherboard 101.

[0102] The information processing device may include: a first adapter 107 and a second adapter 108. The first adapter 107 is located between the first compressed additional memory module 121 and the first surface, and is used to electrically connect the mainboard 101 and the first compressed additional memory module 121. The second adapter 108 is located between the first compressed additional memory module 121 and the second compressed additional memory module 122, and is used to electrically connect the external connection structure 105. The second adapter 108 is electrically connected to the first compressed additional memory module 121 and the second compressed additional memory module 122, and is used to transmit the signal in the external connection structure 105 to the first compressed additional memory module 121 and the second compressed additional memory module 122, respectively.

[0103] In a specific example, the first adapter 107 may be a first silicon interposer, the second adapter 108 may be a second silicon interposer, the first silicon interposer includes a first through silicon via 111, the first through silicon via 111 runs through the first silicon interposer, the top of the first through silicon via 111 is electrically connected to the first compressed additional memory module 121, and the bottom of the first through silicon via 111 is electrically connected to the mainboard 101. Specifically, the mainboard 101 may have a signal line 10, the signal line 10 is electrically connected to the central processing unit 102, and the bottom of the first through silicon via 111 may be electrically connected to the signal line 10.

[0104] The second silicon interposer includes a second through silicon via 112 , which penetrates the second silicon interposer, a top end of the second through silicon via 112 is electrically connected to the second compression additional memory module 122 , and a bottom end of the second through silicon via 112 is electrically connected to the first compression additional memory module 121 .

[0105] In some embodiments, the surface of the second silicon interposer may include: a fourth pin 32, the fourth pin 32 is located on either a surface of the second silicon interposer away from the mainboard 101 or a surface of the second silicon interposer facing the mainboard 101. The surface of the external connection structure 105 facing the second silicon interposer is in electrical contact with the third pin 31, so that the signal transmitted in the external connection structure 105 can be transmitted to the second silicon through via 112 through the third pin 31, and finally transmitted to the first compressed additional memory module 121 through the second silicon through via 112.

[0106] The second compressed additional memory module 122 may include a fifth pin 33 facing the surface of the second silicon interposer, and the fifth pin 33 is electrically contacted with the surface of the external connection structure facing the second compressed additional memory module 122, so that the signal transmitted in the external connection structure 105 can be transmitted to the second compressed additional memory module 122 through the fifth pin 33.

[0107] In some embodiments, the fourth pin 32 may be any one of a gold finger or a ball grid array, the electrical connection structure may be a conductive metal wire, and the material of the electrical connection structure may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art. In some embodiments, the fifth pin 33 may be any one of a gold finger or a ball grid array, the electrical connection structure may be a conductive metal wire, and the material of the electrical connection structure may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.

[0108] refer to Fig.12In some embodiments, the signal processing device further includes: a top pad 11, located on a surface of the compressed additional memory module 103 away from the mainboard 101, the top pad 11 having at least one mounting hole 13; a bottom pad 12, fixed to the first surface, the bottom pad 12 is located on a surface of the compressed additional memory module 103 facing the mainboard 101, the bottom pad 12 having at least one pin 14 corresponding to the mounting hole 13; a fastener 15, matching the pin 14, the fastener 15 is used to fix the pin 14 after the pin 14 passes through the mounting hole 13, so that the top pad 11 and the bottom pad 12 clamp and fix the compressed additional memory module 103.

[0109] In some embodiments, the top pad 11 may have two mounting holes 13, and the bottom pad 12 may also have two latches 14, each latch 14 corresponding to a mounting hole 13. The two mounting holes 13 are respectively located on opposite sides of the top pad 11, so that the mounting stability of the top pad and the bottom pad 12 can be improved.

[0110] In some embodiments, the top pad 11 may have more than two mounting holes 13, and the bottom pad 12 may have more than two latches 14; or the top pad 11 may have only one mounting hole 13, and the bottom pad 12 may have only one latch 14. It is only necessary to match the number of mounting holes 13 with the number of latches 14. The number of mounting holes 13 and latches 14 can be flexibly set according to different requirements.

[0111] In some embodiments, the latch 14 may be a wire screw sleeve, which is an internal thread fastener 15 having an internal thread on the inside. The fastener 15 may be any screw, which can be locked with the wire screw sleeve by being screwed into the inside of the wire screw sleeve, and then after the wire screw sleeve is inserted into the mounting hole 13, the wire screw sleeve is fixed in the mounting hole 13 to prevent the wire screw sleeve from slipping out of the mounting hole 13.

[0112] In some embodiments, the pin 14 may also be a bolt, and the fastener 15 may also be a nut. The side of the bolt has an external thread, and the inside of the nut has an internal thread that matches the external thread on the outside of the bolt. After the bolt is inserted into the mounting hole 13, the nut is screwed into the outer side of the bolt and locked with the bolt, thereby fixing the bolt in the mounting hole 13 to prevent the bolt from slipping out of the mounting hole 13, so that the top and bottom pads 12 can clamp and fix the compressed additional memory module 103 to prevent the compressed additional memory module 103 from moving.

[0113] In the information processing device provided in the above embodiment, an external connection structure 105 is arranged on one side of the first surface of the mainboard 101, and is used to electrically connect the compressed additional memory module 103 and the central processing unit 102. That is, the external connection structure 105 is routed from the outside of the mainboard 101, and is connected to the compressed additional memory module 103 and the central processing unit 102. In this way, the number of signal lines 10 in the mainboard 101 for electrically connecting the central processing unit 102 and the compressed additional memory module 103 can be reduced, and even the arrangement of the signal lines 10 in the mainboard 101 can be omitted, thereby greatly reducing the thickness of the mainboard 101, so that the heat dissipation path of the mainboard 101 is greatly reduced, which is conducive to enhancing the heat dissipation of the mainboard 101.

[0114] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. An information processing device, characterized in that: include: A mainboard having a first surface, wherein the first surface has a central processing unit electrically connected to the mainboard; A compression additional memory module is located on one side of the first surface, and at least one surface of the compression additional memory module has a plurality of chips; The external connection structure is located on one side of the first surface and is configured to electrically connect the compressed additional memory module and the central processing unit. The central processing unit is configured to read and write data to each of the chips at least via the external connection structure.

2. The information processing device according to claim 1, characterized in that The mainboard has a plurality of signal lines, each of which is electrically connected to the central processing unit and the compressed additional memory module, and the central processing unit is configured as follows: Data is read and written to each of the chips via the signal lines and the external connection structure.

3. The information processing device according to claim 1, characterized in that The external connection structure is located on a side of the compressed additional memory module facing the central processing unit.

4. The information processing device according to claim 3, characterized in that: The height of the compressed additional memory module compared to the mainboard is greater than the height of the central processing unit compared to the mainboard.

5. The information processing device according to claim 1, characterized in that Also includes: A central processing unit connector is located on the first surface, and a height of the central processing unit connector compared to the mainboard is greater than a height of the central processing unit compared to the mainboard.

6. The information processing device according to claim 5, characterized in that: The height of the CPU connector relative to the motherboard is the same as the height of the CCAM relative to the motherboard.

7. The information processing device according to claim 5, characterized in that The bottom surface of the CPU connector facing the first surface is electrically connected to the CPU, and the top surface of the CPU connector away from the first surface is electrically connected to the external connection structure.

8. The information processing device according to claim 6, characterized in that: The mainboard is configured to: electrically connect the central processing unit connector and the central processing unit, the central processing unit and the mainboard are electrically connected through a gold finger or a ball grid array; the central processing unit connector and the external connection structure are electrically connected through any one of a ball grid array, a press-type connector or a silicon interposer.

9. The information processing device according to claim 1, characterized in that: Also includes: The first adapter is located between the mainboard and the compression additional memory module and is used to electrically connect the mainboard and the compression additional memory module. The first adapter is also used to electrically connect the external connection structure and the compression additional memory module.

10. The information processing device according to claim 9, characterized in that: The external connection structure is in electrical contact with a surface of the first adapter on a side facing the CCMM.

11. The information processing device according to claim 1, characterized in that: Also includes: A first adapter, located between the mainboard and the compressed additional memory module, for electrically connecting the mainboard and the compressed additional memory module; The second adapter is located at a side of the compression additional memory module away from the mainboard, and the second adapter is electrically connected to the external connection structure and the compression additional memory module.

12. The information processing device according to claim 11, characterized in that: The number of the compressed additional memory modules is two, the two compressed additional memory modules are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules are electrically connected to the central processing unit through the same external connection structure.

13. The information processing device according to claim 9 or 11, characterized in that: The first adapter is a silicon interposer or a z-axis compression connector; the external connection structure is a flexible circuit board.

14. The information processing device according to claim 1, characterized in that: The compressed additional memory module has the multiple chips on one of its surfaces along a direction perpendicular to the first surface; or, the compressed additional memory module has the multiple chips on two opposite surfaces along a direction perpendicular to the first surface.

15. The information processing device according to claim 1, characterized in that: Also includes: A top pad, located on a surface of the compressed additional memory module away from the mainboard, the top pad having at least one mounting hole; A bottom pad fixed to the first surface, the bottom pad being located on a surface of the compressed additional memory module facing the mainboard, the bottom pad having at least one latch corresponding to the mounting hole; A fastener matches the latch and is used to fix the latch after the latch passes through the mounting hole, so that the top pad and the bottom pad clamp and fix the compressed additional memory module.

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