True random number generator and true random number generation method

Abstract

The present application provides a true random number generator and a true random number generation method, which relates to the field of chip design technology. The method outputs a current difference value through a first transistor and a second transistor, and adjusts the threshold voltage of the first transistor and the second transistor, wherein the first transistor and the second transistor are charge capture transistors, and the current difference value is used to control the output of the first output terminal and the second output terminal; outputs random data according to a first enable signal and the current difference value, and then performs chain processing on the random data to output a true random number. The method solves the mismatch problem of the true random number generator through a programmable charge capture transistor, eliminates the mismatch in the comparator in a non-volatile manner, and uses a post-processing circuit to further improve the randomness of the data and reduce the area and power consumption.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a true random number generator and a true random number generation method. Background Art

[0002] A true random number generator (TRNG) is a device that can generate unpredictable random number sequences. The true random number generator is that the number sequence it generates has true randomness, rather than a pseudo-random number generator that generates a seemingly random but actually predictable sequence through an algorithm.

[0003] Comparator-based true random number generators generate random numbers by capturing the unpredictability of physical processes, using the uncertainty of the comparator when processing two almost equal input signals. When the two input signals are very close, the output of the comparator may tend to be either 0 or 1 due to the slight asymmetry inherent in the circuit.

[0004] However, the comparator-based true random number generator requires a large area to eliminate the mismatch problem caused by process deviation. In addition, since the mismatch of the comparator cannot be eliminated with high precision, the output 0 / 1 ratio is difficult to reach the ideal 50%, so it is necessary to rely on complex post-processing circuits to correct the data, which not only increases the circuit area, but also reduces the randomness of the comparator output. Summary of the invention

[0005] The present application provides a true random number generator and a true random number generation method to solve the problem of increased circuit area and reduced randomness of comparator output.

[0006] In a first aspect, the present application provides a true random number generator, comprising:

[0007] A first entropy source, wherein the first entropy source is a comparison unit, the comparison unit is connected to a first enable signal, and the first enable signal is used to control a working state of the comparison unit;

[0008] The comparison unit includes: a first transistor, a second transistor, a first output terminal and a second output terminal;

[0009] The first transistor and the second transistor are charge trapping transistors, which are used to output a current difference value when a first voltage signal is input, and adjust the threshold voltages of the first transistor and the second transistor through a second voltage signal and a third voltage signal, the first voltage signal is used to turn on the first transistor and the second transistor, and the current difference value is used to control the output of the first output terminal and the second output terminal;

[0010] The first output terminal and the second output terminal are used to output random data according to the first enable signal and the current difference value;

[0011] An XOR chain processing unit is used to perform chain processing on the random data to output a true random number.

[0012] In some feasible embodiments, the comparison unit further includes a third transistor, a fourth transistor, a first input terminal, a second input terminal, a fifth transistor and a sixth transistor;

[0013] The gate of the first transistor is connected to the first input terminal, the source of the first transistor is connected to the drain of the fifth transistor, and the drain of the first transistor is connected to a positive feedback amplifier circuit;

[0014] The gate of the second transistor is connected to the second input terminal, the source of the second transistor is connected to the drain of the sixth transistor, and the drain of the second transistor is connected to the positive feedback amplifier circuit;

[0015] The gate of the third transistor is connected to the second voltage signal, the source of the third transistor is connected to the first voltage compensation terminal, the drain of the third transistor is connected to the first input terminal, and the third transistor is used to isolate interference between the first input terminal and the first voltage compensation terminal;

[0016] The gate of the fourth transistor is connected to the third voltage signal, the source of the fourth transistor is connected to the second voltage compensation terminal, the drain of the fourth transistor is connected to the second input terminal, and the fourth transistor is used to isolate the interference between the first input terminal and the first voltage compensation terminal;

[0017] The gate of the fifth transistor is connected to a fourth voltage signal, the gate of the sixth transistor is connected to a first enable signal, the sources of the fifth transistor and the sixth transistor are grounded, and the fourth voltage signal is an inverted signal of the first voltage signal.

[0018] In some feasible embodiments, the second voltage signal is connected to the first input terminal, and the third voltage signal is connected to the second input terminal;

[0019] The second voltage signal is used to increase the threshold voltage of the first transistor, and the third voltage signal is used to increase the threshold voltage of the second transistor.

[0020] In some feasible embodiments, the gate of the seventh transistor is connected to the first output terminal via the first output signal, the source of the seventh transistor is connected to the power supply, and the drain of the seventh transistor is connected to the drain of the eighth transistor;

[0021] The source of the eighth transistor is the drain of the first transistor, and the gate of the eighth transistor is connected to the first output terminal via the first output signal;

[0022] The gate of the ninth transistor is connected to the second output terminal via the second output signal, the source of the ninth transistor is connected to the power supply, and the drain of the ninth transistor is connected to the drain of the tenth transistor;

[0023] The source of the tenth transistor is the drain of the second transistor, and the gate of the tenth transistor is connected to the second output terminal via the second output signal.

[0024] In some feasible embodiments, the positive feedback amplifier circuit is connected to the second enable signal and the third enable signal;

[0025] When the second enable signal is at a high level, the seventh transistor and the eighth transistor are turned on to amplify the current difference of the first output signal;

[0026] When the third enable signal is at a high level, the ninth transistor and the tenth transistor are turned on to amplify the current difference of the second output signal.

[0027] In some feasible embodiments, the invention further comprises: a second entropy source, a third entropy source and a fourth entropy source, wherein the second entropy source, the third entropy source and the fourth entropy source have the same structure as the first entropy source;

[0028] The XOR chain processing unit comprises:

[0029] a first XOR gate connected to the first entropy source and the second entropy source, and configured to perform an XOR operation on the first entropy source and the second entropy source to output first combined data;

[0030] a second XOR gate connected to the third entropy source and the fourth entropy source, and configured to perform an XOR operation on the third entropy source and the fourth entropy source to output second combined data;

[0031] The third XOR gate is connected to the first XOR gate and the second XOR gate, and is used to perform an XOR operation on the first XOR gate and the second XOR gate to output a true random number.

[0032] In a second aspect, the present application provides a method for generating true random numbers, comprising:

[0033] Outputting a current difference value through a first transistor and a second transistor, and adjusting a threshold voltage of the first transistor and the second transistor, wherein the current difference value is used to control outputs of the first output terminal and the second output terminal;

[0034] outputting random data according to a first enable signal and a current difference value, wherein the first enable signal is used to control a working state of a comparison unit;

[0035] Chain processing is performed on the random data to output a true random number.

[0036] In some feasible embodiments, adjusting the threshold voltages of the first transistor and the second transistor includes:

[0037] Start the first enable signal and count the number of the second output terminal outputting the first value, wherein the second output terminal is used to output the first value and the second value;

[0038] calculating a probability of a first value and a second value based on the number of said first values;

[0039] If the probability of the first value or the second value is greater than or equal to a probability threshold, the voltage of the second voltage signal is adjusted to the first voltage, the voltage of the first voltage signal is adjusted to 0, the voltage of the fourth voltage signal is adjusted to the second voltage, and the voltage of the first input terminal and the second input terminal is adjusted from the third voltage to the fourth voltage to increase the threshold voltage of the first transistor and the second transistor, the first voltage is greater than the third voltage, the fourth voltage is greater than the first voltage, and the third voltage is greater than the second voltage.

[0040] In some feasible embodiments, the step of outputting random data according to the first enable signal and the current difference value includes:

[0041] Adjust the voltages of the current source and the second voltage signal, the third voltage signal, and the fourth voltage signal to 0, and adjust the voltage of the first voltage signal to a second voltage, so that the voltages of the first input terminal and the second input terminal are a compensation voltage, and the compensation voltage is a second voltage. When the second voltage is reached, the first transistor and the second transistor can be started;

[0042] amplifying the current difference value by a positive feedback amplifier circuit so that the voltage at the first output terminal is 0 and the voltage at the second output terminal is a high level;

[0043] The states of the first output signal and the second output signal are output to the first output terminal and the second output terminal to generate random data.

[0044] In some feasible embodiments, performing chain processing on the random data to output a true random number includes:

[0045] Obtaining first random data, second random data, third random data, and fourth random data, wherein the first random data is data output by a first entropy source, the second random data is data output by a second entropy source, the third random data is data output by a third entropy source, and the fourth random data is data output by a fourth entropy source;

[0046] When the first enable signal is at a high level, chain processing is performed on the first random data and the second random data to output first combined data, and chain processing is performed on the third random data and the fourth random data to output second combined data;

[0047] Chain processing is performed on the first combined data and the second combined data to output a true random number.

[0048] As can be seen from the above technical solutions, the present application provides a true random number generator and a true random number generation method, the method outputs a current difference value through a first transistor and a second transistor, and adjusts the threshold voltage of the first transistor and the second transistor, the first transistor and the second transistor are charge capture transistors, and the current difference value is used to control the output of the first output terminal and the second output terminal; outputs random data according to the first enable signal and the current difference value, and then performs chain processing on the random data to output a true random number. The method solves the mismatch problem caused by process deviation in the true random number generator through programmable charge capture transistors, avoids occupying a large area and complex post-processing circuits, and eliminates the mismatch in the comparator in a non-volatile manner, and uses post-processing circuits to further improve the randomness of the data and reduce area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 A circuit diagram of a comparison unit provided in an embodiment of the present application;

[0051] Figure 2 A circuit diagram of an XOR chain processing unit provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of a process for generating true random numbers according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0054] In the semiconductor manufacturing process, due to process deviations, even chips produced in the same batch may have different parameters of internal circuits (such as resistance, capacitance, transistor threshold voltage, etc.). This difference can cause comparator mismatch, which in turn affects the performance of TRNG. Comparator mismatch may cause deviations in the generated random number sequence, that is, an imbalance in the ratio of 0 and 1. This deviation will affect the randomness and statistical characteristics of the random number sequence, thereby reducing the reliability and security of TRNG.

[0055] Mismatch elimination schemes rely on specific circuit structures or algorithms, which may fail as environmental conditions (e.g., temperature, voltage) change. Therefore, these schemes need to be calibrated or updated regularly to ensure the stability and reliability of TRNG. This volatility increases the maintenance cost and usage complexity of TRNG.

[0056] In addition, due to process deviations and comparator mismatch, the ratio of 0 to 1 in the random number sequence generated by TRNG is often difficult to reach the ideal 50%. This deviation may be caused by factors such as inaccurate comparator threshold settings and instability of noise sources. The imbalance of the output 0 / 1 ratio will affect the randomness and statistical characteristics of the random number sequence, and thus affect the application effect of TRNG.

[0057] In summary, the comparator-based true random number generator must rely on complex post-processing circuits to correct data, which not only increases the circuit area but also reduces the randomness of the comparator output.

[0058] In order to solve the problem of increased circuit area and reduced randomness of comparator output, some embodiments of the present application provide a true random number generator, which uses a Strong Arm comparator as an entropy source, replaces its input pair of tubes with a CTT (Charge Trapping Transistor) pair of tubes, and programs the CTT pair of tubes to eliminate mismatches in a non-volatile manner. When the input signals are equal, due to the influence of noise, the output can reach a 50% 0 / 1 ratio. In order to further increase the entropy value of the output random data, four independent entropy sources are used, and the correlation in the data is eliminated through an XOR cascade post-processing circuit, so that a random data output with a high entropy value can be obtained.

[0059] The true random number generator includes a first entropy source (ES1). In the true random number generator, the entropy source is a physical process or environmental factor used to generate random numbers. Entropy represents uncertainty or a degree of confusion, and the entropy source is a source of uncertainty. In this embodiment, the first entropy source is a comparison unit, see Figure 1 , the comparison unit is a CTT-based comparator.

[0060] The comparison unit includes: a first transistor (CTT0), a second transistor (CTT1), a first output terminal (SAQB) and a second output terminal (SAQ).

[0061] The first transistor and the second transistor are charge trap transistors, which are CMOS-compatible NMOS devices, and whose threshold voltage (VTH) can be adjusted by applying a specific voltage.

[0062] By applying a positive pulse voltage to the gate, for example, a peak value of 2V, a frequency of 1kHz, a duty cycle of 50%, and a duration of 800ms, while connecting the drain to 0.9V, and the source and substrate to ground, the threshold voltage of CTT can be increased. Conversely, if a positive pulse voltage is applied to the substrate, for example, a square wave with a peak value of 2V, a frequency of 1kHz, and a duty cycle of 50%, and the drain is connected to VDD (power supply voltage), and the source and gate are grounded, the threshold voltage of CTT can be reduced, and the process is non-volatile.

[0063] The first output signal (OUTB) is output to SAQB through the buffer power supply to complete the output of the first random data, wherein SAQB is the signal after the OUTB signal passes through the buffer circuit. Similarly, the second output signal (OUT) is output to SAQ through the buffer power supply to complete the output of the second random data, wherein SAQ is the signal after the OUT signal passes through the buffer circuit.

[0064] The comparison unit is connected to the first enable signal (SAE1). When SAE1 is programmed, the voltage is 0V. When it works normally, it is a clock signal with a voltage of 0V to 0.9V. SAE1 is used to control the working state of the comparison unit. When SAE1 is activated (high level), the source path of CTT0 and CTT1 is opened, that is, CTT0 and CTT1 are turned on. This allows current to flow through CTT0 and CTT1, thereby generating a current difference of I0 and I1, completing the comparison process. Among them, I0 is the current at the drain end of CTT0, and I1 is the current at the drain end of CTT1.

[0065] When the first voltage signal (CH) is input, the first transistor and the second transistor output a current difference value and adjust the threshold voltage of the first transistor and the second transistor. When CH is programmed, the voltage is 0V, and when it is working normally, it is 0.9V. CH controls the input voltage of the comparator. The current difference value reflects the difference in the input signal, thereby determining the logical state of the output signal, that is, the current difference value is used to control the state switching of the first output terminal and the second output terminal, thereby controlling the output.

[0066] Due to the asymmetry in the manufacturing process, there may be a slight voltage mismatch between the two inputs of the comparator, resulting in a non-zero output when the input signal is indistinguishable. Using the adjustable threshold feature of CTT, the threshold voltage of the transistor can be precisely adjusted by programming different amounts of charge, minimizing the mismatch at the input and achieving the purpose of correction.

[0067] During the non-volatile offset calibration phase, CH and CHB (the fourth voltage signal) together control the state of the input voltage. During the offset calibration process, CH is set to a specific voltage value, for example, 0.9V, to ensure that the circuit enters a known state and adjusts the thresholds of CTT0 and CTT1. Among them, CHB is the inverted signal of the CH signal, that is, when CH is high, CHB is low; when CH is low, CHB is high.

[0068] HV_CHB1 and HV_CHB2 are the second and third voltage signals. When programming, the voltage is 1.8V, and when working normally, the voltage is 0V. VCOMP is the common mode voltage, which is the voltage value when the voltage difference between all input or output terminals is equal in a multi-port electronic device or system. VCOMP is used for the positive and negative terminals of the comparator.

[0069] In some embodiments, the second voltage signal is connected to the first input terminal, the third voltage signal is connected to the second input terminal, the second voltage signal is used to increase the threshold voltage of the first transistor, and the third voltage signal is used to increase the threshold voltage of the second transistor. In the offset calibration stage, the voltages of HV_CHB1 and HV_CHB2 eliminate the offset voltage by adjusting the thresholds of CTT0 and CTT1. When HV_CHB1 and HV_CHB2 are set to specific voltages, the circuit will enter different operating modes, such as programming, erasing or normal operation.

[0070] In the normal working mode of the comparator, the input voltages of the first input terminal and the second input terminal are both VCOMP (common mode voltage). The first output terminal or the second output terminal will be biased towards a high level or a low level due to the influence of the offset voltage. To correct the deviation, the number of high levels or low levels is used. If the number exceeds the range, the voltages of the first input terminal and the second input terminal are adjusted through the second voltage signal and the third voltage signal, thereby adjusting the threshold voltages of the first transistor and the second transistor to achieve non-volatile offset voltage elimination.

[0071] In some embodiments, the comparison unit further includes a first input terminal (P1), a second input terminal (P2), a fifth transistor (M1) and a sixth transistor (M2). The gate of the first transistor is connected to the first input terminal, the source of the first transistor is connected to the drain of the fifth transistor, and the drain of the first transistor is connected to a positive feedback amplifier circuit. The first output terminal and the second output terminal are used to output random data according to the first enable signal and the current difference value.

[0072] In order to isolate the interference between the first input terminal and the first voltage compensation terminal and the interference between the first input terminal and the first voltage compensation terminal, the comparison unit also includes a third transistor (M3), a fourth transistor (M4), and the third transistor and the fourth transistor are 1.8V thick oxide layer I / O (input / output) transistors, powered by a 1.8V power supply, and transistors with thick oxide layers, the oxide layer is a component of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor), located between the metal gate and the semiconductor. The thick oxide layer can provide better insulation effect, prevent breakdown, and also increase the voltage resistance of the transistor. Transistors with thick oxide layers are used to improve voltage resistance, reduce leakage current, and enhance stability.

[0073] The gate of the second transistor is connected to the second input terminal, the source of the second transistor is connected to the drain of the sixth transistor, and the drain of the second transistor is connected to the positive feedback amplifier circuit; the gate of the third transistor is connected to the second voltage signal, the source of the third transistor is connected to the first voltage compensation terminal (VCOMP1), and the drain of the third transistor is connected to the first input terminal, and the third transistor is used to isolate the interference between the first input terminal and the first voltage compensation terminal.

[0074] The gate of the fourth transistor is connected to the third voltage signal, the source of the fourth transistor is connected to the second voltage compensation terminal (VCOMP2), the drain of the fourth transistor is connected to the second input terminal of the second transistor, the fourth transistor is used to isolate the interference between the first input terminal and the first voltage compensation terminal, the second voltage signal and the third voltage signal are used to adjust the voltage during programming; the gate of the fifth transistor is connected to the fourth voltage signal, the gate of the sixth transistor is connected to the first enable signal, and the sources of the fifth transistor and the sixth transistor are grounded.

[0075] Among them, after the comparison results come out, the M5 to M8 transistors will latch the results, and M5-M8 are 0.9V core tubes, and the 0.9V core tubes are transistors with an operating voltage of 0.9 volts.

[0076] Introducing positive feedback in a comparator can increase switching speed. When the input signal approaches the critical voltage of the comparator, positive feedback can quickly push up or pull down the output, allowing the circuit to reach a stable state faster. Positive feedback can also introduce hysteresis, that is, when the input signal fluctuates within a certain range, it will not immediately cause the output to change. This feature can make the comparator insensitive to noise in the input signal, thereby avoiding false triggering.

[0077] In some embodiments, the positive feedback amplifier circuit includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the gate of the seventh transistor is connected to the first output terminal via the first output signal, the source of the seventh transistor is connected to the power supply, and the drain of the seventh transistor is connected to the drain of the eighth transistor; the source of the eighth transistor is the drain of the first transistor, and the gate of the eighth transistor is connected to the first output terminal via the first output signal.

[0078] The gate of the ninth transistor is connected to the second output terminal via the second output signal, the source of the ninth transistor is connected to the power supply, and the drain of the ninth transistor is connected to the drain of the tenth transistor; the source of the tenth transistor is the drain of the second transistor, and the gate of the tenth transistor is connected to the second output terminal via the second output signal.

[0079] The purpose of the positive feedback mechanism is to amplify the change of the signal by returning part of the output signal to the input. In the comparator circuit, positive feedback is used to quickly amplify the small difference at the input end to determine the final output result. SAE2 and SAE3 form the positive feedback loop of the output stage with transistors M5, M6, M7, and M8. SAE2 and SAE3 are used to enable the positive feedback mechanism when the comparator is working normally, so that the small current difference can be amplified through feedback, thereby determining the output results of OUT and OUTB. During the comparison process, ensure that the current difference is amplified through the feedback mechanism of M5-M8 to quickly obtain the comparison result.

[0080] In some embodiments, the positive feedback amplifier circuit is connected to a second enable signal and a third enable signal; when the second enable signal is at a high level, the seventh transistor and the eighth transistor are turned on to amplify the current difference of the first output signal; when the third enable signal is at a high level, the ninth transistor and the tenth transistor are turned on to amplify the current difference of the second output signal.

[0081] When SAE2 and SAE3 are high, M5 and M6, M7 and M8 are turned on, allowing the feedback current to pass, further amplifying the differential signal, so that the OUT and OUTB signals reach a stable state. This positive feedback can speed up the response speed of the comparator circuit and ensure that a quick judgment can be made even when the difference between I0 and I1 is small.

[0082] like Figure 2As shown, in some embodiments, the true random number generator further includes: a second entropy source (ES2), a third entropy source (ES3) and a fourth entropy source (ES4), and the second entropy source, the third entropy source and the fourth entropy source have the same structure as the first entropy source.

[0083] The true random number generator also includes: an XOR chain processing unit, which is used to perform chain processing on random data to output a true random number.

[0084] The XOR chain processing unit includes: a first XOR gate (XOR1), a second XOR gate (XOR2) and a third XOR gate (XOR3); the first XOR gate is connected to the first entropy source and the second entropy source, and is used to perform an XOR operation on the first entropy source and the second entropy source to output first combination data; the second XOR gate is connected to the third entropy source and the fourth entropy source, and is used to perform an XOR operation on the third entropy source and the fourth entropy source to output second combination data; the third XOR gate is connected to the first XOR gate and the second XOR gate, and is used to perform an XOR operation on the first XOR gate and the second XOR gate to output a true random number.

[0085] The outputs of ES1 and ES2 are combined in XOR1. The XOR operation is used in cryptography and random number generation applications because if either input is random, the output of the XOR gate is random. Similarly, the outputs of ES3 and ES4 are combined in XOR2. The outputs of XOR1 and XOR2 are combined in XOR3 to produce the final output (XOR-OUT). The XOR-OUT signal is the result of processing the four entropy sources through an XOR chain. The XOR operation helps reduce the dependency or correlation between the entropy sources, thereby increasing the overall entropy of the random data output, which ensures that the random number generator produces high-quality, entropy-enhanced random data.

[0086] Based on the above-mentioned true random number generator, some embodiments of the present application also provide a true random number generation method. It can be understood that this embodiment and the above-mentioned embodiment can refer to each other, and the content described in the above-mentioned embodiment will not be repeated in this embodiment.

[0087] like Figure 3 As shown, the method includes:

[0088] S100: Outputting a current difference value through a first transistor and a second transistor, and adjusting threshold voltages of the first transistor and the second transistor.

[0089] To adjust the threshold voltages of the first transistor and the second transistor, in some embodiments, the first enable signal is started, the number of outputs of the first value in the second output terminal is counted, and the second output terminal is used to output the first value and the second value;

[0090] calculating the probability of the first value and the second value based on the number of the first value;

[0091] If the probability of the first value or the second value is greater than or equal to the probability threshold, the voltage of the second voltage signal is adjusted to the first voltage, the voltage of the first voltage signal is adjusted to 0, the voltage of the fourth voltage signal is adjusted to the second voltage, and the voltage of the first input terminal and the second input terminal is adjusted from the third voltage to the fourth voltage to increase the threshold voltage of the first transistor and the second transistor.

[0092] The first value is 1, indicating a high level, and the second value is 0, indicating a low level. The first voltage is greater than the third voltage, the fourth voltage is greater than the first voltage, the third voltage is greater than the second voltage, the first voltage is 1.8V, the second voltage is 0.9V, the third voltage is 1.7V, and the fourth voltage is 2.0V.

[0093] Exemplarily, under the condition that CH is 0.9V, CHB is 0V, HV_CHB1, and HV_CHB2 are 0V, the input voltages of P1 and P2 are both VCOMP. Therefore, through the SAE1 signal, the output of SAQ will be biased towards '0' or '1' due to the influence of the offset voltage. To correct this deviation, the number of '1' in the SAQ output is counted through the SAE1 signal 1 million times. If the probability of '1' or '0' exceeds the target range, the HV_CHB1, HV_CHB2, CHB, and CH signals are adjusted to 1.8V, 1.8V, 0.9V, and 0V, respectively. In addition, when the probability of '1' ('0') exceeds the target range, the voltages of P1 and P2 are gradually increased from 1.7V to 2.0V to increase the threshold voltage (VTH) of CTT0 (CTT1) to achieve non-volatile offset voltage elimination.

[0094] S200: Outputting random data according to the first enable signal and the current difference value.

[0095] When SAE1 is at a low level, the first output signal and the second output signal are pulled up to the power supply voltage to reset the comparison unit. OUTB and OUT terminals are charged to VDD at the same time, and the SAQ and SAQB signal outputs are both 0, thus completing the reset.

[0096] When SAE1 is at a high level, the voltages of the current source and the second voltage signal, the third voltage signal and the fourth voltage signal are adjusted to 0, and the voltage of the first voltage signal is adjusted to the second voltage, so that the voltages of the first input terminal and the second input terminal are the compensation voltage, and the compensation voltage is the second voltage. When the voltage is the second voltage, the first transistor and the second transistor can be started;

[0097] amplifying the current difference value through a positive feedback amplifier circuit so that the voltage at the first output terminal is 0 and the voltage at the second output terminal is a high level;

[0098] The states of the first output signal and the second output signal are output to the first output terminal and the second output terminal to generate random data.

[0099] Exemplarily, after completing the non-volatile offset voltage calibration, the HV_CHB1, HV_CHB2, CHB and CH signals are set to 0V, 0V, 0V and 0.9V respectively. At this time, the VCOMP voltage can be transmitted to the P1 and P2 terminals at the same time, so that the voltages of P1 and P2 are both VCOMP. In this case, VCOMP is 0.9V, and CTT0 and CTT1 can be turned on at the same time.

[0100] When the SAE signal is 1, the gate voltage of CTT0 and CTT1 is 0.9V, so both are turned on. Since the offset voltage has been calibrated, the currents of I0 and I1 are consistent, but in reality, due to white noise interference, there will be a slight difference in the currents of I0 and I1. This difference generates positive feedback through the M5-M8 circuit until one end of OUT or OUTB becomes 0V.

[0101] For example, if the noise causes the current of I0 to be greater than I1, the voltage of OUTB drops faster than OUT. As the voltage of OUTB drops, the M7 transistor gradually turns on, further charging the OUT terminal, causing the OUT voltage to start to rise, while M8 gradually turns off, causing the current of I1 to drop. At the same time, the rise in OUT voltage causes M6 to turn on, further increasing the current of I0, and eventually causing the OUTB voltage to drop to 0V, while the OUT voltage remains at VDD. Finally, OUT and OUTB are output to SAQ and SAQB through the buffer unit, completing the output of one data.

[0102] S300: Perform chain processing on random data to output true random numbers.

[0103] After completing the non-volatile offset voltage elimination, the CTT-based comparator can be used as an entropy source for a true random number generator. To further increase the entropy value of the output random data, four independent entropy sources are used, and the correlation between the data is eliminated through an XOR chain post-processing circuit, thereby generating a high-entropy random data output.

[0104] In some embodiments, chain processing is performed on random data to output a true random number, including:

[0105] Obtaining first random data, second random data, third random data, and fourth random data;

[0106] When the first enable signal is at a low level, the true random number comparator is in a reset stage, and the outputs of all entropy sources are 0, so the output is 0 to complete the reset.

[0107] When the first enable signal is at a high level, the first random data and the second random data are combined to output first combined data, and the third random data and the fourth random data are combined to output second combined data, and then the first combined data and the second combined data are combined to output a true random number.

[0108] The first random data is the data output by the first entropy source, the second random data is the data output by the second entropy source, the third random data is the data output by the third entropy source, and the fourth random data is the data output by the fourth entropy source. When the SAE1 signal is 1, the entropy source (ES1-ES4) will output random data due to the interference of white noise. The outputs of ES1 and ES2 are input to one port of XOR3 through the XOR1 circuit, while the outputs of ES3 and ES4 are input to another port of XOR3 through the XOR2 circuit. The output result XOR-OUT of XOR3 is the random data after the four independent entropy sources pass through the XOR chain post-processing circuit. This processing process can eliminate the possible correlation in each entropy source, further improving the randomness of the data.

[0109] Since the offset voltage of the CTT-based comparator varies at different voltages and temperatures, offset voltage cancellation must be performed when the true random number generator operates under different voltage or temperature conditions. The offset cancellation method is the same as described above. Based on this design, the true random number generator is highly robust to process, temperature, and voltage. In addition, since the programming and erasing of CTT are non-volatile, no additional calibration circuit is required, further reducing area overhead. By accurately eliminating the mismatch of the comparator and using a simple and efficient post-processing circuit, the randomness of the data is further improved while reducing area and power consumption.

[0110] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A true random number generator, characterized in that: include: A first entropy source, wherein the first entropy source is a comparison unit, the comparison unit is connected to a first enable signal, and the first enable signal is used to control a working state of the comparison unit; The comparison unit includes: a first transistor, a second transistor, a first output terminal and a second output terminal; The first transistor and the second transistor are charge trapping transistors, which are used to output a current difference value when a first voltage signal is input, and adjust the threshold voltages of the first transistor and the second transistor through a second voltage signal and a third voltage signal, the first voltage signal is used to turn on the first transistor and the second transistor, and the current difference value is used to control the output of the first output terminal and the second output terminal; The first output terminal and the second output terminal are used to output random data according to the first enable signal and the current difference value; An XOR chain processing unit is used to perform chain processing on the random data to output a true random number.

2. The true random number generator according to claim 1, characterized in that: The comparison unit further includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first input terminal and a second input terminal; The gate of the first transistor is connected to the first input terminal, the source of the first transistor is connected to the drain of the fifth transistor, and the drain of the first transistor is connected to a positive feedback amplifier circuit; The gate of the second transistor is connected to the second input terminal, the source of the second transistor is connected to the drain of the sixth transistor, and the drain of the second transistor is connected to the positive feedback amplifier circuit; The gate of the third transistor is connected to the second voltage signal, the source of the third transistor is connected to the first voltage compensation terminal, the drain of the third transistor is connected to the first input terminal, and the third transistor is used to isolate interference between the first input terminal and the first voltage compensation terminal; The gate of the fourth transistor is connected to the third voltage signal, the source of the fourth transistor is connected to the second voltage compensation terminal, the drain of the fourth transistor is connected to the second input terminal, and the fourth transistor is used to isolate the interference between the first input terminal and the first voltage compensation terminal; The gate of the fifth transistor is connected to a fourth voltage signal, the gate of the sixth transistor is connected to a first enable signal, the sources of the fifth transistor and the sixth transistor are grounded, and the fourth voltage signal is an inverted signal of the first voltage signal.

3. The true random number generator according to claim 2, characterized in that: The second voltage signal is connected to the first input terminal, and the third voltage signal is connected to the second input terminal; The second voltage signal is used to increase the threshold voltage of the first transistor, and the third voltage signal is used to increase the threshold voltage of the second transistor.

4. The true random number generator according to claim 2, characterized in that: The positive feedback amplifier circuit includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The gate of the seventh transistor is connected to the first output terminal via the first output signal, the source of the seventh transistor is connected to the power supply, and the drain of the seventh transistor is connected to the drain of the eighth transistor; The source of the eighth transistor is the drain of the first transistor, and the gate of the eighth transistor is connected to the first output terminal via the first output signal; The gate of the ninth transistor is connected to the second output terminal via the second output signal, the source of the ninth transistor is connected to the power supply, and the drain of the ninth transistor is connected to the drain of the tenth transistor; The source of the tenth transistor is the drain of the second transistor, and the gate of the tenth transistor is connected to the second output terminal via the second output signal.

5. The true random number generator according to claim 4, characterized in that: The positive feedback amplifier circuit is connected to the second enable signal and the third enable signal; When the second enable signal is at a high level, the seventh transistor and the eighth transistor are turned on to amplify the current difference of the first output signal; When the third enable signal is at a high level, the ninth transistor and the tenth transistor are turned on to amplify the current difference of the second output signal.

6. The true random number generator according to claim 1, characterized in that: Also includes: A second entropy source, a third entropy source and a fourth entropy source, wherein the second entropy source, the third entropy source and the fourth entropy source have the same structure as the first entropy source; The XOR chain processing unit comprises: a first XOR gate connected to the first entropy source and the second entropy source, and configured to perform an XOR operation on the first entropy source and the second entropy source to output first combined data; a second XOR gate connected to the third entropy source and the fourth entropy source, and configured to perform an XOR operation on the third entropy source and the fourth entropy source to output second combined data; The third XOR gate is connected to the first XOR gate and the second XOR gate, and is used to perform an XOR operation on the first XOR gate and the second XOR gate to output a true random number.

7. A method for generating true random numbers, characterized in that: include: Outputting a current difference value through a first transistor and a second transistor, and adjusting a threshold voltage of the first transistor and the second transistor, wherein the first transistor and the second transistor are charge trapping transistors, and the current difference value is used to control the output of a first output terminal and a second output terminal; outputting random data according to a first enable signal and a current difference value, wherein the first enable signal is used to control a working state of a comparison unit; Chain processing is performed on the random data to output a true random number.

8. The method for generating true random numbers according to claim 7, wherein: The adjusting the threshold voltages of the first transistor and the second transistor includes: Start the first enable signal and count the number of the second output terminal outputting the first value, wherein the second output terminal is used to output the first value and the second value; calculating a probability of a first value and a second value based on the number of said first values; If the probability of the first value or the second value is greater than or equal to a probability threshold, the voltage of the second voltage signal is adjusted to the first voltage, the voltage of the first voltage signal is adjusted to 0, the voltage of the fourth voltage signal is adjusted to the second voltage, and the voltage of the first input terminal and the second input terminal is adjusted from the third voltage to the fourth voltage to increase the threshold voltage of the first transistor and the second transistor, the first voltage is greater than the third voltage, the fourth voltage is greater than the first voltage, and the third voltage is greater than the second voltage.

9. The method for generating true random numbers according to claim 8, wherein: The step of outputting random data according to the first enable signal and the current difference value comprises: Adjust the voltages of the current source and the second voltage signal, the third voltage signal, and the fourth voltage signal to 0, and adjust the voltage of the first voltage signal to a second voltage, so that the voltages of the first input terminal and the second input terminal are a compensation voltage, and the compensation voltage is a second voltage. When the second voltage is reached, the first transistor and the second transistor can be started; amplifying the current difference value by a positive feedback amplifier circuit so that the voltage at the first output terminal is 0 and the voltage at the second output terminal is a high level; The states of the first output signal and the second output signal are output to the first output terminal and the second output terminal to generate random data.

10. The method for generating true random numbers according to claim 7, wherein: The performing chain processing on the random data to output a true random number comprises: Obtaining first random data, second random data, third random data, and fourth random data, wherein the first random data is data output by a first entropy source, the second random data is data output by a second entropy source, the third random data is data output by a third entropy source, and the fourth random data is data output by a fourth entropy source; When the first enable signal is at a high level, chain processing is performed on the first random data and the second random data to output first combined data, and chain processing is performed on the third random data and the fourth random data to output second combined data; Chain processing is performed on the first combined data and the second combined data to output a true random number.

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