Firmware upgrade effective method and device of PCIe device, storage medium and program product

Abstract

The invention provides a firmware upgrade effective method and equipment of PCIe equipment, a storage medium and a program product. The method comprises the steps that if a firmware updating instruction for target PCIe equipment is detected in the running process, an updating version identifier carried in the firmware updating instruction is acquired; based on the update version identifier, executing a firmware update program for the target PCIe device; after the firmware is successfully updated, removing a root port where the target PCIe device is located, and triggering to restart the target PCIe device; and responding to the restart of the target PCIe device, scanning and identifying all PCIe devices including the target PCIe device, and initializing all PCIe devices, which includes reallocating bus resources. The method is used for achieving the effect of upgrading and taking effect of firmware of PCIe equipment under the condition that a host end is not restarted.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, storage medium and program product for activating firmware upgrade of a PCIe device. Background Art

[0002] In modern computer systems, high-speed serial computer expansion bus standard Peripheral Component Interconnect Express (PCIe) devices are widely used due to their flexibility and scalability. With the development of technology and changes in functional requirements, it is often necessary to upgrade the firmware of PCIe devices.

[0003] However, traditional firmware upgrade methods usually require restarting the host, which will cause system interruption and affect the normal operation of the system and user experience. Especially in some critical business scenarios, restarting the host may cause great losses.

[0004] Therefore, it is of great significance to develop a solution that can implement the firmware upgrade of PCIe devices and make it effective without restarting the host side. Summary of the invention

[0005] The present application provides a method, device, storage medium and program product for activating firmware upgrade of a PCIe device, so as to achieve the effect of upgrading the firmware of the PCIe device and making it effective without restarting the host side.

[0006] In a first aspect, the present application provides a method for validating firmware update of a PCIe device, comprising:

[0007] If a firmware update instruction for the target PCIe device is detected during the operation, an update version identifier carried in the firmware update instruction is obtained;

[0008] Based on the update version identifier, executing a firmware update procedure for the target PCIe device;

[0009] After the firmware is successfully updated, the root port where the target PCIe device is located is removed, and the target PCIe device is triggered to restart;

[0010] In response to the target PCIe device restarting, all PCIe devices including the target PCIe device are scanned and identified, and all PCIe devices are initialized, wherein the initialization includes reallocating bus resources.

[0011] In a possible implementation, restarting the target PCIe device includes at least one of the following:

[0012] Restart the target PCIe device through the operating system and / or Complex Programmable Logic Device (CPLD);

[0013] Restart the target PCIe device by physically removing and reinserting it.

[0014] In a possible implementation, if physical removal and reinsertion of the target PCIe device is supported, before restarting the target PCIe device, perform the following operations:

[0015] Enable the hot-swap function of the PCIe device. The hot-swap function can be enabled when the BIOS initializes the PCIe device.

[0016] In a possible implementation, the firmware update validation method further includes, in order to successfully scan and identify all PCIe devices including the target PCIe device, the BIOS performs the following operations during the device initialization process:

[0017] The mapping relationship of the amount of bus resources required by the PCIe device firmware stored in the storage space is read, and bus resources are allocated to the PCIe device according to the mapping relationship, wherein the mapping relationship includes the bus number corresponding to each root bridge and the maximum bus resources supported by the root port corresponding to the PCIe channel.

[0018] In a possible implementation, a basic input / output system (BIOS) reads a mapping relationship of bus resource amounts required by PCIe device firmware stored in a storage space, including:

[0019] The BIOS accesses the storage space based on the SMBUS protocol to read the mapping relationship between the bus resource amount required by the PCIe device firmware stored in the storage space.

[0020] In a possible implementation, the firmware update validation method further includes obtaining a modification instruction for a startup parameter in the BIOS, wherein the modification instruction enables the BIOS to read a mapping relationship in the storage space when the system is initialized;

[0021] Based on the modification instruction, the startup parameters of the BIOS are modified.

[0022] In a second aspect, the present application provides a firmware update validation device for a PCIe device, comprising:

[0023] An acquisition module, used to acquire an update version identifier carried in a firmware update instruction when a firmware update instruction for a target PCIe device is detected during operation;

[0024] An update module, used for executing a firmware update procedure for a target PCIe device based on an update version identifier;

[0025] The validation module is used to remove the root port where the target PCIe device is located after the firmware update is successful, and trigger the restart of the target PCIe device; and, in response to the restart of the target PCIe device, scan and identify all PCIe devices including the target PCIe device, and reallocate bus resources for all PCIe devices.

[0026] In a possible implementation, the acquisition module is used to obtain modification instructions for startup parameters in the BIOS, and the modification instructions enable the BIOS to read the mapping relationship in the storage space during system initialization; based on the modification instructions, the acquisition module is also used to modify the startup parameters of the BIOS.

[0027] In a possible implementation, the acquisition module is also used for BIOS to access the storage space to read the mapping relationship of the bus resource amount required by the PCIe device firmware stored in the storage space. Based on the SMBUS protocol, the BIOS can access the storage space.

[0028] In one possible implementation, an acquisition module is used to read a mapping relationship between the amount of bus resources required by the PCIe device firmware stored in a storage space, and allocate bus resources to the PCIe device according to the mapping relationship, wherein the mapping relationship includes the bus number corresponding to each root bridge and the maximum bus resources supported by the root port corresponding to the PCIe channel.

[0029] In a possible implementation, the validation module is used to restart the target PCIe device, including at least one of the following methods: restarting the target PCIe device through the operating system and / or CPLD; restarting the target PCIe device by physically removing and then inserting the target PCIe device.

[0030] In a possible implementation, the validation module is further used to enable a hot-plug function of the PCIe device, wherein the hot-plug function can be enabled when the BIOS initializes the PCIe device.

[0031] In a third aspect, the present application provides a computing device, including: a memory, a processor;

[0032] Memory stores computer-executable instructions;

[0033] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementation methods of the first aspect.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed by a processor, they are used to implement the above first aspect and / or various possible implementation methods of the first aspect.

[0035] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementation methods of the first aspect.

[0036] The present application provides a method, device, storage medium and program product for activating firmware upgrade of a PCIe device. First, by detecting a firmware update instruction for a target PCIe device during operation, an update version identifier carried in the firmware update instruction is obtained, so that the computer has the ability to detect and respond to the firmware update instruction in a timely manner; then, the operating system executes the firmware update program for the target PCIe device based on the update version identifier; thereafter, after the firmware update is successful, the operating system triggers and responds to restarting the target PCIe device by removing the root port where the target PCIe device is located, and then scans and identifies all PCIe devices including the target PCIe device, so that the PCIe device runs in the latest state, thereby achieving the effect of realizing the firmware upgrade and activation of the PCIe device without restarting the host side. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0038] Figure 1 A schematic diagram of a scenario for the method for taking effect of a firmware upgrade of a PCIe device provided in this application;

[0039] Figure 2 Schematic diagram of the process of the firmware update validation method for the PCIe device provided in this application Figure 1 ;

[0040] Figure 3 Schematic diagram of the process of the firmware update validation method for the PCIe device provided in this application Figure 2 ;

[0041] Figure 4 Schematic diagram of the process of the firmware update validation method for the PCIe device provided in this application Figure 3

[0042] Figure 5 A schematic diagram of the structure of a firmware update validation device for a PCIe device provided in this application;

[0043] Figure 6A schematic diagram of the structure of the computing device provided in this application.

[0044] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] First, the terms involved in this application are explained:

[0047] PCIe is a computer bus standard used to connect computer motherboards and external devices. PCIe devices are various external devices connected to the computer motherboard through the PCIe bus, including graphics cards, network cards, sound cards, storage controllers, etc. The PCIe bus provides a high-bandwidth and high-speed data transmission channel, allowing these devices to exchange data with the computer system quickly and stably.

[0048] Root port is a term used in the PCIe architecture to describe the communication port between the host or root complex device (Root Complex) connected to the PCIe bus and other PCIe devices. In the PCIe topology, the root port refers to the physical slot or logical port connected to the root complexity device, where the root complexity device can be the chipset on the motherboard. The root port is responsible for managing data traffic and transferring data from the root complexity device to other PCIe devices, or from other PCIe devices to the root complexity device. The root port is also responsible for handling the initialization and configuration process of the PCIe bus to ensure that all connected devices can recognize and communicate correctly. It also coordinates data transfer and communication between various PCIe devices in the system.

[0049] The root bridge is the root node in the PCIe topology, usually integrated in the processor or south bridge chip, and is responsible for handling the communication between the central processing unit (CPU) and the PCIe devices.

[0050] PCIe firmware is embedded software installed on PCIe devices to control and manage the operation of the device, including functions such as initialization, configuration, data transfer, and power management.

[0051] Resource allocation refers to the process by which the operating system or system management software allocates limited hardware or software resources (such as CPU time, memory space, storage, network bandwidth, etc.) to running tasks, processes, or devices in a computer system. The purpose of resource allocation is to ensure efficient operation of the system, avoid waste or overuse of resources, balance resource requirements between tasks, and maximize system performance when resources are limited.

[0052] The Bus Device Function Number (BDF) is a unique identifier used to identify PCIe (Peripheral Component Interconnect Express) devices. The BDF number consists of three parts: the bus number (Bus), the device number (Device), and the function number (Function). The BDF number is used by the operating system and device management software to locate and manage PCIe devices in the system.

[0053] Bus resources refer to the resources that can be provided by the bus used for connection and communication in a computer system, including bandwidth, address space, interrupt request lines, etc. Bus resources are used to support data transmission and instruction communication between various hardware devices in the system.

[0054] Hot plugging refers to the technology of adding or removing hardware devices without turning off the power while the computer system is running. This technology allows users to dynamically add or remove devices such as hard disks, PCIe cards, etc. while the system is working normally without affecting the operation or stability of the system.

[0055] Basic Input / Output System (BIOS) is a firmware program embedded on the computer motherboard. BIOS is the first program executed when the computer starts up. It is responsible for initializing and detecting the computer's hardware components, such as the CPU, memory, hard disk, and other peripherals. BIOS also provides a set of basic input and output operations for the operating system and application programs to use.

[0056] The System Management Bus (SMBus) protocol is a low-speed, bidirectional communication protocol, mainly used for communication between devices such as smart batteries, temperature sensors, and fan controllers in computer systems. It has the characteristics of low power consumption, data integrity, and device address uniqueness, supports master-slave mode, and is suitable for system management tasks of low-speed devices.

[0057] Figure 1 A schematic diagram of a scenario for a method for taking effect of a firmware upgrade of a PCIe device provided in this application, such as Figure 1 As shown, the specific application scenario of this application includes an operating system 11, a PCIe device 12, a bus 13, a storage space 14, and a BIOS 15, wherein the operating system 11 is located at the core of the operating system and is responsible for processing computing tasks. During the firmware upgrade process, ensure that the upgrade requirements of the PCIe device are met; the PCIe device 12 represents a PCIe card or device that is undergoing a firmware upgrade; the bus 13 connects the operating system 11, the PCIe device 12, the BIOS 15, and the storage space 14, and is a key channel for data and instruction transmission; the storage space 14 represents a mapping relationship between the storage of firmware upgrade files and the stored firmware and the amount of bus resources required by the firmware.

[0058] BIOS 15 accesses storage space 14 through bus 13 to obtain the mapping relationship between the stored firmware and the amount of bus resources required by the firmware, allocates BUS resources to PCIe device 12 when performing PCIe device initialization, and hands over control to operating system 11. Operating system 11 manages PCIe device 12 through bus 13 to upgrade PCIe device firmware, re-identifies PCIe device 12, and performs initialization operations according to the characteristics of PCIe device 12.

[0059] In combination with the above scenarios, it can be seen that in the prior art, there are technical problems such as insufficient bus resource allocation or the need to restart the host side when upgrading the PCIe device, which results in the PCIe device failing to work properly without restarting the host side after the firmware upgrade. Specifically, some PCIe device manufacturers currently have adapted device firmware with multiple functions based on the same PCIe device. Different functional firmware need to be switched during use to achieve different functional purposes. However, different functional firmware have different requirements for resources. When the PCIe device firmware is upgraded from a PCIe device firmware with a small resource requirement to a PCIe device firmware with a large resource requirement, if there is no reasonable resource allocation mechanism, the PCIe device cannot work properly or take effect after restarting. At the same time, after the firmware upgrade is completed, some PCIe devices need to go through the reinitialization and configuration process before the new firmware can be fully loaded and put into use.

[0060] The present application provides a method for activating the firmware update of a PCIe device. The method queries the bus resource with the largest demand for the firmware of the target PCIe device, builds a mapping relationship for the amount of bus resources required by the firmware of the PCIe device, and stores the mapping relationship in a storage space. At the same time, the startup parameters of the BIOS are modified so that the BIOS allocates bus resources to the firmware of the target PCIe device by reading the mapping relationship in the storage space during system initialization, and enables the hot-swap function of the PCIe device. After the firmware of the target PCIe device is upgraded, the target PCIe device is restarted, and the target PCIe device is initialized and configured, thereby solving the technical problem of being able to upgrade and activate the firmware of the PCIe device without restarting the host side.

[0061] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0062] Figure 2 Schematic diagram of the process of the firmware update validation method for the PCIe device provided in this application Figure 1 ,like Figure 2 As shown, the method includes:

[0063] S201: If a firmware update instruction for a target PCIe device is detected during operation, an update version identifier carried in the firmware update instruction is obtained.

[0064] A firmware update instruction is a command sent by the system or management software to a device to update the device's firmware. It is embedded software inside the device that controls the basic functions of the hardware. It usually contains specific information required for the update, such as the new version of the firmware code, update process, and checkpoints. The target PCIe device refers to the specific PCIe device that is receiving the firmware update, including network interface cards, graphics processing units, storage controllers, etc. The target PCIe device communicates with the host system through the PCIe bus. The update version identifier is the information carried in the firmware update instruction, which is used to identify the version number of the firmware. It is used to confirm whether the new firmware version is higher or different from the version currently running on the device to decide whether to update it.

[0065] In this step, the operating system detects the firmware update instruction, which can be triggered periodically or by a specific event to determine whether a new firmware update instruction is sent to the target PCIe device. Once the firmware update instruction is detected, the operating system will parse the instruction to extract information, including the update version identifier.

[0066] S202: Execute a firmware update program for the target PCIe device based on the update version identifier.

[0067] The firmware update procedure is a process performed by the operating system or device management software to load a new firmware version onto a target PCIe device, which includes multiple steps such as downloading the firmware, verifying its integrity, suspending device operation, writing the new firmware, and restarting the device.

[0068] Boot into the operating system and upgrade the firmware of the specified PCIe device first using the firmware upgrade method provided by the PCIe vendor. The operating system compares the extracted update version identifier with the firmware version currently running on the target PCIe device. If the new version is higher than the current version, the operating system will continue the update process, otherwise it may ignore the update instruction and / or prompt that the latest version is already available. If the version comparison result shows that an update is required, the system will download or load the new firmware from memory and update it according to the process steps in the instruction.

[0069] S203: After the firmware is successfully updated, remove the root port where the target PCIe device is located, and trigger a restart of the target PCIe device.

[0070] A successful firmware update means that the firmware update procedure is successfully completed and the new firmware version has been correctly installed and loaded onto the target PCIe device.

[0071] In this step, after the firmware update procedure is complete, the operating system performs a verification step to confirm that the new firmware has been correctly installed. After that, the operating system temporarily removes the root port where the target PCIe device is located, suspending communication between the device and the system host so that the operating system can prepare for the PCIe device restart process. The root port removal operation is usually achieved by disabling the corresponding port on the PCIe bus. With the root port removed, the operating system triggers the restart process of the target PCIe device.

[0072] S204, in response to the target PCIe device restarting, scanning and identifying all PCIe devices including the target PCIe device, and initializing all PCIe devices, wherein the initialization includes reallocating bus resources.

[0073] In response to the target PCIe device restarting, the restart steps include turning off the device power, clearing the current operating state, reloading the new firmware and device driver, and scanning the PCIe device again, and performing initialization for the PCIe device. After the root port is restored and the target PCIe device restarts, the system will perform a final functional verification to ensure that the target PCIe device operates normally under the new firmware version and can continue to perform its expected functions.

[0074] In this step, after the target PCIe device is restarted, the operating system rescans the device through Rescan and allocates bus resources to the device. It is worth noting that the bus resource interval between the root ports split in each root bridge needs to be planned according to the maximum resource demand of the PCIe device firmware. The maximum BUS number register storage supported by the configuration space of each root port needs to meet the number of buses of the firmware with the largest bus resources required, ensuring that the bus number interval used by the current root port can meet the needs of the device firmware under it. This setting can ensure that there will be no problem of insufficient resources causing the PCIe device to fail to work properly after the firmware upgrade.

[0075] The firmware update validation method for a PCIe device provided in an embodiment of the present application obtains an update version identifier by detecting a firmware update instruction during computer operation; executes a firmware update program for a target PCIe device; after a successful firmware update, removes the root port where the target PCIe device is located, and restarts the target PCIe device; then, scans and identifies all PCIe devices including the target PCIe device, and performs a means of initializing all PCIe devices, thereby solving the Bus resource conflict problem caused by firmware differences during the process of upgrading the PCIe device firmware, and achieving the effect of enabling the updated firmware of the PCIe device to take effect through PCIe Remove and Rescan without restarting the Host end.

[0076] Figure 3 Schematic diagram of the process of the firmware update validation method for the PCIe device provided in this application Figure 2 ,like Figure 3 As shown, in this embodiment Figure 2 Based on the embodiment, a method for taking effect of firmware update of a PCIe device is described in detail, and the method includes:

[0077] S301, obtaining a modification instruction for a startup parameter in BIOS.

[0078] Boot parameters are configuration information passed by BIOS or other firmware to the operating system or hardware device when the system starts. Modification instructions refer to specific commands or operations used to change BIOS settings or parameters. These instructions can come from users, system management software, or other control modules, with the purpose of adjusting BIOS behavior or configuration to meet specific needs. System initialization refers to the process of configuring and preparing the computer hardware and software environment during the BIOS or operating system startup process after the machine is powered on, including detecting hardware, loading drivers, setting system parameters, and preparing for the startup of the operating system. Modification instructions enable BIOS to read the mapping relationship in the storage space when the system is initialized. In this application, the mapping relationship involves the memory address mapping of the hardware device or the resource allocation of the storage space.

[0079] Before the system starts, modify the modification instruction of the startup parameters in the BIOS to instruct the BIOS to perform specific operations at startup, including reading the mapping relationship between the PCIe device firmware and the amount of bus resources required by the firmware, and initializing the PCIe device according to the mapping relationship. Optionally, in this step, the modification instruction can be issued by the system management software or the control module.

[0080] S302: Modify the startup parameters of the BIOS based on the modification instruction.

[0081] According to the received modification instruction, BIOS adjusts the BIOS startup parameters, including obtaining the storage space address of the mapping relationship, obtaining the PCIe bus resource mapping relationship, and initializing the PCIe device. The modified startup parameters will allow BIOS to read the mapping relationship between the PCIe device firmware and the bus resource amount required by the firmware in the storage space during the system initialization phase.

[0082] S303: BIOS accesses the storage space based on the SMBUS protocol to read the mapping relationship of the bus resource amount required by the PCIe device firmware stored in the storage space.

[0083] In one possible implementation, the bus resource sizes required for the operation of all supported PCIe device firmware are obtained from the PCIe manufacturer, and then a reasonable mapping relationship list between the PCIe device firmware and the bus resource amounts required by the firmware is designed based on the maximum bus resource firmware when the PCIe device firmware is running, and then the mapping relationship is written into the storage space. During the startup process, the BIOS will access the mapping relationship in the storage space to adjust the PCIe device bus resource allocation.

[0084] A possible implementation method is to dynamically adjust the mapping relationship of the bus resource amount required by the existing stored PCIe device firmware according to the information in the storage space. If there is firmware that exceeds the current bus resource setting in the future, the storage space information can be adjusted, so that the BIOS can be automatically re-adapted to meet the new firmware resource requirements without modifying the BIOS. The BIOS version can be automatically adapted to meet the new firmware resource requirements without releasing it again, saving manpower for adaptation development and verification, and there is no need to re-release the BIOS to adapt to the differences brought by the new device firmware.

[0085] S304. BIOS initializes the PCIe device according to a mapping relationship, wherein the mapping relationship includes a bus number corresponding to each root bridge and a maximum bus resource supported by a root port corresponding to a PCIe channel; PCIe device initialization includes allocating bus resources to the PCIe device.

[0086] In this step, the BIOS reads the mapping relationship of the amount of bus resources required by the PCIe device firmware stored in the storage space from the corresponding storage location, including the bus number corresponding to each root bridge, the correspondence between the PCIe channel and the root port, and the maximum amount of bus resources supported by each root port. The BIOS obtains the firmware information of the PCIe device, including the device type, the type and quantity of bus resources required, etc. According to the mapping relationship, the PCIe device is initialized and appropriate bus resources are allocated. When the BIOS performs PCIe device initialization, the PCIe hot plug function is also turned on to support the operating system to remove and rescan the PCIe device.

[0087] S305: If a firmware update instruction for the target PCIe device is detected during the running process, an update version identifier carried in the firmware update instruction is obtained.

[0088] The implementation principle and technical effect of this step are similar to those of step S201, and are not described in detail in this embodiment.

[0089] S306: Execute a firmware update program for the target PCIe device based on the update version identifier.

[0090] The implementation principle and technical effect of this step are similar to those of step S202, and are not described in detail in this embodiment.

[0091] S307: After the firmware is successfully updated, remove the root port where the target PCIe device is located, and trigger a restart of the target PCIe device.

[0092] In a possible implementation manner, Remove is used to remove the root port of the target PCIe device, triggering a restart operation on the target PCIe device.

[0093] S308 , in response to the target PCIe device restarting, scanning and identifying all PCIe devices including the target PCIe device, and initializing all PCIe devices, wherein the initialization includes reallocating bus resources.

[0094] In this step, first restart the PCIe device, then use Rescan to scan all PCIe devices, initialize all devices, and reallocate bus resources to the target device. Through this process, the PCIe device firmware upgrade can be implemented and take effect without restarting the host.

[0095] Optionally, restart the target PCIe device, including at least one of the following:

[0096] Restart the target PCIe device through the operating system and / or CPLD;

[0097] Restart the target PCIe device by physically removing and reinserting it.

[0098] In a possible implementation, the target PCIe device is restarted by the operating system and / or CPLD. The operating system may send a specific command and / or signal to the PCIe device through the device driver or the management interface provided by the operating system after receiving the instruction to restart the PCIe device, so that the PCIe device enters a reset state and / or requires it to be reinitialized. Optionally, the operating system may execute the restart of the PCIe device by controlling a programmable hardware component, wherein the programmable hardware component may be a CPLD. When the CPLD receives the instruction to restart the PCIe device, it generates and outputs a reset signal to the PCIe device according to the received instruction and the preset logic function to ensure that the reset is performed. Optionally, during this process, the CPLD may also monitor the status feedback signal of the PCIe device for real-time monitoring. When it is determined that the PCIe device has been successfully reset, the CPLD may release the reset signal and run the PCIe device to resume normal operation.

[0099] In one possible implementation, the steps of restarting the device by physically removing and reinserting the target PCIe device may be, first, ensuring that hot plugging is turned on in the computer, and unplugging the target PCIe device from the PCIe slot on the motherboard; after removing the device, check whether the slot and the gold fingers of the device have dust or dirt, and clean them appropriately; next, reinsert the PCIe device into the same slot, ensuring that it is firmly fixed in place; finally, the operating system will re-enumerate and initialize the PCIe device, thereby achieving the purpose of restarting the device.

[0100] For example, after restarting the PCIe device, wait for the PCIe device to start up, and then execute PCIeDevice Rescan on the Host to rescan all PCIe devices. The command is as follows: echo1> / sys / bus / pci / rescan. After the command is executed, the operating system recognizes and re-recognizes the type, manufacturer information and device ID of the PCIe device. The driver performs initialization operations according to the characteristics of the device, including setting the device working mode, allocating system resources and initializing the internal state of the device. Finally, all PCIe devices are successfully scanned and the PCIe device is effective. After the rescan is completed, lspci-tv can be used to check that all current devices can be recognized normally without errors, and the PCIe device can also operate normally.

[0101] Optionally, if physical removal and reinsertion is supported, before restarting the target PCIe device, perform the following operations: enable the hot-swap function of the PCIe device, where the hot-swap function can be enabled when the BIOS initializes the PCIe device.

[0102] During the computer startup process, BIOS finds and enables the hot-plug function through hardware or advanced settings options. Specifically, in the hardware or advanced settings menu, find the hot-plug related options and set them to enabled. Then BIOS performs the necessary initialization and configuration for the PCIe device to support the hot-plug function.

[0103] By enabling the hot-swap function of PCIe devices, the target PCIe device can be restarted without restarting the Host, saving the time of restarting the system and improving the efficiency of PCIe firmware upgrades. At the same time, it avoids the problem of data loss caused by restarting and minimizes the impact on the normal operation of the system.

[0104] The firmware update validation method for a PCIe device provided in an embodiment of the present application constructs a mapping relationship of the amount of bus resources required by the PCIe device firmware according to the bus resource size information required by the PCIe firmware and stores it in a storage space; when the PCIe device is initialized, the storage space is accessed through the BIOS to obtain the mapping relationship, and the bus resources are dynamically adjusted for the PCIe device according to the mapping relationship, so as to meet the needs of the PCIe device to upgrade and switch to a firmware with larger resources, thereby solving the technical problem that the PCIe device cannot be normally identified during Rescan because the BUS number required by the target PCIe device is greater than the maximum BUS number supported by the root port, and ensuring the normal validation and use of the firmware of the PCIe device after the firmware update; after driving Remove and Rescan under the operating system, the device can be normally identified under the operating system, thereby solving the technical problem that the PCIe device cannot be normally used due to bus resource conflicts caused by firmware differences during the PCIe firmware upgrade, and achieving the effect of taking effect after the PCIe device upgrades its firmware without restarting the Host end.

[0105] Figure 4 Schematic diagram of the process of the firmware update validation method for the PCIe device provided in this application Figure 3 ,like Figure 4 As shown, in this embodiment Figure 2 Based on the embodiment, a method for taking effect of firmware update of a PCIe device is described in detail by way of example. The method includes:

[0106] S401. According to the size of resources required by the firmware provided by the PCIe manufacturer and based on supporting the maximum resource firmware, the Bus space of each X16 channel is reasonably allocated and written into Eeprom.

[0107] During the BIOS configuration phase, the operating system allocates enough bus space for each X16 channel based on the firmware resource requirements provided by the PCIe device manufacturer to ensure that the PCIe device can work properly and will not have problems due to insufficient resources. After the allocation is completed, this information will be written to the Eeprom for use by the BIOS in the subsequent boot process.

[0108] The embodiment of the present application also provides Table 1, a mapping relationship table of resources required by PCIe devices, to facilitate those skilled in the art to understand the mapping relationship between firmware upgrade files and stored firmware and the amount of bus resources required by the firmware. As shown in Table 1, the mapping relationship describes the detailed information of the channel configuration supported by the CPU and the bus resources required by the PCIe device firmware. The table content can be broken down into the following parts for explanation:

[0109] Table 1 PCIe device required resource mapping table

[0110]

[0111] Table 1 is a mapping relationship of resources required by the PCIe device provided by this application. As shown in Table 1, the mapping relationship describes the detailed information of the channel configuration supported by the CPU and the bus resources required by the PCIe device firmware. The content of the table can be broken down into the following parts for explanation:

[0112] In the CPU supported channel configuration, the CPU supports 3 X16 channels, which means that the CPU used in the current solution supports a total of 3 PCIe X16 channels. Although each channel was originally designed for X16 bandwidth, in the current configuration, due to specific hardware design or performance requirements, each X16 channel is split into two X8 channels for use.

[0113] The bus resources required by the firmware lists in detail the bus resource information required by the PCIe device.

[0114] The Eeprom offset lists the offset addresses in the EEPROM used to store bus resource information. Here, 0x00 to 0x08 are the offset addresses used to store different root bridge information, while 0x10 to 0x15 are the specific offset addresses used to store the X8 channel information in each stack.

[0115] The bus number corresponding to each root bridge of the CPU lists the bus number corresponding to each root bridge of the CPU. For example, 0x10, 0x20, and 0x30 correspond to the bus numbers of the three root bridges respectively, and NA means that no bus number is assigned to this position.

[0116] The maximum number of bus resources supported by each root port indicates the maximum number of bus resources supported by each root port. Here, all listed root ports support a maximum of 0x7 (i.e. 7) bus resources, while the remaining NA indicates no additional information or unsupported ports.

[0117] In one possible case, the CPU of the current solution supports X16 channels, and there are 6 PCIe devices that need to be effective. Among them, the PCIe devices can be 6 PCIe device cards that support X8 channels. The PCIe devices need to support 3 types of firmware. The smallest of these three firmwares has 3 Bus devices, and the largest has 7 Bus devices. In order to make all PCIe devices available, each X16 channel in the CPU is further allocated into two X8 channels, where CPU Root Bridge 0 is designed as X8X8, CPURoot Bridge 1 is designed as X8X8, and CPU Root Bridge 2 is designed as X8X8. If the mapping relationship of the amount of bus resources required by the PCIe device firmware is not established, the bus resources of the PCIe device are reserved, and the operating system is booted from the firmware of 3 Buses by default. At this time, if the PCIe device is upgraded and upgraded to the firmware of 7 Buses, the PCIe device needs to be restarted. At the same time, the PCIe device will have insufficient bus resources, resulting in the inability to normally identify the PCIe device.

[0118] For example, if the BDF numbers corresponding to the root ports of the two x8x8 channels in the default CPU Root Bridge 0 are 10:00.0 and 10:00.1 respectively; the BDF numbers corresponding to the root ports of the two x8x8 channels in the CPU Root Bridge 0 are 19:00.0 and 19:00.1 respectively, they need to be allocated to two PCIe device firmwares that require 7 bus resources. From the bus number in the BDF number, we can know that the offsets of CPU Root Bridge0 and CPU Root Bridge 0 are 0x10 and 0x19 respectively, so the corresponding bus resources in CPU RootBridge0 are 0x19-0x10=0x9, which cannot be allocated to the PCIe device firmware that requires 7+7=14 bus resources. At this time, there will be a problem of insufficient resources, which can be solved by designing the offsets representing CPU Root Bridge 0 and CPU Root Bridge 0 in the storage space. By setting the offsets of CPU Root Bridge 0 and CPURoot Bridge 0 to 0x10 and 0x20 respectively, the corresponding bus resources in CPU Root Bridge 0 are 0x20-0x10=0x10, and 16 buses can be distributed to the PCIe device firmware that requires 14 bus resources. In this way, CPU RootBridge0 has enough bus resources to meet the needs of two PCIe devices that require 7 Bus numbers. At the same time, the definition of the offset corresponding to CPU Root Bridge0 is the same as above; write the number of BUSs of the maximum resources supported by the current X8 PCIe device at offset 0x10 (CPU Root Bridge0). If the number of BUSs of the maximum resources mentioned above is 7, then fill in 7. The values ​​of other offsets 0x11, 0x12, and 0x13 are defined the same as 0x10.

[0119] S402, start powering on and starting BIOS.

[0120] When a computer is plugged in and powered on, it begins the boot process, which starts with the BIOS.

[0121] S403, BIOS first allocates a bus number to each X16 root bridge according to the bus resource information planned by Eeprom.

[0122] During system startup, BIOS obtains and assigns a bus number to each X16 root bridge (ie, X16 channel) based on the bus resource information stored in Eeprom, ensuring that the PCIe device can be connected to the PCIe bus in a pre-set manner.

[0123] For example, BIOS accesses Eeprom through SMBUS protocol to obtain the mapping relationship of the bus resources required by the stored PCIe device firmware, and then assigns the following fixed BUS numbers to CPU RootBridge 0, CPU Root Bridge 1, and CPU Root Bridge 2 according to the mapping relationship reflected by the values ​​of Eeprom offsets 0x00, 0x01, and 0x02:

[0124] BDF numbers of the X8X8 RootPorts of CPU Root Bridge 0: 10:00.0 and 10:00.1

[0125] BDF numbers of the X8X8 RootPorts of CPU Root Bridge 1: 20:00.0 and 20:00.1

[0126] BDF numbers of the X8X8 RootPorts of CPU Root Bridge 2: 30:00.0 and 30:00.1

[0127] For example, when BIOS initializes the PCIe device, it fills the bus number of the firmware with the maximum required Bus resources obtained from the corresponding position in the storage space in the maximum Bus number register of the configuration space of each root port, ensuring that the bus number range used by the current root port can meet the needs of the device firmware under it;

[0128] S404. Each X16 root bridge is divided into two channels of X8X8, which is equivalent to having two root ports for one X16 root bridge. The BIOS allocates a starting bus number and a maximum supported bus number resource to the device connected to the root port according to the maximum bus resource information stored in the storage space.

[0129] Each X16 channel is divided into two X8 channels, each X8 channel corresponds to a root port, and an X16 channel can support two independent PCIe devices or device groups. For each root port, the BIOS will allocate the starting bus number and the maximum supported bus number resources to the devices connected to it according to the maximum bus resource information (0x10-0x15) stored in Eeprom, ensuring that each device has enough resources to work properly.

[0130] When initializing the device under the root port with BDF number 10:00.0, according to the Eeprom list information, the bus number 0x10 is obtained from the Eeprom offset 0x00 and the maximum BUS resource 7 supported by the bridge is added, and the maximum BUS number supported by the bridge is 0x10+7=0x17. The bus number starting from the root port is 0x10+1=0x11. The Bus interval occupied by the root port is [0x11, 0x17], with a total of 7 bus numbers. The resource requirement of the maximum resource firmware of the device under the bridge is 7, which can meet the resource requirement of the maximum resource firmware of the device under the bridge.

[0131] When initializing the device under the root port with BDF number 10:00.1, the device Bus number under the bridge is allocated from the largest BUS number 0x17+7+1=0x18 under the root port with BDF number 10:00.1, and the occupied Bus interval is [0x18, 0x18+7]. Similarly, the device bus resources under the root ports with BDF numbers 20:00.0, 20.00.1, 30:00.0 and 30.00.1 are not described here.

[0132] S405. Enable the PCIe hot-swap function.

[0133] The BIOS turns on the PCIe hot-plug function, allowing users to add or remove PCIe devices while the Host is running without shutting down the Host.

[0134] S406 , boot into the OS and upgrade the specified PCIe device firmware.

[0135] After booting and entering the operating system, update and / or upgrade the firmware of the specified PCIe device.

[0136] S407. Remove the root port corresponding to the PCIe device, restart the PCIe device, wait for the PCIe device to start up, and then rescan all PCIe devices.

[0137] After upgrading the firmware of the specified PCIe device, remove the root port corresponding to the PCIe device. Restart the PCIe device to ensure that the new configuration takes effect. After the PCIe device restarts, the operating system rescans all PCIe devices to ensure that all devices are correctly identified and configured.

[0138] In a possible implementation of this step, the root port where the target PCIe device is located is removed and rescanned by using commands such as Lspci and echo. For example, after completing the PCIe device firmware upgrade, PCIeDevice Remove is executed on the host side, such as echo 1> / sys / bus / pci / devices / $devaddr / remove, where devaddr is the device number of the root port corresponding to the target PCIe device.

[0139] For example, to remove the root port with device number 0000\:17\:02.0, use the echo 1> / sys / bus / pci / devices / 0000\:17\:02.0 / remove command. After executing this command, the system will remove the root port and the devices attached to it from the bus. After removing the PCIe device, the Lspci command will not be able to find the root port and the devices attached to it. Finally, restart the PCIe device.

[0140] The firmware update validation method for a PCIe device provided in the embodiment of the present application describes the firmware validation method in detail by taking examples, and achieves the effect of enabling the PCIe device update to take effect without restarting the host end by adjusting the allocation method of the PCIe device bus resources.

[0141] Figure 5 The schematic diagram of the structure of the firmware update validation device for the PCIe device provided by this application is as follows: Figure 5 As shown, the firmware update validation device 50 of the PCIe device provided in this embodiment includes:

[0142] The acquisition module 501 is used to acquire the update version identifier carried in the firmware update instruction when a firmware update instruction for the target PCIe device is detected during operation;

[0143] An update module 502, configured to execute a firmware update procedure for a target PCIe device based on an update version identifier;

[0144] The validation module 503 is used to remove the root port where the target PCIe device is located after the firmware update is successful, and trigger the restart of the target PCIe device; and, in response to the restart of the target PCIe device, scan and identify all PCIe devices including the target PCIe device, and reallocate bus resources for all PCIe devices.

[0145] In a possible implementation, the acquisition module 501 is used to obtain modification instructions for the startup parameters in the BIOS, and the modification instructions enable the BIOS to read the mapping relationship in the storage space during system initialization; based on the modification instructions, the acquisition module 501 is also used to modify the startup parameters of the BIOS.

[0146] In a possible implementation, the acquisition module 501 is also used for the BIOS to access the storage space to read the mapping relationship of the bus resource amount required by the PCIe device firmware stored in the storage space. Based on the SMBUS protocol, the BIOS can access the storage space.

[0147] In one possible implementation, the acquisition module 501 is used to read the mapping relationship of the amount of bus resources required by the PCIe device firmware stored in the storage space, and allocate bus resources to the PCIe device according to the mapping relationship, wherein the mapping relationship includes the bus number corresponding to each root bridge and the maximum bus resources supported by the root port corresponding to the PCIe channel.

[0148] In one possible implementation, the validation module 503 is used to restart the target PCIe device, including at least one of the following methods: restarting the target PCIe device through the operating system and / or BIOS; restarting the target PCIe device by using a command line tool; restarting the target PCIe device by physically removing and then inserting the target PCIe device.

[0149] In a possible implementation, the validation module 503 is further used to enable a hot-plug function of the PCIe device, wherein the hot-plug function can be enabled when the BIOS initializes the PCIe device.

[0150] The firmware update validation device for a PCIe device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be described in detail in this embodiment.

[0151] Figure 6 This is a schematic diagram of the structure of the computing device provided in this application. Figure 6 As shown, the electronic device 60 provided in this embodiment includes: at least one processor 601 and a memory 602. Optionally, the device 60 also includes a communication component 603. The processor 601, the memory 602 and the communication component 603 are connected via a bus 604.

[0152] In a specific implementation process, at least one processor 601 executes the computer execution instructions stored in the memory 602, so that at least one processor 601 executes the above method.

[0153] The specific implementation process of the processor 601 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0154] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0155] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0156] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0157] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0158] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0159] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory, erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0160] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0161] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0162] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0163] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0164] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0165] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0166] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for validating firmware update of a PCIe device, characterized in that: include: If a firmware update instruction for the target PCIe device is detected during the operation, an update version identifier carried in the firmware update instruction is obtained; Based on the update version identifier, executing a firmware update program for the target PCIe device; After the firmware is successfully updated, the root port where the target PCIe device is located is removed, and the target PCIe device is triggered to restart; In response to the target PCIe device restarting, all PCIe devices including the target PCIe device are scanned and identified, and all PCIe devices are initialized, wherein the initialization includes reallocating bus resources.

2. The method for validating firmware update of a PCIe device according to claim 1, characterized in that: The restarting of the target PCIe device includes at least one of the following: Restarting the target PCIe device through an operating system and / or a complex programmable logic device CPLD; Restart the target PCIe device by physically removing and reinserting the target PCIe device.

3. The method for validating firmware update of a PCIe device according to claim 2, characterized in that: If physical removal and reinsertion is supported, before restarting the target PCIe device, perform the following operations: Enable the hot-swap function of the PCIe device, wherein the hot-swap function can be enabled when the BIOS initializes the PCIe device.

4. The method for validating firmware update of a PCIe device according to any one of claims 1 to 3, characterized in that: In order to successfully scan and identify all PCIe devices including the target PCIe device, the BIOS performs the following operations during the device initialization process: Read the mapping relationship of the amount of bus resources required by the PCIe device firmware stored in the storage space, and initialize the PCIe device according to the mapping relationship, wherein the mapping relationship includes the bus number corresponding to each root bridge and the maximum bus resources supported by the root port corresponding to the PCIe channel; the PCIe device initialization includes allocating bus resources to the PCIe device.

5. The method for validating firmware update of a PCIe device according to claim 4, characterized in that: The BIOS reads a mapping relationship of bus resource amounts required by the PCIe device firmware stored in the storage space, including: The BIOS accesses the storage space based on the SMBUS protocol to read the mapping relationship between the bus resource amount required by the PCIe device firmware stored in the storage space.

6. The method for validating firmware update of a PCIe device according to claim 4, characterized in that: Also includes: Obtaining a modification instruction for a startup parameter in the BIOS, wherein the modification instruction enables the BIOS to read the mapping relationship in the storage space when the system is initialized; Based on the modification instruction, the startup parameters of the BIOS are modified.

7. A firmware update validation device for a PCIe device, characterized in that: include: An acquisition module, configured to acquire an update version identifier carried in a firmware update instruction when a firmware update instruction for a target PCIe device is detected during operation; An update module, configured to execute a firmware update program for the target PCIe device based on the update version identifier; An effective module, used for removing the root port where the target PCIe device is located and triggering the restart of the target PCIe device after the firmware is successfully updated; And, in response to the target PCIe device restarting, all PCIe devices including the target PCIe device are scanned and identified, and bus resources are reallocated to all PCIe devices.

8. A computing device, characterized in that The computing device is connected to a PCIe device, and the computing device includes: a memory and a processor; The memory stores computer-executable instructions; The processor executes the computer-implemented instructions so that the processor performs the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed.

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