Method and apparatus for general register value profiling for RISC-V processors

Abstract

The present application relates to a method and device for general register value profiling of a RISC‑V processor. The method comprises: determining a target instruction to be monitored and a target general register to be value profiled for the target instruction among a plurality of general registers of a RISC‑V processor; inserting a RISC‑V HINT instruction before the target instruction; and triggering value profiling of the target general register in response to the execution of the RISC‑V HINT instruction.

Description

Technical Field

[0001] The present application relates to the field of computers, and more specifically, to a method and device for general register value analysis of a RISC-V processor. Background Art

[0002] Sampling general purpose register (GPR) values ​​at runtime is a powerful means to gain in-depth insight into the dynamic behavior of software programs. Sampling data plays a vital role in Profile-Guided Optimization (PGO) tools. By carefully analyzing the distribution of GPR values ​​during runtime of the relevant program, the PGO tool can accurately identify performance bottlenecks in the program and implement targeted optimization strategies in subsequent iterative executions, thereby significantly improving the operating efficiency and performance of the target program. Summary of the invention

[0003] This disclosure provides a new technique for general register value profiling for RISC-V processors. The proposed value profiling framework utilizes RISC-V HINT instructions and control and status register (CSR) space to achieve precise control over GPR value sampling, while allowing real-time aggregation of profiling data during execution. This approach significantly reduces the size of sampling profiles and data, and minimizes the associated profiling burden.

[0004] According to an embodiment of the present disclosure, a method for general register value profiling of a RISC-V processor is provided, comprising: determining a target instruction to be monitored and a target general register among multiple general registers of the RISC-V processor for which value profiling is to be performed with respect to the target instruction; inserting a RISC-V HINT instruction before the target instruction; and triggering value profiling of the target general register in response to execution of the RISC-V HINT instruction.

[0005] According to an embodiment of the present disclosure, a device for general register value profiling of a RISC-V processor is provided, comprising: a processor; and a memory, coupled to the processor and containing instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to perform the following operations: determine a target instruction to be monitored and a target general register among a plurality of general registers of the RISC-V processor for which value profiling is to be performed with respect to the target instruction; insert a RISC-V HINT instruction before the target instruction; and trigger value profiling of the target general register in response to execution of the RISC-V HINT instruction.

[0006] According to an embodiment of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored, wherein the instructions, when executed by a processor, cause the processor to perform the above-mentioned method for general register value profiling of a RISC-V processor.

[0007] According to an embodiment of the present disclosure, a computer program product is provided, on which instructions are stored, wherein the instructions, when executed by a processor, cause the processor to perform the above-mentioned method for general register value profiling of a RISC-V processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be described by way of example and not limitation with reference to the figures of the accompanying drawings in which like reference numerals refer to like elements and in which:

[0009] Figure 1 Illustrated is a block diagram of an example processor and / or SoC 100 that may have one or more cores and with an integrated memory controller.

[0010] Figure 2 A schematic diagram of the value profiling process based on traditional sampling is shown.

[0011] Figure 3 A flowchart of general register value analysis for a RISC-V processor according to an embodiment of the present disclosure is shown.

[0012] Figure 4 A schematic diagram of an example field encoding structure of a value parsing configuration CSR according to an embodiment of the present disclosure is shown.

[0013] Figure 5 A schematic diagram of an example field encoding structure of value profiling data CSR according to an embodiment of the present disclosure is shown.

[0014] Figure 6 A schematic diagram of an example field encoding structure of a RISC-V HINT instruction according to an embodiment of the present disclosure is shown.

[0015] Figure 7 The disassembled code of the RISC-V memset() function is shown.

[0016] Figure 8 A flowchart of a method 800 for general register value profiling of a RISC-V processor according to an embodiment of the present disclosure is shown.

[0017] Fig. 9 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (eg, a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. DETAILED DESCRIPTION

[0018] The features and exemplary embodiments of various aspects of the application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the application by illustrating the example of the application. The application is by no means limited to any specific configuration proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the spirit of the application. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid causing unnecessary ambiguity to the application.

[0019] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0020] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may. The terms "comprising," "having," and "including" are synonymous unless the context dictates otherwise. The phrases "A or B" and "A / B" mean "(A), (B) or (A and B)."

[0021] Figure 1 A block diagram of an example processor and / or SoC 100 is illustrated, which may have one or more cores and have an integrated memory controller. The processor 100 illustrated by the solid line box has a single core 102(A), a system agent unit circuit 110, and a set of one or more interface controller unit circuits 116, while the optionally added dashed line box illustrates an alternative processor 100 as having multiple cores 102(A)-(N), a set of one or more integrated memory control unit circuits 114 in the system agent unit circuit 110, dedicated logic 108, and a set of one or more interface controller unit circuits 116.

[0022] Different implementations of processor 100 may include: 1) a CPU, where dedicated logic 108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 102 (A)-(N) are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 102 (A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 102 (A)-(N) are a large number of general-purpose in-order cores. Thus, processor 100 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-in-one (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 100 may be part of and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0023] The memory hierarchy includes one or more levels of cache unit circuits 104(A)-(N) within the cores 102(A)-(N), a set of one or more shared cache unit circuits 106, and external memory (not shown) coupled to the set of integrated memory controller unit circuits 114. The set of one or more shared cache unit circuits 106 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples an interface network circuit 112 (e.g., a ring interconnect) provides an interface to the dedicated logic 108 (e.g., integrated graphics logic), the set of shared cache unit circuits 106, and the system agent unit circuit 110, alternative examples use any number of well-known techniques to provide interfaces to these units. In some examples, coherency is maintained between one or more circuits in the shared cache unit circuits 106 and the cores 102(A)-(N). In some examples, interface controller unit circuitry 116 couples the cores to one or more other devices 118 , such as one or more I / O devices, storage, one or more communication devices (eg, wireless network, wired network, etc.), and the like.

[0024] In some examples, one or more of the cores 102(A)-(N) have multi-threading capabilities. The system agent unit circuit 110 includes those components that coordinate and operate the cores 102(A)-(N). The system agent unit circuit 110 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) logic and components required to adjust the power state of the cores 102(A)-(N) and / or the dedicated logic 108 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0025] The cores 102(A)-(N) may be homogeneous with respect to instruction set architecture (ISA). Alternatively, the cores 102(A)-(N) may be heterogeneous with respect to ISA; that is, a subset of the cores 102(A)-(N) may be capable of executing one ISA, while other cores may be capable of executing only a subset of the ISA or another ISA. The processor cores 102(A)-(N) may employ various instruction set architectures, and the present disclosure is not limited thereto.

[0026] Several techniques have been developed for collecting GPR values ​​in commercial processors. PR value analysis usually involves recording GPR values ​​using performance monitoring unit (PMU) hardware when a specific sampling trigger is activated. For example, Intel x86 processors are equipped with Precise Event Based Sampling (PEBS), which can record a series of key information such as branch history, GPR values, and memory read and write events in detail. PEBS and similar techniques use PMU counters and their overflow events as sampling triggers to sample the required values ​​at a preset frequency. This approach often produces a large set of execution profiles, which are interspersed with a large amount of data that is not necessary for PGO. This not only greatly wastes storage space, but also increases the cost burden of the sampling process. In addition, such PMU techniques have limitations in achieving fine-grained control, which is manifested in the inability to flexibly set trigger recording for specific instructions. At the same time, the sampling mechanism relies on the triggering of interrupt signals, which means that the operating system (OS) kernel (that is, the software in hypervisor mode) must intervene to dump the sampled data into memory, resulting in a lack of efficiency in statistical and aggregate processing of the data.

[0027] In addition, some compilers such as the Low-Level Virtual Machine (LLVM) provide a stub method for probing GPR values. This method records and stores register values ​​by inserting a code segment before a specific area of ​​the target program. Although this technology can accurately record relevant information about specific instructions, the resulting context save / restore operations and frequent memory accesses bring a considerable performance burden to the system.

[0028] Figure 2 FIG. 1 shows a schematic diagram of a value analysis process based on traditional sampling. The process is initiated when a PMU counter overflow event is triggered. Figure 2 As shown in the figure, the process includes the following steps: 1) the overflow event of the PMU counter of the CPU core triggers an interrupt; 2) the OS software reads the overflow event metadata to store it in the event buffer of the kernel space; 3) the OS software reads the values ​​of all GPRs and stores them in the event buffer of the kernel space in a manner associated with the event metadata; 4) the raw event data in the buffer is written to the performance (perf) data file; 5) the aggregation tool in the user space software reads data from the data file to collect events; 6) the aggregation tool in the user space software generates a value distribution graph for each GPR when the event is triggered.

[0029] exist Figure 2In the traditional profiling process shown, the profiling tool cannot control which GPRs are sampled and when the GPRs are sampled. This usually results in a large amount of performance data and wastes a lot of time on data collection and aggregation calculation.

[0030] In view of the above problems, the present disclosure provides a new technology for general register value profiling of RISC-V processors. The proposed value profiling framework utilizes RISC-V HINT instructions and CSR space to achieve precise control of GPR value sampling, while allowing real-time aggregation of profiling data during execution. This method significantly reduces the size of sampling profiles and data, and minimizes the associated profiling burden.

[0031] Specifically, in an embodiment of the present disclosure, on the one hand, a RISC-V HINT instruction is used as a trigger for GPR value profiling; on the other hand, a specialized hardware structure (i.e., a hardware counter) dedicated to real-time statistical performance data aggregation is introduced into the RISC-V core, and a customized value profiling CSR is used to configure and control the specialized hardware structure and retrieve the data aggregated therein.

[0032] Figure 3 FIG. 1 shows a flow chart of general register value analysis for a RISC-V processor according to an embodiment of the present disclosure. Figure 3 As shown, the process includes: 1) initializing a value profiling configuration CSR to store a selected GPR and multiple thresholds for aggregating sampled values ​​in the value profiling configuration CSR, wherein the selection of the target GPR and the threshold is implemented by writing a value profiling configuration CSR named, for example, vpcfg0 to vpcfgX; 2) executing a RISC-V HINT instruction to trigger value profiling of the target GPR, wherein the instruction is inserted into a program executable and linkable format (ELF) file before the target hot zone; 3) in response to the execution of the RISC-V HINT instruction, the CPU core can automatically increment a set of hardware counters through aggregation logic to achieve aggregation of sampled values, wherein the aggregated counter data is saved in a value profiling data CSR named, for example, vpdata0 to vpdataX; 4) after the target program is executed, the GPR value distribution of the target GPR can be directly read from the data CSR, for example, for use by a PGO tool.

[0033] Figure 4 FIG. 2 shows an example field encoding structure diagram of a value parsing configuration CSR according to an embodiment of the present disclosure. Figure 4 The field encoding of the value parsing configuration CSR shown is shown as being implemented in a 64-bit RISC-V CPU. It can be understood that the embodiments of the present application can also be implemented in a 32-bit RISC-V CPU based on limited modifications.

[0034] like Figure 4 As shown, the value parsing configuration CSR (named vpcfgX, where X is the index value of the relevant CSR) is used to store mode parameters, the number of the target general register, and multiple thresholds for comparison with the value of the target general register, wherein the multiple thresholds are used as numerical values ​​for exact comparison in AGGR_EXACT mode, and as demarcation thresholds for multiple intervals in AGGR_RANGE mode. Specifically, bits 62-63 of vpcfgX are the mode field, bits 57-61 are the target number (xtarget) field, bits 0-7, 8-15, 16-23, and 24-31 are 4 value (value#, where # is 0-3) fields, and bits 32-37, 38-43, 44-49, and 50-55 are four shift amount (shamt#, where # is 0-3) fields. Table 1 shows the configuration structure and field definitions of the value parsing configuration CSR.

[0035] Table 1

[0036]

[0037] As shown in Table 1, the encoding of the CSR field uses a value and displacement representation method to encode larger values ​​within a limited number of bits.

[0038] Figure 5 FIG. 2 shows an example field encoding structure diagram of the value analysis data CSR according to an embodiment of the present disclosure. Figure 5 The field encoding of the value parsing data CSR shown is shown as being implemented in a 64-bit RISC-V CPU. It can be understood that the embodiments of the present application can also be implemented in a 32-bit RISC-V CPU based on limited modifications.

[0039] In order to simplify the expression, cvalue# is defined, where cvalue# represents the result of shifting the value in the value# field of the value parsing configuration CSR left by shamt# bits.

[0040] like Figure 5 As shown, bits 0-15, 16-31, 32-47, 48-63 of the value parsing data CSR (named vpdataX, where X corresponds to the index value of the CSR) are four count value (count#) fields. Table 2 shows the configuration structure and field definition of the value parsing data CSR.

[0041] Table 2

[0042]

[0043] As shown in Table 2, the count3 field of the value profiling data CSR is used to record the number of times the register value in the target GPR indicated by the xtarget field is equal to cvalue3 when the mode field of the corresponding configuration CSR is set to 10, or to record the number of times the register value in the target GPR is greater than or equal to cvalue3 when the mode field of the corresponding configuration CSR is set to 11; the count2 field is used to record the number of times the register value in the target GPR indicated by the xtarget field is equal to cvalue2 when the mode field of the corresponding configuration CSR is set to 10, or to record the number of times the register value in the target GPR is greater than or equal to cvalue2 and less than cvalue3 when the mode field of the corresponding configuration CSR is set to 11. The count1 field is used to record the number of times the register value in the target GPR indicated by the xtarget field is equal to cvalue1 when the mode field of the corresponding configuration CSR is set to 10, or the number of times the register value in the target GPR is greater than or equal to cvalue1 and less than cvalue2 when the mode field of the corresponding configuration CSR is set to 11; the count0 field is used to record the number of times the register value in the target GPR indicated by the xtarget field is equal to cvalue0 when the mode field of the corresponding configuration CSR is set to 10, or the number of times the register value in the target GPR is greater than or equal to cvalue0 and less than cvalue1 when the mode field of the corresponding configuration CSR is set to 11.

[0044] Figure 6 FIG. 1 shows an example field encoding structure diagram of a RISC-V HINT instruction according to an embodiment of the present disclosure. Figure 6 In the example shown, the HINT.VP instruction is encoded as an SLLIW instruction, where rd = x0. This instruction has no effect on cores that do not support the HINT instruction. In other examples of the present disclosure, the HINT.VP instruction can be encoded as any other instruction that does not actually perform any operation, and the present application does not make specific restrictions on this.

[0045] On a core supporting the present disclosure, the HINT.VP instruction triggers all comparison and counting logic in the hardware to capture and count the value of the target GPR (the value before the HINT.VP execution) based on the configuration in the vpcfg CSR. The HINT.VP instruction causes the count in the vpdataX CSR to be updated according to the configuration in the vpcfgX CSR.

[0046] In an embodiment of the present disclosure, the RISC-V HINT instruction may be used to trigger the profiling of values ​​of multiple target GPRs simultaneously. In an embodiment of the present disclosure, the RISC-V HINT instruction may be used to trigger the profiling of multiple sets of ranges or values ​​of a GPR simultaneously.

[0047] like Figure 6 As shown, the fields vp1 and vp2 in the HINT.VP instruction are used to store the index (X) of the vpdataX and vpcfgX CSRs. This instruction can trigger two entry updates at the same time, which means that two GPRs can be profiled at the same time, or two sets of ranges / values ​​of one GPR can be profiled. Since the HINT.VP instruction does not change any architectural state, multiple HINT.VP instructions can be executed to monitor more GPRs or more sets of ranges / values.

[0048] The following is an example use case for applying the present disclosure. In applications written in C / C++, it is very common to call standard library functions. For simple library functions such as memcpy() or memset() in small memory areas, these calls may cause huge overhead. Through value profiling, the PGO tool can automatically convert small memory operation calls into simple assembly instructions, thereby avoiding the overhead caused by frequent calls to library functions. Figure 7 The disassembly code of the RISC-V memset() function is shown. In the RISC-V architecture, the memset() function is usually used to copy a specified value to a memory area. Its parameters include the target memory address (ptr) stored in GPR a0, a1, and a2, the specified value (value), and the specified number of bytes (num). When the num parameter is small, calling the full memset() function may become inefficient due to the overhead of the function call. In this case, PGO technology can identify these small memory setting operations by analyzing the runtime performance data of the program and optimize them in the subsequent compilation process.

[0049] According to an embodiment of the present disclosure, in order to analyze the num parameter of the RISC-V memset() function at runtime, the compiler may perform the following operations:

[0050] 1) Inject a code segment for initializing a random vpcfg CSR before main() of the program, where the xtarget field of the vpcfg CSR can be set to a2, the mode field can be set to AGGR_RANGE, and the cvalueX field can be set to a small common value (for example, 0, 4, 8, 16);

[0051] 2) Inject a HINT.VP instruction at the beginning of the memset() function, where the vp1 field of the HINT.VP instruction is set to the index value of the initialized vpcfg entry;

[0052] 3) A code segment for disabling numerical profiling is injected after the program main(), so that in response to the execution of the code segment, the data in the vpdata CSR is read out, thereby generating a report for the value distribution of the num parameter of the memset() function.

[0053] By analyzing the value distribution report of the num parameter, PGO technology can avoid unnecessary library function calls, reduce runtime overhead, and improve performance by, for example, inlining expansion and specialization of code.

[0054] Figure 8 A flow chart of a method 800 for general register value analysis of a RISC-V processor according to an embodiment of the present disclosure is shown. In one embodiment, method 800 may be performed by a RISC-V processor. In another embodiment, method 800 may be performed by a processor supporting any other instruction set. Method 800 may include steps S802, S804, and S806. However, in some embodiments, method 800 may include more or fewer different steps, which is not limited by the present disclosure.

[0055] In step S802, a target instruction to be monitored and a target general register of a plurality of general registers of a RISC-V processor for which a value analysis is to be performed on the target instruction are determined;

[0056] In step S804, a RISC-V HINT instruction is inserted before the target instruction;

[0057] In step S806, in response to the execution of the RISC-V HINT instruction, value analysis of the target general register is triggered.

[0058] In an embodiment of the present disclosure, the method further includes: before executing the RISC-V HINT instruction, initializing a value analysis configuration CSR to store the number of a target general register and a plurality of thresholds for comparison with the value of the target general register in the value analysis configuration CSR.

[0059] In an embodiment of the present disclosure, triggering value profiling of a target general register in response to execution of a RISC-V HINT instruction includes: capturing current values ​​of all general registers of a RISC-V processor in response to execution of the RISC-V HINT instruction; and updating the value profiling configuration CSR according to the configuration of the value profiling configuration CSR.

[0060] New value analysis data CSR, wherein the value analysis data CSR is used to store the value distribution result of the target general register.

[0061] In an embodiment of the present disclosure, updating the value profiling data CSR according to the configuration of the value profiling configuration CSR includes: automatically incrementing a hardware counter in a set of hardware counters based on a comparison between a current value of a captured target general register and a plurality of thresholds stored in the value profiling configuration CSR; and storing the counting results of the set of hardware counters in the value profiling data CSR.

[0062] In an embodiment of the present disclosure, the method further includes: based on parameter configuration of the value profiling configuration CSR, configuring a group of hardware counters to use precise values ​​to perform aggregate statistics on the values ​​of the target general registers.

[0063] In an embodiment of the present disclosure, the method further comprises: based on parameter configuration of a value profiling configuration CSR, configuring a group of hardware counters to use a value range to perform aggregate statistics on the value of the target general register.

[0064] In an embodiment of the present disclosure, the method further includes: after executing the target instruction, directly reading the value distribution result stored in the target general register from the value profiling data CSR for use by a profile guided optimization (PGO) tool.

[0065] In an embodiment of the present disclosure, inserting a RISC-V HINT instruction before the target instruction includes: inserting a RISC-V HINT instruction in an executable and linkable format (ELF) file before the target instruction.

[0066] In an embodiment of the present disclosure, a RISC-V HINT instruction is used to trigger value analysis of multiple target general registers at the same time.

[0067] In an embodiment of the present disclosure, a RISC-V HINT instruction is used to simultaneously trigger profiling of multiple groups of ranges or values ​​of a general register.

[0068] The present disclosure provides a new technique for general register value profiling for RISC-V processors. The proposed value profiling framework utilizes RISC-V HINT instructions and CSR space to achieve precise control over GPR value sampling, while allowing real-time aggregation of profiling data during execution. This method significantly reduces the size of sampling profiles and data, and minimizes the associated profiling burden.

[0069] Fig. 9 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Specifically, Fig. 9A schematic diagram of hardware resources 900 is shown, which includes one or more processors (or processor cores) 910, one or more memory / storage devices 920, and one or more communication resources 930, wherein each of these processors, memory / storage devices, and communication resources can be communicatively coupled via a bus 940 or other interface circuits. For embodiments utilizing node virtualization (e.g., network function virtualization (NFV)), a hypervisor 902 can be executed to provide an execution environment for one or more network slices / sub-slices to utilize hardware resources 900.

[0070] Processor 910 may include, for example, processor 912 and processor 914. Processor 910 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0071] The memory / storage device 920 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 920 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0072] The communication resources 930 may include interconnect or network interface controllers, components, or other suitable devices to communicate with one or more peripheral devices 904 or one or more databases 906 or other network elements via the network 908. For example, the communication resources 930 may include wired communication components (e.g., for coupling via USB, Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® low energy) components, Wi-Fi® components, and other communication components.

[0073] The instructions 950 may include software, programs, applications, applet, applications, or other executable code for causing at least any one of the processors 910 to perform any one or more of the methods discussed herein. The instructions 950 may reside in whole or in part in at least one of the processors 910 (e.g., in a cache of the processor), the memory / storage device 920, or any suitable combination thereof. In addition, any portion of the instructions 950 may be transmitted to the hardware resources 900 from any combination of the peripheral device 904 or the database 906. Therefore, the memory of the processor 910, the memory / storage device 920, the peripheral device 904, and the database 906 are examples of computer-readable and machine-readable media.

[0074] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, APIs, instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination of these.

[0075] According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that, when executed by a machine, a computing device, or a system, cause the machine, the computing device, or the system to perform methods and / or operations according to the described examples. The instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, a computing device, or a system to perform a specific function. The instructions may be implemented using any appropriate high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0076] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium representing various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores", may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to load into fabrication machines that actually fabricate the logic or processor.

[0077] The appearance of the phrase "an example" or "an example" does not necessarily refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, whether or not these aspects are described with respect to the same figure or element. The division, omission or inclusion of block functions depicted in the figures does not infer that the hardware components, circuits, software and / or elements used to implement these functions will necessarily be divided, omitted or included in the embodiments.

[0078] Some examples may be described using the expressions "coupled" and "connected," and their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also refer to two or more elements that are not in direct contact with each other, but still cooperate or interact with each other.

[0079] The terms "first", "second" and the like do not represent any order, quantity or importance in this article, but are used to distinguish one element from another element. The term "one" herein does not represent a limitation on quantity, but rather represents the presence of at least one item mentioned. The term "assertion" used when referring to a signal herein refers to a state of the signal, in which the signal is valid, and the state can be achieved by applying any logic level (whether logic 0 or logic 1) to the signal. The term "subsequently" or "afterwards" may refer to immediately following or following some or some other event. According to alternative embodiments, other step sequences may also be performed. In addition, depending on the specific application, additional steps may be added or removed. Any combination of variations may be used, and those of ordinary skill in the art who benefit from the present disclosure will understand its many variations, modifications and alternative embodiments.

[0080] Unless specifically stated otherwise, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood within the context to be generally used to state that an item, term, etc. can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require the presence of each of at least one X, at least one Y, or at least one Z. Furthermore, unless specifically stated otherwise, conjunctive language such as the phrase "at least one of X, Y, and Z" should also be understood to refer to X, Y, Z, or any combination thereof, including "X, Y, and / or Z."

Claims

1. A method for general register value analysis of a RISC-V processor, comprising: Determine a target instruction to be monitored and a target general register among multiple general registers of the RISC-V processor for value analysis of the target instruction; Insert RISC-V HINT instruction before the target instruction; Before executing the RISC-V HINT instruction, initialize the value profiling configuration control and status register CSR to store the number of the target general register and a plurality of thresholds for comparison with the value of the target general register in the value profiling configuration CSR; as well as In response to the execution of the RISC-V HINT instruction, the value analysis of the target general register is triggered, specifically including: In response to execution of a RISC-V HINT instruction, capturing current values ​​of all general registers of the RISC-V processor; and The value analysis data CSR is updated according to the configuration of the value analysis configuration CSR, wherein the value analysis data CSR is used to store the value distribution result of the target general register, Wherein, updating the value profiling data CSR according to the configuration of the value profiling configuration CSR comprises: automatically incrementing a hardware counter from a set of hardware counters based on a comparison of a current value of a captured target general register to a plurality of thresholds stored in a value profiling configuration CSR; and The count results of a set of hardware counters are stored in the value profile data CSR.

2. The method according to claim 1, further comprising: Based on the parameter configuration of the value profiling configuration CSR, a group of hardware counters are configured to aggregate statistics on the values ​​of target general registers using precise values.

3. The method according to claim 1, further comprising: Based on parameter configuration of the value profiling configuration CSR, a group of hardware counters are configured to aggregate statistics on the values ​​of target general registers using a value range.

4. The method according to any one of claims 1 to 3, further comprising: After executing the target instruction, the value distribution results stored in the target general registers are read directly from the value profiling data CSR for use by the Profile Guided Optimization (PGO) tool.

5. The method according to any one of claims 1 to 3, wherein: The inserting of the RISC-VHINT instruction before the target instruction comprises: Inserts RISC-V HINT instructions in an Executable and Linkable Format (ELF) file before the target instructions.

6. The method according to any one of claims 1 to 3, wherein: The RISC-V HINT instruction is used to trigger the analysis of the values ​​of multiple target general registers simultaneously.

7. The method according to any one of claims 1 to 3, wherein: The RISC-V HINT instruction is used to trigger the profiling of multiple sets of ranges or values ​​of a general register simultaneously.

8. A device for general register value analysis of a RISC-V processor, comprising: processor; as well as a memory coupled to the processor and containing instructions stored thereon, the instructions, when executed by the processor, causing the processor to perform the following operations: Determine a target instruction to be monitored and a target general register among multiple general registers of the RISC-V processor for value analysis of the target instruction; inserting a RISC-V HINT instruction before said instruction; Before executing the RISC-V HINT instruction, initialize the value profiling configuration control and status register CSR to store the number of the target general register and a plurality of thresholds for comparison with the value of the target general register in the value profiling configuration CSR; as well as In response to the execution of the RISC-V HINT instruction, the value analysis of the target general register is triggered, specifically including: In response to execution of a RISC-V HINT instruction, capturing current values ​​of all general registers of the RISC-V processor; and The value analysis data CSR is updated according to the configuration of the value analysis configuration CSR, wherein the value analysis data CSR is used to store the value distribution result of the target general register, The instructions further cause the processor to: automatically incrementing a hardware counter from a set of hardware counters based on a comparison of a current value of a captured target general register to a plurality of thresholds stored in a value profiling configuration CSR; and The count results of a set of hardware counters are stored in the value profile data CSR.

9. The device according to claim 8, wherein: The instructions further cause the processor to: Based on the parameter configuration of the value profiling configuration CSR, a group of hardware counters are configured to aggregate statistics on the values ​​of target general registers using precise values.

10. The device according to claim 8, wherein: The instructions further cause the processor to: configure the set of hardware counters to perform aggregate statistics on the value of the target general register using a value range based on the parameter configuration of the value profiling configuration CSR.

11. The device according to any one of claims 8 to 10, wherein: The instructions further cause the processor to: After executing the target instruction, the value distribution results stored in the target general registers are read directly from the value profiling data CSR for use by the Profile Guided Optimization (PGO) tool.

12. The device according to any one of claims 8 to 10, wherein: The instructions further cause the processor to: Inserts RISC-V HINT instructions in an Executable and Linkable Format (ELF) file before the target instructions.

13. The apparatus according to any one of claims 8 to 10, wherein: The RISC-V HINT instruction is used to trigger the analysis of the values ​​of multiple target general registers simultaneously.

14. The apparatus according to any one of claims 8 to 10, wherein: The RISC-V HINT instruction is used to trigger the profiling of multiple sets of ranges or values ​​of a general register simultaneously.

15. A computer-readable storage medium having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1-7.

16. A computer program product having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 7.

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