Instruction execution method and related equipment
By using the identification information carried by the instructions in the processor to allocate pipeline resources, multiple instructions are executed in parallel, solving the problem of waste of pipeline resources in the prior art and improving processor performance.
Patent Information
- Application Number
- CN202411368246.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2024-12-27
AI Technical Summary
When executing memory access instructions, some resources are not fully utilized, resulting in waste of pipeline resources, affecting processor performance.
The identification information carried by the instructions determines the pipeline resources required for its execution, allocates pipeline resources to achieve parallel execution of multiple instructions, and improves the utilization rate of pipeline resources.
Reduces instruction delay due to pipeline bandwidth limitations and improves processor performance.
Smart Images
Figure CN119201235A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to an instruction execution method and related equipment. Background Art
[0002] Existing processors allow instructions to be executed that occupy all the resources of the corresponding pipeline. However, since some memory access instructions may only occupy part of the resources of the pipeline when executed, this may lead to a waste of pipeline resources. Summary of the invention
[0003] The present application discloses an instruction execution method and related equipment to improve the utilization rate of pipeline resources.
[0004] In a first aspect, the present application discloses an instruction execution method, comprising: obtaining an instruction to be executed, the instruction carrying identification information; based on the identification information, determining the pipeline resources that need to be occupied when the instruction is executed; if the identification information indicates that the instruction needs to occupy a part of all the resources of the pipeline when it is executed, then allocating a part of all the resources of the pipeline to the instruction, and allocating another part of all the resources of the pipeline to other instructions to be executed, the other instructions including instructions that need to occupy another part of all the resources of the pipeline when executed, and controlling the pipeline to execute the instruction and the other instructions in parallel.
[0005] In some embodiments, it also includes: if the identification information indicates that the instruction needs to occupy all resources of the pipeline when executed, all resources of the pipeline are allocated to the instruction, and the pipeline is controlled to execute the instruction.
[0006] In some embodiments, if the identification information indicates that the instruction needs to occupy a part of all resources of the pipeline when executed, then a part of all resources of the pipeline are allocated to the instruction, and another part of all resources of the pipeline are allocated to other instructions to be executed, and the pipeline is controlled to execute the instruction and the other instructions in parallel, including: if the identification information indicates that the instruction is a first instruction, the first instruction includes an instruction that needs to occupy a first resource of the pipeline when executed, and the other instructions to be executed include a second instruction, the second instruction includes an instruction that needs to occupy a second resource of the pipeline when executed, and all resources of the pipeline include the first resource and the second resource, then the first resource is allocated to the first instruction, the second resource is allocated to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel.
[0007] In some embodiments, it also includes: if the identification information indicates that the instruction is the first instruction, and other instructions to be executed do not include the second instruction but include a third instruction and / or a fourth instruction, the third instruction includes an instruction that needs to occupy a third resource of the pipeline when executed, and the fourth instruction includes an instruction that needs to occupy a fourth resource of the pipeline when executed, and the second resource includes the third resource and the fourth resource, then the first resource is allocated to the first instruction, the third resource is allocated to the third instruction, and / or the fourth resource is allocated to the fourth instruction, and the pipeline is controlled to execute the first instruction, the third instruction and / or the fourth instruction in parallel.
[0008] In some embodiments, it also includes: if the identification information indicates that the instruction is the second instruction, and other instructions to be executed include the first instruction, the first resource is allocated to the first instruction, the second resource is allocated to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel; if the identification information indicates that the instruction is the third instruction, and other instructions to be executed include the first instruction and / or the fourth instruction, the first resource is allocated to the first instruction, and / or the fourth resource is allocated to the fourth instruction, and the pipeline is controlled to execute the first instruction and / or the fourth instruction in parallel; if the identification information indicates that the instruction is the fourth instruction, and other instructions to be executed include the first instruction and / or the third instruction, the first resource is allocated to the first instruction, and / or the third resource is allocated to the third instruction, and the pipeline is controlled to execute the first instruction and / or the third instruction in parallel.
[0009] In some embodiments, the first resource includes a bus of the pipeline; the second resource includes a port of a first-level cache of the pipeline; the third resource includes an access port of a data array of the first-level cache of the pipeline; and the fourth resource includes an access port of an address array of the first-level cache of the pipeline.
[0010] In some embodiments, the identification information includes numerical information, and different numerical information indicates different pipeline resources that need to be occupied when the instruction is executed.
[0011] In some embodiments, the identification information includes instruction queue information, which is used to indicate the instruction queue from which the instruction comes and the pipeline resources that need to be occupied when the instructions in the instruction queue are executed. The instructions in the same instruction queue require the same pipeline resources to be occupied when they are executed, and the instructions in different instruction queues require different pipeline resources to be occupied when they are executed.
[0012] In some embodiments, before obtaining the instructions to be executed, it also includes: based on the numerical information carried by each instruction in the multiple instructions, dividing the multiple instructions into multiple instruction queues, and making the instructions in the same instruction queue require the same pipeline resources when executing, and making the instructions in different instruction queues require different pipeline resources when executing; wherein different numerical information represents different pipeline resources that need to be occupied when the instructions are executed.
[0013] In some embodiments, the multiple instruction queues include a first instruction queue, a second instruction queue, a third instruction queue, a fourth instruction queue and a fifth instruction queue; when the instructions in the first instruction queue are executed, they need to occupy the first resource of the pipeline; when the instructions in the second instruction queue are executed, they need to occupy the third resource and the fourth resource of the pipeline; when the instructions in the third instruction queue are executed, they need to occupy the third resource of the pipeline; when the instructions in the fourth instruction queue are executed, they need to occupy the fourth resource of the pipeline; when the instructions in the fifth instruction queue are executed, they need to occupy the first resource, the third resource and the fourth resource of the pipeline.
[0014] In some embodiments, the obtaining of the instruction to be executed includes: obtaining the oldest instruction among all the instructions in the multiple instruction queues as the instruction to be executed. In some embodiments, the oldest instruction in each of the multiple instruction queues is obtained; if it is determined based on the instruction queue information that the instructions in any two instruction queues need to occupy the same pipeline resources when executing, then the oldest instruction among the oldest instructions in the two instruction queues is used as the instruction to be executed; if it is determined based on the instruction queue information that the instructions in any two instruction queues need to occupy different pipeline resources when executing, then the oldest instructions in the two instruction queues are respectively used as the instruction to be executed and the other instruction to be executed.
[0015] In a second aspect, the present application discloses a processor configured to execute the instruction execution method as described in any one of the above items.
[0016] In a third aspect, the present application discloses an electronic device, comprising the processor as described above.
[0017] In a fourth aspect, the present application discloses a computer-readable storage medium having stored thereon instructions for causing a computer to execute the instruction execution method as described in any one of the above items.
[0018] The instruction execution method and related devices disclosed in the present application determine the pipeline resources that need to be occupied when the instruction is executed through the identification information carried by the instruction. If the instruction only needs to occupy a part of the total resources of the pipeline when it is executed, then a part of the total resources of the pipeline are allocated to the instruction, and another part of the total resources of the pipeline are allocated to other instructions to be executed, and the other instructions include instructions that need to occupy another part of the total resources of the pipeline when executed. By making the pipeline execute the instruction and the other instructions in parallel, the resource utilization of the pipeline is improved, thereby reducing the instruction delay caused by the pipeline bandwidth limitation, and thereby improving the performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.
[0020] Figure 1 A flowchart of an instruction execution method disclosed in an embodiment of the present application.
[0021] Figure 2 A schematic diagram of the instruction execution process of an instruction execution method disclosed in an embodiment of the present application.
[0022] Figure 3 A schematic diagram of the instruction execution process of another instruction execution method disclosed in an embodiment of the present application. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0024] The number of instructions that existing processors allow to be executed is tightly coupled to the number of pipelines. That is, if a processor has N pipelines, the processor allows N pipelines to execute N instructions in parallel, and allows each instruction to occupy all the resources of a corresponding pipeline, where N is a natural number greater than or equal to 2. However, because some instructions do not need to occupy all the resources of the corresponding pipeline when executing, but only need to occupy part of the resources of the pipeline, it will lead to a waste of pipeline resources.
[0025] For example, existing processors allow the execution of memory access instructions to occupy the corresponding pipeline result bus, the access port of the data array of the first-level cache, and the access port of the address (tag) array. However, when the pipeline executes certain memory access instructions, if the first-level cache of the pipeline does not have the data that the memory access instruction needs to access, it is necessary to use the result bus of the pipeline to obtain data from the lower-level cache of the first-level cache (such as the second-level cache or the third-level cache). At this time, the memory access instruction only needs to occupy the result bus of the pipeline, and does not need to access the first-level cache, that is, it does not need to occupy the access port of the data array and the access port of the address array of the first-level cache. Therefore, it will cause a waste of the access port of the data array and the access port of the address array of the first-level cache.
[0026] Based on this, the present application discloses an instruction execution scheme, which determines the pipeline resources that need to be occupied when the instruction is executed through the identification information carried by the instruction. If the instruction only needs to occupy a part of the total resources of the pipeline when it is executed, then a part of the total resources of the pipeline will be allocated to the instruction, and another part of the total resources of the pipeline will be allocated to other instructions to be executed, and the pipeline will be controlled to execute instructions and other instructions in parallel to improve the utilization of pipeline resources.
[0027] As an optional implementation of the content disclosed in the present application, the embodiment of the present application discloses an instruction execution method, which is applied to a processor, and the processor includes one or more pipelines, such as Figure 1 As shown, Figure 1 This is a flowchart of an instruction execution method disclosed in an embodiment of the present application, the method comprising:
[0028] S101: Obtain an instruction to be executed, where the instruction carries identification information.
[0029] In an embodiment of the present application, the identification information carried by the instruction can be used to identify the resources of the pipeline that need to be occupied when the instruction is executed. It should be noted that the identification information can be a manually set variable, and different identification information carried by the instruction will require different resources of the pipeline to be occupied by the instruction. For example, if the instruction carries the first identification information, it means that the instruction needs to occupy the first resource of the pipeline; if the instruction carries the second identification information, it means that the instruction needs to occupy the second resource of the pipeline, where the second resource is different from the first resource.
[0030] S102: Based on the identification information, determine the pipeline resources that need to be occupied when the instruction is executed.
[0031] In an embodiment of the present application, the pipeline resources that need to be occupied when the instruction is executed can be determined based on the identification information carried by the instruction. For example, if the first identification information carried by the instruction indicates that the instruction needs to occupy the first resource of the pipeline, and the first resource is part of the resources of the pipeline, then the instruction does not need to occupy all the resources of the pipeline when it is executed.
[0032] Taking the example that the pipeline resources include the result bus, the access port of the data array of the first-level cache, and the access port of the address array, if the identification information carried by the instruction indicates that the instruction needs to occupy the result bus of the pipeline, then the instruction does not need to occupy all the resources of the pipeline when executed.
[0033] S103: If the identification information indicates that the instruction needs to occupy a part of all the resources of the pipeline when it is executed, then a part of all the resources of the pipeline are allocated to the instruction, and another part of all the resources of the pipeline are allocated to other instructions to be executed, the other instructions include instructions that need to occupy another part of all the resources of the pipeline when they are executed, and the pipeline is controlled to execute the instruction and the other instructions in parallel.
[0034] In some embodiments of the present application, if it is determined based on the identification information of the instruction that the instruction only needs to occupy a part of all the resources of the pipeline when executed, then other instructions to be executed are obtained, and the other instructions include instructions that need to occupy another part of all the resources of the pipeline when executed, and a part of all the resources of the pipeline are allocated to the instruction, and another part of all the resources of the pipeline are allocated to the other instructions, and the pipeline is controlled to execute the instruction and the other instructions in parallel.
[0035] Taking the case where the resources of a pipeline include a result bus, an access port of a data array of a first-level cache, and an access port of an address array as an example, if it is determined based on the identification information carried by the instruction that the instruction only needs to occupy the result bus of the pipeline when executed, then other instructions to be executed are obtained, and the other instructions include instructions that need to occupy the access port of the data array and / or the access port of the address array of the first-level cache of the pipeline when executed, the result bus of the pipeline is assigned to the instruction, the access port of the data array and / or the access port of the address array of the first-level cache of the pipeline is assigned to the other instruction, and the pipeline is controlled to execute the instruction and the other instruction in parallel.
[0036] Based on this, compared with allowing the pipeline to execute only the instruction that needs to occupy part of the resources of the pipeline, allowing the pipeline to execute in parallel the instruction and the other instructions that occupy different resources of the pipeline respectively can improve the resource utilization of the pipeline, thereby reducing the instruction delay caused by the pipeline bandwidth limitation, and thus improving the performance of the processor.
[0037] Of course, in other embodiments of the present application, if the identification information indicates that the instruction needs to occupy all the resources of the pipeline when executed, all the resources of the pipeline are allocated to the instruction, and the pipeline is controlled to execute the instruction.
[0038] Taking the example that the resources of the pipeline include the result bus, the access port of the data array of the first-level cache, and the access port of the address array, if it is determined based on the identification information carried by the instruction that the execution of the instruction needs to occupy the result bus of the pipeline, the access port of the data array of the first-level cache, and the access port of the address array, then other instructions are not obtained, but all the resources of the pipeline are allocated to the instruction, and the pipeline is controlled to execute the instruction.
[0039] In some embodiments of the present application, based on the identification information of the instruction, it is determined whether the instruction is a first instruction, and the first instruction includes an instruction that needs to occupy a first resource of the pipeline when executed; if the identification information indicates that the instruction is the first instruction, and other instructions to be executed include a second instruction, and the second instruction includes an instruction that needs to occupy a second resource of the pipeline when executed, and the resources of the pipeline include a first resource and a second resource, then the second instruction is obtained, the first resource of the pipeline is allocated to the first instruction, the second resource of the pipeline is allocated to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel.
[0040] Take the case where the resources of the pipeline include the result bus, the access port of the data array of the first level cache, and the access port of the address array as an example for explanation. If the instruction is the first instruction, and the first instruction is an instruction that needs to occupy the result bus of the pipeline, i.e., the first resource, when executed, then determine whether the other instructions to be executed include the second instruction, and the second instruction is an instruction that needs to occupy the access port of the data array of the first level cache of the pipeline, i.e., the access port of the address array, i.e., the second resource, when executed, if the other instructions to be executed include the second instruction, then the result bus of the pipeline is allocated to the first instruction, the access port of the data array of the first level cache of the pipeline and the access port of the address array are allocated to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel. At this time, all the resources of the pipeline are utilized, so that the resource utilization rate of the pipeline is high.
[0041] It should be noted that the first instruction may be a load instruction for obtaining data from a lower level cache of the first level cache, and the second instruction may be a backfill instruction for backfilling data obtained from the lower level cache of the first level cache to the first level cache.
[0042] In some other embodiments of the present application, if the identification information indicates that the instruction is the first instruction, and the other instructions to be executed do not include the second instruction but include the third instruction and / or the fourth instruction, the third instruction includes an instruction that needs to occupy the third resource of the pipeline when executed, and the fourth instruction includes an instruction that needs to occupy the fourth resource of the pipeline when executed, and the second resource includes the third resource and the fourth resource, then the third instruction and / or the fourth instruction is obtained, the first resource of the pipeline is allocated to the first instruction, the third resource of the pipeline is allocated to the third instruction, and / or the fourth resource of the pipeline is allocated to the fourth instruction, and the pipeline is controlled to execute the first instruction, the third instruction and / or the fourth instruction in parallel.
[0043] Taking the case where the resources of the pipeline include a result bus, an access port of a data array of a first-level cache, and an access port of an address array as an example, if the instruction is a first instruction, and the first instruction is an instruction that needs to occupy the result bus of the pipeline, i.e., the first resource, when executed, then determine whether the other instructions to be executed include a second instruction, and the second instruction is an instruction that needs to occupy the access port of the data array of the first-level cache of the pipeline, i.e., the second resource, when executed. If the other instructions to be executed do not include the second instruction, then determine whether the other instructions to be executed include a third instruction and / or a fourth instruction, and the third instruction The first instruction is an instruction that needs to occupy the access port of the data array of the first-level cache of the pipeline, i.e., the third resource, when executed. The fourth instruction is an instruction that needs to occupy the access port of the address array of the first-level cache of the pipeline, i.e., the fourth resource, when executed. If the other instructions to be executed include the third instruction and / or the fourth instruction, the result bus of the pipeline is assigned to the first instruction, the access port of the data array of the first-level cache of the pipeline is assigned to the third instruction, and / or the access port of the address array of the first-level cache of the pipeline is assigned to the fourth instruction, and the pipeline is controlled to execute the first instruction, the third instruction and / or the fourth instruction in parallel.
[0044] It should be noted that the first instruction may be a load instruction for obtaining data from a lower-level cache of the first-level cache, the second instruction may be a backfill instruction for backfilling data obtained from the lower-level cache of the first-level cache to the first-level cache, and the third instruction may be an instruction for pre-accessing the access port of the address array of the first-level cache to determine whether the address array of the first-level cache contains the address of the data to be accessed, wherein if the address array of the first-level cache contains the address of the data to be accessed, the address information is recorded; the fourth instruction may be an instruction for storing the data in the data array of the first-level cache based on the recorded address information.
[0045] In some other embodiments of the present application, if the identification information indicates that the instruction is the second instruction, and the other instructions to be executed include the first instruction, then the first instruction is obtained, the first resource of the pipeline is allocated to the first instruction, the second resource of the pipeline is allocated to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel; if the identification information indicates that the instruction is the third instruction, and the other instructions to be executed include the first instruction and / or the fourth instruction, then the first instruction and / or the fourth instruction are obtained, the first resource of the pipeline is allocated to the first instruction, and / or the fourth resource of the pipeline is allocated to the fourth instruction, and the pipeline is controlled to execute the first instruction and / or the fourth instruction in parallel; if the identification information indicates that the instruction is the fourth instruction, and the other instructions to be executed include the first instruction and / or the third instruction, then the first instruction and / or the third instruction are obtained, the first resource of the pipeline is allocated to the first instruction, and / or the third resource of the pipeline is allocated to the third instruction, and the pipeline is controlled to execute the first instruction and / or the third instruction in parallel.
[0046] Take the case where the resources of the pipeline include a result bus, an access port of a data array of a first-level cache, and an access port of an address array as an example for explanation. If the instruction is not the first instruction, and the first instruction is an instruction that needs to occupy the result bus of the pipeline, i.e., the first resource, when executed, then determine whether the instruction is the second instruction, the third instruction, or the fourth instruction. The second instruction is an instruction that needs to occupy the access port of the data array of the first-level cache of the pipeline, i.e., the second resource, when executed, the third instruction is an instruction that needs to occupy the access port of the data array of the first-level cache of the pipeline, i.e., the third resource, when executed, the fourth instruction is an instruction that needs to occupy the access port of the address array of the first-level cache of the pipeline, i.e., the fourth resource, when executed. If the instruction is the second instruction, and the first instruction is included in other instructions to be executed, then obtain the first instruction, assign the result bus of the pipeline to the first instruction, assign the first-level cache ... The access port of the data array and the access port of the address array stored in the pipeline are assigned to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel; if the instruction is the third instruction, and the other instructions to be executed include the first instruction and / or the fourth instruction, the first instruction and / or the fourth instruction are obtained, the result bus of the pipeline is assigned to the first instruction, and / or the access port of the address array of the first-level cache of the pipeline is assigned to the fourth instruction, and the pipeline is controlled to execute the first instruction and / or the fourth instruction in parallel; if the instruction is the fourth instruction, and the other instructions to be executed include the first instruction and / or the third instruction, the first instruction and / or the third instruction are obtained, the result bus of the pipeline is assigned to the first instruction, and / or the access port of the data array of the first-level cache of the pipeline is assigned to the third instruction, and the pipeline is controlled to execute the first instruction and / or the third instruction in parallel.
[0047] Of course, in the above embodiments, only the first resource is the result bus, the second resource is the access port of the data array and the access port of the address array of the first-level cache, the third resource is the access port of the data array of the first-level cache, and the fourth resource is the access port of the address array of the first-level cache. The present application is not limited to this. In other embodiments, the first resource may also be the access port of the address array of the first-level cache, the second resource may also be the result bus and the access port of the data array of the first-level cache, the third resource may also be the access port of the data array of the first-level cache, the fourth resource may also be the result bus, etc., which will not be repeated here.
[0048] It can be understood that the above embodiment is only described by taking the example that the priority of the second instruction is greater than the third instruction and the fourth instruction, that is, first determine whether the second instruction is included and then determine whether the third instruction and / or the fourth instruction are included. However, the present application is not limited to this. In other embodiments, the priority of the third instruction and the fourth instruction may also be equal to or greater than the priority of the second instruction, which will not be repeated here.
[0049] In some embodiments of the present application, the identification information may include numerical information, and different numerical information indicates that different pipeline resources need to be occupied when the instruction is executed. The numerical information includes but is not limited to binary values.
[0050] Taking the case where the resources of the pipeline include a result bus, an access port of a data array of a first-level cache, and an access port of an address array as an example, if the identification information carried by the instruction includes the first numerical information (such as 001), it indicates that the instruction is the first instruction that needs to occupy the result bus of the pipeline; if the identification information carried by the instruction includes the second numerical information (such as 011), it indicates that the instruction is the second instruction that needs to occupy the access port of the address array and the access port of the data array of the first-level cache of the pipeline; if the identification information carried by the instruction includes the third numerical information (such as 100), it indicates that the instruction is the third instruction that needs to occupy the access port of the data array of the first-level cache of the pipeline; if the identification information carried by the instruction includes the fourth numerical information (such as 010), it indicates that the instruction is the fourth instruction that needs to occupy the access port of the address array of the first-level cache of the pipeline; if the identification information carried by the instruction includes the fifth numerical information (such as 111), it indicates that the instruction is the fifth instruction that needs to occupy the result bus of the pipeline, the access port of the address array of the first-level cache, and the access port of the data array, and the fifth instruction is an instruction that needs to occupy all resources of the pipeline.
[0051] In some embodiments, Figure 2 As shown, Figure 2A schematic diagram of the instruction execution process of an instruction execution method disclosed in an embodiment of the present application, wherein an instruction to be executed is obtained from an instruction queue. If the identification information carried by the instruction is fifth numerical information, it can be determined that the instruction is the fifth instruction 5 that needs to occupy all resources of the pipeline. In this case, all resources of the pipeline are allocated to the fifth instruction 5, and the pipeline is controlled to execute the fifth instruction 5.
[0052] If the identification information carried by the instruction is the first numerical information, it can be determined that the instruction is the first instruction 1 that needs to occupy part of the resources of the pipeline, such as the result bus. At this time, it is necessary to obtain the next instruction of the first instruction 1 from the instruction queue. If the identification information carried by the next instruction is the second numerical information, it can be determined that the next instruction is the second instruction 2 that needs to occupy another part of the resources of the pipeline, such as the access port of the address array of the first-level cache and the access port of the data array. Then, part of the resources of the pipeline, such as the result bus, can be allocated to the first instruction 1, and another part of the resources of the pipeline, such as the access port of the address array of the first-level cache and the access port of the data array, can be allocated to the second instruction 2, and the pipeline is controlled to execute the first instruction 1 and the second instruction 2 in parallel. If the next instruction is not the second instruction 2, the third instruction 3 or the fourth instruction 4, the next instruction is obtained, and so on. If there is no executable instruction or the resources of the pipeline are allocated, no new instruction is obtained. The situation of obtaining other instructions is the same as the above embodiment and will not be repeated here.
[0053] Of course, the present application is not limited to this. In other embodiments, the identification information may also include instruction queue information, which is used to indicate the instruction queue from which the instruction comes and the pipeline resources that need to be occupied when the instructions in the instruction queue are executed. The instructions in the same instruction queue require the same pipeline resources to be occupied when they are executed, and the instructions in different instruction queues require different pipeline resources to be occupied when they are executed.
[0054] Taking the case where the resources of the pipeline include the result bus, the access port of the data array of the first-level cache, and the access port of the address array as an example, if the identification information carried by the instruction includes the first instruction queue information, it means that the instruction comes from the first instruction queue and the instructions in the first instruction queue are all the first instructions 1 that need to occupy the result bus of the pipeline, then it can be determined that the instruction is the first instruction 1 that needs to occupy the result bus of the pipeline; if the identification information carried by the instruction includes the second instruction queue information, it means that the instruction comes from the second instruction queue and the instructions in the second instruction queue are all the second instructions 2 that need to occupy the access port of the address array and the access port of the data array of the first-level cache of the pipeline, then it can be determined that the instruction is the second instruction 2 that needs to occupy the access port of the address array and the access port of the data array of the first-level cache of the pipeline; if the identification information carried by the instruction includes the third instruction queue information, it means that the instruction comes from the third instruction queue and the instructions in the third instruction queue are all the second instructions 2 that need to occupy the access port of the address array and the access port of the data array of the first-level cache of the pipeline. If the third instruction 3 is to occupy the access port of the data array of the first-level cache of the pipeline, then it can be determined that the instruction is the third instruction 3 that needs to occupy the access port of the data array of the first-level cache of the pipeline; if the identification information carried by the instruction includes the fourth instruction queue information, then it means that the instruction comes from the fourth instruction queue and the instructions in the fourth instruction queue are all the fourth instructions 4 that need to occupy the access port of the address array of the first-level cache of the pipeline, then it can be determined that the instruction needs to occupy the fourth instruction 4 of the access port of the address array of the first-level cache of the pipeline; if the identification information carried by the instruction includes the fifth instruction queue information, then it means that the instruction comes from the fifth instruction queue and the instructions in the fifth instruction queue are all the fifth instructions 5 that need to occupy the result bus of the pipeline, the access port of the address array of the first-level cache and the access port of the data array, then it can be determined that the instruction is the fifth instruction 5 that needs to occupy the result bus of the pipeline, the access port of the address array of the first-level cache and the access port of the data array.
[0055] It is understandable that before obtaining the instructions to be executed, multiple instructions need to be divided into multiple instruction queues, and the instructions in the same instruction queue need to occupy the same pipeline resources when executing, while the instructions in different instruction queues need to occupy different pipeline resources when executing.
[0056] In some embodiments of the present application, multiple instructions can be divided into multiple instruction queues based on the numerical information carried by each instruction in the multiple instructions, and the instructions in the same instruction queue need to occupy the same pipeline resources when they are executed, while the instructions in different instruction queues need to occupy different pipeline resources when they are executed; wherein different numerical information represents different pipeline resources that need to be occupied when the instructions are executed.
[0057] In some embodiments of the present application, multiple instruction queues include a first instruction queue, a second instruction queue, a third instruction queue, a fourth instruction queue, and a fifth instruction queue; when executing instructions in the first instruction queue, it is necessary to occupy the first resource of the pipeline; when executing instructions in the second instruction queue, it is necessary to occupy the third resource and the fourth resource of the pipeline; when executing instructions in the third instruction queue, it is necessary to occupy the third resource of the pipeline; when executing instructions in the fourth instruction queue, it is necessary to occupy the fourth resource of the pipeline; when executing instructions in the fifth instruction queue, it is necessary to occupy the first resource, the third resource, and the fourth resource of the pipeline. Among them, the first resource includes the bus of the pipeline; the third resource includes the access port of the data array of the first-level cache of the pipeline; the fourth resource includes the access port of the address array of the first-level cache of the pipeline.
[0058] In some embodiments, Figure 3 As shown, Figure 3 A schematic diagram of the instruction execution process of another instruction execution method disclosed in an embodiment of the present application, wherein the instruction queue is divided into a first instruction queue, a second instruction queue, a third instruction queue, a fourth instruction queue and a fifth instruction queue, and the instructions in the first instruction queue are all first instructions 1 that need to occupy the result bus of the pipeline, the instructions in the second instruction queue are all second instructions 2 that need to occupy the access port of the address array and the access port of the data array of the first-level cache of the pipeline, the instructions in the third instruction queue are all third instructions 3 that need to occupy the access port of the data array of the first-level cache of the pipeline, the instructions in the fourth instruction queue are all fourth instructions 4 that need to occupy the access port of the address array of the first-level cache of the pipeline, and the instructions in the fifth instruction queue are all fifth instructions 5 that need to occupy all resources of the pipeline.
[0059] In some embodiments of the present application, the oldest instruction among all instructions in multiple instruction queues can be obtained as the instruction to be executed. For example, if the oldest instruction in the fifth instruction queue is the oldest instruction among all instructions in the first instruction queue, the second instruction queue, the third instruction queue, the fourth instruction queue and the fifth instruction queue, the oldest instruction in the fifth instruction queue is used as the instruction to be executed.
[0060] If the instruction to be executed is the fifth instruction 5 in the fifth instruction queue, no instruction is obtained from other instruction queues, all resources of the pipeline are allocated to the fifth instruction 5, and the pipeline is controlled to execute the fifth instruction 5.
[0061] If the instruction to be executed is the first instruction 1 in the first instruction queue, the second instruction 2 in the second instruction queue is obtained, the result bus of the pipeline is assigned to the first instruction 1, the access port of the address array and the access port of the data array of the first-level cache of the pipeline are assigned to the second instruction 2, and the pipeline is controlled to execute the first instruction 1 and the second instruction 2 in parallel; or, the third instruction 3 in the third instruction queue and the fourth instruction 4 in the fourth instruction queue are obtained, the result bus of the pipeline is assigned to the first instruction 1, the access port of the data array of the first-level cache of the pipeline is assigned to the third instruction 3, the access port of the address array of the first-level cache of the pipeline is assigned to the fourth instruction 4, and the pipeline is controlled to execute the first instruction 1, the third instruction 3 and the fourth instruction 4 in parallel. If there is no executable instruction or the resources of the pipeline are allocated, no new instructions are obtained. The situation of obtaining other instructions is the same as the above embodiment and will not be repeated here.
[0062] In some embodiments of the present application, instructions to be executed and other instructions to be executed may be acquired in sequence. Of course, the present application is not limited thereto. In other embodiments, instructions to be executed and other instructions to be executed may be acquired at the same time.
[0063] In some embodiments of the present application, the oldest instruction in each instruction queue in multiple instruction queues can be obtained simultaneously; if it is determined based on the instruction queue information that the instructions in any two instruction queues need to occupy the same pipeline resources when they are executed, the oldest instruction in the two instruction queues is used as the instruction to be executed; if it is determined based on the instruction queue information that the instructions in any two instruction queues need to occupy different pipeline resources when they are executed, the oldest instructions in the two instruction queues are respectively used as the instruction to be executed and the other instruction to be executed.
[0064] For example, the oldest instruction in the first instruction queue, the oldest instruction in the second instruction queue, the oldest instruction in the third instruction queue, the oldest instruction in the fourth instruction queue and the oldest instruction in the fifth instruction queue can be obtained at the same time. If it is determined based on the instruction queue information that the instructions in the second instruction queue and the fifth instruction queue need to occupy the same pipeline resources when they are executed, then the oldest instruction in the second instruction queue and the oldest instruction in the fifth instruction queue are used as instructions to be executed; if it is determined based on the instruction queue information that the instructions in the first instruction queue and the fifth instruction queue need to occupy the same pipeline resources when they are executed, then the oldest instruction in the first instruction queue and the oldest instruction in the fifth instruction queue are used as instructions to be executed; if it is determined based on the instruction queue information that the instructions in the first instruction queue and the second instruction queue need to occupy different pipeline resources when they are executed, then the oldest instruction in the first instruction queue and the oldest instruction in the second instruction queue are used as instructions to be executed and other instructions to be executed, respectively.
[0065] As another optional implementation of the disclosure of the present application, the embodiment of the present application further discloses a processor configured to execute the instruction execution method disclosed in any of the above embodiments. The processor may include, for example, an out-of-order superscalar processor.
[0066] As another optional implementation of the disclosure of the present application, the present application also discloses an electronic device, including a processor disclosed in any of the above embodiments. The electronic device may be, for example, a computer server, a cloud server, a distributed server, etc.
[0067] As an optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer-readable storage medium on which instructions for executing the instruction execution method disclosed in any of the above embodiments are stored.
[0068] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
[0069] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the instruction execution method disclosed in any of the above embodiments.
[0070] The computer program product may be written in any combination of one or more programming languages to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0071] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0072] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.
Claims
1. A method for executing an instruction, characterized in that: include: Obtaining an instruction to be executed, wherein the instruction carries identification information; Based on the identification information, determining pipeline resources that need to be occupied when the instruction is executed; If the identification information indicates that the instruction needs to occupy a part of all resources of the pipeline when executed, then a part of all resources of the pipeline are allocated to the instruction, and another part of all resources of the pipeline are allocated to other instructions to be executed, the other instructions include instructions that need to occupy another part of all resources of the pipeline when executed, and the pipeline is controlled to execute the instruction and the other instructions in parallel.
2. The method according to claim 1, characterized in that Also includes: If the identification information indicates that the instruction needs to occupy all resources of the pipeline when executed, all resources of the pipeline are allocated to the instruction, and the pipeline is controlled to execute the instruction.
3. The method according to claim 1, characterized in that If the identification information indicates that the instruction needs to occupy a part of all resources of the pipeline when it is executed, a part of all resources of the pipeline is allocated to the instruction, another part of all resources of the pipeline is allocated to other instructions to be executed, and the pipeline is controlled to execute the instruction and the other instructions in parallel, including: If the identification information indicates that the instruction is a first instruction, the first instruction includes an instruction that needs to occupy a first resource of the pipeline when executed, and other instructions to be executed include a second instruction, and the second instruction includes an instruction that needs to occupy a second resource of the pipeline when executed, and all resources of the pipeline include the first resource and the second resource, then the first resource is allocated to the first instruction, the second resource is allocated to the second instruction, and the pipeline is controlled to execute the first instruction and the second instruction in parallel.
4. The method according to claim 3, characterized in that Also includes: If the identification information indicates that the instruction is the first instruction, and other instructions to be executed do not include the second instruction but include a third instruction and / or a fourth instruction, the third instruction includes an instruction that needs to occupy a third resource of the pipeline when executed, the fourth instruction includes an instruction that needs to occupy a fourth resource of the pipeline when executed, and the second resource includes the third resource and the fourth resource, then the first resource is allocated to the first instruction, the third resource is allocated to the third instruction, and / or the fourth resource is allocated to the fourth instruction, and the pipeline is controlled to execute the first instruction, the third instruction and / or the fourth instruction in parallel.
5. The method according to claim 4, characterized in that Also includes: If the identification information indicates that the instruction is the second instruction, and other instructions to be executed include the first instruction, allocating the first resource to the first instruction, allocating the second resource to the second instruction, and controlling the pipeline to execute the first instruction and the second instruction in parallel; If the identification information indicates that the instruction is the third instruction, and other instructions to be executed include the first instruction and / or the fourth instruction, the first resource is allocated to the first instruction, and / or the fourth resource is allocated to the fourth instruction, and the pipeline is controlled to execute the first instruction and / or the fourth instruction in parallel; If the identification information indicates that the instruction is the fourth instruction, and other instructions to be executed include the first instruction and / or the third instruction, the first resource is allocated to the first instruction, and / or the third resource is allocated to the third instruction, and the pipeline is controlled to execute the first instruction and / or the third instruction in parallel.
6. The method according to claim 4 or 5, characterized in that: The first resource includes the bus of the pipeline; the second resource includes the port of the first-level cache of the pipeline; the third resource includes the access port of the data array of the first-level cache of the pipeline; the fourth resource includes the access port of the address array of the first-level cache of the pipeline.
7. The method according to claim 1, characterized in that The identification information includes numerical information, and different numerical information indicates different pipeline resources that need to be occupied when the instruction is executed.
8. The method according to claim 1, characterized in that The identification information includes instruction queue information, and the instruction queue information is used to indicate the instruction queue from which the instruction comes and the pipeline resources that need to be occupied when the instructions in the instruction queue are executed, wherein the pipeline resources that need to be occupied when the instructions in the same instruction queue are executed are the same, and the pipeline resources that need to be occupied when the instructions in different instruction queues are executed are different.
9. The method according to claim 8, characterized in that Before obtaining the instruction to be executed, the method further includes: Based on the numerical information carried by each instruction in the multiple instructions, the multiple instructions are divided into multiple instruction queues, and the instructions in the same instruction queue need to occupy the same pipeline resources when they are executed, and the instructions in different instruction queues need to occupy different pipeline resources when they are executed; wherein different numerical information represents different pipeline resources that need to be occupied when the instructions are executed.
10. The method according to claim 9, characterized in that The multiple instruction queues include a first instruction queue, a second instruction queue, a third instruction queue, a fourth instruction queue and a fifth instruction queue; when the instructions in the first instruction queue are executed, the first resource of the pipeline needs to be occupied; when the instructions in the second instruction queue are executed, the third and fourth resources of the pipeline need to be occupied; when the instructions in the third instruction queue are executed, the third resource of the pipeline needs to be occupied; when the instructions in the fourth instruction queue are executed, the fourth resource of the pipeline needs to be occupied; when the instructions in the fifth instruction queue are executed, the first, third and fourth resources of the pipeline need to be occupied.
11. The method according to claim 9, characterized in that The obtaining of instructions to be executed comprises: The oldest instruction among all instructions in the plurality of instruction queues is obtained as the instruction to be executed.
12. The method according to claim 9, characterized in that The obtaining of instructions to be executed comprises: Obtaining the oldest instruction in each of the plurality of instruction queues; If it is determined based on the instruction queue information that the instructions in any two instruction queues need to occupy the same pipeline resources when they are executed, the oldest instruction among the oldest instructions in the two instruction queues is used as the instruction to be executed; If it is determined based on the instruction queue information that the pipeline resources required to be occupied when executing instructions in any two instruction queues are different, the oldest instructions in the two instruction queues are respectively used as instructions to be executed and other instructions to be executed.
13. A processor, characterized in that: The method is configured to execute the instruction execution method according to any one of claims 1 to 12.
14. An electronic device, characterized in that: Comprising the processor of claim 13.
15. A computer-readable storage medium, characterized in that: Instructions for causing a computer to execute the instruction execution method according to any one of claims 1 to 12 are stored thereon.