MMC controller driving method and system

Abstract

The invention discloses an MMC controller driving method and system. The method comprises the steps that a processor core receives an operation request for a peripheral target memory card; the processor core packages the operation request into a first MMC message packet; the processor core fills the first MMC message packet into a shared memory; the RV core takes out the first MMC message packet from the shared memory; and the RV core writes an operation instruction on a register of the target MMC controller according to the first MMC message packet, wherein the operation instruction is used for driving the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card. According to the scheme, the processor core only needs to issue a simple instruction to the RV core, and the RV core completes a series of interactions with the MMC controller, so that the disturbance of the MMC controller to the processor core is reduced. Moreover, the register operation is completely split to the RV side, and the code in the kernel can close the source, so that the confidentiality of the related design of the MMC controller register is realized.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an MMC controller driving method and system. Background Art

[0002] Linux provides the MMC protocol to access various peripheral storage devices, such as SD (secure digital memory card), MMC (Multi Media Card), EMMC (Embedded Multi Media Card), SDIO (Secure Digital Input and Output), etc.

[0003] The MMC protocol framework can be divided into three layers from top to bottom, including the MMC card layer, the MMC core layer, and the MMC host layer. Among them, the MMC card layer mainly implements a card block device driver according to the framework of the Linux block device driver. The MMC core layer is responsible for processing the communication protocol, including providing specific read and write interfaces for the upper layer and providing the host interface for the lower layer. The MMC host layer implements operations related to the MMC controller. The MMC host layer directly operates the hardware and is also the main implementation part of the MMC protocol framework.

[0004] The existing MMC controller code is placed in the kernel. When the kernel driver needs to be open source, the specific design of the MMC controller is exposed. In addition, when the MMC controller communicates with peripherals such as SD, MMC, EMMC, and SDIO, the processor core needs to be frequently involved, causing frequent interruptions to the processor core. Summary of the invention

[0005] The present invention aims to at least solve the technical problems existing in the prior art. To this end, the present invention provides, in a first aspect, an MMC controller driving method, which is applied to an MMC controller driving system. The system includes a processor core and an RV core. The method includes:

[0006] The processor core receives an operation request for a target memory card of a peripheral device sent by a user space;

[0007] The processor core encapsulates the operation request into a first MMC message packet; the first MMC message packet at least includes: a first instruction ID of the operation request and an ID of a target MMC controller to be driven;

[0008] The processor core fills the first MMC message packet into the shared memory;

[0009] The RV core takes out the first MMC message packet from the shared memory;

[0010] The RV core writes an operation instruction to a register of the target MMC controller according to the first MMC message packet, wherein the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

[0011] The MMC controller driving method provided by the embodiment of the present invention comprises the following steps: the processor core receives an operation request for a target memory card of a peripheral device issued by a user space; the processor core encapsulates the operation request into a first MMC message packet; the first MMC message packet includes at least: a first instruction ID of the operation request and an ID of a target MMC controller to be driven; the processor core fills the first MMC message packet into a shared memory; the RV core takes out the first MMC message packet from the shared memory; the RV core writes an operation instruction to a register of the target MMC controller according to the first MMC message packet, and the operation instruction is used to drive the target MMC controller to perform the operation corresponding to the first instruction ID on the target memory card. In this solution, the processor core only needs to issue simple instructions to the RV core, and the RV core will complete a series of interactions with the MMC controller, reducing the disturbance of the MMC controller to the processor core. Moreover, the register operation is completely split to the RV side, and the code in the kernel can be closed source, achieving the purpose of keeping the MMC controller register-related design confidential.

[0012] Optionally, the processor core fills the first MMC message packet into a shared memory, including:

[0013] The processor core fills the first MMC message packet into the shared memory, and writes a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core;

[0014] The RV core fetches the first MMC message packet from the shared memory, including:

[0015] The RV core fetches the first MMC message packet from the shared memory according to the first interrupt instruction.

[0016] In this way, the processor core triggers the interrupt of the RV core by writing the first interrupt instruction, so that the RV core promptly knows that the first MMC message packet is written into the shared memory, and through the interrupt instruction, the RV core immediately executes the operation instruction in the first MMC message packet, thereby improving the execution efficiency of the operation request.

[0017] Optionally, the processor core fills the first MMC message packet into the shared memory and writes a first interrupt instruction in a register of the shared memory, including:

[0018] The processor core fills the first MMC message packet into the send message ring of the shared memory according to the message ring filling rule of the first transmission protocol;

[0019] The processor core writes a first interrupt instruction in a register of the shared memory to trigger an interrupt of the RV core, wherein the first interrupt instruction includes first position information of the first MMC message packet in the message sending ring;

[0020] The RV core fetches the first MMC message packet from the shared memory according to the first interrupt instruction, including:

[0021] The RV core fetches the first MMC message packet from the first location according to the first interrupt instruction.

[0022] In this way, the processor core fills the first MMC message packet into the send message ring of the shared memory, and informs the location of the first MMC message packet in the first interrupt instruction, which facilitates the RV core to take out the first MMC message packet from the location and improves operation efficiency.

[0023] Optionally, before the processor core writes the first interrupt instruction in the register of the shared memory, the process further includes:

[0024] The processor core reads first position information of the first MMC message packet in the message sending ring from the register of the shared memory, where the first position information is pre-acquired by the register from the message sending ring.

[0025] In this way, the message control function of the register can control the execution and filling of the message in the shared memory, so that the shared memory can read the specific position of the first MMC message packet from the register.

[0026] Optionally, the processor core includes an MMC core layer and an MMC operation layer, and the processor core receives an operation request for a target memory card of a peripheral device sent by a user space, including:

[0027] The MMC core layer receives an operation request for a target memory card of a peripheral device issued by a user space;

[0028] After the processor core receives the operation request for the target memory card of the peripheral device sent by the user space, the method further includes:

[0029] The MMC core layer converts the operation request into an MMC request, and sends the MMC request to the MMC operation layer; the MMC request includes: a first instruction ID of the operation request and an ID of the target MMC controller;

[0030] The MMC core layer determines the type of the MMC request, and fills corresponding transmission parameters in the MMC request according to the type;

[0031] The MMC operation layer determines the interface for processing the first instruction according to a preset first transmission protocol, and converts the first instruction ID into a first interface instruction ID; the first transmission protocol is a data transmission protocol from the processor core to the RV core;

[0032] The processor core encapsulates the operation request into a first MMC message packet, including:

[0033] The MMC operation layer obtains the ID of the target MMC controller connected to the target memory card;

[0034] The MMC operation layer fills the first interface instruction ID, the ID of the target MMC controller and the transmission parameters into a message packet having the first transmission protocol format to obtain a first MMC message packet.

[0035] In this way, the processor core is divided into an MMC core layer and an MMC operation layer to process the operation request, thereby improving the processing efficiency of the operation request. In addition, according to the preset first transmission protocol, the interface for processing the first instruction is determined, and the first instruction ID is converted into a first interface instruction ID, so that the processor core and the RV core process the operation request through the same interface, thereby improving the processing efficiency.

[0036] Since a universal interface is defined in the first transmission protocol, when the kernel is iteratively updated, only the driver code related to the kernel architecture on the processor core side needs to be updated. If the MMC controller design is updated, only the code related to register operations on the RV side needs to be updated, which facilitates porting between different platforms.

[0037] Optionally, after writing an operation instruction to a register corresponding to the target MMC controller, the method further includes:

[0038] The target MMC controller executes the operation corresponding to the first instruction ID on the target memory card, and fills the operation completion information into the register of the target MMC controller to trigger an interrupt of the target MMC controller;

[0039] In response to the interrupt, the RV core reads the response information obtained by the target MMC controller from the target memory card; the response information includes a second instruction ID;

[0040] The RV core fills the response information into the receiving message ring of the shared memory, and writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core;

[0041] The processor core obtains the response information from the receiving message ring according to the second interrupt instruction to obtain the second instruction ID;

[0042] The processor core executes the operation corresponding to the second instruction ID.

[0043] In this way, the RV core communicates with the processor core through shared memory, so that the processor obtains the response information and executes the operation corresponding to the second instruction, so that the processor core completes the entire operation request processing flow from receiving the operation request to receiving the response information of the target memory card and executing the relevant operation. Since the RV core completes a series of interactions with the MMC controller, the disturbance of the MMC controller to the processor core is reduced. In addition, the register operation is completely split to the RV side, and the code in the kernel can be closed source, achieving the purpose of keeping the MMC controller register-related design confidential.

[0044] Optionally, the RV core fills the response information into the receive message ring of the shared memory and writes a second interrupt instruction in the register of the shared memory, including:

[0045] The RV core determines the interface for processing the second instruction according to a preset second transmission protocol, and converts the second instruction ID into a second interface instruction ID; the second transmission protocol is a data transmission protocol from the RV core to the processor;

[0046] The RV core encapsulates the response information and the second interface instruction ID into a second MMC message packet supporting the second transmission protocol;

[0047] The RV core fills the second MMC message packet into the receiving message ring of the shared memory according to the message ring filling rule in the second transmission protocol;

[0048] The RV core writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core, wherein the second interrupt instruction includes a second position of the second MMC message packet in the receiving message ring;

[0049] The processor core obtains the response information from the receiving message ring according to the second interrupt instruction, including:

[0050] The processor core retrieves the second MMC message packet from the second location according to the second interrupt instruction, where the second MMC message packet includes the response information.

[0051] In this way, the RV core triggers the interrupt of the processor core by writing the second interrupt instruction, so that the processor core promptly knows that the second MMC message packet is written into the shared memory, and through the interrupt instruction, the processor core immediately executes the operation instruction in the second MMC message packet, thereby improving the execution efficiency of the operation request.

[0052] Furthermore, the RV core fills the second MMC message packet into the send message ring of the shared memory, and informs the position of the second MMC message packet in the second interrupt instruction, which facilitates the processor core to take out the second MMC message packet from the position, thereby improving operation efficiency.

[0053] Optionally, the processor core includes an MMC core layer and an MMC operation layer, and after the processor core executes the operation corresponding to the second instruction ID, further includes:

[0054] The MMC operation layer fills in the operation completion information of the first MMC message packet in the shared memory;

[0055] The MMC operation layer enables the MMC core layer to obtain the completion status of the operation request by calling the operation completion function of the MMC core layer.

[0056] In this way, the completion status of the operation request is obtained through the MMC core layer, so that the processor core is informed of the completion status of the operation request in a timely manner, and the entire operation request processing process forms a closed loop.

[0057] A second aspect of the present invention provides an MMC controller driving system, the system comprising a processor core and an RV core, the processor core being communicatively connected with the RV core;

[0058] The processor core is used for:

[0059] Receive an operation request for a target storage card of a peripheral device issued by a user space;

[0060] Encapsulating the operation request into a first MMC message packet; the first MMC message packet at least includes: a first instruction ID of the operation request and an ID of a target MMC controller to be driven;

[0061] Filling the first MMC message packet into the shared memory;

[0062] The RV core is used to:

[0063] Taking out the first MMC message packet from the shared memory;

[0064] An operation instruction is written to a register of the target MMC controller according to the first MMC message packet, wherein the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

[0065] Optionally, the processor core is specifically used for:

[0066] Filling the first MMC message packet into the shared memory, and writing a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core;

[0067] The RV core is specifically used for:

[0068] According to the first interrupt instruction, the first MMC message packet is retrieved from the shared memory.

[0069] Optionally, the processor core is specifically used for:

[0070] Filling the first MMC message packet into the send message ring of the shared memory according to the message ring filling rule of the first transmission protocol;

[0071] Writing a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core, wherein the first interrupt instruction includes first position information of the first MMC message packet in the message sending ring;

[0072] The RV core is specifically used for:

[0073] The RV core fetches the first MMC message packet from the first location according to the first interrupt instruction.

[0074] Optionally, the processor core is further used for:

[0075] The first position information of the first MMC message packet in the message sending ring is read from the register of the shared memory, where the first position information is pre-acquired by the register from the message sending ring.

[0076] Optionally, the processor core includes an MMC core layer and an MMC operation layer, and the processor core is specifically used for:

[0077] The MMC core layer receives an operation request for a target memory card of a peripheral device issued by a user space;

[0078] The MMC core layer converts the operation request into an MMC request, and sends the MMC request to the MMC operation layer; the MMC request includes: a first instruction ID of the operation request and an ID of the target MMC controller;

[0079] The MMC core layer determines the type of the MMC request, and fills corresponding transmission parameters in the MMC request according to the type;

[0080] The MMC operation layer determines the interface for processing the first instruction according to a preset first transmission protocol, and converts the first instruction ID into a first interface instruction ID; the first transmission protocol is a data transmission protocol from the processor core to the RV core;

[0081] The processor core is specifically used for:

[0082] The MMC operation layer obtains the ID of the target MMC controller connected to the target memory card;

[0083] The MMC operation layer fills the first interface instruction ID, the ID of the target MMC controller and the transmission parameters into a message packet having the first transmission protocol format to obtain a first MMC message packet.

[0084] Optionally, the target MMC controller is further used for:

[0085] Execute the operation corresponding to the first instruction ID on the target memory card, and fill the operation completion information into the register of the target MMC controller to trigger an interrupt of the target MMC controller;

[0086] The RV core is also used to:

[0087] In response to the interrupt, reading response information obtained by the target MMC controller from the target memory card; the response information includes a second instruction ID;

[0088] Filling the response information into the receiving message ring of the shared memory, and writing a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core;

[0089] According to the second interrupt instruction, acquiring the response information from the receiving message ring to obtain the second instruction ID;

[0090] Execute the operation corresponding to the second instruction ID.

[0091] Optionally, the RV core is specifically used for:

[0092] According to a preset second transmission protocol, determining an interface for processing the second instruction, and converting the second instruction ID into a second interface instruction ID; the second transmission protocol is a data transmission protocol from the RV core to the processor;

[0093] Encapsulating the response information and the second interface instruction ID into a second MMC message packet supporting the second transmission protocol;

[0094] Filling the second MMC message packet into the receiving message ring of the shared memory according to the message ring filling rule in the second transmission protocol;

[0095] Writing a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core, wherein the second interrupt instruction includes a second position of the second MMC message packet in the receiving message ring;

[0096] The processor core is specifically used for:

[0097] According to the second interrupt instruction, the second MMC message packet is retrieved from the second position, where the second MMC message packet includes the response information.

[0098] Optionally, the processor core includes an MMC core layer and an MMC operation layer, and the processor core is further used for:

[0099] The MMC operation layer fills in the operation completion information of the first MMC message packet in the shared memory;

[0100] The MMC operation layer enables the MMC core layer to obtain the completion status of the operation request by calling the operation completion function of the MMC core layer.

[0101] A third aspect of the present invention provides a system-on-chip, comprising an MMC controller driving system, wherein the MMC controller driving system is used to execute the MMC controller driving method described in the first aspect.

[0102] A fourth aspect of the present invention provides an electronic device, comprising the system-level chip as claimed in claim 9, wherein the system-level chip is used to execute the MMC controller driving method as described in the first aspect.

[0103] A fifth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the MMC controller driving method described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] Figure 1 It is a general architecture diagram of MMC in the prior art provided by an embodiment of the present invention;

[0105] Figure 2 This is a diagram of an improved MMC architecture provided by an embodiment of the present invention;

[0106] Figure 3is a hardware structure diagram of an MMC controller driving system provided by an embodiment of the present invention;

[0107] Figure 4 is a flow chart of the steps of a first MMC controller driving method provided by an embodiment of the present invention;

[0108] Figure 5 is a flow chart of the steps of a second MMC controller driving method provided by an embodiment of the present invention;

[0109] Figure 6 is a processing flow chart of an MMC operation request provided by an embodiment of the present invention;

[0110] Figure 7 is a flowchart of the steps of a third MMC controller driving method provided by an embodiment of the present invention;

[0111] Figure 8 It is a structural block diagram of an MMC controller driving system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0112] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0113] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​may be based on additional conditions or values ​​beyond the described values ​​in practice.

[0114] Figure 1 It is a general architecture diagram of MMC in the prior art provided by an embodiment of the present invention.

[0115] like Figure 1As shown, the inventors found in the process of studying related technologies that the existing MMC system space includes H / W (hardware), kernel space and user space from bottom to top. Among them, kernel space includes MMC framework, MMC framework (there are two hierarchical structures from "left to right" and "from bottom to top".

[0116] For the "from left to right" structure: the MMC protocol is a bus protocol, so it includes three entities: Host controller (driver controller), Bus (bus), and Card (card). Accordingly, the MMC architecture abstracts the three software entities of host, bus, and card to correspond one-to-one with the hardware. Among them:

[0117] The host is responsible for driving the host controller and providing operations such as accessing the card registers, detecting the card insertion and removal, reading and writing the card, etc. From the perspective of the device model, the host will detect the insertion of the card and register the MMC card device with the bus.

[0118] The bus is a virtual abstraction of the MMC bus, which contains the MMC card and the corresponding MMC driver in the form of a standard device model.

[0119] card, that is Figure 1 The mmc (Multi Media Card), sd (secure digital memory card), sdio (Secure Digital Input and Output) and so on are abstractions of the card and are driven by the corresponding MMC driver.

[0120] For a "bottom-up" structure:

[0121] The MMC architecture also has three levels from bottom to top:

[0122] MMC core, located in the middle layer, is the core implementation of the MMC framework. It is responsible for abstracting software entities such as host, bus, and card, and for providing a unified and convenient application programming interface for writing host controller drivers to the bottom layer.

[0123] MMC controller host drivers are located at the bottom layer and drive specific hardware, such as MMC controller, based on the framework provided by MMC core.

[0124] MMC card drivers, located at the top, are responsible for driving the virtual card device abstracted by the MMC core and connecting to other kernel frameworks, such as block devices, TTY (Teletypes, terminal devices), wireless, etc., to achieve specific functions.

[0125] In the process of studying related technologies, the inventors found that the code of the existing MMC controller is placed in the kernel. If the design of the MMC controller needs to be kept confidential, and the kernel driver needs to be open source, the specific design of the MMC controller is exposed. In addition, when the MMC controller communicates with SD / SDIO / eMMC peripherals, the CPU needs to be frequently involved, resulting in frequent interruptions to the CPU and reduced CPU efficiency. In addition, there is a coupling between the MMC driver architecture logic and the register operation logic in the kernel. The MMC controller needs to be ported to other platforms, iterated, or replaced, which requires substantial modifications to the driver, which is not conducive to maintenance.

[0126] In order to solve the above problems, the present invention provides an MMC controller driving method and a system-level chip.

[0127] Figure 2 This is a diagram of an improved MMC architecture provided by an embodiment of the present invention.

[0128] like Figure 2 As shown, the improved MMC architecture diagram splits the original MMC controller driver into two parts in software: mmc-host-driver and rv-mmc-host-driver.

[0129] The part that is strongly related to the original architecture is retained in the kernel, and the mmc-host-driver is used to implement the original architecture function; all the logic related to the MMC controller register operation is separated into an independent driver, and the rv-mmc-host-driver is used to implement the logic related to the register operation, and the instruction interaction interface between the two is formulated according to the driver architecture. An interface is usually designed with a specific function, and the instructions are issued in the mmc-host-driver, while the rv-mmc-host-driver executes a large amount of specific register operation logic.

[0130] In terms of hardware structure, an additional RV (Risk-V) core is added. The RV core communicates with the CPU through inter-core communication and interacts with the MMC controller by reading and writing MMC controller registers. The RV core runs RTOS (Real Time Operating System), and the rv-mmc-host-driver with a large amount of register operation logic runs in the RTOS of the RV core.

[0131] In this way, first of all, since all register operations are split into the RV-side RTOS, the code in the RTOS can be closed source, and the only code that needs to be open source in the kernel is the part related to the architecture and the part that communicates with the RV, thus achieving the purpose of keeping the MMC controller register-related design confidential.

[0132] Secondly, the functions are split, and the operation logic related to the MMC controller register is delegated to the RTOS on the RV side. The CPU no longer interacts directly with the MMC controller. It only needs to send simple instructions to the RV and receive the final results processed by the RV. The RV will complete a series of interactions with the MMC controller, reducing the disturbance of the MMC controller to the CPU.

[0133] Finally, since a common interface is defined after the functions are split, for example, when the kernel is iteratively updated, only the AP driver code related to the kernel architecture needs to be updated. If the MMC controller design is updated, only the code for RV register operations needs to be updated. This also facilitates porting between different platforms.

[0134] Figure 3 It is a hardware structure diagram of an MMC controller driving system provided by an embodiment of the present invention.

[0135] The system is Figure 2 The hardware structure diagram corresponding to the MMC architecture diagram. Figure 3 As shown, the MMC controller driving system includes a processor core and an RV core, and the processor core and the RV core interact with each other through an inter-core communication mode of shared memory.

[0136] The RV core interacts with the MMC controller by reading and writing MMC controller registers. The MMC controller interacts with devices such as MMC / SD / SDIO card through the SDIO bus and corresponding protocols.

[0137] Figure 4 1 is a flowchart of the steps of the first MMC controller driving method provided by an embodiment of the present invention. The method is applied to an MMC controller driving system, which includes a processor core and an RV core, such as Figure 4 As shown, the method comprises the following steps:

[0138] Step 101: The processor core receives an operation request for a target memory card of a peripheral device sent by a user space.

[0139] The operation request for the target memory card is generally generated when a user performs an operation on the target memory card in a user space.

[0140] The operation request refers to an input request or an output request sent from the user space. For example, a user sends a command from the user space to copy a file to the SD card, which is an input request, and a user sends a command from the user space to read a file on the SD card, which is an output request.

[0141] The operation request may specifically include the ID of the target MMC controller for the requested operation and the first instruction ID of the operation request. Since the MMC controller and the target memory card are operated in a one-to-one correspondence, one MMC controller corresponds to one memory card or a group of memory cards, the target MMC controller ID is sufficient here, and the target memory card ID is not required.

[0142] The target storage card of the peripheral device refers to an independent storage medium on the computer, which can expand the internal storage space of the computer. Specifically, it can include SD (secure digital memory card), MMC (Multi Media Card), EMMC (Embedded Multi Media Card), SDIO (Secure Digital Input and Output), etc.

[0143] Step 102: The processor core encapsulates the operation request into a first MMC message packet; the first MMC message packet at least includes: a first instruction ID of the operation request and an ID of a target MMC controller to be driven.

[0144] After receiving the operation request, the processor core interacts with the RV core through the inter-core communication of shared memory in order to pass the operation request to the target memory card. The RV core interacts with the MMC controller by reading and writing the MMC controller registers. Finally, the MMC controller interacts with the target memory card through the SDIO bus and the corresponding protocol.

[0145] Therefore, the processor core needs to first write the content of the operation request into the shared memory.

[0146] The processor core encapsulates the operation request into a first MMC message packet, which at least includes: a first instruction ID of the operation request and an ID of a target MMC controller to be driven.

[0147] Step 103: The processor core fills the first MMC message packet into the shared memory.

[0148] Shared memory is actually a section of memory opened by the operating system in the actual physical memory. Shared memory enables inter-process communication between the processor core and the RV core. Specifically, the processor core forms a mapping relationship between this space and a block of address space in the shared area of ​​the process address space in its own page table. The RV core forms a mapping relationship between the same physical space and a block of address space in the shared area of ​​the process address space in the page table. When the processor core writes content to this space, the RV core accesses this space and obtains the written value, thus achieving inter-process communication.

[0149] The processor core specifically writes the first MMC message packet into the shared memory, and informs the RV core of the address of the message packet in the shared memory by writing instructions in the register of the shared memory.

[0150] Step 104: The RV core retrieves the first MMC message packet from the shared memory.

[0151] After receiving the instruction, the RV core parses the instruction, obtains the address of the message packet in the shared memory, and takes out the first MMC message packet from the address.

[0152] Step 105: The RV core writes an operation instruction to a register of the target MMC controller according to the first MMC message packet, where the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

[0153] Since the RV core interacts with the MMC controller by reading and writing the MMC controller register, after the RV core parses the first MMC message packet to obtain the ID of the target MMC controller, it writes an operation instruction to the register of the target MMC controller corresponding to the ID.

[0154] The register of the target MMC controller acquires the operation instruction, parses it to obtain the first instruction ID, and then sends a driving instruction to the target memory card corresponding to the target MMC controller to drive the target memory card to execute the operation corresponding to the first instruction ID.

[0155] This solution splits all register operations to the RV side, and the code on the RV side can be closed source, achieving the purpose of keeping the MMC controller register-related design confidential. In addition, the MMC controller register-related operation logic is decentralized to the RV core. The processor core only needs to send simple instructions to the RV core and no longer interacts directly with the MMC controller. The RV core will complete a series of interactions with the MMC controller, reducing the interference of the MMC controller on the processor core.

[0156] In summary, in an embodiment of the present invention, the processor core receives an operation request for a target memory card of a peripheral device issued by a user space; the processor core encapsulates the operation request into a first MMC message packet; the first MMC message packet includes at least: the first instruction ID of the operation request and the ID of the target MMC controller to be driven; the processor core fills the first MMC message packet into a shared memory; the RV core takes out the first MMC message packet from the shared memory; the RV core writes an operation instruction to the register of the target MMC controller according to the first MMC message packet, and the operation instruction is used to drive the target MMC controller to perform the operation corresponding to the first instruction ID on the target memory card. In this solution, the processor core only needs to issue simple instructions to the RV core, and the RV core will complete a series of interactions with the MMC controller, reducing the disturbance of the MMC controller to the processor core. In addition, the register operation is completely split to the RV side, and the code in the kernel can be closed source, achieving the purpose of keeping the MMC controller register-related design confidential.

[0157] Figure 5 1 is a flow chart of the steps of a second MMC controller driving method provided by an embodiment of the present invention. The method is applied to an MMC controller driving system, the system including a processor core and an RV core, such as Figure 5 As shown, the method comprises the following steps:

[0158] Step 201: The MMC core layer receives an operation request for a target memory card of a peripheral device sent by a user space.

[0159] Specifically, the operation request is sent from the user space to the block layer, and then from the block layer to the MMC core layer. The block layer is an abstract layer between the user space and the hardware device, providing a set of unified interfaces and functions to facilitate the upper-layer application to access and manage the block device.

[0160] Figure 6 FIG. 1 is a flowchart of a processing of an MMC operation request provided by an embodiment of the present invention. Figure 6 As shown, the hardware device includes a processor core, an RV core, an MMC controller and a target memory card.

[0161] The processor core includes the MMC core layer (MMC core) and the MMC operation layer (MMC host). The MMC core layer process is the original design framework in the kernel, and the MMC operation layer is connected to the framework design by a fixed interface ops_request. The MMC layer is further divided into specific register operations.

[0162] Step 202: The MMC core layer converts the operation request into an MMC request, and sends the MMC request to the MMC operation layer; the MMC request includes: a first instruction ID of the operation request and an ID of the target MMC controller.

[0163] After receiving the operation request, the MMC core layer converts the operation request into an MMC request through a series of processes. Figure 6 The mmc_wait_for_req and requestmmc_start_request processes in the MMC_wait_for_req ...

[0164] The MMC request includes the first instruction ID in the operation request and the ID of the target MMC controller.

[0165] Step 203: The MMC core layer determines the type of the MMC request, and fills corresponding transmission parameters in the MMC request according to the type.

[0166] The MMC operation layer parses the first instruction ID in the MMC request to determine the type of the MMC request. The first instruction ID can be used to distinguish whether the MMC request is a data request (data request) or a cmd request (command request), or other operation requests.

[0167] Then, according to the type of MMC request, the preparation process required before sending is performed, such as filling in the corresponding transmission parameters. The transmission parameters are obtained from the operation request, and may specifically include information such as data length and data content.

[0168] Specifically, Figure 6 As shown, if it is a data request, the prepare_data process is entered to prepare data; if it is a data request with dma enabled, the dma_map_sg operation will be performed, and then the start_data process will be entered. If it is a cmd request, the prepare_cmd process will be entered to fill in raw cmd / arg and other values, and then the start_command process will be entered.

[0169] Step 204: The MMC operation layer determines the interface for processing the first instruction according to a preset first transmission protocol, and converts the first instruction ID into a first interface instruction ID; the first transmission protocol is a data transmission protocol from the processor core to the RV core.

[0170] The first transmission protocol is a predefined AP2RV interface protocol. The AP2RV interface protocol mainly defines the content of the first MMC message packet sent by the processor core to the RV core and the interface protocol function table.

[0171] The interface protocol function table defines the calling functions, interface command IDs, command names and content descriptions of various operation commands for MMC.

[0172] Since the first transmission protocol defines an interface between the processor core and the RV core, both the processor core and the RV core must have corresponding functions to the interface to process the same request.

[0173] Therefore, in the start_data process or the start_command process, the first instruction ID needs to be converted into the first interface instruction ID to determine the interface through which the processor core and the RV core interact with the operation request. Specifically, the first interface instruction ID is used to specify the interface through which the processor core sends the message packet and the interface through which the RV core receives the message packet.

[0174] Regarding the interface protocol function table, some of the contents are shown in Table 1:

[0175] Table 1

[0176]

[0177] As shown in Table 1, "function" indicates the calling function of the interface instruction, "ID" indicates the interface instruction ID, "CMD" indicates the interface instruction name, and "description" is a description of the specific content of the instruction. The first interface instruction ID specifically refers to "ID" in Table 1. Among them, the interface instruction ID of the command request is 0x03, which is used to transmit instructions to the target memory card, and the interface instruction ID of the data request is 0x04, which is used to transmit data to the target memory card.

[0178] Step 205: The MMC operation layer fills the first interface instruction ID, the ID of the target MMC controller and the transmission parameter into a message packet having the first transmission protocol format to obtain a first MMC message packet.

[0179] The first transmission protocol defines the interface between the processor core and the RV core. Both the processor core and the RV core must have corresponding functions to the interface to process the same request.

[0180] In this way, both the processor core and the RV core have interfaces for receiving and sending MMC message packets of request information. By sending the MMC message packets, the other party can know the operation that needs to be performed currently.

[0181] According to the provisions of the first transmission protocol, the first MMC message packet includes: a first interface instruction ID, an ID of a target MMC controller and transmission parameters. The transmission parameters may specifically include information such as data length and data content.

[0182] Step 206: The processor core fills the first MMC message packet into the shared memory, and writes a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core.

[0183] The processor core fills the first MMC message packet into the shared memory, which is an action that the RV core cannot perceive, and an interrupt is required to inform the RV core. The RV core may be in any state at the time, such as in a dormant state, and an interrupt must be used to wake up the RV core to process the first MMC message packet. Therefore, the processor core informs the RV core to process the first MMC message packet by writing the first interrupt instruction. In addition, operations triggered by interrupts generally need to be completed immediately, so they have a high timeliness.

[0184] The specific way to trigger an interrupt is to write an interrupt instruction in a register in the shared memory.

[0185] In a possible implementation, step 206 includes:

[0186] Step 2061: The processor core fills the first MMC message packet into the send message ring of the shared memory according to the message ring filling rule of the first transmission protocol;

[0187] Step 2062: The processor core writes a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core, wherein the first interrupt instruction includes first position information of the first MMC message packet in the message sending ring.

[0188] In step 2061-step 2062, the mmc-host-driver and rv-mmc-host-driver split from the original driver interact through shared memory and registers (regfile). The shared memory mainly includes a send message ring (TXmsg ring) and a receive message ring (RX msg ring), which are two message rings for storing processor core to RV core messages and RV core to processor core messages respectively. The register mainly includes message control function in shared memory, direct transfer register function, interrupt register function, etc.

[0189] like Figure 6 As shown, the processor core fills the first MMC message packet into the send message ring (share_memTX_RING) of the shared memory.

[0190] In order to inform the RV core to process the first MMC message packet, the processor core writes a first interrupt instruction in the register of the shared memory to trigger the interrupt of the RV core. In order to let the RV core know where to obtain the first MMC message packet, the first interrupt instruction also includes the first position information of the first MMC message packet in the shared memory.

[0191] In a possible implementation manner, before the processor core writes the first interrupt instruction in the register of the shared memory in step 2062, the process further includes:

[0192] The processor core reads first position information of the first MMC message packet in the message sending ring from the register of the shared memory, where the first position information is pre-acquired by the register from the message sending ring.

[0193] In the embodiment of the present invention, in order to write the position of the first MMC message packet into the first interrupt instruction, the processor core reads the first position information of the first MMC message packet from the register of the shared memory in advance.

[0194] The register has a message control function, which refers to the control of executing and filling messages in the shared memory. This function can record the current execution position in the message ring and the position of the currently filled message. In this way, the shared memory can read the specific position information of the first MMC message packet from the register.

[0195] Step 207: The RV core retrieves the first MMC message packet from the shared memory according to the first interrupt instruction.

[0196] The interrupt is triggered by writing a register. After the processor core writes the first interrupt instruction in the register, the RV core is awakened. The RV core obtains the first interrupt instruction and parses the first MMC message packet therefrom.

[0197] In a possible implementation, step 207 includes:

[0198] The RV core fetches the first MMC message packet from the first location according to the first interrupt instruction.

[0199] In the embodiment of the present invention, since the first interrupt instruction includes the first position, the RV core directly takes out the first MMC message packet from the first position.

[0200] Step 208: The RV core writes an operation instruction to a register of the target MMC controller according to the first MMC message packet, where the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

[0201] In the embodiment of the present invention, step 208 may refer to step 105 and will not be described in detail here.

[0202] Specific as Figure 6 As shown, the RV core obtains the first MMC message packet through the shared memory, and executes the rv_start_data process or the rv_start_command process according to the type of the message, generates an operation instruction according to the first interface instruction content of the first MMC message packet, and writes it into the target MMC controller.

[0203] In an embodiment of the present invention, Figure 5 The MMC controller driving method in Figure 4 In addition to the beneficial effects of the MMC controller driving method, the processor core also triggers the interrupt of the RV core by writing the first interrupt instruction, so that the RV core is informed in time that the first MMC message packet is written into the shared memory, and the RV core immediately executes the operation instruction in the first MMC message packet by means of the interrupt instruction, thereby improving the execution efficiency of the operation request.

[0204] In addition, the processor core fills the first MMC message packet into the send message ring of the shared memory, and informs the location of the first MMC message packet in the first interrupt instruction, which facilitates the RV core to take out the first MMC message packet from the location, thereby improving the operation efficiency; the message control function of the register can control the execution and filling of the message in the shared memory, so that the shared memory can read the specific location of the first MMC message packet from the register. The processor core is divided into an MMC core layer and an MMC operation layer to process the operation request, thereby improving the processing efficiency of the operation request.

[0205] In addition, according to the preset first transmission protocol, the interface for processing the first instruction is determined, and the first instruction ID is converted into a first interface instruction ID, so that the processor core and the RV core process the operation request through the same interface, thereby improving processing efficiency.

[0206] Since a universal interface is defined in the first transmission protocol, when the kernel is iteratively updated, only the driver code related to the kernel architecture on the processor core side needs to be updated. If the MMC controller design is updated, only the code related to register operations on the RV side needs to be updated, which facilitates porting between different platforms.

[0207] Figure 72 is a flowchart of the steps of the third MMC controller driving method provided by the embodiment of the present invention. After the method is applied to step 209, the method includes:

[0208] Step 301: The target MMC controller executes the operation corresponding to the first instruction ID on the target memory card, and fills the operation completion information into the register of the target MMC controller to trigger an interrupt of the target MMC controller.

[0209] The RV core writes an operation instruction to the register of the target MMC controller according to the first MMC message packet, wherein the operation instruction includes an operation to be executed by the target MMC controller, and the target MMC controller executes the operation corresponding to the first instruction ID according to the first instruction ID included in the operation instruction.

[0210] Specifically, if the first instruction ID is an instruction to write a file to the SD card, the target MMC controller writes the corresponding file to the SD card; if the first instruction ID is an instruction to read a file on the SD card, the target MMC controller reads the corresponding file on the SD card.

[0211] The processor core initiates the action of the RV core to execute the first instruction ID. In fact, the processor core needs to know whether the RV core has completed this action. Therefore, after the target MMC controller completes the operation, the target MMC controller fills the operation completion information into the register of the target MMC controller, triggering an interrupt of the target MMC controller.

[0212] Step 302: The RV core responds to the interruption by reading response information obtained by the target MMC controller from the target memory card; the response information includes a second instruction ID.

[0213] When the RV core learns of the interruption of the target MMC controller, it reads the response information obtained by the target MMC controller from the target memory card.

[0214] When the target MMC controller interacts with the target memory card, the target memory card transmits response information for the first instruction to the target MMC controller, where the response information includes the ID of the second instruction to be executed by the processor core.

[0215] Exemplarily, when the first instruction is an instruction to read a file on an SD card, the target memory card is an SD card, and the SD card sends the information of the corresponding file as response information to the target MMC controller. The second instruction is specifically an instruction to instruct the processor core to read the file.

[0216] Step 303: The RV core fills the response information into the receive message ring of the shared memory, and writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core.

[0217] The RV core and the processor core also communicate through the shared memory, specifically writing the response information into the receiving message ring of the shared memory, and writing the second interrupt instruction in the register of the shared memory so that the processor core executes the processing operation on the response information.

[0218] like Figure 6 As shown, the target MMC controller interacts with the target memory card via the SD bus, and the target memory card transmits response information for the first instruction to the target MMC controller. The MMC controller writes a second interrupt instruction (IRQ) to the RV core.

[0219] In a possible implementation, step 303 includes:

[0220] Step 3031: The RV core determines the interface for processing the second instruction according to a preset second transmission protocol, and converts the second instruction ID into a second interface instruction ID; the second transmission protocol is a data transmission protocol from the RV core to the processor;

[0221] Step 3032: The RV core encapsulates the response information and the second interface instruction ID into a second MMC message packet supporting the second transmission protocol;

[0222] Step 3033: The RV core fills the second MMC message packet into the receiving message ring of the shared memory according to the message ring filling rule in the second transmission protocol;

[0223] Step 3034: The RV core writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core, wherein the second interrupt instruction includes the second position of the second MMC message packet in the receiving message ring.

[0224] In step 3031 to step 3034, the second transmission protocol is a predefined RV2AP interface protocol. The RV2AP interface protocol mainly defines the content of the second MMC message packet sent by the RV core to the processor core.

[0225] like Figure 6 As shown, in the cmd_done to cmd_next process, or the data_done to data_next process, the second instruction ID is converted into the second interface instruction ID according to the definition in the interface protocol function table.

[0226] The RV core encapsulates the response information and the second interface instruction ID into a second MMC message packet supporting the second transmission protocol.

[0227] The RV core fills the second MMC message packet into the receive message ring (share_mem RX_RING) of the shared memory.

[0228] To inform the processor core to process the second MMC message packet, the RV core writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core. To let the processor core know where to get the second MMC message packet, the second interrupt instruction also includes the second position of the second MMC message packet in the shared memory.

[0229] Step 304: The processor core obtains the response information from the receive message ring according to the second interrupt instruction to obtain the second instruction ID.

[0230] After the RV core writes the first interrupt instruction in the register, the processor core is awakened, and the processor core obtains the second interrupt instruction and parses it to obtain the second instruction ID in the second MMC message packet.

[0231] In a possible implementation, step 304 includes:

[0232] The processor core retrieves the second MMC message packet from the second location according to the second interrupt instruction, where the second MMC message packet includes the response information.

[0233] In the embodiment of the present invention, since the second interrupt instruction includes the second position, the processor core directly retrieves the second MMC message packet from the second position.

[0234] Step 305: The processor core executes the operation corresponding to the second instruction ID.

[0235] like Figure 6 As shown, after the processor core takes out the message, it parses the message packet in check_msg and executes the corresponding function according to the second instruction ID.

[0236] In a possible implementation manner, after step 305, the method further includes:

[0237] Step 306: The MMC operation layer fills in the operation completion information of the first MMC message packet in the shared memory;

[0238] Step 307: The MMC operation layer calls the operation completion function of the MMC core layer, so that the MMC core layer obtains the completion status of the operation request.

[0239] In step 306-step 307, if Figure 6 As shown, after the processor core executes the second instruction through cmd_next or data_next, it fills in complete in the shared memory, then calls request_done, and finally calls mmc_request_done of the MMC core layer to complete the closed loop.

[0240] In summary, the target MMC controller performs the operation corresponding to the first instruction ID on the target memory card, and fills the operation completion information into the register of the target MMC controller to trigger the interrupt of the target MMC controller; the RV core responds to the interrupt, reads the response information of the target memory card, and fills the response information into the receiving message ring of the shared memory, and writes the second interrupt instruction in the register of the shared memory to trigger the interrupt of the processor core; the processor core obtains the response information from the receiving message ring according to the second interrupt instruction, and obtains the second instruction ID; the processor core executes the operation corresponding to the second instruction ID. In this way, the RV core communicates with the processor core through the shared memory, so that the processor obtains the response information and executes the operation corresponding to the second instruction, so that the processor core completes the entire operation request processing flow from receiving the operation request to receiving the response information of the target memory card and executing the relevant operation. Since the RV core completes a series of interactions with the MMC controller, the disturbance of the MMC controller to the processor core is reduced. In addition, the register operation is completely split to the RV side, and the code in the kernel can be closed source, achieving the purpose of keeping the MMC controller register-related design confidential.

[0241] Furthermore, the RV core triggers the interruption of the processor core by writing the second interruption instruction, so that the processor core is informed in time that the second MMC message packet is written into the shared memory, and the processor core is made to immediately execute the operation instruction in the second MMC message packet by means of the interruption instruction, thereby improving the execution efficiency of the operation request. The RV core fills the second MMC message packet into the send message ring of the shared memory, and informs the location of the second MMC message packet in the second interruption instruction, thereby facilitating the processor core to take out the second MMC message packet from the location, thereby improving the operation efficiency.

[0242] In addition, the MMC operation layer fills the operation completion information of the first MMC message packet in the shared memory; the MMC operation layer calls the operation completion function of the MMC core layer to enable the MMC core layer to obtain the completion status of the operation request. In this way, the completion status of the operation request is obtained through the MMC core layer, so that the processor core can be informed of the completion status of the operation request in a timely manner, and the entire operation request processing process forms a closed loop.

[0243] Figure 8300 includes a processor core 301 and an RV core 302, and the processor core 301 is in communication connection with the RV core 302;

[0244] The processor core 301 is used for:

[0245] Receive an operation request for a target storage card of a peripheral device issued by a user space;

[0246] Encapsulating the operation request into a first MMC message packet; the first MMC message packet at least includes: a first instruction ID of the operation request and an ID of a target MMC controller to be driven;

[0247] Filling the first MMC message packet into the shared memory;

[0248] The RV core 302 is used for:

[0249] Taking out the first MMC message packet from the shared memory;

[0250] An operation instruction is written to a register of the target MMC controller according to the first MMC message packet, wherein the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

[0251] Optionally, the processor core 301 is specifically used for:

[0252] Filling the first MMC message packet into the shared memory, and writing a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core;

[0253] The RV core 302 is specifically used for:

[0254] According to the first interrupt instruction, the first MMC message packet is retrieved from the shared memory.

[0255] Optionally, the processor core 301 is specifically used for:

[0256] Filling the first MMC message packet into the send message ring of the shared memory according to the message ring filling rule of the first transmission protocol;

[0257] Writing a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core, wherein the first interrupt instruction includes first position information of the first MMC message packet in the message sending ring;

[0258] The RV core 302 is specifically used for:

[0259] The RV core fetches the first MMC message packet from the first location according to the first interrupt instruction.

[0260] Optionally, the processor core 301 is further configured to:

[0261] The first position information of the first MMC message packet in the message sending ring is read from the register of the shared memory, where the first position information is pre-acquired by the register from the message sending ring.

[0262] Optionally, the processor core includes an MMC core layer and an MMC operation layer, and the processor core 301 is specifically used for:

[0263] The MMC core layer receives an operation request for a target memory card of a peripheral device issued by a user space;

[0264] The MMC core layer converts the operation request into an MMC request, and sends the MMC request to the MMC operation layer; the MMC request includes: a first instruction ID of the operation request and an ID of the target MMC controller;

[0265] The MMC core layer determines the type of the MMC request, and fills corresponding transmission parameters in the MMC request according to the type;

[0266] The MMC operation layer determines the interface for processing the first instruction according to a preset first transmission protocol, and converts the first instruction ID into a first interface instruction ID; the first transmission protocol is a data transmission protocol from the processor core to the RV core;

[0267] The processor core 301 is specifically used for:

[0268] The MMC operation layer obtains the ID of the target MMC controller connected to the target memory card;

[0269] The MMC operation layer fills the first interface instruction ID, the ID of the target MMC controller and the transmission parameters into a message packet having the first transmission protocol format to obtain a first MMC message packet.

[0270] Optionally, the target MMC controller 301 is further used for:

[0271] Execute the operation corresponding to the first instruction ID on the target memory card, and fill the operation completion information into the register of the target MMC controller to trigger an interrupt of the target MMC controller;

[0272] The RV core 302 is also used for:

[0273] In response to the interrupt, reading response information obtained by the target MMC controller from the target memory card; the response information includes a second instruction ID;

[0274] Filling the response information into the receiving message ring of the shared memory, and writing a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core;

[0275] According to the second interrupt instruction, acquiring the response information from the receiving message ring to obtain the second instruction ID;

[0276] Execute the operation corresponding to the second instruction ID.

[0277] Optionally, the RV core 302 is specifically used for:

[0278] According to a preset second transmission protocol, determining an interface for processing the second instruction, and converting the second instruction ID into a second interface instruction ID; the second transmission protocol is a data transmission protocol from the RV core to the processor;

[0279] Encapsulating the response information and the second interface instruction ID into a second MMC message packet supporting the second transmission protocol;

[0280] Filling the second MMC message packet into the receiving message ring of the shared memory according to the message ring filling rule in the second transmission protocol;

[0281] Writing a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core, wherein the second interrupt instruction includes a second position of the second MMC message packet in the receiving message ring;

[0282] The processor core 301 is specifically used for:

[0283] According to the second interrupt instruction, the second MMC message packet is retrieved from the second position, where the second MMC message packet includes the response information.

[0284] Optionally, the processor core includes an MMC core layer and an MMC operation layer, and the processor core 301 is further used for:

[0285] The MMC operation layer fills in the operation completion information of the first MMC message packet in the shared memory;

[0286] The MMC operation layer enables the MMC core layer to obtain the completion status of the operation request by calling the operation completion function of the MMC core layer.

[0287] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0288] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0289] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0290] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A MMC controller driving method, characterized in that: Applied to an MMC controller driving system, the system includes a processor core and an RV core, and the method includes: The processor core receives an operation request for a target memory card of a peripheral device sent by a user space; The processor core encapsulates the operation request into a first MMC message packet; the first MMC message packet at least includes: a first instruction ID of the operation request and an ID of a target MMC controller to be driven; The processor core fills the first MMC message packet into the shared memory; The RV core takes out the first MMC message packet from the shared memory; The RV core writes an operation instruction to a register of the target MMC controller according to the first MMC message packet, wherein the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

2. The method according to claim 1, characterized in that The processor core fills the first MMC message packet into the shared memory, including: The processor core fills the first MMC message packet into the shared memory, and writes a first interrupt instruction in the register of the shared memory to trigger an interrupt of the RV core; The RV core fetches the first MMC message packet from the shared memory, including: The RV core fetches the first MMC message packet from the shared memory according to the first interrupt instruction.

3. The method according to claim 2, characterized in that The processor core fills the first MMC message packet into the shared memory and writes a first interrupt instruction in a register of the shared memory, including: The processor core fills the first MMC message packet into the send message ring of the shared memory according to the message ring filling rule of the first transmission protocol; The processor core writes a first interrupt instruction in a register of the shared memory to trigger an interrupt of the RV core, wherein the first interrupt instruction includes first position information of the first MMC message packet in the message sending ring; The RV core fetches the first MMC message packet from the shared memory according to the first interrupt instruction, including: The RV core fetches the first MMC message packet from the first location according to the first interrupt instruction.

4. The method according to claim 3, characterized in that Before the processor core writes the first interrupt instruction in the register of the shared memory, the method further includes: The processor core reads first position information of the first MMC message packet in the message sending ring from the register of the shared memory, where the first position information is pre-acquired by the register from the message sending ring.

5. The method according to claim 1, characterized in that The processor core includes an MMC core layer and an MMC operation layer, and the processor core receives an operation request for a target memory card of a peripheral device issued by a user space, including: The MMC core layer receives an operation request for a target memory card of a peripheral device issued by a user space; After the processor core receives the operation request for the target memory card of the peripheral device sent by the user space, the method further includes: The MMC core layer converts the operation request into an MMC request, and sends the MMC request to the MMC operation layer; the MMC request includes: a first instruction ID of the operation request and an ID of the target MMC controller; The MMC core layer determines the type of the MMC request, and fills corresponding transmission parameters in the MMC request according to the type; The MMC operation layer determines the interface for processing the first instruction according to a preset first transmission protocol, and converts the first instruction ID into a first interface instruction ID; the first transmission protocol is a data transmission protocol from the processor core to the RV core; The processor core encapsulates the operation request into a first MMC message packet, including: The MMC operation layer fills the first interface instruction ID, the ID of the target MMC controller and the transmission parameters into a message packet having the first transmission protocol format to obtain a first MMC message packet.

6. The method according to claim 1, characterized in that After writing the operation instruction to the register corresponding to the target MMC controller, the method further includes: The target MMC controller executes the operation corresponding to the first instruction ID on the target memory card, and fills the operation completion information into the register of the target MMC controller to trigger an interrupt of the target MMC controller; The RV core responds to the interruption, and in response to the interruption, reads the response information obtained by the target MMC controller from the target memory card; the response information includes a second instruction ID; The RV core fills the response information into the receiving message ring of the shared memory, and writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core; The processor core obtains the response information from the receiving message ring according to the second interrupt instruction to obtain the second instruction ID; The processor core executes the operation corresponding to the second instruction ID.

7. The method according to claim 6, characterized in that The RV core fills the response information into the receiving message ring of the shared memory and writes a second interrupt instruction in the register of the shared memory, including: The RV core determines the interface for processing the second instruction according to a preset second transmission protocol, and converts the second instruction ID into a second interface instruction ID; the second transmission protocol is a data transmission protocol from the RV core to the processor; The RV core encapsulates the response information and the second interface instruction ID into a second MMC message packet supporting the second transmission protocol; The RV core fills the second MMC message packet into the receiving message ring of the shared memory according to the message ring filling rule in the second transmission protocol; The RV core writes a second interrupt instruction in the register of the shared memory to trigger an interrupt of the processor core, wherein the second interrupt instruction includes a second position of the second MMC message packet in the receiving message ring; The processor core obtains the response information from the receiving message ring according to the second interrupt instruction, including: The processor core retrieves the second MMC message packet from the second location according to the second interrupt instruction, where the second MMC message packet includes the response information.

8. The method according to claim 6, characterized in that The processor core includes an MMC core layer and an MMC operation layer. After the processor core executes the operation corresponding to the second instruction ID, the processor core further includes: The MMC operation layer fills in the operation completion information of the first MMC message packet in the shared memory; The MMC operation layer enables the MMC core layer to obtain the completion status of the operation request by calling the operation completion function of the MMC core layer.

9. An MMC controller driving system, characterized in that: The system comprises a processor core and an RV core, wherein the processor core is communicatively connected with the RV core; The processor core is used for: Receive an operation request for a target storage card of a peripheral device issued by a user space; Encapsulating the operation request into a first MMC message packet; The first MMC message packet at least includes: the first instruction ID of the operation request and the ID of the target MMC controller to be driven; Filling the first MMC message packet into the shared memory; The RV core is used to: Taking out the first MMC message packet from the shared memory; An operation instruction is written to a register of the target MMC controller according to the first MMC message packet, wherein the operation instruction is used to drive the target MMC controller to execute an operation corresponding to the first instruction ID on the target memory card.

10. A system-on-chip, characterized in that: It comprises an MMC controller driving system, and the MMC controller driving system is used to execute the MMC controller driving method according to any one of claims 1 to 8.

11. An electronic device, characterized in that: The electronic device comprises the system-on-chip according to claim 9, and the system-on-chip is used to execute the MMC controller driving method according to any one of claims 1-8.

12. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the MMC controller driving method according to any one of claims 1 to 8 is implemented.

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