Test methods, test configuration methods, and related equipment for cache design

Abstract

This application provides a testing method, testing configuration method, and related apparatus for cache design. The testing method includes: acquiring configuration information for test cases, wherein the configuration information includes multiple cache environment parameters and configuration information for multiple test stimuli; wherein the addresses corresponding to the configuration information of the test stimuli cover the performance bottlenecks of the cache design in the cache architecture; configuring the cache environment of the cache design according to the multiple cache environment parameters; generating multiple test stimuli according to the configuration information of the multiple test stimuli; and applying the multiple test stimuli to the simulated cache design to test the cache design. This application embodiment can test the comprehensive performance bottlenecks of the cache design, improving the comprehensiveness of cache design performance testing and enhancing the effectiveness of cache design performance testing.

Description

Technical Field

[0001] This application relates to the field of testing technology, specifically to a testing method, testing configuration method, and related apparatus for cache design. Background Technology

[0002] A cache is a storage device located between the processor and main memory, used to improve the processor's data and instruction access efficiency. For example, a cache can store frequently accessed data and instructions, thereby reducing the number of times the processor accesses main memory and improving the processor's data and instruction access efficiency. Therefore, when designing a cache, its performance has a direct impact on the processor's data and instruction access efficiency.

[0003] The design used for caching can be called cache design. To evaluate and optimize the performance of a cache design, performance testing is necessary. However, how to provide a testing scheme for cache design to improve the effectiveness of performance testing has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a testing method, testing configuration method, and related apparatus for cache design, so as to improve the effectiveness of performance testing of cache design.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a method for testing cache design, including:

[0007] Obtain the configuration information of the test cases, which includes multiple caching environment parameters and configuration information of multiple test stimuli; wherein, the address corresponding to the configuration information of the test stimuli covers the performance bottleneck point of the cache design in the cache architecture.

[0008] Configure the cache environment for the cache design based on the multiple cache environment parameters;

[0009] In addition, multiple test stimuli are generated based on the configuration information of multiple test stimuli;

[0010] Multiple test stimuli are applied to the simulated cache design to test the cache design.

[0011] Secondly, embodiments of this application provide a test configuration method for cache design, including:

[0012] Get test configuration input;

[0013] Based on the test configuration input, the configuration information of the test cases for the configuration cache design is configured; the configuration information of the test cases includes multiple cache environment parameters and configuration information of multiple test stimuli;

[0014] The multiple cache environment parameters are used to configure the cache environment of the cache design, the configuration information of the multiple test stimuli is used to generate multiple test stimuli, and the address corresponding to the configuration information of the test stimuli covers the performance bottleneck point of the cache design in the cache architecture.

[0015] Thirdly, embodiments of this application provide a test system for cache design, including a test stimulus generator and a simulator;

[0016] The test stimulus generator is used to obtain the configuration information of test cases, which includes multiple caching environment parameters and configuration information of multiple test stimuli. The addresses corresponding to the configuration information of the test stimuli cover the performance bottleneck points of the caching design in the caching architecture. The generator configures the caching environment of the caching design according to the multiple caching environment parameters, generates multiple test stimuli based on the configuration information of the multiple test stimuli, and applies the multiple test stimuli to the simulated caching design to test the caching design.

[0017] The simulator is used to simulate cache design; in response to test stimuli applied to the simulated cache design, it obtains test results corresponding to the test stimuli; the test results of each test stimuli of the test case form the test results of the test case.

[0018] Fourthly, embodiments of this application provide a test stimulus device, including at least one memory and at least one processor, wherein the memory stores computer instructions, and the processor invokes the computer instructions stored in the memory to execute the test method for the cache design described in the first aspect.

[0019] Fifthly, embodiments of this application provide a test configuration device, including at least one memory and at least one processor, wherein the memory stores computer instructions, and the processor invokes the computer instructions stored in the memory to execute the test configuration method of the cache design described in the second aspect above.

[0020] Sixthly, embodiments of this application provide a storage medium that stores one or more computer instructions, which, when executed, implement the test method for cache design as described in the first aspect above, or the test configuration method for cache design as described in the second aspect above.

[0021] In a seventh aspect, embodiments of this application provide a computer program product, including one or more computer instructions, which, when executed, implement the test method for cache design as described in the first aspect above, or the test configuration method for cache design as described in the second aspect above.

[0022] The caching design testing method provided in this application embodiment can obtain test case configuration information, which includes multiple caching environment parameters and multiple test incentive configuration information. The addresses corresponding to the test incentive configuration information cover the performance bottleneck points of the caching design in the caching architecture. Then, based on the multiple caching environment parameters, the caching environment of the caching design is configured; and multiple test incentives are generated based on the configuration information of the multiple test incentives. The multiple test incentives are then applied to the simulated caching design to test the caching design.

[0023] As can be seen, the caching design testing method provided in this application embodiment can configure the caching environment of the caching design through multiple caching environment parameters of the test cases. By using the configuration information of multiple test stimuli from the test cases, test stimuli for testing the caching design are generated. Since the addresses corresponding to the configuration information of the test stimuli cover the performance bottlenecks of the caching design within the caching architecture, the addresses corresponding to the generated test stimuli can cover these performance bottlenecks. This enables testing of the performance bottlenecks of the caching design, thereby identifying the location of these bottlenecks. Therefore, the caching design testing method provided in this application embodiment can test all performance bottlenecks of the caching design, improving the comprehensiveness and effectiveness of caching design performance testing. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a structural example diagram of a cache.

[0026] Figure 2 A block diagram of a test system for a cache design provided in an embodiment of this application.

[0027] Figure 3 A flowchart illustrating the test configuration method for the cache design provided in this application embodiment.

[0028] Figure 4This is an example diagram illustrating the composition of configuration information for test cases provided in embodiments of this application.

[0029] Figure 5 Example image of the requested address.

[0030] Figure 6 This is an example diagram illustrating the configuration method of various configuration information for the test incentives provided in the embodiments of this application.

[0031] Figure 7 This is an example diagram of a test configuration table provided in an embodiment of this application.

[0032] Figure 8 A flowchart of a test method for cache design provided in an embodiment of this application.

[0033] Figure 9 Another flowchart of the test method for cache design provided in the embodiments of this application.

[0034] Figure 10 An example diagram of the test platform provided for the implementation of this application.

[0035] Figure 11 A flowchart illustrating the back-annotation test results provided in this application embodiment.

[0036] Figure 12 An example diagram of the performance test result table provided in the embodiments of this application.

[0037] Figure 13 This is an example graph for performance analysis. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] Cache design refers to the design used for caching, which can be represented by cache design documents, such as cache design code written in a hardware description language. The cache design process involves determining design parameters that meet the cache specifications at the initial stage, and analyzing performance bottlenecks after the design is completed. Therefore, performance testing of the cache design is necessary.

[0040] Performance testing of cache designs can be achieved through simulation testing. For example, computer software simulation tools (such as simulators) can use cache design files to simulate the cache design; test stimuli can then be applied to the simulated cache design, and the performance of the cache design can be evaluated by observing its operational behavior under the test stimuli.

[0041] Among them, the test stimulus serves as the input signal for testing the cache design. It can be used to simulate the real hardware operation of the cache design, such as simulating the operation and access scenarios that the cache design may encounter in the actual operating environment. At the same time, in order to discover the performance bottlenecks of the cache design, the test stimulus needs to test the performance bottlenecks of the cache design (such as impact testing). That is, the test stimulus needs to be configured purposefully so that the test stimulus can cover the performance bottlenecks of the cache design.

[0042] It should be explained that the performance bottleneck of cache design may lie at different levels of the cache structure. For ease of understanding, Figure 1 An example diagram of a cache structure is shown, such as... Figure 1 As shown, the cache can receive access requests from upstream modules (e.g., processor cores) through multiple cache input ports. That is, the cache input ports are channels used to manage and control the flow of access requests from upstream modules (e.g., processor cores) to the cache. Optionally, multiple cache input ports can be adapted to a multi-processor core architecture. For example, multiple cache input ports allow multiple data requests to be processed simultaneously, thereby improving the cache's parallel processing capability. For instance, different processor cores can simultaneously initiate access requests to different cache input ports to reduce cache input port contention and waiting time between multiple memory access requests. It should be noted that the number of cache input ports can be determined according to the cache design requirements, and this embodiment does not impose a limitation.

[0043] The hierarchical structure of a cache mainly consists of cache libraries, cache sets, and cache lines; such as Figure 1As shown, a cache can contain multiple cache libraries, a cache library can include multiple cache sets, and a cache set can include multiple cache lines. A cache library is a partition of the cache. Multiple cache libraries can be designed to process multiple access requests in parallel; for example, each cache library can independently perform data read and write operations, thereby improving the cache's access response speed and efficiency. A cache set is a component of a cache library, containing a set of cache lines. The address of each access request for the cache can be mapped to a cache set, and the cache lines within that set can store the data corresponding to that address. The main function of a cache set is to organize cache lines and implement cache replacement strategies, thereby managing the storage and updating of data in the cache. A cache line is the basic storage unit of the cache, containing a block of data read from memory at once; that is, the cache line stores the actual data. The size of a cache line can be set, such as 32 bytes, 64 bytes, etc.

[0044] It should be noted that the number of cache libraries in the cache, the number of cache sets in each cache library, and the number of cache lines in each cache set can be determined according to the design requirements of the cache, and this application embodiment does not impose any limitations.

[0045] Based on the above-mentioned hierarchical structure of the cache, the address of the access request sent by the upstream module of the cache (such as the processor core) can be organized according to the hierarchical addressing method of cache library, cache set, and cache line. For example, the address of the access request can carry cache library addressing bits (for addressing the cache library), cache set addressing bits (for addressing the cache set), and label bits (for addressing the cache line). Therefore, after the access request is passed to the cache input port, based on the cache library addressing bit of the access request address, the access request can be passed to the target cache library corresponding to the cache library addressing bit; based on the cache set addressing bit of the access request address, the target cache set to which the access request is directed in the target cache library can be determined (the target cache set corresponds to the cache set addressing bit); furthermore, based on the label bit of the access request address, it can be determined whether there is a target cache line corresponding to the label bit in the cache lines organized by the target cache set; if it exists, the access request hits the cache, and the access operation (such as read, write, etc.) corresponding to the access request can be performed in the target cache line; if it does not exist, the access request misses the cache, and a cache fill operation needs to be triggered to pull the data corresponding to the address from memory and fill it into the target cache line, so as to try the access again.

[0046] In the above-mentioned hierarchical structure of caching, performance bottlenecks can occur in the cache library, cache set, and cache line (i.e., the cache library, cache set, and cache line can all become performance bottlenecks). Furthermore, the performance bottlenecks may differ between different cache designs. For example, due to differences in microarchitecture, different cache designs may result in different specific locations of performance bottlenecks in the cache library, cache set, and cache line.

[0047] Therefore, when generating test stimuli for cache design, the test stimuli need to cover the performance bottlenecks of the cache design as much as possible. That is, generating test stimuli needs to consider the comprehensive coverage of performance bottlenecks and improve the coverage of performance bottlenecks of cache design by test stimuli.

[0048] As an optional implementation Figure 2 An exemplary block diagram of a test system for a cache design provided in an embodiment of this application is shown, such as... Figure 2 As shown, the test system may include: a test configuration device 210 and a test platform 220.

[0049] Test configuration device 210 is an electronic device used to test and configure cache design. For example, test configuration device is mainly used to configure test cases for cache design. Configuring test cases for cache design can be regarded as setting configuration information for test cases of cache design. A test case can include multiple test stimuli.

[0050] In an optional implementation, the test configuration device can be an electronic device usable by testers. Testers can input the configuration information of test cases (i.e., set the configuration information of test cases) through the graphical user interface or command-line interface provided by the test configuration device, thereby implementing the test cases for configuring the cache design. In this optional implementation, the embodiments of this application support testers manually configuring the configuration information of test cases. In other optional implementations, the configuration information of test cases may not be provided by testers, but automatically generated by the test configuration device; for example, testers can input the test requirements of the cache design into the test configuration device, so that the test configuration device can automatically generate the configuration information of test cases based on the test requirements, thereby implementing the test cases for configuring the cache design.

[0051] Test platform 220 is a device platform for testing cache design. For example, test platform 120 can simulate cache design and generate multiple test stimuli based on the configuration information of test cases configured by test configuration device 210, and then use multiple test stimuli to perform performance testing on the simulated cache design.

[0052] In an optional implementation, the test platform can be a software and hardware system platform for testing cache design, which at least implements functions such as generating test stimuli and software simulation (simulating cache design and responding to test stimuli). In an optional implementation, the test platform can be implemented as a single device or a device system composed of multiple devices; different functions implemented by the test platform can be implemented by different software components or different devices. Of course, the embodiments of this application can also support the integration of some functions implemented by the test platform into the same software component or device, and the embodiments of this application do not set any limitations in this regard.

[0053] In one alternative implementation example, the test configuration device can be implemented as a front-end device for testers to use and operate; the test platform can be implemented as a back-end device or a back-end device system (the device system can consist of multiple devices) to provide test services for cache design.

[0054] The following sections describe the solutions provided in this application from the perspectives of test configuration of cache design and test of cache design, based on test configuration equipment and test platform.

[0055] As an optional implementation Figure 3 An exemplary flowchart illustrates a test configuration method for a cache design provided in an embodiment of this application. This test configuration method can be implemented by a test configuration device. (Refer to...) Figure 3 The process of this test configuration method may include the following steps.

[0056] In step S310, test configuration input is obtained.

[0057] In step S311, based on the test configuration input, the configuration information of the test cases for the cache design is configured.

[0058] The test configuration for a cache design can be achieved by configuring the test cases for the cache design. The test case configuration information can include at least several cache environment parameters for the cache design, as well as configuration information for multiple test stimuli. In other words, configuring a test case for a cache design can be achieved by configuring the cache environment that the test case will test, and by configuring multiple test stimuli to test the cache design in that cache environment.

[0059] As an optional implementation, the test configuration input can be the configuration content of the test cases entered by the tester. Therefore, according to the configuration content of the test cases entered by the tester, this embodiment of the application can configure multiple cache environment parameters and configuration information of multiple test stimuli for the test cases. For example, this embodiment of the application supports testers manually filling in the configuration information of the test cases, including manually filling in each cache environment parameter and the configuration information of each test stimulus.

[0060] In other optional implementations, the test configuration input can be the performance test requirements of the cache design entered by the tester. The performance test requirements can be the performance test content of the cache design expressed by the tester in text or natural language. Thus, the embodiments of this application can support the automatic generation of configuration information for test cases of the cache design when the tester enters the performance test requirements of the cache design expressed in text or natural language. This includes multiple cache environment parameters that match the cache environment of the cache design expressed in text or natural language, as well as configuration information for multiple test stimuli that meet the performance test requirements expressed in text or natural language.

[0061] In the optional implementation, Figure 4 An exemplary diagram illustrating the composition of configuration information for test cases provided in embodiments of this application is shown, such as... Figure 4 As shown, the configuration information for a test case can include: test case identifier, multiple cache environment parameters, and configuration information for multiple test stimuli.

[0062] The test case identifier can be a unique identifier for a test case, used to distinguish different test cases; in an optional implementation, the test case identifier may be, for example, the test case name.

[0063] Multiple caching environment parameters can indicate the caching environment of a caching design, such as the caching specifications. For example, multiple caching environment parameters for a caching design might include the cache size (i.e., cache capacity) and the depth of the first-in, first-out (FIFO) queue in the cache. Multiple caching environment parameters in the test case configuration information can be used to generate the caching environment configuration stimulus for the test cases. The caching environment configuration stimulus is the input signal for configuring the environment parameters of the caching design to create a caching environment that meets the performance testing requirements, so that the performance of the caching design can be evaluated within that environment. The performance of the caching design can be represented by performance metrics, such as the caching design's bandwidth, request data return time, request handshake time, number of incomplete requests, cache hit rate, and access latency.

[0064] It's important to note that the cache architecture in cache design refers to the basic structure and characteristics of the cache determined during the design phase, such as the cache hierarchy. In contrast, cache environment configuration stimuli (generated from multiple cache environment parameters of test cases) are parameters used to adjust the cache environment of the cache design, based on the cache architecture, to adapt to different test scenarios.

[0065] Continue to refer to Figure 4In an optional implementation, the configuration information of a test stimulus can be used to generate a test stimulus. The configuration information of a test stimulus may include the test stimulus's request feature configuration information, address configuration information, transport configuration information, and extended configuration information.

[0066] The request feature configuration information can be configuration information related to the request characteristics and request behavior of the test stimulus, including but not limited to: the number of requests, the request type, and the request data size. The number of requests is the number of requests issued by a single test stimulus (in this embodiment, a request can be a test request corresponding to the test stimulus used for performance testing of the cache design). The request type is the operation type of the request, such as read (read-only), write (write-only), or random (i.e., randomly selecting the operation type between read and write operations). The request data size is the amount of data involved in the request, such as the amount of data read in a read request or the amount of data written in a write request.

[0067] It should be noted that the above-described request feature configuration information is merely an example. Since the request feature configuration information relates to the request characteristics and behaviors of the test incentive, the embodiments of this application can configure the specific content of the request feature configuration information according to actual circumstances, and are not limited to the above-described example. For example, not all of the request feature configuration information in the above example may be used; some may be selected for use, or some request feature configuration information may be adjusted and modified before use.

[0068] Address configuration information refers to the configuration information of the addresses involved in the test stimulus, which determines the data access location of the test stimulus, including but not limited to the request address range, starting address, request address type, and address granularity. The request address range refers to the upper and lower limits of the request address. The starting address is the starting address of the request from the test stimulus, i.e., the address point where the request begins. The request address type is the address change pattern of the request, such as a random address pattern (the request address is randomly determined) or an incrementing address pattern (the request address changes in an incrementing manner). The address granularity is the smallest unit of address change for the request; that is, the address granularity determines the degree of address change in the request.

[0069] The transmission configuration information is related to the transmission of test stimulus requests, including but not limited to cached input ports and transmission priorities. A cached input port refers to the cached input port used to transmit test stimulus requests (simply referred to as the cached input port corresponding to the test stimulus); optionally, the cached input port can be represented by a cached input port identifier (e.g., cached input port number). Transmission priority refers to the transmission order of test stimulus requests at the corresponding cached input ports; that is, the transmission priority determines the order in which test stimulus requests are sent to the cached design at the corresponding cached input ports.

[0070] Extended configuration information refers to custom configuration parameters for test stimuli, allowing testers to customize these parameters according to specific test requirements, thus adapting to complex and variable performance testing scenarios in cache design. While extended configuration information can be customized based on the performance testing needs of the cache design, this embodiment does not impose any limitations on it.

[0071] As an optional implementation, the configuration information for test cases in the cache design can be configured according to the performance testing requirements of the cache design. For example, multiple cache environment parameters and test stimulus configuration information in the test case configuration information can be defined according to the performance testing requirements of the cache design.

[0072] In an optional implementation, embodiments of this application can define multiple cache environment parameters in the configuration information of test cases according to the performance testing requirements of the cache design. For example, based on the cache environment required by the performance testing requirements of the cache design, multiple cache environment parameters such as the corresponding cache size and the depth of the first-in-first-out queue in the cache can be configured so that the cache environment of the cache design indicated by the configured multiple cache environment parameters matches the cache environment required by the performance testing requirements of the cache design. It should be noted that the cache environment of the cache design required by the performance testing requirements can be determined according to the actual testing situation, and embodiments of this application do not set limitations.

[0073] In an optional implementation, embodiments of this application can define the configuration information of each test stimulus in the configuration information of the test cases according to the performance testing requirements of the cache design. Optionally, in order to improve the coverage of the test stimulus for the performance bottlenecks of the cache design, when defining the configuration information of the test stimulus, it is necessary to ensure that the address corresponding to the configuration information of the test stimulus (i.e., the address of the request corresponding to the test stimulus) covers the performance bottlenecks of the cache design.

[0074] As a further optional implementation, different caching designs may result in different locations of performance bottlenecks in the cache library, cache set, and cache line due to differences in microarchitecture. Therefore, when configuring the configuration information of the test incentive, the address corresponding to the configuration information of the test incentive (e.g., the address corresponding to the request of the test incentive) should cover the performance bottleneck of the cache design in the corresponding cache architecture, so as to improve the possibility of the test incentive covering the performance bottleneck of the cache design.

[0075] In an optional implementation, embodiments of this application may configure at least the address granularity in the address configuration information of the test stimulus, so that the address corresponding to the configuration information of the test stimulus covers the performance bottleneck point of the cache design corresponding to the cache architecture. As an implementation example, combined with Figure 1 The cache structure shown may present a performance bottleneck in the following situations:

[0076] The overall cache may have performance bottlenecks. For example, when all cache libraries in the cache receive access requests from upstream modules, if the number of access requests is too large and the overall processing capacity of the cache is limited, it may lead to overall performance bottlenecks in the cache. Correspondingly, all cache libraries in the cache may be the performance bottleneck points of the cache.

[0077] Specific cache libraries may have performance bottlenecks. For example, if a specific cache library in the cache receives too many access requests, and its processing capacity is insufficient to handle these requests, it may lead to a performance bottleneck for that specific cache library. Accordingly, a specific cache library in the cache may be the performance bottleneck point of the cache.

[0078] A specific cache set may have a performance bottleneck. For example, if a specific cache set receives too many access requests, and the processing capacity of that specific cache set is limited, it may lead to a performance bottleneck for that specific cache set. Accordingly, a specific cache set in the cache may be the performance bottleneck point of the cache.

[0079] In other words, caching performance bottlenecks may exist in scenarios where upstream modules send access requests to all cache libraries, to a specific cache library, or to a specific cache set. Therefore, embodiments of this application can configure the address granularity of at least multiple test stimuli in test cases based on the cache architecture corresponding to the cache, so that the addresses corresponding to multiple test stimuli can cover the performance bottlenecks of the cache design under the cache architecture (e.g., all cache libraries, a specific cache library, a specific cache set, etc. under the cache architecture). Specifically, the performance bottlenecks of the cache design under the cache architecture can be determined by analyzing the cache architecture of the cache design; for example, by analyzing the cache architecture of the cache design, a series of performance bottlenecks can be identified (e.g., specific cache libraries and specific cache sets that may potentially experience performance bottlenecks), and these performance bottlenecks require a series of test stimuli for test coverage.

[0080] To facilitate further understanding, Figure 5 An example diagram of a requested address is shown below, such as... Figure 5 As shown, the requested address, from least significant bit to most significant bit, includes cache library addressing bits, cache set addressing bits, and a label bit. The cache library addressing bits are used to address the cache library, i.e., the target cache library to which the requested address belongs in the cache; the cache set addressing bits are used to address the cache set, i.e., the target cache set to which the requested address belongs in the target cache library; and the label bit indicates the target cache line to be accessed within the target cache set. The hierarchical addressing method based on cache libraries, cache sets, and cache lines can be referred to the corresponding sections above, and will not be elaborated upon here. It should be noted that, combined with… Figure 5As shown, assuming the cache library addressing bits are N bits, the cache set addressing bits are M bits, and the label bits are K bits, then the cache can include 2 N There are 2 cache libraries, each cache library can include 2 M There are three cache sets, each containing K cache lines. The specific values ​​of N, M, and K can be determined based on the cache architecture of the cache design, and different cache architectures may have different values ​​for N, M, and K.

[0081] In an optional implementation, embodiments of this application can configure the address granularity according to the type of performance bottleneck to be tested by the test stimulus, so that the address change granularity of the test stimulus request corresponds to the type of performance bottleneck to be tested by the test stimulus.

[0082] For example, if the performance bottleneck to be tested is any cache library in the cache, then the address granularity of the test stimulus can be configured to correspond to the cache library addressing bits. In other words, the address granularity of the test stimulus can be configured to adjust the cache library addressing bits, thereby allowing different cache libraries to be tested through different requests from the test stimulus by changing the cache library addressing bits. For instance, to test the performance of all cache libraries, the value of N bits of the cache library addressing bits can be changed to generate requests pointing to different cache libraries, thus covering all cache libraries in the cache.

[0083] For example, if the performance bottleneck to be tested by the test stimulus is a specific cache library, then, with a fixed cache library addressing bit corresponding to the specific cache library (fixed cache library addressing bits can be achieved by fixing the request address range, for example, fixing the request address range to the address range of the specific cache library), the address granularity of the test stimulus can be configured to correspond to the cache set addressing bit. In other words, the address granularity of the test stimulus can be set to adjust the cache set addressing bit. Therefore, with a fixed cache library addressing bit, by changing the cache set addressing bit, different requests can be generated by the test stimulus to test the performance of different cache sets within the specific cache library, thus achieving performance testing of the specific cache library. For example, to test the performance of a specific cache library, the value of the N-bit cache library addressing bit can be fixed, and the value of the M-bit cache set addressing bit can be changed to generate requests pointing to different cache sets of the specific cache library.

[0084] For example, if the performance bottleneck to be tested is a specific cache set, then, with a fixed cache set addressing bit corresponding to the specific cache set (this can be achieved by fixing the request address range, for example, fixing the request address range to the address range of the specific cache set), the address granularity of the test stimulus can be configured to correspond to the label bit. In other words, the address granularity of the test stimulus can be set to adjust the label bit. Therefore, with a fixed cache set addressing bit, different requests can be generated by changing the label bit to test the performance of the specific cache set. For example, to test the performance of a specific cache set, the value of the M-bit cache set addressing bit can be fixed, and the value of the K-bit label bit can be changed to generate different requests pointing to the specific cache set.

[0085] In other words, the address granularity of the test stimulus can be defined based on whether the performance bottleneck to be tested is all cache libraries, a specific cache library, or a specific cache set. When performing performance bottleneck impact tests on all cache libraries, a specific cache library, or a specific cache set, different address granularities need to be used accordingly.

[0086] In a further optional implementation, the address granularity of the multiple test stimuli configurations for test cases should cover all performance bottlenecks in the cache design, such as all cache libraries, specific cache libraries, and specific cache sets. Therefore, when configuring multiple test stimuli, the following test stimuli can be included:

[0087] Address granularity is used to adjust the test stimulus for cache library addressing bits. Different requests generated by this test stimulus can point to different cache libraries, thereby covering all cache libraries in the cache.

[0088] For any given cache library, the address granularity is used to adjust the test stimulus for cache set addressing bits. Different requests generated by this test stimulus can point to different cache sets of the specific cache library, thereby covering the specific cache library. Optionally, there may be multiple specific cache libraries, so there can be multiple test stimuli in this case.

[0089] For any given cache set, address granularity is used to adjust the test stimuli of the label bit. Different requests generated by this test stimuli can all point to the specific cache set, thereby covering the specific cache set. Optionally, there may be multiple specific cache sets, so there can be multiple test stimuli in this case.

[0090] In a further optional implementation, Figure 6 An example diagram illustrating the configuration method of various configuration information of the test stimulus provided in the embodiments of this application is shown. Figure 6From the perspective of the configuration format and configuration description of each configuration information of the test incentive, the configuration method of the configuration information is illustrated with examples as follows.

[0091] The number of requests can be configured as a specific request number value; the number of requests can be different for different test stimuli for different cache input ports. For example, different test stimuli can be designed for different cache input ports, and different test stimuli can be set with different request numbers.

[0092] The request type can be configured as read, write, or random; the test stimulus will issue read requests, write requests, or a random combination of read and write requests according to the request type configuration.

[0093] The requested data size can be configured as either random or fixed. The test stimulus determines the size of read or write requests based on this configuration. Optionally, the cache design can support requests of different data sizes, allowing the choice between random or fixed data sizes to be made based on the performance testing requirements of the cache design.

[0094] The request address range can be configured as a specific range of address values; in an optional implementation, the configured request address range can be determined based on the performance testing requirements of the cache design.

[0095] For example, if the performance testing requirement is to test the cache hit rate under simulated actual access scenarios of the cache design, the request address range can be configured based on the cache hit rate. For instance, the cache hit rate and the request address range can be negatively correlated (i.e., the higher the cache hit rate, the smaller the configured request address range, and the lower the cache hit rate, the larger the configured request address range). In other words, cache hit and miss scenarios will directly affect cache performance. The higher the cache hit rate, the better the cache performance, and the lower the cache hit rate, the worse the cache performance. Therefore, the cache hit rate can be controlled by configuring the request address range.

[0096] For example, if the performance testing requirement is to perform a stress test on a performance bottleneck (e.g., all cache libraries, a specific cache library, or a specific cache set), then the request address range can be configured to correspond to the request address range of the performance bottleneck. For instance, if a stress test is performed on all cache libraries, the request address range can be the address range of the entire cache. If a stress test is performed on a specific cache library, the request address range can be the address range of the specific cache library (e.g., the request address range can be configured to fix the cache library addressing bits to correspond to the specific cache library). If a stress test is performed on a specific cache set, the request address range can be the address range of the specific cache set (e.g., the request address range can be configured to fix the cache set addressing bits to correspond to the specific cache library).

[0097] As can be seen, in the optional implementation, the performance testing scenarios for cache design can be divided into performance bottleneck testing scenarios and actual access scenarios simulating cache design. Cache design may have different performance testing requirements under different performance testing scenarios. The request address range can be configured according to the performance testing requirements under different performance testing scenarios. For example, in the impact testing scenario of performance bottleneck, the request address range is configured to determine the address range of the performance bottleneck. Another example is in the actual access scenario simulating cache design, the request address range is configured to control the cache hit rate of the test.

[0098] The starting address can be configured as a specific initial address value requested. In an optional implementation, the starting address can be determined based on the performance testing requirements of the cache design. For example, if the performance testing requirement is to perform a stress test on a performance bottleneck (e.g., all cache libraries, a specific cache library, or a specific cache set), the starting address can be configured to correspond to the starting address of the performance bottleneck. For instance, if a stress test is performed on all cache libraries, the starting address could be the starting address of the first cache library in the cache; if a stress test is performed on a specific cache library, the starting address could be the starting address of the first cache set of that specific cache library; and if a stress test is performed on a specific cache set, the starting address could be the starting address of the first cache line of that specific cache set.

[0099] The request address type can be configured as either an incrementing address mode or a random address mode. In the optional implementation, the configured request address type can be determined based on the performance testing requirements of the cache design. For example, when the performance testing requirement is to perform impact testing on performance bottlenecks (e.g., all cache libraries, a specific cache library, or a specific cache set), the request address type can be configured as an incrementing address mode, allowing the requested address to increment within the range of request addresses, starting from the initial address and increasing in granular increments. Alternatively, when simulating actual access scenarios of the cache design, the request address type can be configured as a random address mode, allowing the requested address to be randomly adjusted within the range of request addresses, based on the initial address.

[0100] Address granularity can be configured as a value representing the granularity of address changes for each request, such as the granularity of address changes for the next request in a test stimulus compared to the previous request. Optionally, the address granularity can be determined based on the type of performance bottleneck. Details regarding address granularity can be found in the relevant sections above and will not be elaborated upon here.

[0101] Based on the address configuration information of the test stimulus configured in this application embodiment (e.g., request address range, starting address, request address type, address granularity, etc.), when performing impact testing on performance bottlenecks (e.g., all cache libraries, specific cache libraries, specific cache sets), this application embodiment can generate multiple test stimulus requests within the request address range corresponding to the performance bottleneck to be tested, based on the starting address of the performance bottleneck, in an address increment pattern. The address increment in the address increment pattern is the address granularity corresponding to the type of the performance bottleneck, thereby testing and covering the performance bottleneck. In other words, in the address increment pattern, the address of the next request of the test stimulus will increment based on the address of the previous request, and the increment magnitude (i.e., address increment) is the address granularity corresponding to the type of the performance bottleneck. That is, the type of the performance bottleneck determines the address increment magnitude of the test stimulus requests.

[0102] For example, taking the impact test on a specific cache library as an example, this embodiment of the application can generate multiple test stimuli within the request address range corresponding to the specific cache library, based on the starting address of the test for the specific cache library, and in an address increment pattern. The address increment in the address increment pattern is the address granularity corresponding to the cache library, thereby performing performance testing on the specific cache library and covering the specific cache library. The impact test of all cache libraries and specific cache sets can be similarly referred to, and will not be elaborated here.

[0103] Continue to refer to Figure 6 As shown, the cached input ports can be configured as all cached input ports or a specific cached input port. For example, all cached input ports or a specific cached input port can be configured to correspond to the test stimulus. The specific cached input port corresponding to the test stimulus can be determined according to the requirements, and this application embodiment does not impose any limitations. Configuring cached input ports can be achieved by configuring cached input port identifiers (e.g., cached input port numbers), that is, the cached input port is represented by the cached input port identifier (e.g., cached input port number).

[0104] Transmission priority, configured as a specific value for transmission priority (e.g., the value of transmission priority can be selected within a limited range), represents the transmission priority of the test stimulus request on the corresponding cached input port.

[0105] Extended configuration information, configured in a custom format, allows testers to customize the configuration parameters of the extended test stimulus according to specific test requirements, in order to meet the specific performance configuration needs of the cache design.

[0106] In an optional implementation, embodiments of this application can configure different cache input ports to correspond to different test stimuli according to the specific performance testing requirements of the cache design. This allows multiple cache input ports to be configured with multiple different test stimuli, thus forming a single test case. Alternatively, embodiments of this application can also support configuring one test stimulus to correspond to all cache input ports, or one test stimulus can correspond to multiple cache input ports, and the cache input ports corresponding to different test stimuli can partially or completely overlap.

[0107] In a further optional implementation, the configuration information of test cases can be stored in a save file. For example, the save file may contain configuration information for multiple test cases. In an optional implementation example, the save file may be in table format, thus allowing the test case configuration information to be stored through a table structure. For ease of explanation, the table storing the test case configuration information is referred to as the test configuration table in this application embodiment. In an optional implementation, Figure 7 An exemplary diagram of an optional test configuration table provided in an embodiment of this application is shown, such as... Figure 7 As shown, the test configuration table can include multiple test case configuration areas. Each test case configuration area can include a test case identifier field, a cache environment parameter configuration area, and a test stimulus configuration area.

[0108] The Test Case Identifier Configuration field is used to configure the test case identifier. For example, if the Test Case Identifier Configuration field is the Test Case Name field, it can be used to configure or fill in the test case name.

[0109] The cache environment parameter configuration area can include multiple cache environment parameter configuration fields, which are used to configure multiple cache environment parameters of the cache design. For example, one cache environment parameter configuration field can configure one cache environment parameter.

[0110] The test incentive configuration area is used to configure the configuration information for multiple test incentives for test cases. The test incentive configuration area may include multiple request feature configuration fields (used to configure the request feature configuration information of the test incentive), multiple address configuration fields (used to configure the address configuration information of the test incentive), multiple transport configuration fields (used to configure the transport configuration information of the test incentive), and multiple extended configuration fields (used to configure the extended configuration information of the test incentive).

[0111] Combination Figure 7 As shown, multiple request feature configuration fields may include: a request number configuration field, used to configure the number of requests for the test incentive; a request type configuration field, used to configure the request type for the test incentive; and a request data size configuration field, used to configure the request data size for the test incentive.

[0112] Multiple address configuration fields may include: a request address range configuration field, used to configure the request address range of the test stimulus; a start address configuration field, used to configure the starting address of the test stimulus; a request address type configuration field, used to configure the request address type of the test stimulus; and an address granularity configuration field, used to configure the address granularity of the test stimulus.

[0113] Multiple transmission configuration fields may include: a cached input port configuration field, used to configure the cached input port corresponding to the test stimulus; and a transmission priority configuration field, used to configure the transmission priority of the test stimulus.

[0114] The configuration methods for the configuration information corresponding to each configuration field can be found in the descriptions of the corresponding sections above, and will not be repeated here.

[0115] In an optional implementation, the test configuration table can store content by column (e.g., rows or columns). For example, for the configuration information of any test case, one column of the test configuration table can store the test case identifier, another column can store a cache environment parameter, and yet another column can store the configuration information of a test stimulus. For example, Figure 7 In the example, the test configuration table can save its content row by row, so that for any test case, the test case identifier is saved on one row, a cache environment parameter is saved on one row, and the configuration information of a test stimulus is saved on one row. Of course, this embodiment of the application can also support a column-based format, so that the test configuration table can save its content column by column. This embodiment of the application does not limit the way the test configuration table saves its content column by column, as long as it can ensure that the configuration information of the test cases is saved in an organized and structured manner in the test configuration table.

[0116] The test configuration method for cache design provided in this application embodiment can configure the configuration information of test cases for the cache design based on test configuration input. The configuration information of the test cases can include at least multiple cache environment parameters of the cache design and configuration information of multiple test stimuli. The addresses corresponding to the configuration information of the test stimuli cover the performance bottlenecks of the cache design in the corresponding cache architecture. The test configuration method for cache design provided in this application embodiment can configure the cache environment of the cache design through multiple cache environment parameters; it can generate test stimuli for testing the cache design through the configuration information of multiple test stimuli, and the addresses corresponding to the configured test stimuli cover the performance bottlenecks of the cache design in the corresponding cache architecture, thereby providing a configuration basis for testing the performance bottlenecks of the cache design, so as to discover the performance bottlenecks of the cache design.

[0117] Therefore, the test configuration method for cache design provided in this application embodiment can provide a foundation for comprehensive performance bottleneck testing of cache design, improving the comprehensiveness of cache design performance testing. Furthermore, cache designs with different architectures can similarly configure test case configuration information according to the test configuration method provided in this application embodiment, thereby supporting performance testing of different cache designs (for example, the configuration information of test cases configured for different cache designs can be stored in different test case configuration areas of the test configuration table). Therefore, the test configuration method for cache design provided in this application embodiment can be applied to different cache designs. Thus, the test configuration method for cache design provided in this application embodiment can support the improvement of the comprehensiveness of cache design performance testing and has universality, providing support and a configuration foundation for improving the effectiveness of cache design performance testing.

[0118] Based on the test configuration method for cache design provided in the embodiments of this application, this application provides a test method for cache design. For example, the configuration information of the test cases configured by the test configuration method provided in the embodiments of this application can be used in the test method for cache design provided in the embodiments of this application. The content of the test configuration method and the test method for cache design provided in the embodiments of this application can be referred to in correspondence with each other.

[0119] As an optional implementation Figure 8 An exemplary flowchart of an optional test method for cache design provided in an embodiment of this application is shown. This test method for cache design can be implemented by a test platform. Figure 8 The process of this testing method may include the following steps.

[0120] In step S810, the configuration information of the test cases is obtained. The configuration information of the test cases includes multiple cache environment parameters and multiple test incentive configuration information. The address corresponding to the configuration information of the test incentives covers the performance bottleneck point of the cache design in the cache architecture.

[0121] In an optional implementation, embodiments of this application can obtain the configuration information of each test case by reading a saved file of the test case configuration information (e.g., a test configuration table); furthermore, for the configuration information of any test case, embodiments of this application can be based on... Figure 8 The method shown generates test cases (including configuring the cache environment of the cache design and generating multiple test stimuli) to test the cache design.

[0122] In an optional implementation, this embodiment of the application can read the configuration information of each test case from the saved file by reading iteratively. In one implementation example, for any test case, for the multiple cache environment parameters of the read test case, this embodiment of the application can use multiple cache environment parameters to configure the cache environment of the cache design. For the configuration information of the read test stimuli, this embodiment of the application can save the configuration information of each test stimulus of the test case in the stimulus saving table according to the cache input port identifier corresponding to the test stimulus; thus, after the configuration information of all test stimuli of the test case has been read into the stimulus saving table, multiple test stimuli of the test case are generated.

[0123] In a further optional implementation, this embodiment of the application can initialize a stimulus storage table, which is used to store the configuration information of test stimuli according to the cache input port identifier. Then, the saved file of the test case configuration information (e.g., a test configuration table) is read cyclically until the file reading is complete. During the reading of the saved file, if the configuration information of a new test case is started, multiple cache environment parameters and the configuration information of each test stimulus can be read from the configuration information of the new test case. Then, the read configuration information of each test stimulus is saved to the stimulus storage table according to the cache input port identifier. In an optional implementation example, the stimulus storage table can be a hash table.

[0124] As an optional implementation, taking the test configuration table as a file for saving, and the test configuration table can save content by column (e.g., row or column); thus, for the configuration information of any test case, one column of the test configuration table can save the test case identifier, one column can save a cache environment parameter, and one column can save the configuration information of a test stimulus; furthermore, after initializing the stimulus saving table (e.g., hash table) in this embodiment, each column of the test configuration table can be read in a loop until the test configuration table is finished reading; during the process of reading the test configuration table, if the column containing the test case identifier is read, it can be confirmed that the configuration information of a new test case has started to be read, so that multiple cache environment parameters can be read from the columns containing multiple cache environment parameters, and the configuration information of each test stimulus can be read from the columns containing the configuration information of each test stimulus, and the read configuration information of each test stimulus can be saved to the stimulus saving table according to the cache input port identifier.

[0125] As an example, the process of reading the configuration information of test cases from the test configuration table can be as follows:

[0126] Initialize a hash table to store the configuration information of the test stimuli according to the cached input port identifier;

[0127] Open the test configuration table, which contains configuration information for multiple test cases;

[0128] Read each row of the test configuration table in a loop until the test configuration table is finished reading;

[0129] If a new test case identifier is detected during the process of reading the test configuration table in a loop, open the file section in the test configuration table related to that test case identifier (e.g., the test case configuration area related to that test case identifier);

[0130] If multiple cache environment parameters are identified in the file section related to the test case identifier (e.g., multiple cache environment parameter configuration fields are identified), then multiple cache environment parameters are read and added to the new test case for configuring the cache environment of the cache design.

[0131] If the read rows contain configuration information for test stimuli (e.g., multiple rows containing the test stimuli configuration area are identified), then the configuration information of each test stimuli read row by row is stored in a hash table according to different cache input port identifiers, until the last row of the test stimuli configuration information is read; at this point, the configuration information of one test case has been read. If the test configuration table still contains the configuration information for the next new test case, then the reading of the new test case configuration information continues. If the test configuration table has been read completely, then the reading of the test case configuration information ends.

[0132] In step S811, the cache environment of the cache design is configured according to the cache environment parameters.

[0133] After obtaining the cache environment parameters from the test case configuration information, the cache environment of the cache design can be configured according to the cache environment parameters to create a cache environment that meets the performance testing requirements. In an optional implementation, this embodiment of the application can generate a cache environment configuration stimulus for the cache design based on the cache environment parameters; and apply the cache environment configuration stimulus to the simulated cache design to configure the cache environment of the cache design.

[0134] In an optional implementation, for any test case, after reading any cache environment parameter of the test case from a saved file (e.g., a test configuration table), this embodiment of the application can generate a cache environment configuration stimulus based on the read cache environment parameter and apply it to the simulated cache design. In other possible implementations, for any test case, after reading all multiple cache environment parameters of the test case from a saved file (e.g., a test configuration table), this embodiment of the application can generate a cache environment configuration stimulus based on the multiple cache environment parameters and apply it to the cache design.

[0135] In step S812, multiple test stimuli are generated based on the configuration information of multiple test stimuli.

[0136] After obtaining the configuration information of multiple test stimuli in the configuration information of the test cases, this embodiment of the application can generate a request corresponding to the test stimulus based on the configuration information of any test stimulus.

[0137] In an optional implementation, if the configuration information of multiple test stimuli for a test case is stored in a stimulus storage table (e.g., a hash table) according to the cached input port identifier, then this embodiment can generate test stimuli corresponding to each cached input port according to the port order of the cached input ports corresponding to the test stimuli. That is, after obtaining the configuration information of all test stimuli for the test case and storing it in the stimulus storage table (e.g., a hash table), this embodiment can generate the test stimuli that need to be transmitted for each cached input port according to the port sequence number of the cached input ports. Generating test stimuli can be regarded as a request to generate test stimuli, and the number of test stimuli requests can be determined by the number of requests in the test stimuli configuration information.

[0138] In one implementation example Figure 9 An exemplary flowchart illustrates another optional flowchart of the test method for cache design provided in an embodiment of this application. Figure 9 From reading and saving the file to generating test stimuli, the process of generating test cases is illustrated (including the cache environment configuration stimuli for generating test cases and each test stimuli). Figure 9 As shown, the process may include the following steps.

[0139] In step S910, it is determined whether the identifier of the new test case is read from the saved file. If not, step S911 is executed; if yes, step S912 is executed.

[0140] In step S911, the reading and saving of the file is completed.

[0141] If no identifier for a new test case can be read from the saved file, it means that the configuration information of the test cases in the saved file has been read completely, and the reading of the saved file can be stopped.

[0142] In step S912, the configuration content of the new test case is read.

[0143] In step S913, it is determined whether the read content is the cache environment parameter of the new test case. If yes, step S914 is executed; otherwise, step S915 is executed.

[0144] In step S914, a cache environment configuration stimulus is generated, and the process returns to step S913.

[0145] In step S915, it is determined whether the read content is the configuration information of the test stimulus for the new test case. If yes, step S916 is executed; otherwise, step S917 is executed.

[0146] In step S916, the configuration information of the read test stimulus is saved in the stimulus saving table according to the cache input port identifier corresponding to the test stimulus, and the process returns to step S915.

[0147] In step S917, test stimuli corresponding to each cache input port are generated according to the configuration information of the test stimuli for each cache input port stored in the stimulus storage table.

[0148] In an optional implementation, the configuration content of a new test case, read column by column based on the saved file, may be either cached environment parameters or test stimulus configuration information. When the read configuration content of a new test case is cached environment parameters, cached environment configuration stimuli can be generated based on these parameters until all cached environment parameters for the new test case have been read. After reading the cached environment parameters, the read configuration content of the new test case becomes test stimulus configuration information. This information can be saved in the stimulus storage table according to the cached input port identifier corresponding to the test stimulus, until all test stimulus configuration information for the new test case has been read. Furthermore, after all test stimulus configuration information for the new test case has been read, test stimuli corresponding to each cached input port can be generated in the order of the cached input ports.

[0149] Furthermore, after executing step S917, you can return to step S910 to determine whether there are any unread new test case identifiers in the saved file.

[0150] It should be noted that generating test stimuli for each cached input port sequentially according to the port order of the cached input ports corresponding to the test stimuli is only one optional implementation, and storing the configuration information of all test stimuli for the test cases in a stimulus storage table (e.g., a hash table) is also only one optional implementation. For example, in other possible implementations, this embodiment can generate test stimuli based on the read configuration information of each test stimulus for a test case; that is, this embodiment can also generate test stimuli in a timely and sequential manner according to the reading order of the test stimulus configuration information, rather than being limited to waiting for the configuration information of all test stimuli for the test cases to be stored in the stimulus storage table before generating test stimuli.

[0151] In this embodiment of the application, the address corresponding to the configuration information of the test incentive covers the performance bottleneck point of the cache design corresponding to the cache architecture. Therefore, the test incentive generated based on the configuration information of the test incentive can cover the performance bottleneck point of the cache design corresponding to the cache architecture.

[0152] In an optional implementation, the configuration information for the test incentive may include at least address configuration information; the address configuration information for the test incentive is used to generate the address corresponding to the request for the test incentive; thus, for any test incentive of a test case, this embodiment can generate multiple requests for the test incentive based at least on the address configuration information of the test incentive. It is understood that, based on the foregoing configuration description of the address configuration information for the test incentive, the address corresponding to the request for the test incentive generated by this embodiment can cover the performance bottleneck points corresponding to the cache architecture.

[0153] In an optional implementation example, the address configuration information may include a request address range, a starting address, a request address type, and an address granularity. Specifically, for any test stimulus of a test case, when the performance testing requirement of the cache design is to test a performance bottleneck (e.g., a crash test), the request address range of the test stimulus is configured to correspond to the request address range of the performance bottleneck, the starting address is configured to correspond to the starting address of the performance bottleneck, the request address type is configured to use an address incrementing pattern, and the address granularity is configured to correspond to the type of the performance bottleneck. Therefore, for any test stimulus of a test case, this embodiment can generate multiple requests for the test stimulus within the request address range corresponding to the performance bottleneck to be tested, based on the starting address of the performance bottleneck, according to an address incrementing pattern. The address increment in the address incrementing pattern is the address granularity corresponding to the type of the performance bottleneck.

[0154] As an example, performance bottlenecks can include any of the following: all cache libraries in the cache design, a specific cache library, and a specific cache set.

[0155] In a further optional implementation, the configuration information of the test incentive may also include request feature configuration information; thus, for any test incentive of a test case, the embodiments of this application may also generate multiple requests for the test incentive based on the request feature configuration information of the test incentive; that is, the embodiments of this application may generate multiple requests for the test incentive based on the request feature configuration information and address configuration information of the test incentive; wherein, the request feature configuration information of the test incentive is used to generate the characteristics and behavior of the request of the test incentive.

[0156] In an optional implementation example, the request feature configuration information may include: the number of requests, the request type, and the request data size; the number of requests is the number of requests corresponding to the test stimulus, the request type indicates the type of operation requested, and the request data size indicates the amount of data requested; wherein, the number of requests for the test stimulus is determined based on the cache input port corresponding to the test stimulus, and the request data size is configured as a random data size or a fixed data size.

[0157] Continue to refer to Figure 8In step S813, multiple test stimuli are applied to the simulated cache design to test the cache design.

[0158] In an optional implementation, for any test stimulus, this embodiment of the application can send the test stimulus request to the simulated cache design through the cache input port corresponding to the test stimulus according to the transmission priority of the test stimulus. That is, when transmitting test stimulus requests, the cache input port sends the test stimulus requests to the simulated cache design according to the transmission priority of the test stimulus. For example, a cache input port may have multiple test stimulus requests, and the transmission order of these multiple test stimulus requests is determined according to the transmission priority of the test stimulus.

[0159] In other alternative implementations, embodiments of this application may not configure cached input ports and transmission priorities for test stimuli. Instead, after generating test stimuli (e.g., after generating multiple requests for test stimuli), a cached input port is randomly selected, thereby sending the test stimuli requests to the simulation cache design through a random cached input port.

[0160] The caching design testing method provided in this application embodiment can obtain test case configuration information, which includes multiple caching environment parameters and multiple test incentive configuration information. The addresses corresponding to the test incentive configuration information cover the performance bottleneck points of the caching design in the caching architecture. Then, based on the multiple caching environment parameters, the caching environment of the caching design is configured; and multiple test incentives are generated based on the configuration information of the multiple test incentives. The multiple test incentives are then applied to the simulated caching design to test the caching design.

[0161] As can be seen, the caching design testing method provided in this application embodiment can configure the caching environment of the caching design through multiple caching environment parameters of the test cases. By using the configuration information of multiple test stimuli from the test cases, test stimuli for testing the caching design are generated. Since the addresses corresponding to the configuration information of the test stimuli cover the performance bottlenecks of the caching design within the caching architecture, the addresses corresponding to the generated test stimuli can cover these performance bottlenecks. This enables testing of the performance bottlenecks of the caching design, thereby identifying the location of these bottlenecks. Therefore, the caching design testing method provided in this application embodiment can test all performance bottlenecks of the caching design, improving the comprehensiveness and effectiveness of caching design performance testing.

[0162] The test method for the above-mentioned cache design provided in the embodiments of this application (e.g.) Figure 8 and Figure 9The test method shown can be implemented by the test stimulus generator in the test platform. Alternatively, Figure 10 An example diagram of the test platform provided in this application is shown as an example, such as... Figure 10 As shown, the test platform may include a test stimulus generator 101 and a simulator 102;

[0163] The test stimulus generator 101 can be used to execute the testing method for the cache design provided in the embodiments of this application. For example, the test stimulus generator can be used to obtain configuration information of test cases, which includes multiple cache environment parameters and configuration information of multiple test stimuli; wherein the address corresponding to the configuration information of the test stimuli covers the performance bottleneck point of the cache design in the cache architecture; configure the cache environment of the cache design according to the multiple cache environment parameters; generate multiple test stimuli according to the configuration information of the multiple test stimuli; and apply the multiple test stimuli to the simulated cache design to test the cache design.

[0164] The implementation details of the test stimulus generator 101 can be found in the description of the relevant section above, and will not be elaborated here.

[0165] The simulator 102 can be used to simulate cache design; in response to the test stimuli applied to the simulated cache design, the test results corresponding to the test stimuli are obtained; the test results of each test stimuli of the test case are used to form the test results of the test case.

[0166] In other words, a simulator is a software simulation tool used to simulate the actual operation of a cache design. When test stimuli generated by a test stimulus generator are applied to the cache design being simulated, the simulator can respond to the test stimuli, simulating the cache design's operational behavior under those stimuli, thus obtaining the test results corresponding to the test stimuli. For any given test case, the test results of each test stimulus within that test case constitute the test results for that test case.

[0167] In an optional implementation, the test results corresponding to the test cases can be used as simulation results of the simulator and saved in a simulation result file. Therefore, when multiple test cases are generated and caching is implemented, the simulation result file can save the test results corresponding to multiple test cases. In a further optional implementation, this application provides a back-annotation scheme for test results, thereby integrating the test results of the test cases with the configuration information of the test cases. Optionally, Figure 11 An exemplary flowchart of an optional back-annotation test result provided in an embodiment of this application is shown. This back-annotation test result flowchart can be implemented by a testing platform, such as... Figure 11 As shown, the process may include the following steps.

[0168] In step S111, the configuration information of the test cases is saved to the performance test result file.

[0169] The performance test result file (e.g., a performance test result table) can be a file that integrates the test results of test cases with the configuration information of test cases, as configured in this application embodiment. In an optional implementation, the way the performance test result file saves the configuration information of test cases can be consistent with the way the test configuration table saves the configuration information of test cases, as described in the corresponding section above, and will not be elaborated here. For example, the test configuration table can save content by column, so that the configuration information of test cases read from the test configuration table can be copied and printed to the performance test result file, so that the performance test result file also saves content by column.

[0170] In step S112, the test results of the test cases are extracted from the simulation result file, the extracted test results are saved to the performance test result file, and associated with the test cases.

[0171] In an optional implementation, embodiments of this application may extract the test results of test cases from the simulation result file based on the test case identifier (e.g., test case name), and save the extracted test results of test cases to the column corresponding to the test case identifier in the performance test result file, so as to associate the extracted test results of test cases with test cases in the performance test result file.

[0172] As an implementation example, the process of back-annotating test results can be as follows:

[0173] Open the simulation results file;

[0174] Open the test configuration table;

[0175] The test configuration table is read in a loop (e.g., each row) until the test configuration table is finished reading. The content read from a certain column (e.g., a certain row) of the test configuration table may be a test case identifier, a cache environment parameter, or a test stimulus configuration information.

[0176] The cache environment parameters and test stimulus configuration information read from the test configuration table will be printed to the performance test result file (e.g., the performance test result table).

[0177] Use the test case identifiers read from the test configuration table to extract the test results of the test cases in the simulation result file;

[0178] The test case identifier is printed to the performance test result file (e.g., the performance test result table); and the test results of the test cases extracted from the simulation result file are printed to the column where the test case identifier is located in the performance test result file (e.g., the performance test result table), thereby achieving back-annotation of the test results to the column corresponding to the test case identifier in the performance test result file.

[0179] As an example, Figure 12 An example diagram of a performance test result table provided in an embodiment of this application is shown. It can be seen that the column containing the test case identifier also displays the performance test result (hereinafter referred to as the test result) of the test case, in addition to the test case identifier. The performance test result can be mapped to the performance test result field in the performance test result file.

[0180] In a further optional implementation, the method for back-annotating test results provided in this application embodiment can be implemented by a test result back-annotator in a testing platform. For example, combined with... Figure 10 As shown, the test platform may also include a test result back-annotator 103; the test result back-annotator 103 can be used to save the configuration information of test cases to a performance test result file; extract the test results of test cases from the simulation result file, save the extracted test results to the performance test result file, and associate them with the test cases. The functional implementation of the test result back-annotator can be found in the description of the corresponding section above, and will not be elaborated here.

[0181] In a possible implementation, the test result back-annotator and the test stimulus generator can also be integrated, for example, the test result back-annotator and the test stimulus generator can be integrated into the same software component or the same device.

[0182] In a further optional implementation, based on the performance test result file with back-annotated test results, it is convenient to analyze the test results of test cases from different dimensions. For example, it is possible to analyze the performance impact of different caching environments and different test stimuli on the test results (that is, by systematically analyzing the back-annotated test results, it is possible to determine the performance impact of different caching environment parameters and different test stimulus configuration information on cache design), which facilitates the rapid determination of cache design parameters and the microarchitecture adjustment for performance bottlenecks that do not meet the performance indicators of the cache design.

[0183] In one implementation example, when performing multi-dimensional analysis of the performance test result file with back-annotated test results, the impact of factors such as request address range and handshake time on the cache hit rate and performance of the cache design can be considered. For example, let's take the impact of request address range on the performance of the cache design. Figure 13 An example graph of performance analysis is shown. Combined with... Figure 13As shown, without changing the caching environment parameters or the configuration information of the test stimuli except for the request address range, the test cases only change the request address range of different test stimuli, and the request address range of different test stimuli changes from small to large. Figure 13 The example illustrates how the maximum handshake time varies for the cached input port. Figure 13 The vertical axis represents the maximum handshake time of the cache design, which can be in nanoseconds (ns), and the horizontal axis represents the size of the range corresponding to the requested address range; Figure 13 As can be seen, with the increase in the range of requested addresses, the cache design needs to access downstream modules (such as memory) more frequently due to the increased miss rate, which in turn increases the maximum handshake time of the cache design.

[0184] It should be noted that, Figure 13 This is merely an example of performance analysis based on performance test result files with back-annotated test results. When performing performance analysis, this embodiment of the application can focus on performance indicators such as cache design hit rate, bandwidth, handshake time, and maximum number of requests processed simultaneously, thereby conducting a comprehensive and multi-dimensional performance analysis of cache design.

[0185] The solution provided in this application embodiment can have the following effects:

[0186] It can improve the comprehensiveness and versatility of performance testing for cache design, thereby enhancing the effectiveness of performance testing for cache design.

[0187] It improves the efficiency of test case generation. By using test configuration tables and automatic generation methods for test stimuli (such as test stimulus generators), the configuration information of test cases can be automatically extracted from the test configuration table, and test cases for performance testing of cache design can be generated quickly in batches (including cache environment configuration stimuli and multiple test stimuli for test cases), thereby improving the efficiency of test case generation.

[0188] To facilitate the modification and maintenance of test cases, the configuration information of multiple test cases is centrally stored in the test configuration table, enabling centralized management and updates of this information. For example, if the design parameters of the cache design are adjusted or the microarchitecture changes, only the configuration information of the test cases needs to be modified in the test configuration table to adapt to the changes. Subsequently, the test stimulus generator can generate test cases adapted to the changes in cache design parameters or microarchitecture based on the updated test case configuration information. This centralized management of test case configuration information simplifies the modification and maintenance of test cases and reduces errors and omissions.

[0189] With flexibility and scalability, the configuration of test cases (especially the configuration of test stimuli) can be designed as a generalized scheme, which can adapt to the testing needs of different microarchitectures and design parameters of cache designs; this flexible and scalable test case configuration method can be applied to a variety of cache designs, thereby supporting the performance testing needs of a wider range of cache designs.

[0190] The performance impact of cache design is intuitively displayed. By back-annotating the test results of test cases to the performance test result file, the changes in cache environment parameter configuration or test stimulus of the cache design can be intuitively reflected. This facilitates multi-dimensional performance analysis of the performance impact of cache design, helping cache design developers understand the performance change trends and reasons of cache design, thereby enabling more targeted cache design optimization and adjustment.

[0191] In an optional implementation, the cache design testing method provided in this application embodiment can be implemented in software. Therefore, the test stimulus device can execute the cache design testing method provided in this application embodiment by running software. The test stimulus device can be an electronic device in a test platform that generates test cases. For example, a test stimulus generator implemented in software can be set in the test stimulus device. Therefore, this application embodiment also provides a test stimulus device, including at least one memory and at least one processor. The memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the cache design testing method provided in this application embodiment.

[0192] In a further optional implementation, the test stimulus generator and the test result back-annotator implemented in software can be integrated. For example, the test result back-annotator can be set on the test stimulus device, so that the test method of the cache design implemented by the test stimulus device can include the content of the test result back-annotation process.

[0193] In a further optional implementation, embodiments of this application also provide a storage medium storing one or more computer instructions that, when executed, implement the cache design testing method provided in embodiments of this application. For example, a cache design testing method executed by a test stimulus generator, or a cache design testing method executed by a test stimulus generator and a test result back-annotator.

[0194] In a further optional implementation, embodiments of this application also provide a computer program product comprising one or more computer instructions that, when executed, implement the cache design testing method provided in embodiments of this application. For example, a cache design testing method executed by a test stimulus generator, or a cache design testing method executed by a test stimulus generator and a test result back-annotator.

[0195] In a further optional implementation, the test configuration method for the cache design provided in this application embodiment supports software implementation, so that the test configuration device can execute the test configuration method for the cache design provided in this application embodiment by running software. Therefore, this application embodiment also provides a test configuration device, including at least one memory and at least one processor, wherein the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the test configuration method for the cache design provided in this application embodiment.

[0196] In a further optional implementation, this application embodiment also provides a storage medium that stores one or more computer instructions, which, when executed, implement the test configuration method for the cache design provided in this application embodiment.

[0197] In a further optional implementation, this application embodiment also provides a computer program product, which includes one or more computer instructions, which, when executed, implement the test configuration method for the cache design provided in this application embodiment.

[0198] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0199] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A test method for cache design, characterized in that, include: Obtain the configuration information of the test cases, which includes multiple caching environment parameters and configuration information of multiple test stimuli; wherein, the address corresponding to the configuration information of the test stimuli covers the performance bottleneck point of the cache design in the cache architecture. Configure the cache environment for the cache design based on the multiple cache environment parameters; In addition, multiple test stimuli are generated based on the configuration information of multiple test stimuli; Multiple test stimuli are applied to the simulated cache design to test the cache design.

2. The method according to claim 1, characterized in that, The configuration information of the test stimulus includes a cache input port identifier corresponding to the test stimulus, which identifies the cache input port for transmitting the test stimulus; The process of obtaining the configuration information for the test cases includes: Initialize the stimulus storage table, which is used to store the configuration information of the test stimulus according to the cache input port identifier; The configuration information of the test cases is read from a saved file in a loop until the file is finished being read; wherein the saved file contains configuration information for multiple test cases; During the process of reading the saved file, if the configuration information of a new test case is read, multiple cache environment parameters and configuration information of each test stimulus are read from the configuration information of the new test case, and the configuration information of each test stimulus is saved to the stimulus saving table according to the cache input port identifier.

3. The method according to claim 2, characterized in that, The configuration information of the test cases also includes test case identifiers; the saved file is a test configuration table, and the test configuration table saves content by column; wherein, for the configuration information of any test case, one column of the test configuration table saves the test case identifier, one column saves a cache environment parameter, and one column saves the configuration information of a test stimulus.

4. The method according to claim 3, characterized in that, The process of repeatedly reading the configuration information of the test cases from the saved file until the file reading is complete includes: Read each column of the test configuration table in a loop until the test configuration table is finished reading; During the process of reading the saved file, if the configuration information of a new test case is read, multiple cache environment parameters and configuration information of each test stimulus are read from the configuration information of the new test case. The configuration information of each test stimulus is then saved to the stimulus saving table according to the cache input port identifier, including: During the process of reading the test configuration table, if the column containing the test case identifier is found, it is confirmed that the configuration information of the new test case will be read. Multiple cache environment parameters are read from the column containing multiple cache environment parameters, and the configuration information of each test stimulus is read from the column containing the configuration information of each test stimulus. The configuration information of each test stimulus is then saved to the stimulus saving table according to the cache input port identifier.

5. The method according to any one of claims 1-4, characterized in that, The step of configuring the cache environment for the cache design based on the multiple cache environment parameters includes: Based on the cache environment parameters, generate cache environment configuration incentives for the cache design; Apply cache environment configuration stimuli to the simulated cache design to configure the cache environment of the cache design.

6. The method according to any one of claims 1-4, characterized in that, The configuration information of the test stimuli includes at least address configuration information; generating multiple test stimuli based on the configuration information of multiple test stimuli includes: For any given test incentive, at least multiple requests for the test incentive are generated based on the address configuration information of the test incentive. The address configuration information of the test incentive is used to generate the address corresponding to the request of the test incentive, and the address corresponding to the request of the test incentive covers the performance bottleneck point of the cache design corresponding to the cache architecture.

7. The method according to claim 6, characterized in that, The address configuration information includes the request address range, starting address, request address type, and address granularity; the request address type indicates the address change pattern of the request, and the address granularity indicates the address change granularity of the request. Specifically, for any test incentive, when the performance test requirement of the cache design is to test the performance bottleneck, the request address range of the test incentive is configured to correspond to the request address range of the performance bottleneck, the starting address is configured to correspond to the starting address of the performance bottleneck, the request address type is configured to address increment mode, and the address granularity is configured to correspond to the type of the performance bottleneck. The step of generating multiple requests for any given test stimulus, based at least on the address configuration information of the test stimulus, includes: For any test stimulus, within the request address range corresponding to the performance bottleneck point to be tested, multiple requests for the test stimulus are generated based on the starting address of the performance bottleneck point and in an address increment pattern. The address increment in the address increment pattern is the address granularity corresponding to the type of the performance bottleneck point.

8. The method according to claim 7, characterized in that, The performance bottlenecks include any of the following: all cache libraries in the cache design, a specific cache library, and a specific cache set; One cache library includes multiple cache sets, and the specific cache set is the cache set that has a performance bottleneck.

9. The method according to claim 7, characterized in that, For any test incentive, when the performance test requirement of the cache design is to simulate the actual access scenario of the cache design, the request address range of the test incentive is configured to be negatively correlated with the cache hit rate of the test, and the request address type is configured to be random address mode.

10. The method according to claim 6, characterized in that, The configuration information of the test incentive also includes request feature configuration information; generating multiple requests for any test incentive, at least based on the address configuration information of the test incentive, includes: For any given test incentive, multiple requests for the test incentive are generated based on the request feature configuration information and address configuration information of the test incentive; wherein, the request feature configuration information of the test incentive is used to generate the characteristics and behavior of the test incentive requests.

11. The method according to claim 10, characterized in that, The request feature configuration information includes: the number of requests, the request type, and the request data size; The number of requests is the number of requests corresponding to the test incentive; the request type indicates the operation type of the request; the request data size indicates the data size of the request; wherein, the number of requests for the test incentive is determined based on the cache input port corresponding to the test incentive, and the request data size is configured as a random data size or a fixed data size.

12. The method according to claim 10, characterized in that, The configuration information for the test stimulus also includes transmission configuration information; the transmission configuration information includes a buffer input port and a transmission priority. Among them, the buffer input port indicates the buffer input port for transmitting test stimuli, and the buffer input port is represented by the buffer input port identifier; the transmission priority indicates the transmission order of test stimuli on the buffer input port; The cache design that applies multiple test stimuli to the simulation includes: For any given test stimulus, the request for the test stimulus is sent to the simulation cache design through the corresponding cache input port of the test stimulus, according to the transmission priority of the test stimulus.

13. The method according to claim 12, characterized in that, When generating multiple test stimuli, the test stimuli corresponding to each cached input port are generated sequentially according to the port order of the cached input ports corresponding to the test stimuli.

14. The method according to claim 12, characterized in that, The configuration information for the test incentives also includes extended configuration information, which is customized according to the performance testing requirements of the cache design.

15. The method according to claim 1, characterized in that, Also includes: Save the configuration information of the test cases to the performance test results file; Extract the test results of the test cases from the simulation result file, save the extracted test results to the performance test result file, and associate them with the test cases; the simulation result file contains the test results corresponding to multiple test cases.

16. The method according to claim 15, characterized in that, The way the performance test result file saves the configuration information of the test cases is consistent with the way the test configuration table saves the configuration information of the test cases. The test configuration table is a file that saves the configuration information of test cases, and the test configuration table saves the content by column; Saving the test case configuration information to the performance test result file includes: The test configuration table is read in a loop, and the read test case identifiers, cache environment parameters and test stimulus configuration information are printed to the performance test result file. The test results extracted from the simulation result file include: Use the test case identifiers read from the test configuration table to extract the test results of the test cases in the simulation result file; Saving the extracted test results to a performance test result file and associating them with test cases includes: The test results extracted from the simulation results file will be printed to the column containing the test case identifier in the performance test results file.

17. A test configuration method for a cache design, characterized in that, include: Get test configuration input; Based on the test configuration input, configure the configuration information of the test cases designed for the cache. The configuration information for the test cases includes multiple cache environment parameters and configuration information for multiple test stimuli; The multiple cache environment parameters are used to configure the cache environment of the cache design, the configuration information of the multiple test stimuli is used to generate multiple test stimuli, and the address corresponding to the configuration information of the test stimuli covers the performance bottleneck point of the cache design in the cache architecture.

18. The method according to claim 17, characterized in that, The configuration information of the test incentive includes at least address configuration information, which is used to generate the address corresponding to the test incentive request; wherein, the address corresponding to the test incentive request covers the performance bottleneck point of the cache design corresponding to the cache architecture.

19. The method according to claim 18, characterized in that, The address configuration information includes the request address range, starting address, request address type, and address granularity; the request address type indicates the address change pattern of the request, and the address granularity indicates the address change granularity of the request. Specifically, for any test incentive, when the performance test requirement of the cache design is to test the performance bottleneck, the request address range of the test incentive is configured to correspond to the request address range of the performance bottleneck, the starting address is configured to correspond to the starting address of the performance bottleneck, the request address type is configured to address increment mode, and the address granularity is configured to correspond to the type of the performance bottleneck.

20. The method according to claim 19, characterized in that, For any test incentive, when the performance test requirement of the cache design is to simulate the actual access scenario of the cache design, the request address range of the test incentive is configured to be negatively correlated with the cache hit rate of the test, and the request address type is configured to be random address mode.

21. The method according to any one of claims 18-20, characterized in that, The configuration information for the test incentive also includes test case identifiers, request feature configuration information, transmission configuration information, and extended configuration information; The request feature configuration information includes: request quantity, request type, and request data size; the request quantity is the number of requests corresponding to the test incentive; the request type indicates the operation type of the request; the request data size indicates the data size of the request; wherein, the request quantity of the test incentive is determined based on the cache input port corresponding to the test incentive, and the request data size is configured as a random data size or a fixed data size; The transmission configuration information includes a buffer input port and a transmission priority; wherein, the buffer input port indicates the buffer input port for transmitting test stimuli, and the buffer input port is represented by a buffer input port identifier; the transmission priority indicates the transmission order of test stimuli at the buffer input port; The extended configuration information is customized according to the performance testing requirements of the cache design.

22. The method according to claim 21, characterized in that, The configuration information for test cases designed based on the test configuration input and the configuration cache includes: Based on the test configuration input, the configuration information of the test cases for the cache design is configured in the test configuration table; wherein, the test configuration table includes multiple test case configuration areas, and each test case configuration area is used to store the configuration information of one test case; The test case configuration area includes a test case identifier field, a cache environment parameter configuration area, and a test incentive configuration area; wherein, the cache environment parameter configuration area includes multiple cache environment parameter configuration fields; the test incentive configuration area includes multiple request feature configuration fields for configuring request feature configuration information, multiple address configuration fields for configuring address configuration information, multiple transmission configuration fields for configuring transmission configuration information, and multiple extended configuration fields for configuring extended configuration information.

23. The method according to claim 22, characterized in that, The multiple request feature configuration fields include: request number configuration field, request type configuration field, and request data size configuration field; the multiple address configuration fields include: request address range configuration field, starting address configuration field, request address type configuration field, and address granularity configuration field; the multiple transmission configuration fields include: cache input port configuration field and transmission priority configuration field.

24. The method according to claim 22 or 23, characterized in that, The test configuration table stores content by column; for any test case configuration information, one column of the test configuration table stores the test case identifier, one column stores a cache environment parameter, and one column stores the configuration information of a test stimulus; where a column can be a row or a column.

25. A test system for cache design, characterized in that, Includes test stimulus generators and simulators; The test stimulus generator is used to obtain the configuration information of test cases, which includes multiple cache environment parameters and configuration information of multiple test stimuli. The addresses corresponding to the configuration information of the test stimuli cover the performance bottleneck points of the cache design in the cache architecture. Based on the multiple cache environment parameters, the generator configures the cache environment of the cache design. Based on the configuration information of the multiple test stimuli, it generates multiple test stimuli and applies them to the simulated cache design to test the cache design. The simulator is used to simulate cache design; in response to test stimuli applied to the simulated cache design, it obtains test results corresponding to the test stimuli; the test results of each test stimuli of the test case form the test results of the test case.

26. The system according to claim 25, characterized in that, Also includes: Test the configuration of the equipment; The test configuration device is used to acquire test configuration input; Configure the test case configuration information based on the test configuration input.

27. The system according to claim 25 or 26, characterized in that, Also includes: Test result backing label; The test result back-annotator is used to save the configuration information of the test cases to the performance test result file; Extract the test results of the test cases from the simulation result file, save the extracted test results to the performance test result file, and associate them with the test cases; the simulation result file contains the test results corresponding to multiple test cases.

28. A test excitation device, characterized in that, It includes at least one memory and at least one processor, the memory storing computer instructions, and the processor calling the computer instructions stored in the memory to execute the test method of the cache design according to any one of claims 1-16.

29. A test configuration device, characterized in that, It includes at least one memory and at least one processor, the memory storing computer instructions, and the processor calling the computer instructions stored in the memory to execute the test configuration method of the cache design according to any one of claims 17-24.

30. A storage medium, characterized in that, The storage medium stores one or more computer instructions, which, when executed, implement the test method for the cache design as described in any one of claims 1-16, or the test configuration method for the cache design as described in any one of claims 17-24.

31. A computer program product, characterized in that, It includes one or more computer instructions, which, when executed, implement the test method for the cache design as described in any one of claims 1-16, or the test configuration method for the cache design as described in any one of claims 17-24.

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