PCIE interface performance test system

Abstract

The invention relates to a PCIE interface performance test system. The system comprises a to-be-tested mainboard, the to-be-tested mainboard comprises a PCIE interface, and the to-be-tested mainboard is used for writing each first PCIE data packet into PCIE equipment through the PCIE interface and recording a data writing start timestamp; after each first PCIE data packet is successfully written, recording a data writing ending timestamp; generating a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet; and the PCIE equipment is used for receiving each first PCIE data packet, and after each first PCIE data packet is successfully received, the first PCIE data packet is discarded. By adopting the method, the test requirement of the theoretical bandwidth of the PCIE interface can be met.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a PCIE interface performance testing system. Background Art

[0002] The PCIE bus is the most commonly used high-speed peripheral component interconnection standard on computer motherboards. Whether it is commonly used graphics cards, disk array cards, sound cards, network cards, interface expansion cards, or professional data acquisition cards, AI acceleration cards, etc., all use the PCIE standard. In addition, solid-state drives (NVME SSDs) are also using the PCIE standard. It can be said that the PCIE interface is an extremely important interface on the computer motherboard. With the development of technology, the PCIE standard has gradually developed from the initial Gen1 (2.5Gbps / s) to different versions of Gen2 (5.0Gbps / s), Gen3 (8.0Gbps / s), and Gen4 (16.0Gbps / s). Each version of PCIE is divided into x1, x2, x4, x8 and x16. x1 is one data channel, x2 is two data channels (twice the speed of x1), and so on. Each generation of PCIE protocol updates almost doubles the bus bandwidth, which also poses a great challenge to the bandwidth test of the PCIE interface.

[0003] In traditional technology, the read and write bandwidth test of the PCIE slot on the computer motherboard is mostly tested using PCIE devices, such as PCIE network cards, PCIE disk arrays, graphics cards, etc.

[0004] Taking PCIE network card as an example, two motherboards to be tested need to be prepared. The tester inserts two PCIE network card devices into the PCIE slots of two computer motherboards respectively, and uses network cables to interconnect the two PCIE network cards. After booting into the system, run the network speed test software (such as iperf) under the operating system of the two motherboards to test the network transmission speed, so as to deduce the actual read and write bandwidth of the PCIE slot. This method is feasible for PCIE Gen3 and previous versions, and for PCIE slots below Gen4 x4. However, it cannot meet the requirements of PCIE Gen4 x8 and x16 slots, because the fastest network card on the market is the 100G network card, and the theoretical communication bandwidth does not exceed 10GB, but the theoretical bandwidth of PCIE Gen4 x8 is 16GB, and the theoretical bandwidth of x16 slot is 32GB. The 100G network card is far from meeting their bandwidth test requirements. Summary of the invention

[0005] Based on this, it is necessary to provide a PCIE interface performance test system that can meet the test requirements of the theoretical bandwidth of the PCIE interface in response to the above technical problems.

[0006] In a first aspect, the present application provides a PCIE interface performance testing system, the system comprising: The motherboard to be tested comprises a PCIE interface, wherein the motherboard to be tested is used to write each first PCIE data packet to a PCIE device through the PCIE interface, and record a data write start timestamp; after each first PCIE data packet is successfully written, record a data write end timestamp; and generate a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet; The PCIE device is used to receive each of the first PCIE data packets and discard the first PCIE data packet after each of the first PCIE data packets is successfully received.

[0007] In one of the embodiments, the PCIE device is further used to verify the first PCIE data packet based on the verification mechanism of the PCIE protocol after receiving the first PCIE data packet, and determine that the first PCIE data packet is received successfully when the verification of the first PCIE data packet succeeds.

[0008] In one of the embodiments, the PCIE device is further used to return data write failure information to the motherboard under test when the first PCIE data packet verification fails; The mainboard to be tested is further configured to record the number of write failures of the first PCIE data packet when receiving information on the data packet write failure.

[0009] In one of the embodiments, the motherboard to be tested is further used to generate a first PCIE data file, and determine each first PCIE data packet based on the first PCIE data file; wherein the size of the first PCIE data file is smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol; The mainboard to be tested is used to repeatedly determine each first PCIE data packet based on the first PCIE data file, and write each first PCIE data packet into the PCIE device.

[0010] In one of the embodiments, the total size of each of the first PCIE data packets is greater than a data size threshold, and the total size of each of the first PCIE data packets increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0011] In a second aspect, the present application further provides a PCIE interface performance testing system, the system comprising: A PCIE device, used for storing second PCIE data, and obtaining a second PCIE data packet based on the second PCIE data; The motherboard to be tested comprises a PCIE interface, wherein the motherboard to be tested is used to read the second PCIE data packet through the PCIE interface, record a read start timestamp, and discard the second PCIE data packet after the second PCIE data packet is successfully read, and record a read end timestamp; and generate a read performance test result of the PCIE interface based on the read start timestamp, the read end timestamp and the total size of each second PCIE data packet.

[0012] In one of the embodiments, the motherboard to be tested is further used to verify the second PCIE data packet based on the verification mechanism of the PCIE protocol after reading the second PCIE data packet, and if the verification of the second PCIE data packet succeeds, it is determined that the second PCIE data packet is read successfully.

[0013] In one of the embodiments, the mainboard to be tested is further used to record the number of times the reading of the second PCIE data packet fails when verification of the second PCIE data packet fails.

[0014] In one of the embodiments, the total size of each second PCIE data packet is greater than a data size threshold, and the total size of each second PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0015] In one of the embodiments, the size of the second PCIE data is smaller than the memory of the motherboard to be tested, and the size of the second PCIE data is an integer multiple of the size of a data packet corresponding to the PCIE protocol.

[0016] The above-mentioned PCIE interface performance test system includes a motherboard to be tested and a PCIE device, wherein the motherboard to be tested is used to write each first PCIE data packet to the PCIE device through the PCIE interface, and record the data write start timestamp; after each first PCIE data packet is successfully written, record the data write end timestamp; based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet, generate the write performance test result of the PCIE interface, the PCIE device is used to receive each first PCIE data packet, and after each first PCIE data packet is successfully received, discard the first PCIE data packet, so that the PCIE device does not have time-consuming operations such as storing data and protocol conversion, and will not limit the write speed of the PCIE interface, and can maximize the write performance of the PCIE interface, so that the test result is accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 This is a schematic diagram of using a PCIE network card device to test the read and write rates of a PCIE slot in traditional technology; Figure 2 A schematic diagram of using a PCIE disk array card to test the read and write rates of a PCIE slot in a conventional technology; Figure 3 is a schematic diagram of a PCIE interface performance test system in one embodiment; Figure 4 A flow chart of PCIE interface performance test is written in one embodiment; Figure 5 A flow chart of a PCIE interface read performance test in one embodiment; Figure 6 The following is a schematic diagram of a PCIE interface performance test in one embodiment; Figure 7 A schematic diagram of a test interface in an embodiment. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] For ease of understanding, combined Figure 1 As shown, Figure 1This is a schematic diagram of using a PCIE network card device to test the read and write rate of a PCIE slot in the traditional technology. In this embodiment, taking a PCIE network card as an example, two motherboards to be tested need to be prepared. The tester inserts two PCIE network card devices into the PCIE slots of two computer motherboards respectively, and interconnects the two PCIE network cards with a network cable. After booting into the system, the network speed test software (such as iperf) is run under the operating system of the two motherboards to be tested respectively, and the actual read and write bandwidth of the PCIE slot is derived by testing the network transmission speed. This method is feasible for PCIE Gen3 and previous versions, and is also feasible for PCIE slots below Gen4 x4. However, it cannot meet the requirements for PCIE Gen4 x8 and x16 slots, because the fastest network card currently is a 100G network card, and the theoretical communication bandwidth does not exceed 10GB, but the theoretical bandwidth of PCIE Gen4 x8 is 16GB, and the theoretical bandwidth of the x16 slot is 32GB. The 100G network card is far from meeting their bandwidth test requirements.

[0021] Combination Figure 2 As shown, Figure 2 This is a schematic diagram of using a PCIE disk array card to test the read and write speed of a PCIE slot in traditional technology. Taking the PCIE disk array as an example, the tester inserts the PCIE disk array into the tested motherboard and connects the disk. The tester boots up the operating system of the tested motherboard, runs the disk read and write test software (such as CrystalDiskMark) to test the disk read and write speed, and then derives the actual bandwidth of the PCIE slot based on the disk read and write speed. However, after receiving the data, the PCIE disk array card will write them to the hard disk. The process of writing data to the hard disk will waste a lot of time, and the read and write performance of the PCIE slot of the tested motherboard cannot be maximized.

[0022] In summary, the current testing methods are all indirect ways to deduce the read and write bandwidth of PCIE, which are limited by the performance limitations of the next-level devices (network cards, hard disks, etc.) and cannot bring out the maximum read and write speed of the PCIE slot of the tested motherboard. The above only takes PCIE network cards and PCIE disk array cards as examples, and other PCIE devices also have the same problem.

[0023] In order to solve the above technical problems, this application proposes a PCIE interface performance test system. Figure 3As shown, the system includes a motherboard to be tested and a PCIE device, the PCIE device includes an FPGA main control chip, for example, in this embodiment, a high-performance FPGA supporting PCIE Gen4 x16 is used as the main control chip (it should be noted that if there is a higher version of the PCIE standard, the main control chip is a high-performance FPGA supporting a higher version of the PCIE standard, and technicians in this field can select a suitable FPGA based on the PCIE standard), such as Intel's Stratix 10 DX. In other embodiments, the main control chip of the PCIE device may also be other models, which is not specifically limited here.

[0024] The PCIE device can be a PCIE test card. The PCIE test card can optionally adopt the standard PCIEx16 board size and can be inserted into all motherboards to be tested that support PCIE x16. In other embodiments, the PCIE test card can also be made into other board types, such as M.2 board type, XMC board type, VPX board type, etc., which are not specifically limited here. In addition, the embodiment of the present application is described using the PCIE Gen4 x16 interface as an example. When testing other versions of the interface, the PCIE test card can also be made into PCIE test cards of different versions (Gen1~Gen4) and different widths (x1~x16), which are backward compatible. In addition, it should be noted that after the emergence of higher versions such as PCIE Gen5D, the PCIE interface performance test system proposed in this application can upgrade the PCIE test card to support the testing of higher versions of the PCIE interface.

[0025] The PCIE test card and the host computer software can realize the read and write performance test of the PCIE Gen4 x16 slot.

[0026] In addition, it should be noted that this PCIE test card only implements the read and write functions of PCIE, and directly discards the written data without any processing, so the power consumption is very low. The 75watt power provided by the PCIE gold finger (Gold Finger is a connector on a printed circuit board (PCB), usually used to connect other devices such as computer motherboards, expansion cards, etc. In the PCI Express (PCIE) interface, the gold finger is the contact point of the connector for transmitting high-speed data signals) is sufficient to support the operation of the board without the need for additional power supply.

[0027] Combination Figure 4 As shown, Figure 4The present invention is a flowchart of a PCIE interface write performance test in an embodiment. In this embodiment, the motherboard to be tested is used to write each first PCIE data packet to a PCIE device through a PCIE interface, and record a data write start timestamp; after each first PCIE data packet is successfully written, record a data write end timestamp; and generate a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet.

[0028] The PCIE device is used to receive each first PCIE data packet, and discard the first PCIE data packet after each first PCIE data packet is successfully received.

[0029] Specifically, in the actual test process, the PCIE device is first inserted into the PCIE interface of the mainboard to be tested, and the mainboard to be tested writes the first PCIE data packet to the PCIE device through the PCIE interface and records the data write start timestamp; the PCIE device receives each first PCIE data packet, and after each first PCIE data packet is successfully received, the first PCIE data packet is discarded, and no processing is performed on the first PCIE data packet; after each first PCIE data packet is successfully written, the mainboard to be tested records the data write end timestamp, and finally the mainboard to be tested generates a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet, such as the total size of the first PCIE data packet / (write end timestamp-write start timestamp), so that the maximum write speed of the PCIE interface of the mainboard to be tested can be obtained.

[0030] In the above writing test process, no storage devices such as memory and hard disk are required, and no additional protocol conversion is required. The PCIE test card directly discards the data after receiving it. Without time-consuming operations such as storing data and protocol conversion, the writing speed of the PCIE interface will not be limited, and the writing performance of the PCIE interface can be maximized, so that the test results are accurate.

[0031] In one of the optional embodiments, the PCIE device is further used to verify the first PCIE data packet based on the verification mechanism of the PCIE protocol after receiving the first PCIE data packet, and determine that the first PCIE data packet is successfully received if the verification of the first PCIE data packet succeeds.

[0032] In addition, it should be noted that the PCIE test card opens up a memory space (write RAM) inside the FPGA to temporarily store the first received PCIE data packet, without writing the first PCIE data packet to the hard disk, etc., so there is no need for storage devices such as memory and hard disk to maximize the write performance of the PCIE interface.

[0033] In order to avoid additional operations such as protocol conversion and data verification, the verification mechanism of the PCIE protocol is used in this embodiment to verify the first PCIE data packet to confirm the accuracy of the first PCIE data written to the PCIE device, and when the first PCIE data packet is successfully verified, it is determined that the first PCIE data packet is received successfully, so that the main card to be tested can continue to send the next first PCIE data packet until all first PCIE data packets are sent successfully.

[0034] In the above embodiment, the verification mechanism of the PCIE protocol is used to verify the first PCIE data packet, avoiding additional operations such as protocol conversion and third-party data verification, thereby not limiting the write speed of the PCIE interface and maximizing the write performance of the PCIE interface.

[0035] In one of the optional embodiments, the PCIE device is also used to return data write failure information to the mainboard under test when the first PCIE data packet verification fails; the mainboard under test is also used to record the number of write failures of the first PCIE data packet when receiving the data packet write failure information.

[0036] In this embodiment, when the first PCIE data packet verification fails, the PCIE device returns data verification failure information to the main card to be tested, so that the main card to be tested can rewrite the first PCIE data packet to the PCIE device.

[0037] Optionally, the main card to be tested may also record the number of write failures of the first PCIE data packet, and the number of write failures may be output so that the tester can determine the cause of the performance test failure when the performance data obtained from the test does not meet the requirements.

[0038] For example, when the performance data obtained from the test does not meet the requirements, and the proportion of the number of write failures to the total number of writes is greater than the first proportion, or greater than the first threshold, it is determined that the cause of the performance test failure is poor transmission quality of the PCIE interface. Otherwise, it can be determined that the cause of the performance test failure is a software reason, etc., which is convenient for troubleshooting.

[0039] The first ratio and the first threshold here can be determined based on experience, and no specific limitation is made here. The total number of write times here is the total number of first PCIE data packets.

[0040] In one of the optional embodiments, the motherboard to be tested is also used to generate a first PCIE data file, and determine each first PCIE data packet based on the first PCIE data file; wherein the size of the first PCIE data file is smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol; the motherboard to be tested is used to repeatedly determine each first PCIE data packet based on the first PCIE data file, and write each first PCIE data packet to the PCIE device.

[0041] The first PCIE data packet may be generated based on a first PCIE data file, the first PCIE data file may be randomly generated by the software of the motherboard to be tested, the content of the first PCIE data file may be a random number, the size of the first PCIE data file may be smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file may be an integer multiple of the size of the data packet corresponding to the PCIE protocol.

[0042] The size of the data packet corresponding to the PCIE protocol is 4KB, which is the size of the maximum data packet corresponding to the PCIE protocol. Therefore, the size of the first PCIE data file can be an integer multiple of 4KB, such as 4MB. In other embodiments, the size of the first PCIE data file can also be other values, which are not specifically limited here, and the size of the first PCIE data file needs to be smaller than the memory size of the motherboard to be tested.

[0043] Since the more first PCIE data packets written during the test process, the more accurate the test results are, in order to improve the accuracy, each first PCIE data packet can be repeatedly determined based on the first PCIE data file, and each first PCIE data packet can be written to the PCIE device, for example, the first PCIE data file can be written to the PCIE device continuously for multiple times.

[0044] In one optional embodiment, the total size of each first PCIE data packet is greater than a data size threshold, and the total size of each first PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0045] The total size of each first PCIE data packet here is the total amount of data successfully written to the PCIE device, that is, the result of the first PCIE data file x the number of file writes in the above text.

[0046] In order to ensure the relative accuracy of the test results, the minimum value of the total size of each first PCIE data packet is limited, that is, the data size threshold, and the data size threshold may be 1GB. In other embodiments, the data size threshold may be other values, and those skilled in the art may adjust the data size threshold based on the test scenario and test accuracy requirements.

[0047] In addition, since different PCIE interfaces support different PCIE standards, and different PCIE standards correspond to different theoretical bandwidths, if the total size of each first PCIE data packet sent for the test of the same PCIE interface is the same, the accuracy of the test result is different. In order to improve the accuracy of the test result, the total size of each first PCIE data packet is determined based on the theoretical bandwidth corresponding to the PCIE interface, wherein the total size of each first PCIE data packet increases with the increase of the theoretical bandwidth corresponding to the PCIE interface. This ensures the total data volume of the data sent during the test and the accuracy of the test on the one hand, and does not require storage devices such as memory and hard disk, and does not require additional protocol conversion on the other hand. The PCIE test card directly discards the data after receiving it, and without the time-consuming operations of storing data and converting protocols, the write speed of PCIE will not be limited, and the write performance of the PCIE interface can be maximized to ensure accuracy.

[0048] The present application also provides a PCIE interface read performance test system, whose specific hardware structure can be combined with Figure 3 As shown, and for ease of understanding, combined Figure 5 As shown, Figure 5 The flowchart of the PCIE interface read performance test in one embodiment is shown. In this embodiment, the PCIE device is used to store the second PCIE data and obtain the second PCIE data packet based on the second PCIE data. The mainboard to be tested is used to read the second PCIE data packet through the PCIE interface and record the read start timestamp, and after the second PCIE data packet is read successfully, the second PCIE data packet is discarded and the read end timestamp is recorded; the read performance test result of the PCIE interface is generated based on the read start timestamp, the read end timestamp and the total size of each second PCIE data packet.

[0049] Specifically, in the actual test process, the PCIE device first opens a memory device in the FPGA, such as a read RAM, for storing the second PCIE data, and then the motherboard to be tested can read the second PCIE data from the PCIE device, wherein the reading method is to read one packet at a time in the manner of the second PCIE data packet. Specifically, the motherboard to be tested is used to read the second PCIE data packet through the PCIE interface, and record the read start timestamp, and after the second PCIE data packet is read successfully, the second PCIE data packet is discarded, and no processing is performed on the second PCIE data packet, and after each second PCIE data packet is read successfully, the read end timestamp is recorded.

[0050] The motherboard to be tested subsequently generates a write performance test result of the PCIE interface based on the read start timestamp, the read end timestamp and the total size of each second PCIE data packet, such as the total size of the second PCIE data packet / (read end timestamp-read start timestamp), so as to obtain the maximum read speed of the PCIE interface of the motherboard to be tested.

[0051] In the above writing test process, no storage devices such as memory and hard disk are required, and no additional protocol conversion is required. After reading the second PCIE data packet, the tested motherboard directly discards it. Without time-consuming operations such as storing data and protocol conversion, the reading speed of the PCIE interface will not be limited, and the reading performance of the PCIE interface can be maximized, thereby making the test results accurate.

[0052] In one of the optional embodiments, the motherboard to be tested is further used to verify the second PCIE data packet based on the verification mechanism of the PCIE protocol after reading the second PCIE data packet, and if the verification of the second PCIE data packet succeeds, it is determined that the second PCIE data packet is read successfully.

[0053] In order to avoid additional operations such as protocol conversion and data verification, the present embodiment adopts the verification mechanism of the PCIE protocol to verify the second PCIE data packet to confirm the accuracy of the second PCIE data read by the tested mainboard, and when the second PCIE data packet verification succeeds, it is determined that the second PCIE data packet is read successfully, so that the tested main card can continue to read the next second PCIE data packet until all second PCIE data packets are read successfully.

[0054] In the above embodiment, the second PCIE data packet is verified using the verification mechanism of the PCIE protocol itself, avoiding additional operations such as protocol conversion and third-party data verification, thereby not limiting the reading speed of the PCIE interface and maximizing the reading performance of the PCIE interface.

[0055] In one of the optional embodiments, the mainboard to be tested is further used to record the number of times the second PCIE data packet fails to be read when the second PCIE data packet fails to be verified.

[0056] In this embodiment, when the second PCIE data packet verification fails, the main card to be tested re-reads the second PCIE data packet in the PCIE device.

[0057] Optionally, the main card to be tested may also record the number of failed reads of the second PCIE data packet, and the number of failed reads may be output so that the tester can determine the cause of the performance test failure when the performance data obtained by the test does not meet the requirements.

[0058] For example, when the performance data obtained from the test does not meet the requirements, and the proportion of read failures to the total read times is greater than the first proportion, or greater than the second threshold, it is determined that the cause of the performance test failure is poor transmission quality of the PCIE interface. Otherwise, it can be determined that the cause of the performance test failure is a software reason, etc., which is convenient for troubleshooting.

[0059] The second ratio and the second threshold here can be determined based on experience, and no specific limitation is made here. The total number of write times here is the total number of second PCIE data packets.

[0060] In one optional embodiment, the total size of each second PCIE data packet is greater than a data size threshold, and the total size of each second PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

[0061] The total size of each first PCIE data packet here is the total amount of data successfully written to the PCIE device, that is, the result of the first PCIE data file x the number of file writes in the above text.

[0062] In order to ensure the relative accuracy of the test results, the minimum value of the total size of each second PCIE data packet is limited, that is, the data size threshold, which can be 1GB. In other embodiments, the data size threshold can be other values, and those skilled in the art can adjust the data size threshold based on the test scenario and test accuracy requirements. It should be noted that the data size thresholds involved in the read performance test and the write performance test can be the same or different, and no specific limitation is made here.

[0063] Since different PCIE interfaces support different PCIE standards, and different PCIE standards correspond to different theoretical bandwidths, if the total size of each second PCIE data packet sent for the test of the same PCIE interface is the same, the accuracy of the test result is different. In order to improve the accuracy of the test result, the total size of each second PCIE data packet is determined based on the theoretical bandwidth corresponding to the PCIE interface, wherein the total size of each second PCIE data packet increases with the increase of the theoretical bandwidth corresponding to the PCIE interface. This ensures the total amount of data read during the test and the accuracy of the test on the one hand, and does not require storage devices such as memory and hard disk, and does not require additional protocol conversion. The motherboard to be tested directly discards the data after receiving it. Without the time-consuming operations of storing data and converting protocols, the reading speed of PCIE will not be limited, and the reading performance of the PCIE interface can be maximized to ensure accuracy.

[0064] In one of the optional embodiments, the size of the second PCIE data is smaller than the memory of the motherboard to be tested, and the size of the second PCIE data is an integer multiple of the size of the data packet corresponding to the PCIE protocol.

[0065] The second PCIE data packet is generated based on the second PCIE data, and the second PCIE data can be randomly generated by the PCIE device, for example, the PCIE device opens a memory space of a certain size in the FPGA as a read RAM, and fills it with random numbers, then the random numbers stored in the space constitute the second PCIE data. The second PCIE data can be a plurality of random numbers, and the size of the second PCIE data is smaller than the memory of the motherboard to be tested, and the size of the second PCIE data is an integral multiple of the size of the data packet corresponding to the PCIE protocol.

[0066] The size of the data packet corresponding to the PCIE protocol is 4KB, which is the size of the maximum data packet corresponding to the PCIE protocol. Therefore, the size of the second PCIE data can be an integer multiple of 4KB, such as 4MB. In other embodiments, the size of the second PCIE data can also be other values, which are not specifically limited here, and the size of the second PCIE data needs to be smaller than the memory size of the motherboard to be tested.

[0067] Since the more second PCIE data packets are read during the test, the more accurate the test result is, in order to improve the accuracy, each second PCIE data packet can be repeatedly determined based on the second PCIE data, and the second PCIE data packet can be read. For example, the motherboard to be tested reads the second PCIE data packet from the PCIE device multiple times in succession.

[0068] For ease of understanding, combined Figure 6 As shown, Figure 6 The schematic diagram of the PCIE interface performance test in one embodiment is shown in the figure. In the embodiment, the PCIE interface performance test system includes a mainboard to be tested and a PCIE test card, wherein the mainboard to be tested includes a PCIE interface, and the PCIE test card is the PCIE device mentioned above, including an FPGA, and the FPGA includes two high-speed transceivers, which are used for read performance test and write performance test respectively, a PCIE IP core, and a write memory and a read memory. The write memory is used to temporarily store the first PCIE data packet written by the mainboard to be tested, and the read memory is used to store the second PCIE data that the mainboard to be tested needs to read.

[0069] Combination Figure 7 As shown, Figure 7Schematic diagram of a test interface in an embodiment, which includes a read performance test, a write performance test, and a PCIE device selection box. After completing the hardware connection, the corresponding PCIE device, such as a PCIE test card, can be selected through the PCIE device selection box. The read performance test and the write performance test can be implemented by triggering the control button corresponding to the read performance test or the write performance test. The specific test process can be combined with the above Figure 4 and Figure 5 After the test is completed, the test interface can also display the test results. The write performance test results include the amount of written data (that is, the total size of each first PCIE data packet in the above text), the number of written frames (that is, the number of first PCIE data packets in the above text), the number of error frames (the number of times the first PCIE data packet fails to write) and the write speed. The read performance test results include the amount of read data (that is, the total size of each second PCIE data packet in the above text), the number of read frames (that is, the number of second PCIE data packets in the above text), the number of error frames (the number of times the second PCIE data packet fails to read) and the read speed.

[0070] Optionally, Figure 7 The write speed and read speed are displayed in the form of a dashboard to improve the visualization level. In other embodiments, the write speed and read speed can be displayed in other forms, such as in a table form, etc., and no specific limitation is made here.

[0071] In the above embodiment, whether in the write performance test or the read performance test, after reading or writing data, the data is directly discarded, which saves data processing time and can maximize the read and write performance of the PCIE interface of the tested motherboard. And only the data verification mechanism provided by the PCIE protocol is used for verification, without the need for data storage, data conversion, etc., which also saves data processing time. In addition, the number of error frames can be counted based on the data verification mechanism to facilitate subsequent troubleshooting.

[0072] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0073] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0074] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A PCIE interface performance test system, characterized in that: The system comprises: The motherboard to be tested comprises a PCIE interface, wherein the motherboard to be tested is used to write each first PCIE data packet to a PCIE device through the PCIE interface, and record a data write start timestamp; after each first PCIE data packet is successfully written, record a data write end timestamp; and generate a write performance test result of the PCIE interface based on the write start timestamp, the write end timestamp and the total size of each first PCIE data packet; The PCIE device includes an FPGA main control chip, which is used to receive each of the first PCIE data packets and discard the first PCIE data packet after each of the first PCIE data packets is successfully received.

2. The system according to claim 1, characterized in that The PCIE device is further configured to verify the first PCIE data packet based on a verification mechanism of the PCIE protocol after receiving the first PCIE data packet, and determine that the first PCIE data packet is successfully received if the verification of the first PCIE data packet succeeds.

3. The system according to claim 2, characterized in that The PCIE device is further configured to return data write failure information to the motherboard to be tested when the first PCIE data packet verification fails; The mainboard to be tested is further configured to record the number of write failures of the first PCIE data packet when receiving information on the data packet write failure.

4. The system according to claim 1, characterized in that The motherboard to be tested is further used to generate a first PCIE data file, and determine each first PCIE data packet based on the first PCIE data file; wherein the size of the first PCIE data file is smaller than the memory of the motherboard to be tested, and the size of the first PCIE data file is an integer multiple of the size of the data packet corresponding to the PCIE protocol; The mainboard to be tested is used to repeatedly determine each first PCIE data packet based on the first PCIE data file, and write each first PCIE data packet into the PCIE device.

5. The system according to claim 1, characterized in that The total size of each of the first PCIE data packets is greater than a data size threshold, and the total size of each of the first PCIE data packets increases as a theoretical bandwidth corresponding to the PCIE interface increases.

6. A PCIE interface performance test system, characterized in that: The system comprises: A PCIE device, including an FPGA main control chip, is used to store second PCIE data and obtain a second PCIE data packet based on the second PCIE data; The motherboard to be tested comprises a PCIE interface, wherein the motherboard to be tested is used to read the second PCIE data packet through the PCIE interface, record a read start timestamp, and discard the second PCIE data packet after the second PCIE data packet is successfully read, and record a read end timestamp; and generate a read performance test result of the PCIE interface based on the read start timestamp, the read end timestamp and the total size of each second PCIE data packet.

7. The system according to claim 6, characterized in that The mainboard to be tested is further used to verify the second PCIE data packet based on the verification mechanism of the PCIE protocol after reading the second PCIE data packet, and determine that the second PCIE data packet is read successfully when the verification of the second PCIE data packet succeeds.

8. The system according to claim 7, characterized in that The mainboard to be tested is further used to record the number of times the reading of the second PCIE data packet fails when the verification of the second PCIE data packet fails.

9. The system according to claim 6, characterized in that The total size of each second PCIE data packet is greater than a data size threshold, and the total size of each second PCIE data packet increases as a theoretical bandwidth corresponding to the PCIE interface increases.

10. The system according to claim 6, characterized in that The size of the second PCIE data is smaller than the memory of the mainboard to be tested, and the size of the second PCIE data is an integer multiple of the size of a data packet corresponding to the PCIE protocol.

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