Bandwidth allocation system

Abstract

The embodiment of the invention provides a bandwidth allocation system, and relates to the field of bandwidth allocation. The system comprises a mainboard which comprises a central processing unit, an expansion chip and a first connector group; the input / output board comprises a second connector group, the first connector group provides a first signal group to the expansion chip based on whether a cable is connected between the first connector group and the second connector group, and the central processing unit reads the first signal group from the expansion chip and configures a bandwidth branching mode of the central processing unit according to the first signal group; according to the invention, the design process is simplified, the development and maintenance workload and the production cost of the basic input and output system are saved, the purpose of changing the bandwidth branching mode is achieved by changing the connection mode of the connector cable and generating different signal sequences, the operation is simple and convenient, the maintenance is easy, the control cost in the production process is reduced, and the production efficiency is improved. And meanwhile, abnormal bandwidth allocation caused by improper operation is avoided, and the production yield of products is improved.

Description

Technical Field

[0001] The present application relates to the field of bandwidth allocation, and in particular to a bandwidth allocation system. Background Art

[0002] In existing artificial intelligence servers, in order to expand network card or disk array card resources, a separate input and output board is generally designed. The input and output board has several high-speed serial computer expansion bus standard slots. The mainboard and the input and output board are connected through connectors and cables. The purpose of this design is to flexibly match external resource interfaces according to different customer needs.

[0003] In actual application scenarios, the use of input and output boards also faces some design problems, especially under the limitations of server modular design specifications, how to flexibly match different input and output board scenarios. In the artificial intelligence server architecture, most of the high-speed serial computer expansion bus standard resources of the central processing unit are allocated to the high-speed serial computer expansion bus standard switch. Through the high-speed serial computer expansion bus standard switch, the high-speed serial computer expansion bus standard resources that can be allocated by the central processing unit are few. Take the processors of Intel Scalable Processors and NVIDIA Artificial Intelligence Supercomputing Platform Series Architecture as an example: Each Intel Scalable Processor has 5 X16 high-speed serial computer expansion bus standard resources (i.e. 80 channels), of which 4 X16 high-speed serial computer expansion bus standard resources are connected to the high-speed serial computer expansion bus standard switch, so only 1 X16 resource can be used for flexible configuration.

[0004] Therefore, according to the different application devices that the server needs to connect, the X16 resources that can be used for flexible configuration on the input and output board need to be configured. Usually, there are devices connected to 1 X16 high-speed serial computer expansion bus standard slot and devices connected to 2 X8 high-speed serial computer expansion bus standard slots. How to enable the central processor to identify different application scenarios and configure different bandwidth bifurcation modes based on the same software and hardware design has become a problem that needs to be solved urgently. Summary of the invention

[0005] Based on the above technical problems, an embodiment of the present application provides a bandwidth allocation system, which aims to enable a central processing unit to identify different application scenarios and configure different bandwidth bifurcation modes.

[0006] According to a first aspect of an embodiment of the present application, a bandwidth allocation system is provided, the system comprising:

[0007] A mainboard, comprising: a central processing unit, an expansion chip, and a first connector group, wherein the first connector group comprises: a first connector and a second connector;

[0008] An input-output board, comprising: a second connector group, wherein the second connector group comprises: a third connector, a fourth connector, a fifth connector, and a sixth connector; the third connector and the fourth connector are connected to a first slot, and the fifth connector and the sixth connector are connected to a second slot;

[0009] In the case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fourth connector, the central processing unit is connected to the first slot;

[0010] In the case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the central processor is connected to the first slot and the second slot. Optionally, the system further includes:

[0011] In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fourth connector, the first connector group provides a first signal sequence to the expansion chip;

[0012] The central processor reads the first signal sequence from the expansion chip, and configures the bandwidth bifurcation mode of the central processor to a first bandwidth bifurcation mode according to the first signal sequence. In the first bandwidth bifurcation mode, the central processor is connected to the first slot.

[0013] Optionally, the system further comprises:

[0014] In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the first connector group provides a second signal sequence to the expansion chip;

[0015] The central processor reads the second signal sequence from the expansion chip, and configures the bandwidth bifurcation mode of the central processor to a second bandwidth bifurcation mode according to the second signal sequence. In the second bandwidth bifurcation mode, the central processor is connected to the first slot and the second slot.

[0016] Optionally, the mainboard includes: a central processing unit, an expansion chip, a first connector group, and also includes: an isolation module connected between the expansion chip and the first connector group;

[0017] The first connector group provides a second signal group to the isolation module based on whether a cable is connected between the first connector group and the second connector group;

[0018] The isolation module is used to perform signal isolation and reverse processing on the second signal group, and the processed signal group is provided to the extension chip as the first signal group.

[0019] Optionally, in the first bandwidth bifurcation mode, the first signal sequence includes: a low level signal provided by a B30 pin of the first connector;

[0020] The A30 pin of the third connector is connected to the B8 pin of the fifth connector;

[0021] When a cable is connected between the first connector and the third connector and no cable is connected to the fifth connector, the B8 pin of the fifth connector provides a low-level signal to the A30 pin of the third connector, and the low-level signal is transmitted to the B30 pin of the first connector via the cable connected between the first connector and the third connector.

[0022] Optionally, in the second bandwidth bifurcation mode, the second signal sequence includes: a high level signal provided by the B30 pin of the first connector;

[0023] A voltage source is connected to the A8 pin of the second connector;

[0024] The A30 pin of the third connector is connected to the B8 pin of the fifth connector;

[0025] When a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the high-level signal provided by the A8 pin of the second connector is transmitted to the B8 pin of the fifth connector via the cable connected between the second connector and the fifth connector, and the high-level signal is transmitted to the B30 pin of the first connector in sequence via the B8 pin of the fifth connector, the A30 pin of the third connector, and the cable connected between the first connector and the third connector.

[0026] Optionally, in the first bandwidth bifurcation mode or the second bandwidth bifurcation mode, the first signal sequence or the second signal sequence includes: a low level signal provided by a B12 pin of the first connector;

[0027] The A12 pin of the third connector is left floating;

[0028] In the case where a cable is connected between the first connector and the third connector, the A12 pin of the third connector provides a low-level signal, and the low-level signal is transmitted to the B12 pin of the first connector via the cable connected between the first connector and the third connector.

[0029] Optionally, in the first bandwidth bifurcation mode, the first signal sequence includes: a low level signal provided by B30 and B12 of the second connector;

[0030] The A30 pin and A12 pin of the fourth connector are both left floating;

[0031] When a cable is connected between the second connector and the fourth connector, the A30 pin and the A12 pin of the fourth connector both provide low-level signals, and the low-level signals are transmitted to the B30 pin and the B12 pin of the second connector via the cable connected between the second connector and the fourth connector.

[0032] Optionally, in the second bandwidth bifurcation mode, the second signal sequence includes: a high level signal provided by B30 of the second connector;

[0033] A voltage source is connected to the A8 pin of the first connector;

[0034] The A30 pin of the fifth connector is connected to the B8 pin of the third connector;

[0035] When a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the high-level signal provided by the A8 pin of the first connector is transmitted to the B8 pin of the third connector via the cable connected between the first connector and the third connector, and the high-level signal is transmitted to the B30 pin of the second connector in sequence via the B8 pin of the third connector, the A30 pin of the fifth connector, and the cable connected between the second connector and the fifth connector.

[0036] Optionally, in the second bandwidth bifurcation mode, the second signal sequence includes: a low level signal provided by B12 of the second connector;

[0037] The A12 pin of the fifth connector is left floating;

[0038] In the case where a cable is connected between the second connector and the fifth connector, the A12 pin of the fifth connector provides a low-level signal, and the low-level signal is transmitted to the B12 pin of the second connector via the cable connected between the second connector and the fifth connector.

[0039] The bandwidth allocation system of the embodiment of the present application includes a main board, including: a central processing unit, an extension chip, and a first connector group; an input and output board, including: a second connector group; the first connector group provides a first signal group to the extension chip based on whether a cable is connected between the first connector group and the second connector group; the central processing unit reads the first signal group from the extension chip, and configures the bandwidth bifurcation mode of the central processing unit according to the first signal group.

[0040] In this embodiment, through the different situations of the cable connection relationship between the first connector group and the second connector group, a first signal group containing different signal sequences is provided to the expansion chip, the central processing unit reads the first signal group from the expansion chip, and configures the bandwidth bifurcation mode of the central processing unit according to the signal sequence therein. In this way, only a basic input and output system program of the central processing unit needs to be written, and only an input and output board connecting to a high-speed serial computer expansion bus standard device needs to be manufactured on the hardware device, which simplifies the design process, saves the workload of basic input and output system development and maintenance, and can also reduce production costs. In addition, in this application, different signal sequences are generated by changing the connector cable mode between the connector groups to achieve the purpose of changing the bandwidth bifurcation mode. The operation is simple and easy to maintain, and the management and control costs in the production process are reduced. At the same time, the bandwidth allocation abnormality caused by improper operation is avoided, which greatly improves the production yield of the product, meets the user's usage needs, and improves the user's production efficiency, solving the problems existing in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1 This is a schematic diagram of a first bandwidth bifurcation mode proposed in an embodiment of the present application;

[0043] Figure 2 This is a schematic diagram of a second bandwidth bifurcation mode proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] In the drawings, the size of the constituent elements, the thickness of the layer or the area may be exaggerated for the sake of clarity. Therefore, any implementation of the present application is not necessarily limited to the size shown in the drawings, and the shape and size of the components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and any implementation of the present application is not limited to the shape or value shown in the drawings.

[0046] In the prior art, in terms of the allocation of the few X16 high-speed serial computer expansion bus standard resources that can be used for flexible configuration, due to the different bandwidth bifurcation mode allocation situations, manufacturers generally choose to formulate a variety of different basic input and output systems in the central processing unit to configure the corresponding bandwidth bifurcation mode for different device connection situations. However, in this way, first of all, from the design perspective, the design cost is increased, and different codes need to be written for a variety of situations. Moreover, from the perspective of production management, there are different versions of the basic input and output systems of the central processing unit that need to be burned, which makes it inconvenient to control the problems that may occur in the production process, and there is a risk of errors caused by operational errors. Moreover, once there is a problem with the basic input and output system settings, it is not easy to troubleshoot and correct. Therefore, different versions of basic input and output systems are not conducive to a series of problems such as consistent design and quality inspection, and the requirements for the work quality of design, production, and quality inspection personnel are also greatly improved.

[0047] In the prior art, there is another way, which is to formulate different input and output boards according to different bandwidth bifurcation modes to connect different high-speed serial computer expansion bus standard devices. However, this method requires the configuration and preparation of different hardware boards, which first increases the design cost from the design perspective, and from the production perspective, different raw materials need to be equipped. Whether it is the material cost or the allocation and management process in the actual production process, it will increase the possibility of more problems, and the manufacture of input and output boards for a variety of different situations will greatly increase the production cost, resulting in more expenses and waste.

[0048] Based on the problems existing in the prior art, this application proposes a bandwidth allocation system, including:

[0049] Mainboard, including: central processing unit, expansion chip, first connector group,

[0050] The input-output board includes: a second connector group,

[0051] The first connector group provides a first signal group to the expansion chip based on whether a cable is connected between the first connector group and the second connector group;

[0052] The central processing unit reads the first signal group from the extension chip, and configures a bandwidth bifurcation mode of the central processing unit according to the first signal group.

[0053] In the embodiment of the present application, in order to avoid a series of problems that may be caused by different basic input and output systems or different hardware boards, different bandwidth allocation modes are distinguished by distinguishing the connection cables between the mainboard and the input and output board. According to the cable connection relationship between the first connector group located on the mainboard and the second connector group located on the input and output board, the relationship corresponding to the configuration of different high-speed serial computer expansion bus standard devices is generated, so that the first signal group of the high-speed serial computer expansion bus standard device to be connected is sent to the central processing unit. The content of the first signal group is configured accordingly in the basic input and output system of the central processing unit, so that after the central processing unit reads the content of different first signal groups, according to the device connection mode shown therein, different bandwidth allocation can be performed on the corresponding high-speed serial computer expansion bus standard slot, so that there is no need to write multiple basic input and output systems or design multiple hardware boards, and different bandwidth allocation can be performed according to different high-speed serial computer expansion bus standard device connection modes.

[0054] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, wherein the first connector group includes: a first connector, a second connector;

[0055] The second connector group at least includes: a third connector and a fourth connector; the third connector and the fourth connector are connected to the first slot;

[0056] In the embodiment of the present application, the first connector group is arranged on the mainboard and connected to the central processing unit. Here, we take the X16 resource of a central processing unit as an example, and use the two X8 multi-channel input / output connectors connected to the central processing unit on the mainboard as the first connector group, which is used to transmit the X16 resource on the central processing unit and the high-speed serial computer expansion bus standard device for data communication. The two multi-channel input / output connectors are used as the first connector and the second connector. Different bandwidth allocation modes are determined by different connection modes between the connector in the first connector group and the second connector group on the input and output board. The second connector group includes at least the third connector and the fourth connector, which are used as two X8 multi-channel input / output connectors and are connected to the same high-speed serial computer expansion bus standard slot, that is, the first slot. That is to say, if the third connector or the fourth connector is connected to the central processing unit alone, the first slot is used as a high-speed serial computer expansion bus standard slot of an X8 resource, and if the third connector and the fourth connector are connected to the same X16 resource of the central processing unit at the same time, the first slot is used as a high-speed serial computer expansion bus standard slot of an X16 resource.

[0057] Therefore, the present application further proposes that the first connector group provides a first signal group to the extension chip based on whether a cable is connected between the first connector group and the second connector group, including:

[0058] In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fourth connector, the first connector group provides a first signal sequence to the expansion chip.

[0059] When the first connector and the third connector are directly connected to each other, and the second connector and the fourth connector are connected to each other, the connection relationship is equivalent to the X16 resource of the central processing unit being allocated to an X16 high-speed serial computer expansion bus standard device, that is, allocated to the first slot. Therefore, the first connector group provides the expansion chip with a first signal group at this time, and the first signal group is used to express the situation that the X16 resource is allocated to an X16 high-speed serial computer expansion bus standard device. The expansion chip is set on the mainboard and is used to receive the first signal group provided by the first connector group and perform signal processing so that the central processing unit can read the connector connection relationship information contained in the first signal sequence.

[0060] Afterwards, the central processor reads the first signal group from the extension chip, and configures the bandwidth bifurcation mode of the central processor according to the first signal group, including:

[0061] The central processor reads the first signal sequence from the expansion chip, and configures the bandwidth bifurcation mode of the central processor to a first bandwidth bifurcation mode according to the first signal sequence. In the first bandwidth bifurcation mode, the central processor is connected to the first slot.

[0062] In the embodiment of the present application, after receiving the first signal sequence transmitted by the first connector group, the expansion chip performs data processing and sends the processing result to the system management bus interface of the central processing unit. The central processing unit reads the first signal sequence through the system management bus interface, and through the content contained in the first signal sequence, knows the connector connection mode at this time, and performs the corresponding bandwidth bifurcation mode configuration according to the preset basic input and output system program. When the first connector is connected to the third connector, and the second connector is connected to the fourth connector, the central processing unit allocates the X16 resource to an X16 high-speed serial computer expansion bus standard device, and this allocation mode is called the first bandwidth bifurcation mode, that is, a complete X16 resource is allocated to the first slot.

[0063] In combination with the above embodiments, in another implementation manner, the present application further provides a bandwidth allocation system, wherein the first connector group includes: a first connector, a second connector;

[0064] The second connector group includes: a third connector, a fourth connector, a fifth connector, and a sixth connector; the third connector and the fourth connector are connected to the first slot, and the fifth connector and the sixth connector are connected to the second slot.

[0065] In another embodiment of the present application, the first connector group includes a first connector and a second connector, and the second connector group includes not only a third connector and a fourth connector, but also a fifth connector and a sixth connector, wherein the fifth connector and the sixth connector are two X8 multi-channel input / output connectors, which are commonly connected to another high-speed serial computer expansion bus standard slot, namely, the second slot. At this time, there are two high-speed serial computer expansion bus standard slots, namely, the first slot and the second slot, on the input and output board.

[0066] On this basis, providing a first signal group to the extension chip according to whether a cable is connected between the first connector group and the second connector group includes:

[0067] In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the first connector group provides a second signal sequence to the expansion chip.

[0068] In another embodiment of the present application, different from the above-mentioned embodiment, there are two different high-speed serial computer expansion bus standard slots on the input-output board. When two high-speed serial computer expansion bus standard devices need to be connected, the direct cable connection method between the input-output board and the mainboard is different from the above-mentioned case. Since the third connector and the fourth connector belong to the first slot, and the fifth connector and the sixth connector belong to the second slot, in order to connect different high-speed serial computer expansion bus standard devices, the first connector needs to be connected to the third connector, and the second connector needs to be connected to the fifth connector, so as to ensure that the high-speed serial computer expansion bus standard devices in the first slot and the second slot can communicate with the central processing unit. In this case, one X16 resource of the central processing unit is allocated as two X8 resources, which is different from the previous case. Therefore, at this time, the first connector group provides the expansion chip with a second signal sequence representing this situation.

[0069] Afterwards, the central processor reads the first signal group from the extension chip, and configures the bandwidth bifurcation mode of the central processor according to the first signal group, including:

[0070] The central processor reads the second signal sequence from the expansion chip, and configures the bandwidth bifurcation mode of the central processor to a second bandwidth bifurcation mode according to the second signal sequence. In the second bandwidth bifurcation mode, the central processor is connected to the first slot and the second slot.

[0071] In the embodiment of the present application, it is necessary to make corresponding settings in the basic input and output system of the central processing unit, that is, different bandwidth allocations are made according to different signal sequences transmitted from the expansion chip to the system management bus. When reading the second signal sequence transmitted by the expansion chip, the central processing unit can know the connector connection mode at this time through the content contained in the second signal sequence, that is, the first connector is connected to the third connector, and the second connector is connected to the fifth connector, and according to the program preset in the basic input and output system, the bandwidth bifurcation mode configuration under this connection mode is performed, that is, the central processing unit allocates an X16 resource to two X8 high-speed serial computer expansion bus standard devices. This allocation mode is called the second bandwidth bifurcation mode, that is, an X8 resource is allocated to the first slot, and an X8 resource is allocated to the second slot at the same time.

[0072] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, wherein the mainboard further includes: an isolation module connected between the expansion chip and the first connector group.

[0073] In an embodiment of the present application, in the process of the above-mentioned first connector group providing the first signal group to the expansion chip, there is also an isolation module. The isolation module is arranged on the mainboard and is composed of a resistor and a MOS tube. Its input end is connected to the B30 pin and the B12 pin of each connector in the first connector group, that is, the pin in the first connector group for providing the first signal group. The output end of the isolation module is connected to the input end of the expansion chip to provide the first signal group to the expansion module.

[0074] Wherein, the first connector group provides the second signal group to the isolation module based on whether a cable is connected between the first connector group and the second connector group.

[0075] After the first connector group is connected to the second connector group via a cable, or when no cable connection is performed, the connection status will be transmitted as a second signal group and provided to the connected isolation module. After processing by the isolation module, a first signal group containing a first signal sequence or a second signal sequence is finally generated and provided to the central processor as a basis for bandwidth bifurcation mode configuration.

[0076] The isolation module is used to perform signal isolation and reverse processing on the second signal group, and the processed signal group is provided to the extension chip as the first signal group.

[0077] In the embodiment of the present application, the isolation module isolates the second signal group including the connector connection relationship, and obtains the first signal group as input according to the signal processing of the second signal group and provides it to the extension chip. In this way, the input signal of the extension chip is isolated from the input signal in the first connector group, so as to protect the extension chip. Since there are various differences in the signals obtained by the front end, if they are directly transmitted to the extension chip, the function of the extension chip may be affected, and due to reasons such as power-on startup, the power-on sequence of each device is different. Isolating the input signal is also a means of protecting the components, preventing damage to the components themselves due to current pulses, etc., which not only protects the service life of the components, but also improves the reliability of the entire system. In addition, due to differences in the types or models of the extension chips, in different design and manufacturing processes, the isolation module can play a role in level adjustment, converting the signals in the second signal group with a fixed level into the signals in the first signal group suitable for the selected extension chip input level, so that the extension chip can obtain the input signal more accurately, prevent the signal difference caused by level fluctuations, and make the entire system more stable and reliable.

[0078] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, in which, in the first bandwidth bifurcation mode, the first signal sequence includes: a low-level signal provided by B30 of the first connector.

[0079] In the embodiment of the present application, the first signal sequence and the second signal sequence include signals transmitted by two connectors in the first connector group, including the B30 pin and the B12 pin of the first connector and the second connector, that is, the PRSNT in-position signal pin, and the signals transmitted on these four pins and reversed through the isolation module constitute a first signal group including the first signal sequence or the second signal sequence, wherein the corresponding signals are in the order of the first connector B30 pin, the B12 pin, the second connector B30 pin, and the B12 pin, forming a signal sequence, as shown in the following table:

[0080] Table 1

[0081]

[0082] According to the table content, when the signal sequence included in the first signal group is the first signal sequence, that is, when the target bandwidth bifurcation mode is the first bandwidth bifurcation mode, the first connector B30 pin provides a low level signal.

[0083] In this case, the A30 pin of the third connector is connected to the B8 pin of the fifth connector.

[0084] like Figure 1 As shown, in the embodiment of the present application, the A30 pin of the third connector is connected to the B8 pin of the fifth connector on the input and output board to provide in-place signals in different bandwidth bifurcation modes.

[0085] When a cable is connected between the first connector and the third connector and no cable is connected to the fifth connector, the B8 pin of the fifth connector provides a low-level signal to the A30 pin of the third connector, and the low-level signal is transmitted to the B30 pin of the first connector via the cable connected between the first connector and the third connector.

[0086] In an embodiment of the present application, the first connector is connected to the third connector through a cable, wherein according to the provisions of the communication protocol, the B30 pin in the first connector is correspondingly connected to the A30 pin in the third connector. Since on the input and output board, the A30 pin of the first connector is connected to the B8 pin of the fifth connector, and the fifth connector is not connected to other connectors, the B8 pin is left floating and is regarded as providing a low-level signal. The low-level signal is transmitted to the B30 pin of the first connector via the B8 pin of the fifth connector, the A30 pin of the third connector, and the cable between the first connector and the third connector, as a low-level signal provided to the first signal sequence by the B30 pin of the first connector in the first bandwidth bifurcation mode.

[0087] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, in which, in the second bandwidth bifurcation mode, the first signal sequence includes: a high level signal provided by B30 of the first connector.

[0088] Among them, the A8 pin of the second connector is connected to a voltage source; the A30 pin of the third connector is connected to the B8 pin of the fifth connector.

[0089] In the embodiment of the present application, strict restrictions are imposed on the definition of the multi-channel input / output connector signals involved according to the standard specifications, including that the connector B30 and B12 pins are PRSNT in-position signal pins as described above, and that the connector A8 pin is a 3V3 pin connected to a 3.3V power supply, so the A8 pin of the second connector is connected to a 3.3V voltage source on the motherboard.

[0090] When a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the high-level signal provided by the A8 pin of the second connector is transmitted to the B8 pin of the fifth connector via the cable connected between the second connector and the fifth connector, and the high-level signal is transmitted to the B30 pin of the first connector in sequence via the B8 pin of the fifth connector, the A30 pin of the third connector, and the cable connected between the first connector and the third connector.

[0091] like Figure 2 As shown, when the target bandwidth bifurcation mode is the second bandwidth bifurcation mode, the first connector and the third connector are connected by a cable, and the second connector and the fifth connector are connected by a cable. Since the A8 pin of the second connector is connected to a 3.3V voltage source, after the cable connection between the connectors, the B8 pin corresponding to the fifth connector is a 3.3V high level. Since the B8 pin of the fifth connector is connected to the A30 pin of the first connector on the input and output board, the high level signal is sequentially transmitted to the B30 pin of the first connector via the B8 pin of the fifth connector, the A30 pin of the third connector, and the cable connected between the first connector and the third connector. Therefore, when the target bandwidth bifurcation mode is the second bandwidth bifurcation mode, the B30 pin of the first connector is a high level signal as shown in Table 1 above.

[0092] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, in which in the first or second bandwidth bifurcation mode, the first signal sequence or the second signal sequence includes: a low level signal provided by the B12 pin of the first connector;

[0093] The A12 pin of the third connector is left floating;

[0094] In the case where a cable is connected between the first connector and the third connector, the A12 pin of the third connector provides a low-level signal, and the low-level signal is transmitted to the B12 pin of the first connector via the cable connected between the first connector and the third connector.

[0095] In the embodiment of the present application, it can be seen from the above Table 1 that in the first signal sequence and the second signal sequence, the signal provided by the B12 pin of the first connector is always a low-level signal, which is determined by the circuit configuration in the present application. The B12 pin of the first connector is connected to the corresponding A12 pin on the third connector through a connector cable, and on the input and output board, the A12 pin of the third connector is suspended, so when the first connector is connected to the third connector, the A12 pin of the third connector will provide a low-level signal, and the low-level signal is transmitted to the B12 pin of the first connector via the cable connected between the first connector and the third connector, so the A12 pin of the first connector provides a low-level signal.

[0096] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, in which, in the first bandwidth bifurcation mode, the first signal sequence includes: a low level signal provided by B30 and B12 of the second connector;

[0097] The A30 pin and A12 pin of the fourth connector are both left floating;

[0098] When a cable is connected between the second connector and the fourth connector, the A30 pin and the A12 pin of the fourth connector both provide low-level signals, and the low-level signals are transmitted to the B30 pin and the B12 pin of the second connector via the cable connected between the second connector and the fourth connector.

[0099] In the embodiment of the present application, as described above, when the target bandwidth bifurcation mode is the first bandwidth bifurcation mode, the B30 and B12 pins on the second connector are connected to the A30 and A12 pins of the fourth connector through a connector cable, and the A30 and A12 pins of the fourth connector are both in a suspended state on the input and output board. Therefore, when the second connector is connected to the fourth connector, the A30 and A12 pins of the fourth connector provide a low-level signal, and the low-level signal is transmitted to the B30 pin and the B12 pin of the second connector via the cable connected between the second connector and the fourth connector. Therefore, the A30 and A12 pins of the second connector provide a low-level signal.

[0100] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, in which, in the second bandwidth bifurcation mode, the second signal sequence includes: a high level signal provided by B30 of the second connector.

[0101] In the embodiment of the present application, according to the above Table 1, when the target bandwidth bifurcation mode is the second bandwidth bifurcation mode, the second signal sequence provided by the first connector group is 0101, that is, the level provided on the B30 pin of the second connector is a high-level signal, which is also the design that is distinguished from the first bifurcation mode through line configuration in the present application.

[0102] Among them, the A8 pin of the first connector is connected to a voltage source; the A30 pin of the fifth connector is connected to the B8 pin of the third connector.

[0103] By connecting the A30 pin of the fifth connector to the B8 pin of the third connector on the input-output board, the signal on the A30 pin of the fifth connector is determined by the state of the B8 pin on the third connector. In addition, according to the provisions in the standard specification, the A8 pin of the connector is the 3V3 pin connected to the 3.3V power supply.

[0104] When a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the high-level signal provided by the A8 pin of the first connector is transmitted to the B8 pin of the third connector via the cable connected between the first connector and the third connector, and the high-level signal is transmitted to the B30 pin of the second connector in sequence via the B8 pin of the third connector, the A30 pin of the fifth connector, and the cable connected between the second connector and the fifth connector.

[0105] Since the A8 pin of the first connector is connected to a 3.3V voltage source according to the standard specification, after the first connector and the third connector are connected through a cable, the A8 pin on the first connector and the B8 pin on the third connector are also connected accordingly, so that the B8 pin on the third connector is a high level. Since the B8 pin of the third connector is connected to the A30 pin of the fifth connector on the input and output board, the high level signal is transmitted to the B30 pin of the second connector via the B8 pin of the third connector, the A30 pin of the fifth connector, and the cable connected between the second connector and the fifth connector.

[0106] In combination with the above embodiments, in one implementation, the present application further provides a bandwidth allocation system, in which, in the second bandwidth bifurcation mode, the second signal sequence includes: a low level signal provided by B12 of the second connector;

[0107] The A12 pin of the fifth connector is left floating;

[0108] In the case where a cable is connected between the second connector and the fifth connector, the A12 pin of the fifth connector provides a low-level signal, and the low-level signal is transmitted to the B12 pin of the second connector via the cable connected between the second connector and the fifth connector.

[0109] In the embodiment of the present application, it can be seen from the contents of Table 1 above that in the second signal sequence, the signal provided by the B12 pin of the second connector is a low-level signal, which is determined by the circuit configuration in the present application. The B12 pin of the second connector is connected to the corresponding A12 pin on the fifth connector through a connector cable, and on the input and output board, the A12 pin of the fifth connector is suspended, so when the second connector is connected to the fifth connector, the A12 pin of the fifth connector will provide a low-level signal, and the low-level signal is transmitted to the B12 pin of the second connector via the cable connected between the second connector and the fifth connector, so the A12 pin of the second connector provides a low-level signal.

[0110] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0111] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0112] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0113] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0114] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0115] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0116] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0117] The bandwidth allocation system provided by the present application is described in detail above. The principle and implementation method of the present application are described in detail using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A bandwidth allocation system, comprising: A mainboard, comprising: a central processing unit, an expansion chip, and a first connector group, wherein the first connector group comprises: a first connector and a second connector; An input-output board, comprising: a second connector group, wherein the second connector group comprises: a third connector, a fourth connector, a fifth connector, and a sixth connector; the third connector and the fourth connector are connected to a first slot, and the fifth connector and the sixth connector are connected to a second slot; In the case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fourth connector, the central processing unit is connected to the first slot; In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the central processing unit is connected to the first slot and the second slot.

2. The bandwidth allocation system according to claim 1, characterized in that: In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fourth connector, the first connector group provides a first signal sequence to the expansion chip; The central processor reads the first signal sequence from the expansion chip, and configures the bandwidth bifurcation mode of the central processor to a first bandwidth bifurcation mode according to the first signal sequence. In the first bandwidth bifurcation mode, the central processor is connected to the first slot.

3. The bandwidth allocation system according to claim 1, characterized in that: In a case where a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the first connector group provides a second signal sequence to the expansion chip; The central processor reads the second signal sequence from the expansion chip, and configures the bandwidth bifurcation mode of the central processor to a second bandwidth bifurcation mode according to the second signal sequence. In the second bandwidth bifurcation mode, the central processor is connected to the first slot and the second slot.

4. The bandwidth allocation system according to claim 1, characterized in that: The mainboard also includes: an isolation module connected between the expansion chip and the first connector group; The first connector group provides a second signal group to the isolation module based on whether a cable is connected between the first connector group and the second connector group; The isolation module is used to perform signal isolation and reverse processing on the second signal group, and the processed signal group is provided to the extension chip as the first signal group.

5. The bandwidth allocation system according to claim 2, characterized in that: The first signal sequence includes: a low level signal provided by the B30 pin of the first connector; The A30 pin of the third connector is connected to the B8 pin of the fifth connector; When a cable is connected between the first connector and the third connector and no cable is connected to the fifth connector, the B8 pin of the fifth connector provides a low-level signal to the A30 pin of the third connector, and the low-level signal is transmitted to the B30 pin of the first connector via the cable connected between the first connector and the third connector.

6. The bandwidth allocation system according to claim 3, characterized in that: The second signal sequence includes: a high level signal provided by the B30 pin of the first connector; A voltage source is connected to the A8 pin of the second connector; The A30 pin of the third connector is connected to the B8 pin of the fifth connector; When a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the high-level signal provided by the A8 pin of the second connector is transmitted to the B8 pin of the fifth connector via the cable connected between the second connector and the fifth connector, and the high-level signal is transmitted to the B30 pin of the first connector in sequence via the B8 pin of the fifth connector, the A30 pin of the third connector, and the cable connected between the first connector and the third connector.

7. The bandwidth allocation system according to claim 2 or claim 3, characterized in that: The first signal sequence or the second signal sequence includes: a low level signal provided by the B12 pin of the first connector; The A12 pin of the third connector is left floating; In the case where a cable is connected between the first connector and the third connector, the A12 pin of the third connector provides a low-level signal, and the low-level signal is transmitted to the B12 pin of the first connector via the cable connected between the first connector and the third connector.

8. The bandwidth allocation system according to claim 2, characterized in that: The first signal sequence includes: a low level signal provided by B30 and B12 of the second connector; The A30 pin and A12 pin of the fourth connector are both left floating; When a cable is connected between the second connector and the fourth connector, the A30 pin and the A12 pin of the fourth connector both provide low-level signals, and the low-level signals are transmitted to the B30 pin and the B12 pin of the second connector via the cable connected between the second connector and the fourth connector.

9. The bandwidth allocation system according to claim 3, characterized in that: The second signal sequence includes: a high level signal provided by B30 of the second connector; A voltage source is connected to the A8 pin of the first connector; The A30 pin of the fifth connector is connected to the B8 pin of the third connector; When a cable is connected between the first connector and the third connector, and a cable is connected between the second connector and the fifth connector, the high-level signal provided by the A8 pin of the first connector is transmitted to the B8 pin of the third connector via the cable connected between the first connector and the third connector, and the high-level signal is transmitted to the B30 pin of the second connector in sequence via the B8 pin of the third connector, the A30 pin of the fifth connector, and the cable connected between the second connector and the fifth connector.

10. The bandwidth allocation system according to claim 3, characterized in that: The second signal sequence includes: a low level signal provided by B12 of the second connector; The A12 pin of the fifth connector is left floating; In the case where a cable is connected between the second connector and the fifth connector, the A12 pin of the fifth connector provides a low-level signal, and the low-level signal is transmitted to the B12 pin of the second connector via the cable connected between the second connector and the fifth connector.

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