Multi-channel serial digital interface time sequence alignment adjustment method, device and equipment

Abstract

The invention relates to a multi-channel serial digital interface time sequence alignment adjustment method, device and equipment, and the method comprises the steps: determining a first time delay parameter of a clock signal of a serial digital interface of a first channel in a time delay unit; determining a second time delay parameter of the data signal of the second channel in the time delay unit when the data of the second channel can be correctly acquired by the clock signal of the serial digital interface of the first channel, and setting the time delay parameter of the first channel in the time delay unit as a first time delay parameter, the delay parameter of the second channel in the delay unit is set as the second delay parameter, so that the multi-channel data can share the clock signal of the same serial digital interface, the receiving end component can accurately and synchronously acquire the data of the plurality of channels of the transmitting end component, the IO resource of the receiving end component is saved, and the transmission efficiency of the receiving end component is improved. And the expansion possibility, flexibility and reliability are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a method, device and equipment for adjusting timing alignment of a multi-channel serial digital interface. Background Art

[0002] In the fields of communication, radar, software radio, etc., the receiving component will receive the serial data of the transmitting component and process it. In actual use, the transmitting component can be multi-channel, and the interface (IO) of the receiving component is a valuable resource. In order to save resources such as the receiving component IO, especially dedicated clock IO resources, in many practical applications, multi-channel serial digital interface data will share the clock signal of the same channel. Directly using the clock signal of the same channel to collect data from other groups will cause timing errors in data transmission. If the same clock is used to sample multiple groups of data with the same delay, the timing window will be much smaller than that of each group of data adjusting the delay separately, and even a valid timing window cannot be found, causing the sampling system to fail to work properly. Summary of the invention

[0003] According to one aspect of the present disclosure, a method for adjusting timing alignment of a multi-channel serial digital interface is provided, wherein the channels include a first channel and at least one second channel, the multi-channel serial digital interface data share a clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively, and the method includes:

[0004] Determine a first delay parameter of a clock signal of the serial digital interface of the first channel in the delay unit;

[0005] Determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;

[0006] The delay parameter of the first channel in the delay unit is set to a first delay parameter, and the delay parameter of the second channel in the delay unit is set to a second delay parameter.

[0007] In a possible implementation manner, determining a first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit includes:

[0008] Setting the initial delay parameters of the first channel;

[0009] Continuously collecting the conversion signal obtained by the conversion component in the delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, recording the current delay parameter and increasing the delay parameter by the preset step length;

[0010] When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters.

[0011] In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, obtaining the first delay parameter by using a plurality of recorded delay parameters includes:

[0012] An average value or a median value of the plurality of delay parameters is used as the first delay parameter.

[0013] In a possible implementation manner, the determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at the second delay parameter of the delay unit includes:

[0014] Setting the initial delay parameters of the second channel;

[0015] Continuously collecting a plurality of data outputted by the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length;

[0016] When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters.

[0017] In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, obtaining the second delay parameter using a plurality of recorded delay parameters includes:

[0018] An average value or a median value of the plurality of delay parameters is used as the second delay parameter.

[0019] In a possible implementation, the method further includes:

[0020] The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the delay unit.

[0021] In a possible implementation, dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit includes:

[0022] Collect and convert signals N times, where N>1 and is an integer;

[0023] If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel;

[0024] If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel;

[0025] If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel;

[0026] If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel;

[0027] If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

[0028] In a possible implementation manner, the receiving end component uses a delay unit to delay the serial digital interface clock and data respectively, and the delay unit includes:

[0029] An input signal delayer, used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter;

[0030] A serial-to-parallel converter, used for receiving the clock signal or the data signal, performing serial-to-parallel conversion on the clock signal or the data signal, and outputting a conversion signal;

[0031] A frequency division module, used for dividing the frequency of the clock signal, outputting a divided clock, and providing a clock for the serial-to-parallel converter;

[0032] A bit clock alignment state machine, used for judging whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal;

[0033] A delay judgment state machine, used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal;

[0034] A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified;

[0035] The step of determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at the second delay parameter of the delay unit includes:

[0036] In a test mode of the transmitting end component, a second delay parameter of the data signal of the second channel is determined when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel.

[0037] In a possible implementation manner, the first preset value is 0x00, and the second preset value is 0xFF.

[0038] According to one aspect of the present disclosure, a multi-channel serial digital interface timing alignment adjustment device is provided, wherein the channels include a first channel and at least one second channel, the multi-channel serial digital interface data share a clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively, and the device includes:

[0039] A first determining module, used to determine a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit;

[0040] A second determining module, used to determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;

[0041] The setting module is used to set the delay parameter of the first channel in the delay unit to be a first delay parameter, and to set the delay parameter of the second channel in the delay unit to be a second delay parameter.

[0042] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the multi-channel serial digital interface timing alignment adjustment device.

[0043] According to one aspect of the present disclosure, a multi-channel serial digital interface timing alignment adjustment device is provided, wherein the channel comprises a first channel and at least one second channel, the multi-channel serial digital interface data share the clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively, the device comprises a first delay unit and at least one second delay unit, the first delay unit and the second delay unit both comprise an input signal delayer, a serial-to-parallel converter, a bit clock alignment state machine, a data alignment module and a data acquisition module, the first delay unit further comprises a frequency division module, the second delay unit further comprises a delay judgment state machine, the first delay unit is used to determine the first delay parameter of the clock signal of the serial digital interface of the first channel in the first delay unit, the second delay unit is preset to determine the second delay parameter of the data signal of the second channel in the second delay unit when the data of each second channel can be correctly acquired by the clock signal of the serial digital interface of the first channel, wherein,

[0044] The input signal delayer is used to receive a clock signal or a data signal, delay the clock signal or the data signal according to a set delay parameter, and output a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter;

[0045] The serial-to-parallel converter is used to receive the clock signal or the data signal, perform serial-to-parallel conversion on the clock signal or the data signal, and output a conversion signal;

[0046] The frequency division module is used to divide the frequency of the clock signal, output the divided clock, and provide a clock for the serial-to-parallel converter;

[0047] The bit clock alignment state machine is used to determine whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal;

[0048] The delay judgment state machine is used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal;

[0049] A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified;

[0050] The data acquisition module is used to acquire data output by the serial-to-parallel converter.

[0051] In a possible implementation manner, the serial-to-parallel converter in the first delay unit includes a first serial-to-parallel converter, a second serial-to-parallel converter, and a third serial-to-parallel converter, wherein:

[0052] The data input terminal of the input signal delayer is used to input the clock signal.

[0053] The delay parameter input end of the input signal delayer is connected to the output end of the bit clock alignment state machine to receive the delay parameter output by the bit clock alignment state machine.

[0054] The output end of the input signal delayer is connected to the first clock signal end of the first serial-to-parallel converter of the first delay unit, the first clock signal end of the second serial-to-parallel converter of the first delay unit, the first clock signal end of the third serial-to-parallel converter of the first delay unit and the input end of the frequency division module.

[0055] The output end of the frequency division module is connected to the second clock signal end of the first serial-to-parallel converter of the first delay unit, the second clock signal end of the second serial-to-parallel converter of the first delay unit, and the second clock signal end of the third serial-to-parallel converter of the first delay unit.

[0056] The data input terminal of the first serial-to-parallel converter of the first delay unit is used to receive the clock signal.

[0057] The output end of the first serial-to-parallel converter of the first delay unit is connected to the data input end of the bit clock alignment state machine.

[0058] The data input terminal of the second serial-to-parallel converter of the first delay unit is used to receive a frame synchronization signal.

[0059] The output end of the second serial-to-parallel converter of the first delay unit is connected to the input end of the data alignment module.

[0060] The data input terminal of the third serial-to-parallel converter of the first delay unit is used to receive a data signal.

[0061] The output end of the third serial-to-parallel converter of the first delay unit is connected to the input end of the data acquisition module.

[0062] In a possible implementation manner, the input signal delay device in the second delay unit includes a first input signal delay device and a second input signal delay device, and the serial-to-parallel converter in the second delay unit includes a first serial-to-parallel converter and a second serial-to-parallel converter.

[0063] The data input terminal of the first input signal delayer is used to receive a frame synchronization signal.

[0064] The delay parameter input end of the first input signal delayer is connected to the output end of the delay judgment state machine, and is used to receive the delay parameter output by the delay judgment state machine.

[0065] The data output terminal of the first input signal delayer is connected to the data input terminal of the first serial-to-parallel converter of the second delay unit.

[0066] The data input terminal of the second input signal delayer is used to receive a data signal.

[0067] The delay parameter input end of the second input signal delayer is connected to the output end of the delay judgment state machine, and is used to receive the delay parameter output by the delay judgment state machine.

[0068] The data output terminal of the second input signal delayer is connected to the data input terminal of the second serial-to-parallel converter of the second delay unit.

[0069] The first clock signal end of the first serial-to-parallel converter of the second delay unit and the first clock signal end of the second serial-to-parallel converter of the second delay unit are connected to the output end of the input signal delay of the first delay unit.

[0070] The second clock signal end of the first serial-to-parallel converter of the second delay unit and the second clock signal end of the second serial-to-parallel converter of the second delay unit are connected to the output end of the frequency division module.

[0071] The output end of the first serial-to-parallel converter of the second delay unit is connected to the input end of the data alignment module.

[0072] The output end of the second serial-to-parallel converter of the second delay unit is connected to the input end of the data acquisition module and the input end of the delay judgment state machine.

[0073] In a possible implementation manner, determining a first delay parameter of a clock signal of a serial digital interface of the first channel in the first delay unit includes:

[0074] Setting the initial delay parameter of the input signal delay of the first delay unit;

[0075] Continuously collecting a conversion signal obtained by a preset serial-to-parallel converter in the first delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from a previous conversion signal, recording a current delay parameter and increasing the delay parameter by the preset step length;

[0076] When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters.

[0077] In a possible implementation manner, the determining, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the second delay unit includes:

[0078] Setting the initial delay parameter of the input signal delay of the second delay unit;

[0079] Continuously collecting a plurality of data outputted by the preset serial-to-parallel converter of the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length;

[0080] When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters.

[0081] In a possible implementation manner, the device is further used for:

[0082] The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment method of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the preset delay unit.

[0083] In a possible implementation, dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the preset delay unit includes:

[0084] Collect and convert signals N times, where N>1 and is an integer;

[0085] If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel;

[0086] If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel;

[0087] If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel;

[0088] If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel;

[0089] If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

[0090] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above-mentioned multi-channel serial digital interface timing alignment adjustment method, and exemplarily, the processor includes an FPGA or an ASIC, etc.

[0091] According to one aspect of the present disclosure, a storage medium is provided, on which program instructions are stored. When the program instructions are executed by a processor, the above-mentioned multi-channel serial digital interface timing alignment adjustment method is implemented.

[0092] The multi-channel serial digital interface timing alignment adjustment method proposed in the embodiment of the present disclosure determines the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, determines the second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, sets the delay parameter of the first channel in the delay unit to the first delay parameter, and sets the delay parameter of the second channel in the delay unit to the second delay parameter. This can solve the problem that the DCO window is too small and timing errors are prone to occur, enables multi-channel data to share the same serial digital interface clock signal, and enables the receiving end component to accurately and synchronously collect data of multiple channels of the transmitting end component, saves IO resources of the receiving end component, and improves expansion possibility, flexibility and reliability.

[0093] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0095] Figure 1 Figure 1 shows the serial LVDS interface timing diagram for common ADC digital IO outputs.

[0096] Figure 2a A schematic diagram of a delay unit in a receiving end component according to an embodiment of the present disclosure is shown.

[0097] Figure 2bA schematic diagram of a delay unit in an FPGA according to an embodiment of the present disclosure is shown.

[0098] Figure 3 A flowchart of a multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure is shown.

[0099] Figure 4 A flowchart of a multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure is shown.

[0100] Figure 5 A schematic diagram of each delay unit according to an embodiment of the present disclosure is shown.

[0101] Figure 5a , Figure 5b , Figure 5c , Figure 5d , Figure 5e , Figure 5f , Figure 5g A schematic diagram showing the connection relationship of various components of a delay unit according to an embodiment of the present disclosure is shown.

[0102] Figure 6a , Figure 6b Schematic diagrams of adjusting the first delay parameter of channel A and the second delay parameter of channel B using the multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure are respectively shown.

[0103] Figure 7 A schematic diagram of dynamically adjusting delay parameters according to an embodiment of the present disclosure is shown.

[0104] Figure 8 A block diagram of a multi-channel serial digital interface timing alignment adjustment device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0105] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0106] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0107] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0108] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be a connection between two elements or an interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0109] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0110] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0111] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0112] It should be understood that the embodiments of the present disclosure do not limit the specific types of the receiving end component and the transmitting end component. Those skilled in the art can choose according to actual conditions and needs. For example, the receiving end component can be an FPGA, an ASIC chip, etc.; the transmitting end component can be an ADC, or a digital signal source, such as the quantized result of a Transciever, or even a digital chip. As long as the transmitting end component can send out a serial digital code stream, the receiving end component can receive the LVDS code stream sent by the transmitting end component and process it. For ease of description, the embodiments of the present disclosure are introduced by taking the transmitting end component as an ADC (Analog-to-digital Converter) and the receiving end component as an FPGA as an example.

[0113] First, we take the ADC as the transmitting component and the FPGA as the receiving component as an example to introduce the relevant technologies and their existing problems. At present, multi-channel, high-speed, and high-precision ADCs are widely used in communications, radar, software radio and other fields. Due to the large number of channels, if the traditional parallel interface is used to transmit digital signals, more I / O (Input / Output) ports are required, which is not conducive to the miniaturization of chips. At present, the mainstream high-speed multi-channel ADCs mostly use serial LVDS (Low-Voltage Differential Signaling) interfaces as digital output interfaces. This interface has the characteristics of low power consumption, strong anti-interference ability of differential signals, and ultra-high transmission speed, which can effectively reduce the number of device I / Os.

[0114] See also Figure 1 , Figure 1 Figure 1 shows the serial LVDS interface timing diagram for common ADC digital IO outputs.

[0115] The serial LVDS interface timing of common ADC digital IO output is as follows Figure 1 shown. Figure 1 In, ENC - / ENC + Indicates the ADC input sampling clock, driving the ADC sampling circuit; DCO - / DCO + Represents the digital LVDS interface clock. For DDR sampling mode, the rising and falling edges of the sampling clock DCO are aligned with the center of the data to facilitate FPGA (Field Programmable Gate Array) acquisition; FR - / FR + Indicates the frame synchronization signal, which is used to indicate which bits are spliced ​​together to form a complete data. The rising edge of FR is aligned with the data edge; OUT#A - / A+ Indicates data channel A, such as ADC16bit even-bit serial data; OUT#B - / B + Indicates data channel B, such as ADC16bit odd-bit serial data; at the transmitter of serial LVDS, the clock DCO is aligned with the center of Data, and Data is aligned with FR. As the data rate increases, the data sampling window becomes smaller. Taking ADI's LTM9011 as an example, the 16-bit ADC has a data interface rate of 1Gbps and a data cycle of 1ns at a sampling rate of 125MSPS.

[0116] It is known to those skilled in the art that even in the case of a strictly equal-length design of the hardware PCB, it is difficult to ensure the phase relationship between DCO, Data and FR in the FPGA sampling circuit, and it is difficult to ensure a sufficient timing sampling window, which leads to the generation of bit errors, because the DCO and Data take different paths inside the FPGA, thus resulting in the generation of bit errors. In addition, with the improvement of chip integration, multiple groups of DCO / FR / Data have emerged, and each group of FR / Data has an independent DCO for acquisition. However, in some miniaturized applications, it is necessary to use FPGA chips with small package sizes; FPGA IO is a valuable resource. In order to save resources such as FPGA IO, especially dedicated clock IO resources, in many practical applications, multiple groups of Data / FR often share a set of DCO clocks. At this time, due to the timing deviation between multiple groups of DCOs and the timing deviation between DCO and other groups of Data / FR, directly using one group of DCO to directly collect other groups of FR / Data will cause timing errors in data transmission. The relevant technology has a way to perform equal delays on multiple groups of data. However, performing equal delays on two or more groups of data will cause the timing window to be much smaller than adjusting the delay for each group of data separately, and it may even be impossible to find a valid timing window, causing the sampling system to fail to work properly.

[0117] As mentioned above, in the FPGA sampling circuit, it is difficult to ensure the phase relationship between DCO, Data and FR, and it is difficult to ensure a sufficient timing sampling window, which leads to the generation of bit errors. In this regard, the FPGA delay unit can be used to delay the clock path to compensate for the timing reduction and bit error problems caused by the internal wiring path of the FPGA. Of course, the embodiment of the present disclosure does not limit the specific implementation method of the delay unit. For different FPGAs, the implementation method of the delay unit may be different. Those skilled in the art can adopt appropriate technical means to implement it according to actual conditions and needs.

[0118] See also Figure 2a , Figure 2a A schematic diagram of a delay unit in a receiving end component according to an embodiment of the present disclosure is shown.

[0119] In a possible implementation, Figure 2a As shown, the delay unit may include: an input signal delay device, a serial-to-parallel converter, a bit clock alignment state machine, and a frequency division module, wherein:

[0120] The input signal delayer is used to receive a clock signal or a data signal, delay the clock signal or the data signal according to a set delay parameter, and output a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter;

[0121] The serial-to-parallel converter is used to receive the clock signal or the data signal, perform serial-to-parallel conversion on the clock signal or the data signal, and output a conversion signal;

[0122] The frequency division module is used to divide the frequency of the clock signal, output the divided clock, and provide a clock for the serial-to-parallel converter;

[0123] The bit clock alignment state machine is used to determine whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal.

[0124] Of course, the delay unit may also include other components, which are not limited in the embodiments of the present disclosure. Those skilled in the art may set them according to actual conditions and needs, and the number and specific implementation method of each component may also be set according to actual conditions and needs.

[0125] The following is an exemplary introduction using the delay unit in FPGA.

[0126] See also Figure 2b , Figure 2b A schematic diagram of a delay unit in a receiving end component (such as FPGA) according to an embodiment of the present disclosure is shown.

[0127] In a possible implementation, Figure 2b As shown, the delay unit may include:

[0128] A differential input buffer IBUFDS, used for converting a differential signal into a single-ended signal, wherein the differential signal includes a clock signal (DCLK) and a data signal;

[0129] An input signal delay device IDELAYE2, connected to the differential input buffer IBUFDS, for delaying the single-ended signal according to a set delay parameter (such as a delay duration), the input signal delay device IDELAYE2 comprising a signal input terminal IDATAIN, for receiving a single-ended signal output by the differential input buffer IBUFDS;

[0130] The I / O clock buffer IBUFIO and the regional clock buffer BUFR are both connected to the signal output terminal DATAOUT of the input signal delay device IDELAYE2, and are respectively used to output the I / O clock signal CLK and the regional clock signal CLKDIV according to the delayed clock signal (IntBitClk);

[0131] The serial-to-parallel converter ISERDESE2 is used to receive the single-ended signal (such as the input terminal D is used to receive the single-ended clock signal BitClk) and the I / O clock signal CLK, and perform serial-to-parallel conversion on the single-ended signal. The multiple output terminals (Q1-Q8) of the serial-to-parallel converter ISERDESE2 are used to output the conversion signal, wherein the I / O clock signal CLK can be used as a sampling clock of the serial-to-parallel converter ISERDESE2;

[0132] A bit clock phase alignment state machine PASM (Bit Clock Phase Alignment State Machine) is used to determine whether the single-ended signal is aligned with the I / O clock signal CLK according to the conversion signal.

[0133] Among them, the input signal delay device IDELAYE2, the serial-to-parallel converter ISERDESE2, and the bit clock alignment state machine PASM are also used to receive the regional clock signal CLKDIV.

[0134] For example, Figure 2b As shown, a differential input buffer IBUFDS can be set before the input signal delay device IDELAYE2 to convert the differential signal into a single-ended signal. Figure 2a The frequency division module may include an I / O clock buffer IBUFIO and a regional clock buffer BUFR, which are respectively used to output an I / O clock signal CLK and a regional clock signal CLKDIV according to the delayed clock signal (IntBitClk). Of course, the frequency division module may also be implemented through other implementations, which is not limited to the embodiments of the present disclosure.

[0135] The disclosed embodiments do not limit the specific implementation of the differential input buffer IBUFDS, input signal delay IDELAYE2, I / O clock buffer IBUFIO, regional clock buffer BUFR, serial-to-parallel converter ISERDESE2, and bit clock alignment state machine PASM. Those skilled in the art may implement them using appropriate technical means according to actual conditions and needs. For example, those skilled in the art may implement them using mature differential input buffer IBUFDS, input signal delay IDELAYE2, I / O clock buffer IBUFIO, regional clock buffer BUFR, serial-to-parallel converter ISERDESE2, and bit clock alignment state machine PASM in the relevant technology.

[0136] For example, Figure 2b As shown, the clock signal and data signal input to the FPGA are converted from differential signals to single-ended signals through the differential input buffer IBUFDS, so the edge of the single-ended clock signal Bitclk after the clock signal (DCLK) passes through the differential input buffer IBUFDS is aligned with the signal center of the data signal after passing through the differential input buffer IBUFDS. Therefore, it is only necessary to control the delay parameters of the input signal delay device IDELAYE2 so that the clock I / O clock signal CLK and the single-ended clock signal Bitclk after passing through the input signal delay device IDELAYE2 and the I / O clock buffer IBUFIO are aligned, thereby eliminating the delay of the I / O clock buffer IBUFIO, the regional clock buffer BUFR and the network (net), and achieving equal delay. Among them, the I / O clock signal CLK can be used as a sampling clock for the serial-to-parallel converter ISERDESE2 (for example, it can be a dedicated serial-to-parallel converter of FPGA, such as ISERDES (Input SERializer DESerializer)). When the I / O clock signal CLK collects the rising edge or falling edge of the single-ended clock signal Bitclk, the collected data will be metastable, and the serial-to-parallel converter ISERDESE2 will output a continuously changing value, indicating that the I / O clock signal CLK and the single-ended clock signal BitClk are aligned at this time; when the value output by the serial-to-parallel converter ISERDESE2 is 0xFF or 0x00, it means that the edge of the I / O clock signal CLK has not collected the edge of the single-ended clock signal BitClk, that is, it is not aligned. Through the above method, the embodiment of the present disclosure can solve the data transmission problem of the same group of DCO / FR / Data.

[0137] However, because the delay unit of the FPGA cannot perform multiple different delays on one DCO, the above method cannot cope with the situation of multiple groups of DCO / FR / Data. In this regard, the embodiment of the present disclosure can perform equal delays on two groups of data to cope with the situation of multiple groups of DCO / FR / Data. For example, a chip has 2 groups of serial LVDS outputs, each group containing independent DCO / FR / Data. Due to IO limitations, especially clock IO resource limitations, many applications use two groups of Data / FR to share 1 DCO.

[0138] Exemplarily, since the DCO cannot drive two groups of delay units inside the FPGA, a solution of using two groups of Data / FR to share a single-channel delayed DCO can be used. Exemplarily, the specific process of adjusting the window includes:

[0139] Step 1: After power-on, configure the ADC to test mode (Testmode mode) through the register access interface, and configure the digital output to increase or decrease the number;

[0140] Step 2, set the delay parameter of the input signal delay device IDELAYE2 (depending on the timing parameters, the delay parameter is a different value n of 0-31). It should be noted that the delay parameter range of different FPGAs is different. For specific data values, refer to the description document of the delay resource of the corresponding FPGA;

[0141] Step 3, waiting for the data realignment module to complete adjustment, wherein the data realignment module is used to realize the boundary alignment of parallel data. For example, after the serial-to-parallel conversion, 8-bit parallel data can be obtained from the 8-bit data inputted from the outside. However, there may be a misalignment between the front and rear 8-bit data in the parallel data, which cannot be identified by the serial-to-parallel conversion. Therefore, the required parallel data boundary can be found through the data realignment module. Of course, the specific implementation method of the data realignment module is not limited in the embodiment of the present disclosure, and those skilled in the art can realize it through relevant technologies.

[0142] Step 4, when the delay is n, record the N consecutive data output by each group of channels (N is 16384, for example). If the N data of each group are all increasing data, then n at this time is the effective window delay value;

[0143] Step 5, record all valid values ​​of n in the delay parameter range (such as 0-31), if multiple consecutive n are valid values, take the middle value m as the final delay value;

[0144] Step 6, configure m as the delay value of the input signal delay device IDELAYE2, the ADC exits the Testmode mode, enters the normal working mode, and completes the window adjustment operation.

[0145] However, performing equal delay on the two groups of data will cause the timing window to be much smaller than that of adjusting the delay of each group of data separately, and even no effective timing window can be found, resulting in the sampling system being unable to work normally. In view of this, the multi-channel serial digital interface timing alignment adjustment method proposed in the embodiment of the present disclosure determines the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, determines the second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, sets the delay parameter of the first channel in the delay unit to the first delay parameter, and sets the delay parameter of the second channel in the delay unit to the second delay parameter. This can solve the problem that the DCO window is too small and timing errors are prone to occur, can make multi-channel data share the same serial digital interface clock signal, and can realize the receiving end component to accurately and synchronously collect data of multiple channels of the transmitting end component, saving IO resources of the receiving end component and improving the expansion possibility, flexibility and reliability.

[0146] See also Figure 3 , Figure 3 A flowchart of a multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure is shown.

[0147] The channel includes a first channel and at least one second channel. The multi-channel serial digital interface data share the clock signal of the same channel. A delay unit (for example, a receiving end component such as an FPGA delay unit) is used to delay the serial digital interface clock and data (for example, from an original sending end component such as an ADC). Figure 3 As shown, the method includes:

[0148] Step S11, determining a first delay parameter of a clock signal of the serial digital interface of the first channel in the delay unit;

[0149] Step S12, determining a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;

[0150] Step S13, setting the delay parameter of the first channel in the delay unit to a first delay parameter, and setting the delay parameter of the second channel in the delay unit to a second delay parameter.

[0151] It should be understood that different channels of the transmitting component (such as ADC) can correspond to different delay parameters, so that after the ADC enters the normal working mode, the receiving component (such as FPGA) can accurately and synchronously collect data from each channel of the ADC.

[0152] Exemplarily, when the center position of the data signal of the second channel is aligned with the edge of the clock signal of the first channel, the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel. Of course, the embodiment of the present disclosure does not limit the specific method for determining when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel. Those skilled in the art can determine it in an appropriate manner according to actual conditions and needs.

[0153] The disclosed embodiments do not limit the level standard of the serial digital interface, and those skilled in the art may set it according to actual conditions and needs. For example, the serial digital interface may be a digital LVDS interface or an interface of other level standards. The serial digital interface is described below using a digital LVDS interface as an example.

[0154] The presently disclosed embodiment does not limit the specific implementation method of determining the first delay parameter of the delay unit of the clock signal of the serial digital interface of the first channel in step S11. Those skilled in the art may adopt appropriate technical means to implement it according to actual conditions and needs, which is exemplarily introduced below.

[0155] See also Figure 4 , Figure 4 A flowchart of a multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure is shown.

[0156] In a possible implementation, Figure 4 As shown, step S11 determines the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, which may include:

[0157] Step S111, setting the initial delay parameter of the first channel, for example, setting the delay parameter of the input signal delay device IDELAYE2 of the first channel as the initial delay parameter;

[0158] Step S112, continuously collecting the conversion signal obtained by the conversion component in the delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter with a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, recording the current delay parameter and increasing the delay parameter with the preset step length, wherein the conversion component may be a bit clock alignment state machine PASM, for example, continuously collecting the conversion signal through the bit clock alignment state machine PASM, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter with a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, recording the current delay parameter and increasing the delay parameter with the preset step length;

[0159] Step S113: when the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained using a plurality of recorded delay parameters.

[0160] The disclosed embodiment sets the delay parameter of the input signal delay device IDELAYE2 of the first channel as the initial delay parameter, continuously collects the conversion signal through the bit clock alignment state machine PASM, and increases the delay parameter by a preset step when the conversion signal is a first preset value or a second preset value; or records the current delay parameter and increases the delay parameter by the preset step when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal. When the delay parameter reaches the maximum delay parameter, the first delay parameter can be quickly obtained by using the recorded multiple delay parameters to set the delay parameter of the delay unit of the first channel.

[0161] Exemplarily, the initial delay parameter may be, for example, 0, the first preset value may be 0x00, the second preset value may be 0xFF, the preset step may be, for example, 1, and the maximum delay parameter may be, for example, 31. In the embodiment of the present disclosure, when the serial-to-parallel converter ISERDESE2 outputs a continuously changing value (the conversion signal is not the first preset value or the second preset value, and is different from the previous conversion signal), it is determined that the collected data is metastable, which means that the I / O clock signal CLK and the single-ended clock signal BitClk are aligned at this time, so the current delay parameter is recorded and the delay parameter is increased by the preset step; when the value output by the serial-to-parallel converter ISERDESE2 is 0xFF or 0x00 (the conversion signal is the first preset value or the second preset value), it means that the edge of the I / O clock signal CLK has not collected the edge of the single-ended clock signal BitClk, that is, it is not aligned, so the delay parameter is increased by the preset step, but the delay parameter at this time is not recorded. Through such a setting, the embodiment of the present disclosure can conveniently and quickly determine whether the signal is aligned.

[0162] For example, Figure 2b As shown in the figure, the principle of SERDESE2 serial-to-parallel conversion as alignment can be described as follows: I / O clock signal CLK is a delayed clock after IDELAY2, BitCLK is a target alignment clock with the same frequency as I / O clock signal CLK, and the ultimate goal is to align CLK clock with BitClk. CLK is delayed by IDELAY2 to achieve alignment. The way to determine whether it is aligned is: let I / O clock signal CLK be the acquisition clock of ISERDESE2, and BitClk be the input signal of ISERDESE2. For example, let the rising edge of I / O clock signal CLK acquire BitCLK, and acquire 8 times as the output value of ISERDESE2 (parallel 8bit). Among them, if the I / O clock signal CLK acquires the low level of BitCLK, it outputs 0x00; if the I / O clock signal CLK acquires the high level of BitCLK, it outputs 0xFF. Both of these situations indicate that there is no alignment.

[0163] Of course, the specific values ​​of the above parameters are not limited in the embodiments of the present disclosure. For different FPGAs or different receiving end components, the specific values ​​of the above parameters may be different, and those skilled in the art can set them according to actual conditions and needs.

[0164] For example, please refer to Figure 2bFor the first channel, the initial delay parameter of the input signal delay device IDELAYE2 can be set to 0, and the conversion signal output by the serial-to-parallel converter ISERDESE2 is continuously collected through the bit clock alignment state machine PASM, and the state of each conversion signal is determined. When the conversion signal is 0x00 or 0xFF, the delay parameter is increased by 1; or when the conversion signal is not 0x00 or 0xFF and is different from the previous conversion signal, the current delay parameter is recorded, and the delay parameter is increased by 1 until the accumulated delay parameter reaches or exceeds the maximum delay parameter, and multiple recorded delay parameters can be obtained.

[0165] Exemplarily, the delay parameters can be recorded in a storage module, in one example, the storage module can include a computer-readable storage medium, and the storage medium can be a tangible device that can hold and store instructions used by the instruction execution device. The storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples of storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a floppy disk, a mechanical encoding device, such as a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination of the above. The storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (for example, a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0166] In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, obtaining the first delay parameter by using the recorded multiple delay parameters in step S113 may include:

[0167] An average value or a median value of the plurality of delay parameters is used as the first delay parameter.

[0168] The embodiment of the present disclosure does not limit the working mode of the ADC when determining the first delay parameter. The working mode of the ADC when determining the first delay parameter may be a test mode or a normal working mode.

[0169] The embodiment of the present disclosure does not limit the specific implementation method of the second delay parameter of the delay unit for the data signal of the second channel when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel in step S12. Those skilled in the art may adopt appropriate technical means to implement it according to actual conditions and needs, which is exemplarily introduced below.

[0170] In a possible implementation, Figure 4As shown, step S12 determines that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the delay unit may include:

[0171] Step S121, setting the initial delay parameter of the second channel, for example, setting the delay parameter of the input signal delay device IDELAYE2 of the second channel as the initial delay parameter;

[0172] Step S122, continuously collecting a plurality of data outputted by the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length;

[0173] Step S123: when the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained using a plurality of recorded delay parameters.

[0174] The disclosed embodiment sets the delay parameter of the input signal delay device IDELAYE2 of the second channel as the initial delay parameter in the test mode of the ADC, continuously collects multiple data output by the second channel in each cycle, and if the multiple data are not correctly sampled, increases the delay parameter by a preset step size; or if the multiple data are correctly sampled, records the current delay parameter and increases the delay parameter by the preset step size, and when the delay parameter reaches the maximum delay parameter, the second delay parameter can be quickly obtained by using the recorded multiple delay parameters to set the delay parameter of the delay unit of the second channel.

[0175] Of course, the above judgment based on increasing data is exemplary. In other examples, the data may also be decreasing data, or change according to a certain rule. The purpose is to determine whether the current delay value can allow the FPGA to correctly collect data from the ADC. In this way, when multiple data are not increasing data, decreasing data, or other data that changes according to a certain rule, it can be determined that the multiple data are not correctly sampled. On the contrary, when multiple data are increasing data, decreasing data, or other data that changes according to a certain rule, it can be determined that the multiple data are correctly sampled.

[0176] Exemplarily, when the first delay parameter of the first channel is obtained, the embodiment of the present disclosure can fix the first delay parameter of the first channel and determine the second delay parameter of the second channel. For example, the first channel uses the delayed DCO as the sampling clock, because the DCO has been aligned with the data of the first channel. Under the constraint that the input signal delay device IDELAYE2 can only be driven by one IO, the delay value of the DCO cannot be adjusted; for the data of the second channel, when the DCO clock cannot adjust the delay, the embodiment of the present disclosure adds a delay adjustment function of the delay unit to each data of the second channel, and the delayed data is aligned with the DCO of the first channel. Since the DCO of the first channel and the delayed DCO can be judged whether they are aligned through the serial-to-parallel converter ISERDESE2, the delay of the DCO can be dynamically adjusted to keep them aligned at all times. At the same time, since the first channel and the second channel are in the same environment, the electrical parameter change trend is the same, so the delay value of the data of the second channel is also adjusted in the same direction to complete the dynamic alignment of the data of the second channel.

[0177] In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, obtaining the second delay parameter by using a plurality of recorded delay parameters may include:

[0178] An average value or a median value of the plurality of delay parameters is used as the second delay parameter.

[0179] For example, please refer to Figure 2b For the second channel, the initial delay parameter of the input signal delay device IDELAYE2 can be set to 0. By continuously collecting multiple data (such as 16384) output by the second channel in each cycle (continuous time period), if the multiple data are not sampled correctly, the delay parameter is increased by 1; or if the multiple data are sampled correctly, the current delay parameter is recorded, and the delay parameter is increased by 1 until the accumulated delay parameter reaches or exceeds the maximum delay parameter, and multiple recorded delay parameters can be obtained.

[0180] After setting the first delay parameter and the second delay parameter, it is necessary to exit the testmode mode to enter the normal working mode. In the normal sampling mode of the ADC, the timing margin cannot be detected in real time, so the window cannot be automatically adjusted according to changes in the external environment (such as high and low temperatures), which poses a great risk in applications in harsh environments.

[0181] The embodiments of the present disclosure do not limit the number of channels, and those skilled in the art can configure the delay parameters of any number of channels according to actual conditions and needs.

[0182] See also Figure 5 , Figure 5 A schematic diagram of each delay unit according to an embodiment of the present disclosure is shown.

[0183] In one example, if Figure 5 As shown, the embodiment of the present disclosure can configure the delay parameters of each delay unit of channel 0 to channel N, and N can be an integer greater than 1.

[0184] In one example, if Figure 5 As shown, a multi-channel serial digital interface timing alignment adjustment device, wherein the channel includes a first channel ( Figure 5 Channel 0 in ) and at least one second channel ( Figure 5 Channel N in the multi-channel serial digital interface data share the clock signal of the same channel, and use a delay unit to delay the serial digital interface clock and data respectively. The device includes a first delay unit (corresponding to Figure 5 Channel 0 in), at least one second delay unit (corresponding to Figure 5 Channel N in the first delay unit, the first delay unit and the second delay unit both include an input signal delayer, a serial-to-parallel converter, a bit clock alignment state machine, a data alignment module and a data acquisition module, the first delay unit also includes a frequency division module, the second delay unit also includes a delay judgment state machine, the first delay unit is used to determine the first delay parameter of the clock signal of the serial digital interface of the first channel in the first delay unit, and each second delay unit is used to determine when the data of each second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the second delay unit, wherein,

[0185] The input signal delayer is used to receive a clock signal or a data signal, delay the clock signal or the data signal according to a set delay parameter, and output a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter;

[0186] The serial-to-parallel converter is used to receive the clock signal or the data signal, perform serial-to-parallel conversion on the clock signal or the data signal, and output a conversion signal;

[0187] The frequency division module is used to divide the frequency of the clock signal, output the divided clock, and provide a clock for the serial-to-parallel converter;

[0188] The bit clock alignment state machine is used to determine whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal;

[0189] The delay judgment state machine is used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal;

[0190] A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified;

[0191] The data acquisition module is used to acquire data output by the serial-to-parallel converter.

[0192] The multi-channel serial digital interface timing alignment adjustment device proposed in the embodiment of the present disclosure determines the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, determines the second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, sets the delay parameter of the first channel in the delay unit to the first delay parameter, and sets the delay parameter of the second channel in the delay unit to the second delay parameter. This can solve the problem that the DCO window is too small and timing errors are prone to occur, and can make multi-channel data share the same serial digital interface clock signal, and can realize the receiving end component to accurately and synchronously collect data of multiple channels of the transmitting end component, saving the IO resources of the receiving end component and improving the expansion possibility, flexibility and reliability.

[0193] In a possible implementation, Figure 5 As shown, the serial-to-parallel converter in the first delay unit includes a first serial-to-parallel converter, a second serial-to-parallel converter, and a third serial-to-parallel converter, wherein:

[0194] The data input terminal IDATAIN of the input signal delayer is used to input the clock signal DCO_Ch0.

[0195] The delay parameter input terminal CNTVALUEIN of the input signal delayer is connected to the output terminal delay_value of the bit clock alignment state machine to receive the delay parameter Delay_ch0 output by the bit clock alignment state machine.

[0196] The output terminal DATAOUT of the input signal delayer is connected to the first clock signal terminal CLK of the first serial-to-parallel converter of the first delay unit, the first clock signal terminal CLK of the second serial-to-parallel converter of the first delay unit, the first clock signal terminal CLK of the third serial-to-parallel converter of the first delay unit and the input terminal of the frequency division module.

[0197] The output end of the frequency division module is connected to the second clock signal end CLKDIV of the first serial-to-parallel converter of the first delay unit, the second clock signal end CLKDIV of the second serial-to-parallel converter of the first delay unit, and the second clock signal end CLKDIV of the third serial-to-parallel converter of the first delay unit.

[0198] The data input terminal D of the first serial-to-parallel converter of the first delay unit is used to receive the clock signal DCO_Dh0.

[0199] The output terminal Q of the first serial-to-parallel converter of the first delay unit is connected to the data input terminal data of the bit clock alignment state machine.

[0200] The data input terminal D of the second serial-to-parallel converter of the first delay unit is used to receive the frame synchronization signal FR_Ch0.

[0201] The output terminal Q of the second serial-to-parallel converter of the first delay unit is connected to the input terminal of the data alignment module.

[0202] The data input terminal D of the third serial-to-parallel converter of the first delay unit is used to receive a data signal.

[0203] The output terminal Q of the third serial-to-parallel converter of the first delay unit is connected to the input terminal data of the data acquisition module.

[0204] In a possible implementation, Figure 5 As shown, the input signal delay device in the second delay unit includes a first input signal delay device and a second input signal delay device, and the serial-to-parallel converter in the second delay unit includes a first serial-to-parallel converter and a second serial-to-parallel converter.

[0205] The data input terminal IDATAIN of the first input signal delayer is used to receive the frame synchronization signal FR_Ch0.

[0206] The delay parameter input terminal CNTVALUEIN of the first input signal delayer is connected to the output terminal delay_value of the delay judgment state machine, and is used to receive the delay parameter Delay_chN output by the delay judgment state machine.

[0207] The data output terminal DATAOUT of the first input signal delayer is connected to the data input terminal D of the first serial-to-parallel converter of the second delay unit.

[0208] The data input terminal IDATAIN of the second input signal delayer is used to receive the data signal data0_ChN.

[0209] The delay parameter input terminal CNTVALUEIN of the second input signal delayer is connected to the output terminal delay_value of the delay judgment state machine, and is used to receive the delay parameter Delay_chN output by the delay judgment state machine.

[0210] The data output terminal DATAOUT of the second input signal delayer is connected to the data input terminal D of the second serial-to-parallel converter of the second delay unit.

[0211] The first clock signal terminal CLK of the first serial-to-parallel converter of the second delay unit and the first clock signal terminal CLK of the second serial-to-parallel converter of the second delay unit are connected to the output terminal DATAOUT of the input signal delay device of the first delay unit.

[0212] The second clock signal end CLKDIV of the first serial-to-parallel converter of the second delay unit and the second clock signal end CLKDIV of the second serial-to-parallel converter of the second delay unit are connected to the output end of the frequency division module.

[0213] The output terminal Q of the first serial-to-parallel converter of the second delay unit is connected to the input terminal of the data alignment module.

[0214] The output terminal Q of the second serial-to-parallel converter of the second delay unit is connected to the input terminal of the data acquisition module and the input terminal of the delay judgment state machine.

[0215] In one example, if Figure 5 As shown, the output end of the data alignment module in each channel can be connected to the input end of the data acquisition module. Of course, for different types of FPGAs, the output end of the data alignment module can be connected to different ports. For example, the serial-to-parallel converter ISERDES2 is used in the 7 series FPGA, and the bitslip is connected to the bitslip input pin of the serial-to-parallel converter ISERDES2; for another example, the serial-to-parallel converter ISERDES3 is used in the Ultrascale series FPGA, and the serial-to-parallel converter ISERDES3 does not have a bitslip input pin, and the bitslip needs to be directly introduced into the data acquisition module to implement the shift function in the data acquisition module. For the signal bitslip output from the output end of the data alignment module, those skilled in the art can choose to connect to different pins according to the specific FPGA.

[0216] In a possible implementation manner, determining a first delay parameter of a clock signal of a serial digital interface of the first channel in the first delay unit may include:

[0217] Setting the initial delay parameter of the input signal delay of the first delay unit;

[0218] Continuously collect the conversion signal obtained by the preset serial-to-parallel converter in the first delay unit, and when the conversion signal is the first preset value or the second preset value, increase the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, record the current delay parameter and increase the delay parameter by the preset step length; illustratively, the preset serial-to-parallel converter can be a serial-to-parallel converter at the data input terminal D receiving the clock signal DC0_Ch0, for example Figure 5 The first serial-to-parallel converter of the middle channel 0. Of course, in other implementations, the preset serial-to-parallel converter can also be set according to actual conditions and needs, and this is not limited in the embodiments of the present disclosure.

[0219] When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters.

[0220] In a possible implementation manner, determining the second delay parameter of the data signal of the second channel in the second delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel may include:

[0221] Setting the initial delay parameter of the input signal delay of the second delay unit;

[0222] Continuously collecting a plurality of data outputted by the preset serial-to-parallel converter of the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length;

[0223] When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters.

[0224] In a possible implementation, the device may also be used for:

[0225] The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment method of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the preset delay unit.

[0226] In a possible implementation, dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the preset delay unit includes:

[0227] Collect and convert signals N times, where N>1 and is an integer;

[0228] If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel;

[0229] If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel;

[0230] If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel;

[0231] If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel;

[0232] If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

[0233] The following takes the delay unit in FPGA as an example, where the first channel is channel A and the second channel is channel B, and the adjustment of the first delay parameter of channel A and the second delay parameter of channel B is exemplarily introduced.

[0234] First, the connection relationship of each component in each delay unit in the FPGA is introduced by way of example. It should be noted that the following introduction to the connection relationship of each component in the delay unit is exemplary and is only a preferred solution for implementing the technical solution of the present disclosure, and should not be regarded as a limitation on the embodiments of the present disclosure.

[0235] See also Figure 5a , Figure 5b , Figure 5c , Figure 5d , Figure 5e , Figure 5f , Figure 5g , Figure 5a , Figure 5b , Figure 5c , Figure 5d , Figure 5e , Figure 5f , Figure 5g A schematic diagram showing the connection relationship of various components of a delay unit according to an embodiment of the present disclosure is shown.

[0236] It should be understood that the number of output terminals of the serial-to-parallel converter in the embodiment of the present disclosure may include multiple, such as Figure 5a In the example, a total of 8 output terminals, Q1 to Q8, may be included. Of course, in other examples, the number of output terminals may also include other numbers.

[0237] For example, for each channel, the embodiment of the present disclosure may configure a corresponding connection mode respectively, for example, Figure 5a , Figure 5b , Figure 5c It shows the connection mode of each component of the delay unit corresponding to channel 0. Figure 5d , Figure 5e It shows the connection mode of each component of the delay unit corresponding to channel 1. Figure 5f , Figure 5g The connection mode of each component of the delay unit corresponding to channel N is shown.

[0238] For example, for channel 0, Figure 5a As shown, the input end of the differential input buffer IBUFDS is used to receive the clock signal DC0_Ch0 of channel 0, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal delay device IDELAYE2 and the data input end D of the serial-to-parallel converter ISERDESE2, the delay parameter input end of the input signal delay device IDELAYE2 is connected to the output end DelayValue of the bit clock alignment state machine PASM, and is used to receive the delay parameter Delay_Ch0 of channel 0 output by the output end DelayValue of the bit clock alignment state machine PASM, the signal output end DATAOUT of the input signal delay device IDELAYE2 is connected to the input end of the I / O clock buffer IBUFIO and the input end of the regional clock buffer BUFR, I / The output end of the O clock buffer IBUFIO is connected to the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2 to output the I / O clock signal CLK, the output end of the regional clock buffer BUFR is connected to the clock signal terminal C of the input signal delay device IDELAYE2, the second clock signal terminal CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal terminal CLK of the bit clock alignment state machine PASM to output the regional clock signal CLKDIV, the data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is used to receive the bit alignment signal BitSlip_Ch0 output by the output terminal BitSlip of the data alignment module, and each output end (Q1~Q8) of the serial-to-parallel converter ISERDESE2 is connected to each input end of the bit clock alignment state machine PASM.

[0239] For example, for channel 0, Figure 5bAs shown, the input end of the differential input buffer IBUFDS is used to receive the frame synchronization signal FR_Ch0 of channel 0, the output end of the differential input buffer IBUFDS is connected to the data input end D of the serial-to-parallel converter ISERDESE2, the data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is connected to the output end BitSlip of the data alignment module, the first clock signal end CLK of the serial-to-parallel converter ISERDESE2 is used to receive the I / O clock signal CLK outputted from the output end of the I / O clock buffer IBUFIO, the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE2 is used to receive the regional clock signal CLKDIV outputted from the output end of the regional clock buffer BUFR, each output end (Q1~Q8) of the serial-to-parallel converter ISERDESE2 is connected to each input end of the data alignment module, the clock signal end CLKDIV of the data alignment module is used to receive the regional clock signal CLKDIV outputted from the output end of the regional clock buffer BUFR, and the output end BitSlip of the data alignment module is used to output the bit alignment signal BitSlip_Ch0.

[0240] For example, for channel 0, Figure 5c As shown, the input end of the differential input buffer IBUFDS is used to receive the data signal Data_Ch0 of channel 0, the output end of the differential input buffer IBUFDS is connected to the data input end D of the serial-to-parallel converter ISERDESE2, the data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is used to receive the bit alignment signal BitSlip_Ch0 output by the data alignment module, the first clock signal end CLK of the serial-to-parallel converter ISERDESE2 is used to receive the I / O clock signal CLK output by the output end of the I / O clock buffer IBUFIO, the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE2 is used to receive the regional clock signal CLKDIV output by the output end of the regional clock buffer BUFR, each output end (Q1~Q8) of the serial-to-parallel converter ISERDESE2 is connected to each input end of the data acquisition module, the clock signal end CLKDIV of the data acquisition module is used to receive the regional clock signal CLKDIV output by the output end of the regional clock buffer BUFR, and the data acquisition module is used to collect data output by each output end of the serial-to-parallel converter ISERDESE2.

[0241] For example, for channel 1, Figure 5dAs shown, the input end of the differential input buffer IBUFDS is used to receive the frame synchronization signal FR_Ch1 of channel 1, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal delay device IDELAYE2, the delay parameter input end CNTVALUEIN of the input signal delay device IDELAYE2 is used to receive the delay parameter Delay_Ch1 of channel 1, the signal output end of the input signal delay device IDELAYE2 is connected to the data input end D of the serial-to-parallel converter ISERDESE2, the clock signal end C of the input signal delay device IDELAYE2, and the first clock signal of the serial-to-parallel converter ISERDESE2 Terminal CLK is used to receive the I / O clock signal CLK outputted from the output terminal of the I / O clock buffer IBUFIO, the second clock signal terminal CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal terminal CLKDIV of the data alignment module are used to receive the regional clock signal CLKDIV outputted from the output terminal of the regional clock buffer BUFR, the data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is connected to the output terminal BitSlip of the data alignment module to receive the bit alignment signal BitSlip_Ch1, and each output terminal (Q1~Q8) of the serial-to-parallel converter ISERDESE2 is connected to each input terminal of the data alignment module.

[0242] For example, for channel 1, Figure 5eAs shown, the input end of the differential input buffer IBUFDS is used to receive the data signal Data_Ch1 of channel 1, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal delay device IDELAYE2, the delay parameter input end CNTVALUEIN of the input signal delay device IDELAYE2 is connected to the output end DelayValue of the delay judgment state machine to receive the delay parameter Delay_Ch1 of channel 1, the signal output end of the input signal delay device IDELAYE2 is connected to the data input end D of the serial-to-parallel converter ISERDESE2, the output end of the I / O clock buffer IBUFIO is connected to the clock signal end C of the input signal delay device IDELAYE2 and the first clock signal end CLK of the serial-to-parallel converter ISERDESE2, The output end of the domain clock buffer BUFR is connected to the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal end CLKDIV of the delay judgment state machine. The data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is connected to the output end BitSlip of the data alignment module to receive the bit alignment signal BitSlip_Ch1. The various output ends (Q1~Q8) of the serial-to-parallel converter ISERDESE2 are connected to the various input ends of the data acquisition module and the various input ends of the delay judgment state machine. The delay judgment state machine is used to determine whether the data output by the serial-to-parallel converter ISERDESE2 is increasing data or decreasing data, and adjust the delay parameters. The output end DelayValue of the delay judgment state machine is used to output the delay parameter Delay_Ch1.

[0243] For example, for channel N, Figure 5fAs shown, the input end of the differential input buffer IBUFDS is used to receive the frame synchronization signal FR_ChN of channel N, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal delay device IDELAYE2, the delay parameter input end CNTVALUEIN of the input signal delay device IDELAYE2 is used to input the delay parameter Delay_ChN of channel N, the signal output end of the input signal delay device IDELAYE2 is connected to the data input end D of the serial-to-parallel converter ISERDESE2, and the output end of the I / O clock buffer IBUFIO is connected to the input signal delay device I The clock signal terminal C of DELAYE2, the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2, and the output terminal of the regional clock buffer BUFR are connected to the second clock signal terminal CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal terminal CLKDIV of the data alignment module. The data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is connected to the output terminal BitSlip of the data alignment module to receive the bit alignment signal BitSlip_ChN. The various output terminals (Q1~Q8) of the serial-to-parallel converter ISERDESE2 are connected to the various input terminals of the data alignment module.

[0244] For example, for channel N, Figure 5gAs shown, the input end of the differential input buffer IBUFDS is used to receive the data signal Data_ChN of channel N, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal delay device IDELAYE2, the delay parameter input end CNTVALUEIN of the input signal delay device IDELAYE2 is used to input the delay parameter Delay_ChN of channel N, the signal output end of the input signal delay device IDELAYE2 is connected to the data input end D of the serial-to-parallel converter ISERDESE2, the output end of the I / O clock buffer IBUFIO is connected to the clock signal end C of the input signal delay device IDELAYE2 and the first clock signal end CLK of the serial-to-parallel converter ISERDESE2, the input end of the regional clock buffer BUFR is connected to the clock signal end C of the input signal delay device IDELAYE2 and the first clock signal end CLK of the serial-to-parallel converter ISERDESE2, and the output end of the regional clock buffer BUFR is connected to the clock signal end C of the input signal delay device IDELAYE2 and the first clock signal end CLK of the serial-to-parallel converter ISERDESE2. The output end is connected to the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal end CLKDIV of the delay judgment state machine. The data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE2 is connected to the output end BitSlip of the data alignment module to receive the bit alignment signal BitSlip_ChN. The various output ends (Q1~Q8) of the serial-to-parallel converter ISERDESE2 are connected to the various input ends of the data acquisition module and the various input ends of the delay judgment state machine. The delay judgment state machine is used to determine whether the data output by the serial-to-parallel converter ISERDESE2 is increasing data or decreasing data, and adjust the delay parameters. The output end DelayValue of the delay judgment state machine is used to output the delay parameter Delay_ChN.

[0245] After configuring the above connection mode, the embodiment of the present disclosure can determine the delay parameters of each channel, and an exemplary description is given below using channel A and channel B as examples.

[0246] See also Figure 6a , Figure 6b , Figure 6a , Figure 6b Schematic diagrams of adjusting the first delay parameter of channel A and the second delay parameter of channel B using the multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure are respectively shown.

[0247] In one example, if Figure 6a and Figure 6bAs shown, the ADC can be set to the Testmode mode in step S301 (of course, the first delay parameter of channel A can also be set in the working mode. Therefore, in other examples, the ADC can also be set to the Testmode mode when the determination of the first delay parameter is completed and the determination of the second delay parameter of channel B is started), and the initial delay value DelayA of the DCO of channel A in the delay unit is set to 0 in step S302. The serial-to-parallel value Value of the DCO of channel A is collected in step S303. The state of the serial-to-parallel value Value is judged in step S304. If the serial-to-parallel value Val is ue is 0xFF or 0x00, then increase the delay value of the DCO of channel A (step S305); if the serial value Value is a constantly changing value (for example, not 0xFF or 0x00, and the previous and next values ​​are different), then record the current delay value (in step S306), and increase the delay value of the DCO of channel A; in step S307, if the delay value DelayA is less than or equal to 0x31, jump to step 303 to continue to execute the above process, otherwise execute step S308, that is, if there is no recorded delay value for channel A, then jump to step 320 to set the ADC to normal working mode, and set the adjustment failure flag position to 1 , indicating that the window adjustment fails; if there is a recorded delay value for channel A, the middle value of the first delay value is taken as the DCO delay value (first delay parameter) of channel A. After obtaining the first delay parameter, the second delay parameter of channel B can be determined; in step S310, the initial delay value of channel B data is set to 0; in step S311, wait for the data realignment module to be adjusted; in step S312, collect 16384 data output by channel B; in step S313, determine whether the number of 16384 of channel B is incremental data; in step S314, if it is not an incremental number, do not record the current delay value, and the delay value of channel B is increased by one; in step S315, if yes, record the current delay value, add one to the delay value of channel B, and in step S316, if the delay value is less than or equal to 0x31, continue to execute step S311, otherwise execute step S317, if there is no recorded delay value for channel B, jump to step S320 to set the ADC to normal working mode, and set the adjustment failure flag to 1, indicating that the window adjustment failed; if there is a recorded delay value for channel B, execute step S318 to take the middle value of the first delay value of channel B as the delay value of the data of channel B, and then set the ADC to normal working mode in step S319, and set the adjustment success flag to 1, indicating that the window adjustment is successful.

[0248] In a possible implementation, Figure 4 As shown, the method may also include:

[0249] Step S21, dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit, for example, may include:

[0250] Setting the ADC to a normal working mode, in which the FPGA can accurately and synchronously collect data from multiple channels of the ADC;

[0251] According to the alignment method of the clock signal of the serial digital interface after delay of the first channel and the clock signal of the serial digital interface before delay and the conversion signal output by the serial-to-parallel converter ISERDESE2, the delay parameters of the input signal delay device IDELAYE2 of the first channel and the input signal delay device IDELAYE2 of the second channel are dynamically adjusted.

[0252] The disclosed embodiment can dynamically adjust the delay parameters of the input signal delay device IDELAYE2 of the first channel and the input signal delay device IDELAYE2 of the second channel according to the alignment method of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the serial-to-parallel converter ISERDESE2 in the normal working mode, thereby adapting to changes in the external environment, dynamically adjusting the timing window, and dynamically correcting the timing window without interrupting business during system operation to ensure the correctness of collected data.

[0253] Exemplarily, dynamically adjusting the delay parameters of the input signal delay device IDELAYE2 of the first channel and the input signal delay device IDELAYE2 of the second channel may be, for example, synchronously adjusting the delay parameters of the input signal delay device IDELAYE2 of the first channel and the input signal delay device IDELAYE2 of the second channel, and the amplitude of each adjustment may be the same to improve the efficiency of the dynamic adjustment.

[0254] In a possible implementation, step S21 dynamically adjusts the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit, which may include:

[0255] Collect and convert signals N times, where N>1 and is an integer;

[0256] If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel;

[0257] If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel;

[0258] If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel;

[0259] If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel;

[0260] If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

[0261] The present disclosure does not limit the specific size of N, and those skilled in the art may set it according to actual conditions and needs.

[0262] For example, when channel A adjusts the delay value of DCO from 0 to 0X31, the output value Value (conversion signal) of the serial-to-parallel converter ISERDESE2 of channel A may be as shown in the following Table 1.

[0263] Table 1

[0264] Delay value changes Value changes After the delay, the DCO is aligned with the edge of the original DCO 0->0x31 0x00->Uncertain state->0xFF Rising edge 0->0x31 0xFF->Uncertain state->0x00 Falling edge 0->0x31 0x00->Uncertain state Rising edge 0->0x31 0xFF->Uncertain state Falling edge 0->0x31 Uncertain state->0xFF Rising edge 0->0x31 Uncertain state->0x00 Falling edge 0->0x31 Always keep 0xFF unknown 0->0x31 Always keep 0x00 unknown

[0265] For example, after the alignment edge of the DCO is known, the alignment can be dynamically adjusted according to the output value Value of the serial-to-parallel converter ISERDESE2 of channel A, which can be divided into four cases shown in Table 2.

[0266] Table 2

[0267] Align Edge Value Delay Adjustment Rising edge 0xFF Reduce Rising edge 0x00 Increase Falling edge 0xFF Increase Falling edge 0x00 Reduce

[0268] See also Figure 7 , Figure 7 A schematic diagram of dynamically adjusting delay parameters according to an embodiment of the present disclosure is shown.

[0269] For example, Figure 7As shown, the Value value can be collected 5 times; if the Value values ​​obtained from the 5 acquisitions are all 0x00 and the rising edges are aligned, the delay values ​​of channel A and channel B are increased; if the Value values ​​obtained from the 5 acquisitions are all 0x00 and the falling edges are aligned, the delay values ​​of channel A and channel B are reduced; if the Value values ​​obtained from the 5 acquisitions are all 0xFF and the rising edges are aligned, the delay values ​​of channel A and channel B are reduced; if the Value values ​​obtained from the 5 acquisitions are all 0xFF and the falling edges are aligned, the delay values ​​of channel A and channel B are increased; if one or more values ​​greater than 0x00 and less than 0xFF appear in the Value values ​​obtained from the 5 acquisitions, the delay value will not be changed.

[0270] Exemplarily, the disclosed embodiment determines the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, determines in the test mode of the ADC that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is in the second delay parameter of the delay unit, sets the delay parameter of the first channel in the delay unit to the first delay parameter, sets the delay parameter of the second channel in the delay unit to the second delay parameter, and in the normal working mode, aligns the clock signal of the serial digital interface of the first channel after the delay with the clock signal of the serial digital interface before the delay. The conversion signal output by the serial-to-parallel converter ISERDESE2 and the delay parameters of the input signal delay device IDELAYE2 of the first channel and the input signal delay device IDELAYE2 of the second channel are dynamically adjusted, which can effectively solve the timing stability problem of sampling multiple high-speed, serial LVDS data with one clock DCO, effectively increase the timing window, adapt to changes in the external environment, dynamically adjust the timing window, dynamically correct the timing window without interrupting the business during system operation, ensure the correctness of the collected data, save clock resources, and can be further expanded to single-clock, multi-chip application fields, effectively save IO resources, and improve the high and low temperature working robustness of the system.

[0271] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0272] In addition, the present disclosure also provides a multi-channel serial digital interface timing alignment adjustment device, an electronic device, a storage medium, and a program, all of which can be used to implement any multi-channel serial digital interface timing alignment adjustment method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0273] See also Figure 8 , Figure 8 A block diagram of a multi-channel serial digital interface timing alignment adjustment device according to an embodiment of the present disclosure is shown.

[0274] The channels include a first channel and at least one second channel. The multi-channel serial digital interface data share the clock signal of the same channel. The FPGA delay unit is used to delay the serial digital interface clock and data respectively. Figure 8 As shown, the device comprises:

[0275] A first determining module 10, configured to determine a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit;

[0276] A second determining module 20, configured to determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;

[0277] The setting module 30 is used to set the delay parameter of the first channel in the delay unit to a first delay parameter, and to set the delay parameter of the second channel in the delay unit to a second delay parameter.

[0278] The multi-channel serial digital interface timing alignment adjustment method proposed in the embodiment of the present disclosure determines the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, determines the second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, sets the delay parameter of the first channel in the delay unit to the first delay parameter, and sets the delay parameter of the second channel in the delay unit to the second delay parameter. This can solve the problem that the DCO window is too small and timing errors are prone to occur, enables multi-channel data to share the same serial digital interface clock signal, and enables the receiving end component to accurately and synchronously collect data of multiple channels of the transmitting end component, saves IO resources of the receiving end component, and improves expansion possibility, flexibility and reliability.

[0279] In a possible implementation manner, determining a first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit includes:

[0280] Setting the initial delay parameters of the first channel;

[0281] Continuously collecting the conversion signal obtained by the conversion component in the delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, recording the current delay parameter and increasing the delay parameter by the preset step length;

[0282] When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters.

[0283] In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, obtaining the first delay parameter by using a plurality of recorded delay parameters includes:

[0284] An average value or a median value of the plurality of delay parameters is used as the first delay parameter.

[0285] In a possible implementation manner, the determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at the second delay parameter of the delay unit includes:

[0286] Setting the initial delay parameters of the second channel;

[0287] Continuously collecting a plurality of data outputted by the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length;

[0288] When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters.

[0289] In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, obtaining the second delay parameter using a plurality of recorded delay parameters includes:

[0290] An average value or a median value of the plurality of delay parameters is used as the second delay parameter.

[0291] In a possible implementation, the method further includes:

[0292] The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the delay unit.

[0293] In a possible implementation, dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit includes:

[0294] Collect and convert signals N times, where N>1 and is an integer;

[0295] If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel;

[0296] If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel;

[0297] If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel;

[0298] If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel;

[0299] If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

[0300] In a possible implementation manner, the receiving end component uses a delay unit to delay the serial digital interface clock and data respectively, and the delay unit includes:

[0301] A differential input buffer, used for converting a differential signal into a single-ended signal, wherein the differential signal includes a clock signal and a data signal;

[0302] An input signal delayer, connected to the differential input buffer, for delaying the single-ended signal according to a set delay parameter, wherein the delay parameter includes the first delay parameter and the second delay parameter;

[0303] An I / O clock buffer and a regional clock buffer are both connected to the input signal delayer and are used to output an I / O clock signal and a regional clock signal respectively according to the delayed clock signal;

[0304] A serial-to-parallel converter, used for receiving the single-ended signal and the I / O clock signal, performing serial-to-parallel conversion on the single-ended signal, and outputting a conversion signal;

[0305] A bit clock alignment state machine is used to determine whether the single-ended signal is aligned with the I / O clock signal according to the conversion signal,

[0306] The determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel includes:

[0307] In a test mode of the transmitting end component, a second delay parameter of the data signal of the second channel is determined when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel.

[0308] In a possible implementation manner, the first preset value is 0x00, and the second preset value is 0xFF.

[0309] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0310] The embodiment of the present disclosure also provides a storage medium on which program instructions are stored, and the program instructions implement the above method when executed by a processor. The storage medium may be a non-volatile storage medium.

[0311] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0312] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0313] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0314] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A multi-channel serial digital interface timing alignment adjustment method, characterized in that: The channel includes a first channel and at least one second channel, multi-channel serial digital interface data share a clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively. The method includes: Determine a first delay parameter of a clock signal of the serial digital interface of the first channel in the delay unit; Determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel; The delay parameter of the first channel in the delay unit is set to a first delay parameter, and the delay parameter of the second channel in the delay unit is set to a second delay parameter.

2. The method according to claim 1, characterized in that Determining a first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit includes: Setting the initial delay parameters of the first channel; Continuously collecting the conversion signal obtained by the conversion component in the delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, recording the current delay parameter and increasing the delay parameter by the preset step length; When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters.

3. The method according to claim 2, characterized in that When the delay parameter reaches the maximum delay parameter, obtaining the first delay parameter by using the recorded multiple delay parameters includes: An average value or a median value of the plurality of delay parameters is used as the first delay parameter.

4. The method according to claim 1, characterized in that: The determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at the second delay parameter of the delay unit includes: Setting the initial delay parameters of the second channel; Continuously collecting a plurality of data outputted by the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length; When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters.

5. The method according to claim 4, characterized in that When the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded multiple delay parameters includes: An average value or a median value of the plurality of delay parameters is used as the second delay parameter.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the delay unit.

7. The method according to claim 6, characterized in that The method of dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit includes: Collect and convert signals N times, where N>1 and is an integer; If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel; If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel; If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel; If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel; If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

8. The method according to claim 1, characterized in that The receiving end component uses a delay unit to delay the serial digital interface clock and data respectively, and the delay unit includes: An input signal delayer, used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter; A serial-to-parallel converter, used for receiving the clock signal or the data signal, performing serial-to-parallel conversion on the clock signal or the data signal, and outputting a conversion signal; A frequency division module, used for dividing the frequency of the clock signal, outputting a divided clock, and providing a clock for the serial-to-parallel converter; A bit clock alignment state machine, used for judging whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal; A delay judgment state machine, used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal; A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified; The step of determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at the second delay parameter of the delay unit includes: In a test mode of the transmitting end component, a second delay parameter of the data signal of the second channel is determined when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel.

9. The method according to claim 2, 3 or 7, characterized in that: The first preset value is 0x00, and the second preset value is 0xFF.

10. A multi-channel serial digital interface timing alignment adjustment device, characterized in that: The channels include a first channel and at least one second channel, multi-channel serial digital interface data share a clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively. The device includes: A first determining module, used to determine a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit; A second determining module, used to determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel; The setting module is used to set the delay parameter of the first channel in the delay unit to be a first delay parameter, and to set the delay parameter of the second channel in the delay unit to be a second delay parameter.

11. A multi-channel serial digital interface timing alignment adjustment device, characterized in that: The channel includes a first channel and at least one second channel, multi-channel serial digital interface data share the clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively. The device includes a first delay unit and at least one second delay unit. The first delay unit and the second delay unit both include an input signal delayer, a serial-to-parallel converter, a bit clock alignment state machine, a data alignment module and a data acquisition module. The first delay unit also includes a frequency division module, and the second delay unit also includes a delay judgment state machine. The first delay unit is used to determine the first delay parameter of the clock signal of the serial digital interface of the first channel in the first delay unit, and each second delay unit is used to determine the second delay parameter of the data signal of the second channel in the second delay unit when the data of each second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, wherein, The input signal delayer is used to receive a clock signal or a data signal, delay the clock signal or the data signal according to a set delay parameter, and output a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter; The serial-to-parallel converter is used to receive the clock signal or the data signal, perform serial-to-parallel conversion on the clock signal or the data signal, and output a conversion signal; The frequency division module is used to divide the frequency of the clock signal, output the divided clock, and provide a clock for the serial-to-parallel converter; The bit clock alignment state machine is used to determine whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal; The delay judgment state machine is used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal; A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified; The data acquisition module is used to acquire data output by the serial-to-parallel converter.

12. The device according to claim 11, characterized in that The serial-to-parallel converter in the first delay unit includes a first serial-to-parallel converter, a second serial-to-parallel converter, and a third serial-to-parallel converter, wherein: The data input terminal of the input signal delayer is used to input the clock signal. The delay parameter input end of the input signal delayer is connected to the output end of the bit clock alignment state machine to receive the delay parameter output by the bit clock alignment state machine. The output end of the input signal delayer is connected to the first clock signal end of the first serial-to-parallel converter of the first delay unit, the first clock signal end of the second serial-to-parallel converter of the first delay unit, the first clock signal end of the third serial-to-parallel converter of the first delay unit and the input end of the frequency division module. The output end of the frequency division module is connected to the second clock signal end of the first serial-to-parallel converter of the first delay unit, the second clock signal end of the second serial-to-parallel converter of the first delay unit, and the second clock signal end of the third serial-to-parallel converter of the first delay unit. The data input terminal of the first serial-to-parallel converter of the first delay unit is used to receive the clock signal. The output end of the first serial-to-parallel converter of the first delay unit is connected to the data input end of the bit clock alignment state machine. The data input terminal of the second serial-to-parallel converter of the first delay unit is used to receive a frame synchronization signal. The output end of the second serial-to-parallel converter of the first delay unit is connected to the input end of the data alignment module. The data input terminal of the third serial-to-parallel converter of the first delay unit is used to receive a data signal. The output end of the third serial-to-parallel converter of the first delay unit is connected to the input end of the data acquisition module.

13. The device according to claim 12, characterized in that The input signal delay device in the second delay unit includes a first input signal delay device and a second input signal delay device, and the serial-to-parallel converter in the second delay unit includes a first serial-to-parallel converter and a second serial-to-parallel converter. The data input terminal of the first input signal delayer is used to receive a frame synchronization signal. The delay parameter input end of the first input signal delayer is connected to the output end of the delay judgment state machine, and is used to receive the delay parameter output by the delay judgment state machine. The data output terminal of the first input signal delayer is connected to the data input terminal of the first serial-to-parallel converter of the second delay unit. The data input terminal of the second input signal delayer is used to receive a data signal. The delay parameter input end of the second input signal delayer is connected to the output end of the delay judgment state machine, and is used to receive the delay parameter output by the delay judgment state machine. The data output terminal of the second input signal delayer is connected to the data input terminal of the second serial-to-parallel converter of the second delay unit. The first clock signal end of the first serial-to-parallel converter of the second delay unit and the first clock signal end of the second serial-to-parallel converter of the second delay unit are connected to the output end of the input signal delay of the first delay unit. The second clock signal end of the first serial-to-parallel converter of the second delay unit and the second clock signal end of the second serial-to-parallel converter of the second delay unit are connected to the output end of the frequency division module. The output end of the first serial-to-parallel converter of the second delay unit is connected to the input end of the data alignment module. The output end of the second serial-to-parallel converter of the second delay unit is connected to the input end of the data acquisition module and the input end of the delay judgment state machine.

14. The device according to any one of claims 11 to 13, characterized in that: The determining of a first delay parameter of a clock signal of a serial digital interface of the first channel in the first delay unit includes: Setting the initial delay parameter of the input signal delay of the first delay unit; Continuously collecting a conversion signal obtained by a preset serial-to-parallel converter in the first delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from a previous conversion signal, recording a current delay parameter and increasing the delay parameter by the preset step length; When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters.

15. The device according to any one of claims 11 to 13, characterized in that: The determining, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the second delay unit includes: Setting the initial delay parameter of the input signal delay of the second delay unit; Continuously collecting a plurality of data outputted by the preset serial-to-parallel converter of the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length; When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters.

16. The device according to claim 11, characterized in that The device is also used for: The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment method of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the preset delay unit.

17. The device according to claim 16, characterized in that The method of dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the preset delay unit includes: Collect and convert signals N times, where N>1 and is an integer; If the N conversion signals are all the first preset values ​​and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel; If the N conversion signals are all the first preset values ​​and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel; If the N conversion signals are all the second preset values ​​and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel; If the N conversion signals are all the second preset values ​​and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel; If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.

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