Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, the gate drive circuit comprises N shift registers which are adjacent and output in sequence, N is an integer greater than or equal to 3, each shift register comprises a first output stage and a frequency division control module, control signals with different phases are accessed to the control ends of frequency division control modules in every three or more adjacent and sequentially output shift registers which are sequentially cascaded, so that the conduction time of the frequency division control modules can be controlled to be overlapped with the pulse time of a gate driving signal output by a first output stage as much as possible; therefore, the gate driving signal can be controlled to have a wider pulse, and the pulse width of the gate driving signal can be kept unchanged under the condition of refresh frequency switching, so that the condition that the pulse width of the gate driving signal is narrower in the initial switching stage of the refresh frequency in frequency division display is relieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] A GOA (Gate On Array, gate drive integrated on an array substrate) circuit may also be referred to as a gate drive circuit. Each shift register in the gate drive circuit outputs one or more gate drive signals.

[0003] With the development of display technology, frequency division display requires the gate drive circuit to be able to meet the display requirements of different refresh frequencies, but the pulse width of the gate drive signal in the frequency division display has limitations. Summary of the invention

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem that a gate driving signal has a narrow pulse width at the initial stage of switching the refresh frequency in a frequency-divided display.

[0005] In a first aspect, the present application provides a gate drive circuit, which includes one or more shift register groups, each shift register group includes N adjacent shift registers that output in sequence, N is an integer greater than or equal to 3, and each shift register includes a first output stage and a frequency division control module, the first output stage is used to output a gate drive signal; the frequency division control module is used to control the output of the gate drive signal according to the refresh frequency; wherein the control ends of each frequency division control module in each shift register group are respectively connected to control signals with different phases and the same frequency to adjust the pulse width of the gate drive signal and maintain the same pulse width at different refresh frequencies.

[0006] In a second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, wherein the pixel circuit includes a driving transistor, a compensation transistor and a writing transistor, wherein a first electrode of the compensation transistor is connected to the gate of the driving transistor, a second electrode of the compensation transistor is connected to the first electrode or the second electrode of the driving transistor, and the gate of the compensation transistor is connected to a first gate driving line; a first electrode of the writing transistor is connected to the first electrode or the second electrode of the driving transistor, the second electrode of the writing transistor is connected to the data line, and the gate of the writing transistor is connected to the scanning line.

[0007] The gate drive circuit and display panel provided in the present application can control the on-time of the frequency-division control module to overlap as much as possible with the pulse time of the gate drive signal output by the first output stage by connecting the control end of the frequency-division control module in every three or more adjacent and sequentially output shift registers to control signals of different phases. In this way, the gate drive signal can be controlled to have a pulse with a wider width, and the pulse width of the gate drive signal can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate drive signal has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency-division display.

[0008] Furthermore, each control signal of a different phase can increase the pulse width of the gate driving signal by half a clock cycle, thereby not only being able to more accurately control the pulse width of the gate driving signal but also being able to more flexibly adjust the pulse width of the gate driving signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0010] Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0011] Figure 2 for Figure 1 Timing diagram of the pixel circuit shown.

[0012] Figure 3 It is a timing diagram of a gate driving circuit in the related art.

[0013] Figure 4 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application.

[0014] Figure 5 for Figure 4 The timing diagram of the gate drive circuit shown.

[0015] Figure 6 A schematic diagram of the structure of the signal generation module provided in an embodiment of the present application.

[0016] Figure 7 A schematic diagram of the first structure of a shift register provided in an embodiment of the present application.

[0017] Figure 8 A second structural diagram of the shift register provided in an embodiment of the present application.

[0018] Fig. 9 A third structural schematic diagram of the shift register provided in an embodiment of the present application.

[0019] Fig.10for Figures 8 to 10 The timing diagram of the shift register shown.

[0020] Fig.11 A timing diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0022] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0023] Figure 1 A structural schematic diagram of a pixel circuit provided in an embodiment of the present application, in which a first electrode of a compensation transistor T3 is connected to a gate of a driving transistor T1, a second electrode of the compensation transistor T3 is connected to a first electrode or a second electrode of the driving transistor T1, and a gate of the compensation transistor T3 is connected to a gate driving line; a first electrode of a write transistor T2 is connected to a first electrode or a second electrode of the driving transistor T1, a second electrode of the write transistor T2 is connected to a data line, and a gate of the write transistor T2 is connected to a scan line.

[0024] The driving transistor T1 and the writing transistor T2 are both P-channel low-temperature polysilicon thin film transistors, which can improve the dynamic performance of the pixel circuit. The compensation transistor T3 is an N-channel indium gallium zinc oxide thin film transistor, which can reduce the leakage current of the gate of the driving transistor T1, making it easier to maintain the gate potential of the driving transistor T1 under low refresh frequency.

[0025] The first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.

[0026] The data line is used to transmit a data signal Data, the gate drive line is used to transmit a gate drive signal Nscan1, and the scan line is used to transmit a scan signal Pscan.

[0027] like Figure 2 As shown, the maximum refresh frequency of the pixel circuit is 120 Hz for example. When a frame is displayed at a refresh frequency of 60 Hz, it can be divided into a writing frame of 120 Hz and a holding frame of 120 Hz.

[0028] In the writing frame, the pulse of the gate driving signal Nscan1 covers at least a part of the pulse of the scanning signal Pscan, so that the writing transistor T2 and the compensation transistor T3 are synchronously turned on, and the data signal Data is written to the gate of the driving transistor T1.

[0029] In the hold frame, the gate drive signal Nscan1 has no pulse, while the scan signal Pscan still has the same pulse as in the write frame. In this case, the data signal Data can only be written to the source and / or drain of the drive transistor, but not to the gate of the drive transistor T1. Therefore, the hold frame is also called a skip frame.

[0030] In the writing frame, the duration of the pulse of the gate driving signal Nscan1 covering the pulse of the scanning signal Pscan can ensure the desired charging time. Therefore, it is necessary to keep the pulse width of the gate driving signal Nscan1 stable, which needs to be achieved through the corresponding gate driving circuit.

[0031] Specifically, Figure 3 As shown, in the related gate drive circuit, the gate drive circuit may include a plurality of cascaded shift registers, and these shift registers may adopt Figures 7 to 9 In any of the above examples, the control terminals of the frequency division control modules in all the shift registers in the same gate drive circuit are connected to the same control signal Control. When the control signal Control is at a high potential, all the shift registers output low potential and pulse-free gate drive signals Nscan1<1~800>, ... <801> 、Nscan1 <802> 、Nscan1 <802> 、Nscan1 <803> 、Nscan1 <804> ...etc., in this case, the pixel circuits controlled by the 1st to 800th shift registers display at a refresh rate.

[0032] When the 801st-level shift register, the 802nd-level shift register, the 803rd-level shift register, the 804th-level shift register and subsequent shift registers are required to control the corresponding pixel circuit to display at another refresh frequency, the control signal Control is switched from a high potential to a low potential, so that the 801st-level shift register, the 802nd-level shift register, the 803rd-level shift register, the 804th-level shift register and subsequent shift registers all output a gate drive signal Nscan1 with a pulse. <801> 、Nscan1 <802> 、Nscan1 <803> 、Nscan1 <804> ...wait.

[0033] However, due to the defects of the gate driving circuit in the related art, the gate driving signal has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display, for example, Figure 3 Middle gate drive signal Nscan1 <801> The pulse width of the gate drive signal Nscan1 is only 0.5 clock cycles. <802> The pulse width of the gate drive signal is only one clock cycle, which will reduce the charging time of the data signal Data for the pixel circuit, thus causing display abnormality. <803> 、Nscan1 <804> , the width of each pulse remains the same, for example, 1.5 clock cycles.

[0034] In view of the technical problem that the gate drive signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display mentioned above, this embodiment provides a gate drive circuit, see Figures 4 to 11 The gate drive circuit includes one or more shift register groups 111, each shift register group 111 includes N adjacent shift registers that output in sequence, N is an integer greater than or equal to 3, each shift register includes a first output stage 10 and a frequency division control module 20, the first output stage 10 is used to output a gate drive signal Nscan1; the frequency division control module 20 is used to control the output of the gate drive signal Nscan1 according to the refresh frequency; wherein, the control end of each frequency division control module 20 in each shift register group 111 is respectively connected to control signals with different phases and the same frequency to adjust the pulse width of the gate drive signal Nscan1 and maintain the same pulse width at different refresh frequencies.

[0035] It can be understood that the gate drive circuit provided in the present embodiment can control the on-time of the frequency-division control module 20 to overlap as much as possible with the pulse time of the gate drive signal Nscan1 output by the first output stage 10 by connecting the control end of the frequency-division control module 20 in every three or more adjacent and sequentially output shift registers to control signals of different phases. In this way, the gate drive signal Nscan1 can be controlled to have a pulse with a wider width, and the pulse width of the gate drive signal Nscan1 can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate drive signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency-division display.

[0036] Furthermore, each control signal of a different phase can increase the pulse width of the gate driving signal Nscan1 by half a clock cycle, thereby not only being able to more accurately control the pulse width of the gate driving signal Nscan1 but also being able to more flexibly adjust the pulse width of the gate driving signal Nscan1.

[0037] In one embodiment, the shift register group 111 includes a first shift register, a second shift register and a third shift register that output a gate drive signal Nscan1 whose phases lag in sequence; the control signal includes a first control signal Control2, a second control signal Control3 and a third control signal Control4, the frequency of the first control signal Control2, the frequency of the second control signal Control3 and the frequency of the third control signal Control4 are all the same, and the phase of the first control signal Control2, the phase of the second control signal Control3 and the phase of the third control signal Control4 lag in sequence; in each shift register group 111, the control end of the frequency division control module 20 in the first shift register is connected to the first control signal Control2, the control end of the frequency division control module 20 in the second shift register is connected to the second control signal Control3, and the control end of the frequency division control module 20 in the third shift register is connected to the third control signal Control4.

[0038] It should be noted that, in this embodiment, the pulse width of each gate drive signal Nscan1 can be determined to be 1.5 clock cycles, and the clock cycle can be Fig.10 In addition, the pulse width of the gate driving signal Nscan1 can be maintained at 1.5 clock cycles even when the refresh frequency is switched.

[0039] In one embodiment, if Fig.10As shown, there is an interval time between the pulse start edge of the first control signal Control2 and the pulse start edge of the second control signal Control3, and there is an interval time between the pulse start edge of the second control signal Control3 and the pulse start edge of the third control signal Control4.

[0040] It should be noted that the interval time is half a clock cycle, which is beneficial to improving the stability of the pulse width of the gate driving signal Nscan1.

[0041] For a positive pulse, the pulse start edge is the rising edge of the pulse; or, for a negative pulse, the pulse start edge is the falling edge of the pulse.

[0042] In one embodiment, the pulse width of the gate driving signal Nscan1 is the product of N and the interval time.

[0043] It should be noted that, based on this embodiment, the pulse width of the gate drive signal Nscan1 can be adjusted more flexibly and stably. For example, the size of N can be adjusted by increasing the number of shift registers and the number of control signals in each shift register group 111; or, it can also be achieved by adjusting the size of the interval duration.

[0044] In one embodiment, if Figure 5 As shown, the first shift register outputs a first gate drive signal, the second shift register outputs a second gate drive signal, and the third shift register outputs a third gate drive signal; there is an interval time between the pulse start edge of the first gate drive signal and the pulse start edge of the second gate drive signal, and there is an interval time between the pulse start edge of the second gate drive signal and the pulse start edge of the third gate drive signal.

[0045] It should be noted that, it can be determined that the phase difference between adjacent and sequentially output pulse drive signals is the interval duration.

[0046] The first gate drive signal may be Nscan1 <801> , the second gate drive signal can be Nscan1 <802> , the third gate drive signal can be Nscan1 <803> .

[0047] In one embodiment, if Figure 5 As shown, the pulse start edge of the first control signal Control2 is at the same time as the pulse start edge of the first gate drive signal, the pulse start edge of the second control signal Control3 is at the same time as the pulse start edge of the second gate drive signal, and the pulse start edge of the third control signal Control4 is at the same time as the pulse start edge of the third gate drive signal.

[0048] It should be noted that the first control signal Control2 can control the starting time of the pulse of the first gate drive signal through the corresponding frequency division control module 20. The second control signal Control3 can control the starting time of the pulse of the second gate drive signal through the corresponding frequency division control module 20. The third control signal Control4 can control the starting time of the pulse of the third gate drive signal through the corresponding frequency division control module 20.

[0049] In one embodiment, if Figure 4 As shown, each control signal is transmitted through a control line, and the control lines include a first control line CL1, a second control line CL2 and a third control line CL3; each shift register group 111 includes a first shift register, a second shift register and a third shift register that output a gate drive signal Nscan1 whose phases lag in sequence; the first control line CL1 is connected to the control end of the frequency division control module 20 of the first shift register in each shift register group 111, the second control line CL2 is connected to the control end of the frequency division control module 20 of the second shift register in each shift register group 111, and the third control line CL3 is connected to the control end of the frequency division control module 20 of the third shift register in each shift register group 111.

[0050] It should be noted that this embodiment can not only achieve stable and adjustable pulse width of the gate drive signal Nscan1, but also can be achieved by only circularly connecting three control lines to each shift register group 111, which reduces the number of control lines and is conducive to achieving a narrower frame.

[0051] In one embodiment, the control line further includes a fourth control line, the shift register group 111 further includes a fourth shift register, and the fourth control line is connected to the control end of the frequency division control module 20 of the fourth shift register in each shift register group 111 .

[0052] It should be noted that, in this embodiment, N is equal to 4, so that the pulse width of the gate drive signal Nscan1 can be increased to two clock cycles. In other required scenarios, the pulse width of the gate drive signal Nscan1 can also be increased by increasing the value of N through the inventive concept of the present application, for example, 5, 6, 7, 8... etc.

[0053] In one embodiment, the first control line CL1, the second control line CL2, the third control line CL3, and the fourth control line transmit the first control signal Control2, the second control signal Control3, the third control signal Control4, and the fourth control signal in sequence, respectively; the frequency of the first control signal Control2, the frequency of the second control signal Control3, the frequency of the third control signal Control4, and the frequency of the fourth control signal are all the same; the phase of the first control signal Control2, the phase of the second control signal Control3, the phase of the third control signal Control4, and the phase of the fourth control signal lag in sequence.

[0054] It should be noted that, in this embodiment, the frequency division control modules 20 in each register group are controlled by four gate driving signals Nscan1 with sequentially delayed phases, so that the pulse width of the gate driving signal Nscan1 can be stabilized within two clock cycles.

[0055] In one embodiment, see Figures 4 to 11 The gate drive circuit includes N shift registers cascaded in sequence, N is an integer greater than or equal to 3, each shift register includes a first output stage 10 and a frequency division control module 20, a first control terminal of the first output stage 10 is connected to the first pull-up node P1, and a second control terminal of the first output stage 10 is connected to the first pull-up node P2. Figure 7 , Figure 8 The first pull-down node Q1 in Fig. 9 The output end of the first output stage 10 is connected to the gate drive line. One end of the frequency division control module 20 is connected to the first pull-up node P1, and the other end of the frequency division control module 20 is connected to the second pull-up node P. Among them, the control end of each frequency division control module 20 in the N shift registers is respectively connected to N control lines that transmit control signals of different phases, and the control end of the frequency division control module 20 in each shift register is connected to a control line.

[0056] It can be understood that the gate drive circuit provided in the present embodiment connects control signals of different phases to the control end of the frequency division control module 20 in every three or more shift registers cascaded in sequence through different control lines, so that the conduction time of the frequency division control module 20 can be controlled to overlap as much as possible with the pulse time of the gate drive signal Nscan1 output by the first output stage 10, so that the gate drive signal Nscan1 can be controlled to have a wider pulse width, and the pulse width of the gate drive signal Nscan1 can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate drive signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display.

[0057] Furthermore, each control signal of a different phase can increase the pulse width of the gate driving signal Nscan1 by half a clock cycle, thereby not only being able to more accurately control the pulse width of the gate driving signal Nscan1 but also being able to more flexibly adjust the pulse width of the gate driving signal Nscan1.

[0058] In one embodiment, if Figure 4 As shown, the N shift registers include a first shift register, a second shift register and a third shift register which are cascaded in sequence; the N control lines transmitting control signals of different phases include a first control line CL1, a second control line CL2 and a third control line CL3 which transmit control signals with sequentially delayed phases; one of the first shift register, the second shift register and the third shift register is connected to one of the first control line CL1, the second control line CL2 and the third control line CL3, another of the first shift register, the second shift register and the third shift register is connected to another of the first control line CL1, the second control line CL2 and the third control line CL3, and another of the first shift register, the second shift register and the third shift register is connected to another of the first control line CL1, the second control line CL2 and the third control line CL3.

[0059] It should be noted that the first control line CL1 can be used to transmit the first control signal Control2. The second control line CL2 can be used to transmit the second control signal Control3. The third control line CL3 can be used to transmit the third control signal Control4. The phases of the first control signal Control2, the second control signal Control3 and the third control signal Control4 are delayed in sequence, and the frequencies of the first control signal Control2, the second control signal Control3 and the third control signal Control4 are the same.

[0060] In one embodiment, if Figure 4 As shown, the control end of the frequency division control module 20 in the first shift register is connected to the first control line CL1, the control end of the frequency division control module 20 in the second shift register is connected to the second control line CL2, and the control end of the frequency division control module 20 in the third shift register is connected to the third control line CL3.

[0061] It should be noted that, as a specific implementation of the previous embodiment, the present embodiment can also connect control signals of different phases to the control end of the frequency division control module 20 in every three or more cascaded shift registers through different control lines, and can control the on-time of the frequency division control module 20 to overlap as much as possible with the pulse time of the gate drive signal Nscan1 output by the first output stage 10, so that the gate drive signal Nscan1 can be controlled to have a wider pulse width, and the pulse width of the gate drive signal Nscan1 can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate drive signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display.

[0062] In one embodiment, the control end of the frequency division control module 20 in the first shift register is connected to the second control line CL2, the control end of the frequency division control module 20 in the second shift register is connected to the third control line CL3, and the control end of the frequency division control module 20 in the third shift register is connected to the first control line CL1.

[0063] It should be noted that, as another specific implementation of the previous embodiment, the present embodiment can also connect control signals of different phases to the control end of the frequency division control module 20 in every three or more cascaded shift registers through different control lines, and can control the on-time of the frequency division control module 20 to overlap as much as possible with the pulse time of the gate drive signal Nscan1 output by the first output stage 10, so that the gate drive signal Nscan1 can be controlled to have a wider pulse width, and the pulse width of the gate drive signal Nscan1 can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate drive signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display.

[0064] In one embodiment, the control end of the frequency division control module 20 in the first shift register is connected to the third control line CL3, the control end of the frequency division control module 20 in the second shift register is connected to the first control line CL1, and the control end of the frequency division control module 20 in the third shift register is connected to the second control line CL2.

[0065] It should be noted that, as another specific implementation of the previous embodiment, the present embodiment can also connect control signals of different phases to the control end of the frequency division control module 20 in every three or more cascaded shift registers through different control lines, so that the conduction time of the frequency division control module 20 can be controlled to overlap as much as possible with the pulse time of the gate drive signal Nscan1 output by the first output stage 10, so that the gate drive signal Nscan1 can be controlled to have a wider pulse width, and the pulse width of the gate drive signal Nscan1 can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate drive signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display.

[0066] In one embodiment, the N shift registers also include a fourth shift register cascaded after the third shift register; the N control lines transmitting control signals of different phases also include a fourth control line, and the phase of the control signal transmitted by the fourth control line lags behind the phase of the control signal transmitted by the third control line CL3; another one of the first shift register, the second shift register, the third shift register and the fourth shift register is connected to another one of the first control line CL1, the second control line CL2, the third control line CL3 and the fourth control line.

[0067] It should be noted that, in this embodiment, N is set equal to 4. Similarly, N may also be an integer such as 5, 6, 7, 8, etc. As N increases by 1, the pulse width of the gate drive signal Nscan1 output by the gate drive line will increase by 0.5 clock cycles.

[0068] Among them, the corresponding connection relationship between each shift register and each control line in this embodiment can refer to the above case where N is 3, and can be obtained by analogy, so it will not be described in detail here.

[0069] In one embodiment, the gate driving circuit includes one or more groups of N shift registers, and each group of N shift registers is connected to N control lines that transmit control signals of different phases.

[0070] It needs to be explained that if Figure 4As shown, the first shift register, the second shift register and the third shift register are the first group, and the fourth shift register, the fifth shift register and the sixth shift register are the second group. The first group is connected to the first control line CL1, the second control line CL2 and the third control line CL3, and the second group is also connected to the first control line CL1, the second control line CL2 and the third control line CL3. In this way, different groups can share the first control line CL1, the second control line CL2 and the third control line CL3, which not only reduces the number of required control lines, but also can achieve precise control of the gate drive signal Nscan1 output by the gate drive line.

[0071] In one embodiment, each control line is connected to the shift registers in the same cascade order in each group of N shift registers.

[0072] It needs to be explained that if Figure 4 As shown, the cascade order of the first shift register and the fourth shift register in the first group and the second group is the same, the cascade order of the second shift register and the fifth shift register in the first group and the second group is the same, and the cascade order of the third shift register and the sixth shift register in the first group and the second group is the same. The first control line CL1 is connected to the first shift register and the fourth shift register, the second control line CL2 is connected to the second shift register and the fifth shift register, and the third control line CL3 is connected to the third shift register and the sixth shift register.

[0073] like Figure 5 As shown, after the control end of the frequency division control module 20 in different shift registers is connected to the first control signal Control2, the second control signal Control3, and the third control signal Control4 corresponding to different phases, when the pixel circuit controlled by the 801st-stage shift register and subsequent shift registers needs to change the refresh frequency, the first control signal Control2 is switched from a high potential to a low potential, and the 801st-stage shift register controlled by the first control signal Control2 can output a gate drive signal Nscan1 having a pulse width of 1.5 clock cycles. <801> The 802nd shift register controlled by the second control signal Control3 can also output a gate drive signal Nscan1 having a pulse width of 1.5 clock cycles. <802> The 803rd shift register controlled by the third control signal Control4 can also output a gate drive signal Nscan1 having a pulse width of 1.5 clock cycles. <803> Similarly, the 804th shift register can also output a gate drive signal Nscan1 with a pulse width of 1.5 clock cycles. <804> This ensures that each row of pixel circuits at the same refresh rate has a consistent charging time and a consistent display effect.

[0074] Figure 6 A schematic diagram of the structure of a signal generating module provided in an embodiment of the present application. It should be noted that the signal generating module includes N cascaded signal generating units, for example, a first signal generating unit, a second signal generating unit ... and an Nth signal generating unit, that is, the number of signal generating units is the same as the number of shift registers in each shift register group 111.

[0075] Among them, Figure 5 , Figure 6 As shown, the first signal generating unit shifts according to the initial control signal Control to generate the corresponding first control signal Control2, the second signal generating unit shifts according to the first control signal Control2 to generate the corresponding second control signal Control3... the Nth signal generating unit shifts according to the N-1th control signal to generate the corresponding Nth control signal ControlN+1, and when N is equal to 3, the third signal generating unit shifts according to the second control signal Control3 to generate the corresponding third control signal Control4. For example Figure 5 As shown, the phases of the initial control signal Control, the first control signal Control2, the second control signal Control3 and the third control signal Control4 lag in sequence.

[0076] It should be noted that the corresponding driver chip can be used to generate N control signals with different phases and the same frequency through the initial control signal Control, or the signal generation module of this embodiment can be used to achieve this. Since only one input line is required to transmit the initial control signal Control, more required control signals can be generated through the signal generation module, thereby reducing the required number of input lines, which is conducive to reducing the occupied space of the frame.

[0077] In one embodiment, if Figures 7 to 9 As shown, the frequency division control module 20 includes a frequency division control transistor, a first electrode of the frequency division control transistor is connected to the first pull-up node P1, a second electrode of the frequency division control transistor is connected to the second pull-up node P, and a control electrode of the frequency division control transistor is connected to a control line.

[0078] It should be noted that the frequency division control transistor can be Figure 7 , Figure 8 The transistor T14 in the Fig. 9 The transistor T17 in the frequency division control transistor can be, but is not limited to, a P-channel thin film transistor; it can also be an N-channel thin film transistor, and it only needs to adjust the pulse of the corresponding control signal Control2 / 3 / 4 to a positive pulse.

[0079] The frequency division control transistor in this application is used to realize the corresponding refresh frequency. The control electrode can be a gate electrode or a base electrode.

[0080] In one embodiment, if Figure 7 , Figure 8 As shown, the first output stage 10 includes a transistor T15 and a transistor T16, wherein a first electrode of the transistor T16 is connected to a high potential line, a gate of the transistor T16 is connected to a first pull-up node P1, and a second electrode of the transistor T16 is connected to a gate drive line. A first electrode of the transistor T15 is connected to a low potential line, a gate of the transistor T15 is connected to a first pull-down node Q1, and a second electrode of the transistor T15 is connected to a gate drive line.

[0081] It should be noted that the transistor T15 and the transistor T16 can both be P-channel thin film transistors. The high potential line is used to transmit a high potential signal VGH. The low potential line is used to transmit a low potential signal VGL.

[0082] In one embodiment, if Figure 8 As shown, the first output stage 10 further includes a capacitor C4, one end of the capacitor C4 is connected to the high potential line, and the other end of the capacitor C4 is connected to the gate of the transistor T16.

[0083] It should be noted that the capacitor C4 can improve the conduction degree of the transistor T16, thereby improving the stability of the gate driving signal Nscan1.

[0084] In one embodiment, if Fig. 9 As shown, the first output stage 10 includes a transistor T19, a transistor T20 and a capacitor C4, the high potential line is connected to the first electrode of the transistor T20 and one end of the capacitor C4, the gate of the transistor T20 is connected to the first pull-up node P1, and the second electrode of the transistor T20 is connected to the gate drive line. The first electrode of the transistor T19 is connected to the low potential line, the gate of the transistor T19 is connected to the first pull-down node Q, and the second electrode of the transistor T19 is connected to the gate drive line.

[0085] In one embodiment, if Figures 7 to 9 As shown, the gate drive circuit further includes a second output stage, a first control terminal of the second output stage is connected to the second pull-up node P, and a second control terminal of the second output stage is connected to the second pull-up node P. Figure 7 , Figure 8 The first pull-down node Q1 in Fig. 9 The first pull-down node Q in is connected, and the output end of the second output stage is connected to the cascade line.

[0086] In one embodiment, if Figures 7 to 9As shown, the second output stage includes a transistor T9 and a transistor T10, wherein the first electrode of the transistor T10 is connected to the high potential line, the gate of the transistor T10 is connected to the second pull-up node P, and the second electrode of the transistor T10 is connected to the cascade line. The first electrode of the transistor T9 is connected to the low potential line, the gate of the transistor T9 is connected to the Figure 7 , Figure 8 The first pull-down node Q1 in Fig. 9 The first pull-down node Q in is connected, and the second electrode of the transistor T9 is connected to the cascade line.

[0087] In one embodiment, if Figures 7 to 9 As shown, the second output stage further includes a capacitor C3, one end of the capacitor C3 is connected to the high potential line, and the other end of the capacitor C3 is connected to the gate of the transistor T10.

[0088] It should be noted that the capacitor C3 can improve the conduction degree of the transistor T10, thereby improving the stability of the cascade signal Nscan(n) output by the second output stage.

[0089] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T2, a first electrode of the transistor T2 is connected to the cascade line, a second electrode of the transistor T2 is electrically connected to the first pull-down node Q1, and a gate of the transistor T2 is connected to the first clock line.

[0090] It should be noted that the cascade line can be used to transmit the cascade signal Nscan(n-1). The first clock line is used to transmit the first clock signal CK1. The transistor T2 can transmit the cascade signal Nscan(n-1) to the first pull-down node Q1 under the control of the first clock signal CK1.

[0091] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T13, a first electrode of the transistor T13 is connected to the second pull-down node Q and a second electrode of the transistor T2, a second electrode of the transistor T13 is electrically connected to the first pull-down node Q1, and a gate of the transistor T13 is connected to the low potential line.

[0092] It should be noted that the transistor T13 is used to prevent the charge of the first pull-down node Q1 from flowing to the second pull-down node Q.

[0093] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T1, a first electrode of the transistor T1 is connected to the low potential line, a second electrode of the transistor T1 is electrically connected to the second upper node, and a gate of the transistor T1 is connected to the first clock line.

[0094] It should be noted that the transistor T1 is used to transmit the low potential signal VGL to the second pull-up node P under the control of the first clock signal CK1.

[0095] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T3, a first electrode of the transistor T3 is connected to the second electrode of the transistor T1, a second electrode of the transistor T3 is electrically connected to the second upper node, and a gate of the transistor T3 is connected to the low potential line.

[0096] It should be noted that the transistor T1 is used to prevent the charge of the second pull-up node P from flowing to the second electrode of the transistor T1 .

[0097] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T12, a first electrode of the transistor T12 is connected to the second pull-up node P, a second electrode of the transistor T12 is connected to the second electrode of the transistor T3, and a gate of the transistor T12 is connected to the second clock line.

[0098] It should be noted that the second clock line is used to transmit the second clock signal CK2. The transistor T12 is used to control the connection relationship between the second pull-up node P and the second electrode of the transistor T3 according to the second clock signal CK2.

[0099] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register also includes a transistor T7 and a capacitor C2, the second electrode of the transistor T3 is connected to one end of the capacitor C2 and the gate of the transistor T7, the first electrode of the transistor T7 is connected to the second clock line, and the second electrode of the transistor T7 is connected to the other end of the capacitor C2 and the second electrode of the transistor T12.

[0100] It should be noted that the transistor T7 is used to control whether to transmit the second clock signal CK2 to the second electrode of the transistor T12 according to the potential of the second electrode of the transistor T3. The capacitor C2 is used to increase the conduction degree of the transistor T7.

[0101] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T4, a first electrode of the transistor T4 is connected to the first clock line, a gate of the transistor T4 is connected to the second electrode of the transistor T2, and a second electrode of the transistor T4 is connected to the second electrode of the transistor T1.

[0102] It should be noted that transistor T4 is used to transmit the first clock signal CK1 to the second electrode of transistor T1 under the control of the second electrode potential of transistor T2. Transistor T4 is a composite transistor formed by two transistors of the same communication type connected in series, which can reduce the charge of the second electrode of transistor T2 flowing to the first clock line.

[0103] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register also includes a transistor T5, a transistor T6 and a capacitor C1, the first electrode of the transistor T5 is connected to the high potential line, the gate of the transistor T5 is connected to the second electrode of the transistor T1, the second electrode of the transistor T5 is connected to one end of the capacitor C1 and the first electrode of the transistor T6, the other end of the capacitor C1 is connected to the first pull-down node Q1 and the gate of the transistor T6, and the second electrode of the transistor T6 is connected to the second clock line.

[0104] It should be noted that when the cascade signal Nscan(n-1) is a high pulse signal, the first clock signal CK1 enters a low potential, the transistor T4 is turned off, the gate potential of the transistor T5 is VGL (the potential of the low potential signal VGL), and VGH (the potential of the high potential signal VGH) enters the intermediate node where the transistor T5 is connected to the transistor T6. When the potential of the node D is VGH, at this time, the potential of the second pull-up node P is VGL, the transistor T10 is turned on, and the cascade signal Nscan(n) is at a high potential.

[0105] When the cascade signal Nscan(n-1) is pulled low, the transistor T13 is turned on, the potential of the second pull-down node Q is VGL-Vth (Vth is the threshold voltage of the transistor T2), and the potential of the cascade signal Nscan(n) output through the transistor T9 is VGL-Vth.

[0106] Transistor T4 is turned on, and the high potential of the first clock signal CK1 is output to the gate of transistor T5. Transistor T5 is turned off, and the low potential of the second clock potential CK2 is output to the intermediate node connecting transistor T5 and transistor T6. The potential of the intermediate node jumps, and the potential of the first pull-down node Q1 is coupled through capacitor C1, so that the potential of the first pull-down node Q1 is pulled to a potential lower than VGL. Transistor T9 is fully turned on, and the potential of the cascade signal Nscan(n) is VGL.

[0107] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T8, a first electrode of the transistor T8 is connected to the high potential line, a gate of the transistor T8 is connected to the second pull-down node Q, and a second electrode of the transistor T8 is connected to the second pull-up node P.

[0108] It should be noted that the transistor T8 is used to raise the potential of the second pull-up node P to a high potential when the potential of the second pull-down node Q is a low potential, which can improve the reliability of the shift register.

[0109] In one embodiment, if Figure 7 , Figure 8 As shown, the shift register further includes a transistor T11, a first electrode of the transistor T11 is connected to the high potential line, a gate of the transistor T11 is connected to the second pull-down node Q, and a second electrode of the transistor T11 is connected to the first pull-up node P1.

[0110] It should be noted that the transistor T11 is used to raise the potential of the first pull-up node P1 to a high potential when the potential of the second pull-down node Q is a low potential, which can further improve the reliability of the shift register.

[0111] In one embodiment, if Fig. 9 As shown, the shift register also includes a transistor T3 and a transistor T12, the first electrode of the transistor T3 is connected to the start control line, the gate of the transistor T3 is connected to the first clock line, the second electrode of the transistor T3 is connected to the first electrode of the transistor T12, the gate of the transistor T12 is connected to the low potential line, and the second electrode of the transistor T12 is connected to the first pull-down node Q.

[0112] It should be noted that in Fig. 9 In the embodiment, the first clock line is used to transmit the first clock signal XCK. The start control line is used to transmit the start control signal STV.

[0113] In one embodiment, if Fig. 9 As shown, the shift register further includes a transistor T13, a first electrode of the transistor T13 is connected to the high potential line, a gate of the transistor T13 is connected to the global control line, and a second electrode of the transistor T13 is connected to the second electrode of the transistor T3.

[0114] It should be noted that the global control line is used to transmit the global control signal GC. In the initialization phase of the gate drive circuit, the transistor T13 is used to raise the second electrode potential of the transistor T3 to a high potential under the control of the global control signal GC; in the normal display phase, the transistor T13 is in a cut-off state.

[0115] In one embodiment, if Fig. 9 As shown, the shift register further includes a transistor T4, a first electrode of the transistor T4 is connected to the low potential line, a gate of the transistor T4 is connected to the first clock line, and a second electrode of the transistor T4 is connected to the node N2.

[0116] In one embodiment, if Fig. 9As shown, the shift register further includes a transistor T11, a first electrode of the transistor T11 is connected to the node N2, a gate of the transistor T11 is connected to the low potential line, and a second electrode of the transistor T11 is connected to the node N1.

[0117] In one embodiment, if Fig. 9 As shown, the shift register also includes a transistor T6, a transistor T7 and a capacitor C2, a node N1 is connected to one end of the capacitor C2 and a gate of the transistor T6, a first electrode of the transistor T6 is connected to a second clock line, a second electrode of the transistor T6 is connected to the other end of the capacitor C2 and a first electrode of the transistor T7, a second electrode of the transistor T7 is connected to a second pull-up node P, and a gate of the transistor T7 is connected to the second clock line.

[0118] It should be noted that in Fig. 9 In the embodiment, the second clock line is used to transmit the second clock signal CK. When the potential of the node N1 is low, the transistor T6 is turned on, and the low potential of the second clock signal CK is brushed to the connection point between the transistor T6 and the transistor T7. The potential jump of the connection point will cause the potential of the node N1 to be lower than VGL (the potential of the low potential signal VGL) through the coupling of the capacitor C2, thereby ensuring that the transistor T6 is fully turned on. Among them, the potential of the connection point is VGL.

[0119] In one embodiment, if Fig. 9 As shown, the shift register further includes a transistor T5, a first electrode of the transistor T5 is connected to the first clock line, a gate of the transistor T5 is connected to the second electrode of the transistor T3, and a second electrode of the transistor T5 is connected to the node N2.

[0120] In one embodiment, if Fig. 9 As shown, the shift register also includes a transistor T1, a transistor T2 and a capacitor C1, the first electrode of the transistor T1 is connected to the high potential line, the gate of the transistor T1 is connected to the node N2, the second electrode of the transistor T1 is connected to one end of the capacitor C1 and the first electrode of the transistor T2, the second electrode of the transistor T2 is connected to the second clock line, and the gate of the transistor T2 is connected to the other end of the capacitor C1 and the node D.

[0121] In one embodiment, if Fig. 9 As shown, the shift register also includes a transistor T14, a transistor T15, and a transistor T16, the first electrode of the transistor T14 is connected to the start control line, the gate of the transistor T14 is connected to the first clock line, the second electrode of the transistor T14 is connected to the first electrode of the transistor T15, the gate of the transistor T15 is connected to the low potential line, the second electrode of the transistor T15 is connected to the node D, the node D is connected to the gate of the transistor T16 and the first electrode of the transistor T16, and the second electrode of the transistor T16 is connected to the first pull-down node Q.

[0122] It should be noted that when the potential of the start control signal STV is set from high to low, it will have a coupling effect on the node D, and can pull down the potential of the node D. In this case, the transistor T16 is connected in a diode manner. After the potential of the node D rushes into the first pull-down node Q, the potential of the first pull-down node Q will not be affected by the potential change of the node D, and will maintain a relatively low potential. The continuous turn-on effect of the transistor T9 is better and the output is stable.

[0123] In one embodiment, if Fig. 9 As shown, the shift register further includes a transistor T8, a first electrode of the transistor T8 is connected to the high potential line, a gate of the transistor T8 is connected to the second electrode of the transistor T3, and a second electrode of the transistor T8 is connected to the second pull-up node P.

[0124] In one embodiment, if Fig. 9 As shown, the shift register further includes a transistor T18, a first electrode of the transistor T18 is connected to the high potential line, a gate of the transistor T18 is connected to the second electrode of the transistor T3, and a second electrode of the transistor T18 is connected to the first pull-up node P1.

[0125] Fig.10 for Figure 4 The timing of the gate drive circuit shown is described as follows:

[0126] The control end of the frequency division control module 20 in the 800th-stage shift register is connected to the third control signal Control4, and the potential Nscan_P of the second pull-up node P in the 800th-stage shift register is <800> When the potential of the third control signal Control4 is at a low potential, the frequency division control module 20 is turned off, and the Nscan_P at a low potential is <800> Failed to refresh the potential Nscan_P1 of the first pull-up node P1 in the 800th stage shift register <800> , the first output stage 10 Figure 7 , Figure 8 The transistor T16 shown or Fig. 9 The transistor T20 shown in the figure is always turned off, and the potential Nscan1 of the gate drive signal Nscan1 is <800> Continuously output VGL.

[0127] The control end of the frequency division control module 20 in the 801st-stage shift register receives the first control signal Control2, and the potential Nscan_P of the second pull-up node P in the 801st-stage shift register is <801> When the potential of the first control signal Control2 is low, the frequency division control module 20 is turned on, and the Nscan_P <801> Pull down the potential Nscan_P1 of the first pull-up node P1 in the 801st stage shift register <801> , the first output stage 10 Figure 7 , Figure 8 The transistor T16 shown or Fig. 9 The transistor T20 shown in FIG. 1 is turned on, and the potential Nscan1 of the gate drive signal Nscan1 is <801> Output VGH; when node D is at a low potential in the 801st stage shift register, the potential Nscan1 of the gate drive signal Nscan1 <801> VGL is output, and the output of a high potential pulse of the gate drive signal Nscan1 is completed.

[0128] The control end of the frequency division control module 20 in the 802nd-stage shift register receives the second control signal Control3, and the potential Nscan_P of the second pull-up node P in the 802nd-stage shift register is <802> When the potential of the second control signal Control3 is low, the frequency division control module 20 is turned on, and the Nscan_P <802> Pull down the potential Nscan_P1 of the first pull-up node P1 in the 802nd stage shift register <802> , the first output stage 10 Figure 7 , Figure 8 The transistor T16 shown or Fig. 9 The transistor T20 shown in FIG. 1 is turned on, and the potential Nscan1 of the gate drive signal Nscan1 is <802> Output VGH; when node D is at a low potential in the 802nd stage shift register, the potential Nscan1 of the gate drive signal Nscan1 <802> VGL is output, and the output of a high potential pulse of the gate drive signal Nscan1 is completed.

[0129] in, Fig.10 The time interval between two adjacent dotted lines shown is 0.5 clock cycles. For example, the duration of stage ① between the first dotted line from left to right and the second dotted line is 0.5 clock cycles, the duration of stage ② between the second dotted line from left to right and the third dotted line is also 0.5 clock cycles, the duration of stage ③ between the third dotted line from left to right and the fourth dotted line is also 0.5 clock cycles, the duration of stage ④ between the fourth dotted line from left to right and the fifth dotted line is also 0.5 clock cycles, the duration of stage ⑤ between the fifth dotted line from left to right and the sixth dotted line is also 0.5 clock cycles, and stage ⑥ after the sixth dotted line is the end period of the pulse output of the gate drive signal Nscan1.

[0130] Among them, 0.5 clock cycle is half a cycle of the first clock signal CK1 / XCK, and can also be half a cycle of the second clock signal CK2 / CK.

[0131] It is understandable that if there is no Figure 4Before the processing of the gate driving circuit shown in the figure, the control end of the frequency division control module 20 in each shift register is connected to the third control signal Control4, then Nscan_P1 <801> The phase will lag behind by 1 clock cycle, then Nscan1 <801> The pulse width will be reduced by 1 clock cycle and become Figure 3 Nscan1 shown in <801> .

[0132] Similarly, if you have not passed Figure 4 Before the processing of the gate driving circuit shown in the figure, the control end of the frequency division control module 20 in each shift register is connected to the third control signal Control4, then Nscan_P1 <802> The phase will lag behind by 0.5 clock cycles, then Nscan1 <801> The pulse width will be reduced by 0.5 clock cycles, becoming Figure 3 Nscan1 shown in <802> .

[0133] It can be seen from this that Figure 4 The gate driving circuit shown can indeed solve the technical problem that the gate driving signal has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display.

[0134] In one embodiment, the present embodiment provides a display panel, and the display panel includes the gate driving circuit in at least one of the above embodiments.

[0135] It can be understood that since the display panel provided in this embodiment includes the gate driving circuit in at least one of the above-mentioned embodiments, it is also possible to connect control signals of different phases to the control end of the frequency division control module 20 in every three or more shift registers cascaded in sequence through different control lines, and the conduction time of the frequency division control module 20 can be controlled to overlap as much as possible with the pulse time of the gate driving signal Nscan1 output by the first output stage 10, so that the gate driving signal Nscan1 can be controlled to have a wider pulse width, and the pulse width of the gate driving signal Nscan1 can be kept unchanged when the refresh frequency is switched, thereby alleviating the situation where the gate driving signal Nscan1 has a narrow pulse width at the initial stage of switching the refresh frequency in the frequency division display.

[0136] Furthermore, each control signal of a different phase can increase the pulse width of the gate driving signal Nscan1 by half a clock cycle, thereby not only being able to more accurately control the pulse width of the gate driving signal Nscan1 but also being able to more flexibly adjust the pulse width of the gate driving signal Nscan1.

[0137] In one embodiment, the display panel further includes Figure 1The pixel circuit shown includes a driving transistor T1, a compensation transistor T3 and a writing transistor T2, wherein a first electrode of the compensation transistor T3 is connected to a gate of the driving transistor T1, a second electrode of the compensation transistor T3 is connected to a first electrode or a second electrode of the driving transistor T1, and a gate of the compensation transistor T3 is connected to a gate driving line; a first electrode of the writing transistor T2 is connected to a first electrode or a second electrode of the driving transistor T1, a second electrode of the writing transistor T2 is connected to a data line, and a gate of the writing transistor T2 is connected to a scanning line.

[0138] It should be noted that, by combining the gate driving circuit in at least one embodiment described above with the pixel circuit, if each gate driving line is connected to the gate of the compensation transistor T3 in a row of pixel circuits, each row of pixel circuits can display at a desired refresh rate.

[0139] In one embodiment, if Figure 1 As shown, the pixel circuit also includes a first light emitting control transistor T5, a first electrode of the first light emitting control transistor T5 is connected to the first power line, a second electrode of the first light emitting control transistor T5 is connected to the first electrode of the driving transistor T1, and a gate of the first light emitting control transistor T5 is connected to the light emitting control line.

[0140] It should be noted that the first power line is used to transmit a positive power signal VDD, and the light emitting control line is used to transmit a light emitting control signal EM.

[0141] In one embodiment, if Figure 1 As shown, the pixel circuit further includes a second light emitting control transistor T6 and a light emitting device D1, wherein the first electrode of the second light emitting control transistor T6 is connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T6 is connected to the anode of the light emitting device D1, and the gate of the second light emitting control transistor T6 is connected to the light emitting control line. The cathode of the light emitting device D1 is connected to the second power line.

[0142] It should be noted that the second power line is used to transmit the negative power signal VSS. The light emitting device D1 may be an organic light emitting diode, a mini light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0143] In one embodiment, if Figure 1 As shown, the pixel circuit further includes a storage capacitor Cst, one end of the storage capacitor Cst is connected to the gate of the driving transistor T1, and the other end of the storage capacitor Cst is connected to the first power line.

[0144] In one embodiment, if Figure 1As shown, the pixel circuit further includes a bootstrap capacitor Cboost, one end of the bootstrap capacitor Cboost is connected to the gate of the driving transistor T1, and the other end of the bootstrap capacitor Cboost is connected to the gate of the writing transistor T2.

[0145] In one embodiment, if Figure 1 As shown, the pixel circuit further includes a first reset transistor T4, a first electrode of the first reset transistor T4 is connected to the gate of the driving transistor T1, a second electrode of the first reset transistor T4 is connected to the first reset line, and a gate of the first reset transistor T4 is connected to the gate driving line.

[0146] It should be noted that the first reset line is used to transmit the first reset signal Vi_G. The gate drive line is used to transmit the gate drive signal Nscan2, which can be the above-mentioned cascade line or other gate drive lines.

[0147] In one embodiment, if Figure 1 As shown, the pixel circuit further includes a second reset transistor T7, a first electrode of the second reset transistor T7 is connected to the anode of the light emitting device D1, a second electrode of the second reset transistor T7 is connected to the second reset line, and a gate of the second reset transistor T7 is connected to the gate drive wiring.

[0148] It should be noted that the second reset line is used to transmit the second reset signal Vi_ANo. The gate drive line is used to transmit the gate drive signal Pscan2.

[0149] In one embodiment, if Figure 1 As shown, the pixel circuit further includes a third reset transistor T8, a first electrode of the third reset transistor T8 is connected to the first electrode of the driving transistor T1, a second electrode of the third reset transistor T8 is connected to the third reset line, and a gate of the third reset transistor T8 is connected to the gate driving wiring.

[0150] It should be noted that the third reset line is used to transmit the third reset signal Vi3.

[0151] Now combined Fig.11 The process of frequency division or split-screen display of the above display panel is described, taking 120Hz as the highest refresh frequency, 60Hz refresh frequency for the upper 1 / 3 screen, 120Hz refresh frequency for the middle 1 / 3 screen, and 30Hz refresh frequency for the lower 1 / 3 screen as an example, wherein a frame of 60Hz refresh frequency can be divided into two frames of 120Hz refresh frequency, and a frame of 30Hz refresh frequency can be divided into four frames of 120Hz refresh frequency, as follows:

[0152] In the first frame with a refresh rate of 120 Hz, the control signals Control2 / 3 / 4 connected to the shift registers corresponding to the upper 1 / 3 screen, the middle 1 / 3 screen, and the lower 1 / 3 screen are all at a low potential L, all the frequency division control modules 20 are turned on, and all the gate drive signals Nscan <1> ...Nscan <801> ...Nscan <1601> Output the corresponding pulses in sequence, and at the same time, the scanning signal Pscan <1> ...Pscan <801> ...Pscan <1601> The corresponding pulses are also output in sequence to control the data signal Data to be written into the gate of the driving transistor T1 in each pixel circuit.

[0153] In the second frame with a refresh rate of 120 Hz, the control signals Control2 / 3 / 4 connected to the shift registers corresponding to the upper 1 / 3 screen and the lower 1 / 3 screen are all at a high potential H, the frequency division control modules 20 of the shift registers in the upper 1 / 3 screen and the lower 1 / 3 screen are all turned off, and the gate drive signal Nscan <1> ...Nscan <800> 、Nscan <1601> ...stop outputting the corresponding pulses, and at the same time, the scanning signal Pscan <1> ...Pscan <801> ...Pscan <1601> The corresponding pulses are still output in sequence to control the data signal Data to be written into the source and / or drain of the driving transistor T1 in each pixel circuit.

[0154] The control signals Control2 / 3 / 4 connected to the shift register corresponding to the middle 1 / 3 screen are all at low potential L, the frequency division control module 20 of the shift register in the middle 1 / 3 screen is turned on, and the gate drive signal Nscan <801> ...Nscan <1600> Output the corresponding pulses in sequence, and at the same time, the scanning signal Pscan <801> ...Pscan <1600> The corresponding pulses are also output in sequence to control the data signal Data to be written into the gate of the driving transistor T1 in each pixel circuit.

[0155] In the third frame with a refresh rate of 120 Hz, the upper 1 / 3 of the screen maintains its state in the first frame with a refresh rate of 120 Hz, the middle 1 / 3 of the screen also maintains its state in the first frame with a refresh rate of 120 Hz, and the lower 1 / 3 of the screen maintains its state in the second frame with a refresh rate of 120 Hz.

[0156] In the fourth frame with a refresh rate of 120 Hz, the upper 1 / 3 of the screen maintains its state in the second frame with a refresh rate of 120 Hz, the middle 1 / 3 of the screen maintains its state in the first frame with a refresh rate of 120 Hz, and the lower 1 / 3 of the screen maintains its state in the second frame with a refresh rate of 120 Hz.

[0157] At this point, the upper 1 / 3 screen has completed a 60Hz refresh rate frame in the first 120Hz refresh rate frame and the second 120Hz refresh rate frame, and the upper 1 / 3 screen has also completed a 60Hz refresh rate frame in the third 120Hz refresh rate frame and the fourth 120Hz refresh rate frame.

[0158] The middle 1 / 3 screen completes a frame with a refresh rate of 120 Hz in any of the first frame with a refresh rate of 120 Hz, the second frame with a refresh rate of 120 Hz, the third frame with a refresh rate of 120 Hz, and the fourth frame with a refresh rate of 120 Hz.

[0159] The lower 1 / 3 screen completes a 30 Hz refresh rate frame in four frames, namely, the first 120 Hz refresh rate frame, the second 120 Hz refresh rate frame, the third 120 Hz refresh rate frame, and the fourth 120 Hz refresh rate frame.

[0160] From the above analysis, it can be seen that the above split-screen technology can be implemented through a complete gate drive circuit, which can reduce costs compared to implementing the upper 1 / 3 screen, the middle 1 / 3 screen, and the lower 1 / 3 screen through a gate drive circuit respectively.

[0161] In particular, when the above-mentioned display panel is used as a folding screen, one or two of the upper 1 / 3 screen, the middle 1 / 3 screen, and the lower 1 / 3 screen can be used as the main screen, and the other one or two of the upper 1 / 3 screen, the middle 1 / 3 screen, and the lower 1 / 3 screen can be used as the sub-screen.

[0162] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0163] The gate drive circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit includes one or more shift register groups, each of which includes N adjacent shift registers that output in sequence, where N is an integer greater than or equal to 3, and each of which includes: A first output stage, the first output stage is used to output a gate drive signal; A frequency division control module, the frequency division control module is used to control the output of the gate drive signal according to the refresh frequency; The control terminals of the frequency division control modules in each of the shift register groups are respectively connected to control signals with different phases and the same frequency, so as to adjust the pulse width of the gate driving signal and maintain the same pulse width at different refresh frequencies.

2. The gate driving circuit according to claim 1, characterized in that: The shift register group includes a first shift register, a second shift register and a third shift register which output gate drive signals with phases lagging in sequence; The control signal includes a first control signal, a second control signal and a third control signal, the frequency of the first control signal, the frequency of the second control signal and the frequency of the third control signal are the same, and the phase of the first control signal, the phase of the second control signal and the phase of the third control signal lag in sequence; In each of the shift register groups, the control end of the frequency division control module in the first shift register is connected to the first control signal, the control end of the frequency division control module in the second shift register is connected to the second control signal, and the control end of the frequency division control module in the third shift register is connected to the third control signal.

3. The gate driving circuit according to claim 2, characterized in that: There is an interval time length between the pulse start edge of the first control signal and the pulse start edge of the second control signal, and there is the interval time length between the pulse start edge of the second control signal and the pulse start edge of the third control signal.

4. The gate driving circuit according to claim 3, characterized in that: The pulse width of the gate driving signal is the product of N and the interval time length.

5. The gate driving circuit according to claim 3, characterized in that: The first shift register outputs a first gate driving signal, the second shift register outputs a second gate driving signal, and the third shift register outputs a third gate driving signal; There is the interval duration between the pulse start edge of the first gate driving signal and the pulse start edge of the second gate driving signal, and there is the interval duration between the pulse start edge of the second gate driving signal and the pulse start edge of the third gate driving signal.

6. The gate driving circuit according to claim 5, characterized in that: The pulse start edge of the first control signal is at the same time as the pulse start edge of the first gate drive signal, the pulse start edge of the second control signal is at the same time as the pulse start edge of the second gate drive signal, and the pulse start edge of the third control signal is at the same time as the pulse start edge of the third gate drive signal.

7. The gate drive circuit according to any one of claims 1 to 6, characterized in that: Each of the control signals is transmitted via a control line, and the control lines include a first control line, a second control line, and a third control line; Each of the shift register groups includes a first shift register, a second shift register and a third shift register that output gate drive signals with sequentially lagging phases; The first control line is connected to the control end of the frequency division control module of the first shift register in each of the shift register groups, the second control line is connected to the control end of the frequency division control module of the second shift register in each of the shift register groups, and the third control line is connected to the control end of the frequency division control module of the third shift register in each of the shift register groups.

8. The gate driving circuit according to claim 7, characterized in that: The control line further includes a fourth control line, and the shift register group further includes a fourth shift register. The fourth control line is connected to the control end of the frequency division control module of the fourth shift register in each of the shift register groups.

9. The gate driving circuit according to claim 8, characterized in that: The first control line, the second control line, the third control line, and the fourth control line transmit a first control signal, a second control signal, a third control signal, and a fourth control signal respectively in sequence, the frequency of the first control signal, the frequency of the second control signal, the frequency of the third control signal, and the frequency of the fourth control signal are all the same, and the phase of the first control signal, the phase of the second control signal, the phase of the third control signal, and the phase of the fourth control signal lag behind in sequence.

10. The gate driving circuit according to claim 1, characterized in that: The gate driving circuit further includes a signal generating module, which includes N cascaded signal generating units, and the N signal generating units generate N control signals with different phases and the same frequency according to an initial control signal.

11. The gate driving circuit according to claim 10, characterized in that: The N signal generating units include a first signal generating unit, a second signal generating unit and a third signal generating unit. The first signal generating unit generates a first control signal according to the initial control signal, the second signal generating unit generates a second control signal according to the first control signal, and the third signal generating unit generates a third control signal according to the second control signal.

12. A display panel, characterized in that: The display panel comprises: The gate drive circuit according to any one of claims 1 to 11; A pixel circuit, the pixel circuit comprising a driving transistor, a compensation transistor and a writing transistor, wherein the first electrode of the compensation transistor is connected to the gate of the driving transistor, the second electrode of the compensation transistor is connected to the first electrode or the second electrode of the driving transistor, and the gate of the compensation transistor is connected to the gate driving signal; the first electrode of the writing transistor is connected to the first electrode or the second electrode of the driving transistor, the second electrode of the writing transistor is connected to the data line, and the gate of the writing transistor is connected to the scanning line.

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