Chip packaging wire bonding compensation method and structure

Abstract

The present invention provides a chip packaging wire bonding compensation method and structure, in the field of chip packaging technology, wire bonding includes using bonding wires to establish an electrical connection between a chip and a packaging substrate, and the method includes: segmenting a signal link formed by chip packaging wire bonding, defining each segmented signal link as a sub-signal link; obtaining the characteristic impedance of the signal link; measuring the inductance value of the sub-signal link where the wire bonding position is located; setting a compensation capacitor to compensate for the inductance effect caused by the wire bonding; wherein, according to the design principle that the impedance value of each sub-signal link is equal to the characteristic impedance, the inductance value of the sub-signal link where the wire bonding position is located is used to calculate the compensation capacitance value required for the sub-signal link where the wire bonding position is located. The present invention uses a compensation capacitor to compensate for the inductance effect generated by wire bonding, thereby improving signal integrity and system stability, while improving system performance.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging wire bonding compensation method and structure. Background Art

[0002] Chip packaging refers to connecting the contacts on the chip to the pins of the package shell with wires, and these pins are connected to other devices through wires on the printed circuit board. Traditional chip packaging generally uses the process of wire bonding (also known as wire bonding) to connect the chip and the substrate. Specifically, wire bonding is one of the important processes in the integrated circuit packaging industry and one of the most widely used chip connection technologies. It uses metal wires (such as gold, aluminum, copper or silver wires) to establish electrical connections between the chip and the substrate, thereby achieving electrical interconnection between the chip and the external circuit.

[0003] At present, the application of wire bonding technology has gradually become perfect. However, after some chips, especially memory chips, are packaged using wire bonding technology, the speed of the memory chips will decrease to a certain extent. Research has found that one of the factors affecting this speed drop is the inductance effect generated by the wire bonding process. Therefore, a stable and reliable method is urgently needed to eliminate the influence of the inductance effect, that is, to compensate for this inductance effect. If the inductance effect caused by wire bonding is not properly compensated, signal reflection will occur, thereby affecting signal integrity, and then affecting the operating stability and speed of the system. Summary of the invention

[0004] The present invention aims to at least solve the technical problem in the prior art that the inductance effect generated by wire bonding affects the operating stability and speed of the system.

[0005] To this end, a first aspect of the present invention provides a chip packaging wire bonding compensation method.

[0006] A second aspect of the present invention provides a chip packaging wire bonding compensation structure.

[0007] The present invention provides a chip packaging wire bonding compensation method, wherein the wire bonding includes using bonding wires to establish an electrical connection between the chip and the packaging substrate, and is characterized in that it includes:

[0008] The signal link formed by the chip packaging wire bonding is divided into sections, and each section of the divided signal link is defined as a sub-signal link, and the length of each sub-signal link is equal;

[0009] Obtain the characteristic impedance of the signal link;

[0010] Measuring the inductance value of the sub-signal link where the wire bonding position is located;

[0011] A compensation capacitor is set to compensate for the inductance effect caused by wire bonding; wherein, according to the design principle that the impedance value of each sub-signal link is equal to the characteristic impedance, the inductance value of the sub-signal link where the wire bonding position is located is used to calculate the compensation capacitance value required for the sub-signal link where the wire bonding position is located, and a compensation capacitor equal to the compensation capacitance value is set at the wire bonding position.

[0012] The chip packaging wire bonding compensation method according to the above technical solution of the present invention may also have the following additional technical features:

[0013] In the above technical solution, the package substrate includes a first connection layer and a second connection layer, the chip is connected to the metal line on the first connection layer through a bonding wire, and there is a gap between the second connection layer and the first connection layer;

[0014] The compensation capacitor is provided, comprising:

[0015] A metal sheet is arranged at a position corresponding to the wire bonding position on the second connection layer and the first connection layer, and a compensation capacitor is formed between the metal sheet and the metal line at the wire bonding position on the first connection layer.

[0016] In the above technical solution, the method for calculating the compensation capacitance value includes:

[0017]

[0018] in, Indicates the compensation capacitance value; Indicates the characteristic impedance of the signal link; Indicates the inductance value of the sub-signal chain where the wire bonding location is located.

[0019] In the above technical solution, the compensation capacitor is used to compensate the inductance effect caused by wire bonding with the compensation capacitance value obtained according to the dielectric constant of the packaging substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet;

[0020] The dielectric constant of the package substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet and the compensation capacitance value satisfy the following relationship:

[0021]

[0022] in, Indicates the compensation capacitance value; Represents the dielectric constant of the package substrate; Represents the area of ​​the metal sheet; Represents the gap height between the first connection layer and the second connection layer.

[0023] In the above technical solution, the compensation capacitor having a value equal to the compensation capacitance is provided at the wire bonding position, comprising:

[0024] According to the determined dielectric constant of the package substrate and the gap height between the first connection layer and the second connection layer, a suitable metal sheet area is selected so that the capacitance value of the compensation capacitor is equal to the calculated compensation capacitance value.

[0025] In the above technical solution, the metal sheet is completely arranged on the second connection layer in a region opposite to the sub-signal link where the wire bonding position is located.

[0026] In the above technical solution, the signal link formed by chip packaging wire bonding is segmented, including:

[0027] The length of each sub-signal link is determined according to the rise time or fall time of the signal transmitted by the signal link.

[0028] In the above technical solution, determining the length of each sub-signal link according to the rise time or fall time of the signal transmitted by the signal link includes:

[0029] Take half of the rise time or fall time of the signal as the average window travel time;

[0030] The average window length, that is, the length of each sub-signal link, is calculated based on the average window travel time and the signal transmission rate.

[0031] A chip packaging wire bonding compensation structure provided by the present invention is formed by applying the chip packaging wire bonding compensation method described in any one of the above technical solutions;

[0032] The chip package wire bonding compensation structure comprises:

[0033] A packaging substrate, the packaging substrate comprising a first connection layer and a second connection layer arranged in parallel, with a gap being provided between the first connection layer and the second connection layer;

[0034] A chip electrically connected to the first connection layer by bonding wires;

[0035] A metal sheet is provided at a position on the second connection layer corresponding to the bonding point between the bonding wire and the first connection layer; the metal sheet and the bonding point form a compensation capacitor, and the compensation capacitor is used to compensate for the inductance effect caused by wire bonding.

[0036] In the above technical solution, the second connection layer is provided with BGA solder balls.

[0037] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are:

[0038] The present invention proposes a chip packaging wire bonding compensation method and structure, which utilizes a compensation capacitor to compensate for the inductance effect generated by the wire bonding, thereby improving signal integrity and system stability, while also enhancing system performance.

[0039] At the same time, the setting of the compensation capacitor is combined with the chip packaging structure, and there is no need to change the layout. A metal sheet of appropriate area can be set on the basis of the original substrate, which does not affect the system volume. In addition, the present application ensures the effectiveness of compensation by limiting the position of the metal sheet, so that the compensated sub-signal chain maintains impedance matching with other sub-signal chains.

[0040] Additional aspects and advantages of the present invention will become apparent from the following description or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0042] Figure 1 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0043] Figure 2 is a flow chart of a chip packaging wire bonding compensation method according to an embodiment of the present invention;

[0044] Figure 3 is an equivalent circuit diagram of a signal link without wire bonding;

[0045] Figure 4 is an equivalent circuit diagram of a signal link with wire bonding in a chip packaging wire bonding compensation method according to an embodiment of the present invention;

[0046] Figure 5 It is a schematic diagram of the arrangement principle of the compensation capacitor in the chip packaging wire bonding compensation method according to one embodiment of the present invention;

[0047] Figure 6 It is a design principle diagram of a compensation capacitor in a chip packaging wire bonding compensation method according to an embodiment of the present invention.

[0048] in, Figures 1 to 6 The corresponding relationship between the reference numerals and the component names is as follows:

[0049] 1. Chip; 2. Package substrate; 3. Bonding wire; 4. Compensation capacitor;

[0050] 21. first connection layer; 22. second connection layer;

[0051] 41. Metal sheet. DETAILED DESCRIPTION

[0052] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0053] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0054] Refer to the following Figures 1 to 6 The chip package wire bonding compensation method and structure provided according to some embodiments of the present invention are described.

[0055] Some embodiments of the present application provide a chip package wire bonding compensation method. Figure 1 A conventional chip packaging structure using a wire bonding process is shown, wherein the wire bonding is to establish an electrical connection between the chip and the packaging substrate using bonding wires. It can be understood that the packaging substrate has a metal circuit, and the bonding pins on the chip are connected to the metal circuit through bonding wires and are connected to the outside or a specified position; the connection position between the bonding wire and the metal circuit is the wire bonding position, and the link between the bonding pin and the connection end point is the signal link formed by the wire bonding.

[0056] like Figure 2 As shown, the first embodiment of the present invention provides a chip packaging wire bonding compensation method, including the following steps S1-S4.

[0057] S1. Divide the signal link formed by chip packaging wire bonding into sections, and define each section of the divided signal link as a sub-signal link, and the length of each sub-signal link is equal.

[0058] By dividing the signal link into sections in the length direction, the consistency of the signal link can be guaranteed as long as the impedance matching of each section is ensured. At the same time, it is only necessary to identify and compensate for the inductance effect of the sub-signal link where the wire bonding position is located.

[0059] S2. Obtain the characteristic impedance of the signal link.

[0060] It is understandable that characteristic impedance is also called "characteristic impedance". It is not DC resistance, but a concept in long-distance transmission. In the high-frequency range, when the signal reaches the place along the signal line, an instantaneous current will be generated due to the establishment of an electric field between the signal line and the reference plane (power supply or ground plane). If the transmission line is isotropic, then as long as the signal is transmitted, there will always be a current I. If the output level of the signal is V, during the signal transmission process, the transmission line will be equivalent to a resistor with a size of V / I. This equivalent resistance is called the characteristic impedance of the transmission line. During the transmission process of a signal, if the impedance on the transmission path changes, the signal will be reflected at the node where the impedance is discontinuous.

[0061] Typically, the characteristic impedance can be obtained by calculating the output level and current in the above signal chain, or by directly measuring it, or by directly reading the calibrated parameters.

[0062] Figure 3 The equivalent circuit of the signal link without wire bonding is shown. As shown in the figure, after the signal link is divided into sections, the impedance of each sub-signal link is expressed by , ,..., To indicate that the impedance of each sub-signal link is equal and satisfies:

[0063]

[0064] in, , Indicates the total number of sections divided. represents the impedance of the nth sub-signal link, represents the equivalent inductance of the nth sub-signal link, Represents the equivalent capacitance of the nth sub-signal link.

[0065] S3. Measure the inductance value of the sub-signal link where the wire bonding position is located.

[0066] Figure 4 The equivalent circuit diagram of the signal link with wire bonding in the present disclosure is shown. After the signal link is divided into sections, the impedance of each sub-signal link is expressed as , ,..., To express, represents the equivalent inductance of the nth sub-signal link, represents the equivalent capacitance of the nth sub-signal link. In this embodiment, The impedance value of the sub-signal link where the wire bonding position is located is shown as an example. It can be seen that at the sub-signal link where the wire bonding position is located, the impedance of this section is The change is mainly caused by the inductance effect, that is, the equivalent inductance value of the signal link in this node The change information is obtained through step S3. It should be noted that the method for measuring the inductance value of a certain link section is well known to those skilled in the art, and the specific value of this parameter can be obtained by measurement, such as using a TDR (time domain reflectometry) measuring instrument, or by simulation.

[0067] S4. Setting a compensation capacitor to compensate for the inductance effect caused by wire bonding; wherein, according to the design principle that the impedance value of each sub-signal link is equal to the characteristic impedance, the inductance value of the sub-signal link where the wire bonding position is located is used to calculate the compensation capacitance value required for the sub-signal link where the wire bonding position is located, and a compensation capacitor equal to the compensation capacitance value is set at the wire bonding position.

[0068] Specifically, in the circuit system, the reflection coefficient of the nth sub-signal link is The calculation method is as follows:

[0069]

[0070] If the impedance of the sub-signal link is not equal to the characteristic impedance, signal reflection will occur in this section because , resulting in a reflection coefficient is not equal to zero, so it is necessary to maintain , to avoid signal reflection.

[0071] Based on the above design principles, by adding a certain amount of supplementary capacitance to the sub-signal link with impedance mismatch, the impedance of the sub-signal link can be made equal to the characteristic impedance, and the reflection coefficient can be kept at 0.

[0072] In a specific embodiment, the compensation capacitance value can be calculated according to the characteristic impedance obtained in step S2 and step S3, the inductance value of the sub-signal link where the wire bonding position is located, and the design principle. The calculation method is as follows:

[0073]

[0074] in, Indicates the compensation capacitance value; Indicates the characteristic impedance of the signal link; Indicates the inductance value of the sub-signal chain where the wire bonding location is located.

[0075] There are many ways to set the compensation capacitor. In the present disclosure, in order to improve the convenience and ease of operation of compensation and ensure that the set compensation capacitor does not affect the package volume, the following method is used to design the compensation capacitor.

[0076] like Figure 5 As shown, the packaging substrate includes a first connection layer and a second connection layer, the chip is connected to the metal line on the first connection layer through bonding wires, and there is a gap between the second connection layer and the first connection layer; a metal sheet is arranged at a position corresponding to the wire bonding position on the second connection layer and the first connection layer, and a compensation capacitor is formed between the metal sheet and the metal line at the wire bonding position on the first connection layer.

[0077] It should be noted that the configurations of the first connection layer and the second connection layer are both common packaging substrate properties. In some embodiments, the gap between the first connection layer and the second connection layer can be partially filled with insulating materials, a number of metal lines are provided on the first connection layer, and a number of solder pins are provided on the second connection layer. The number of solder pins can be in the form of BGA (ball grid array) solder balls. The compensation capacitor formed between the metal sheet and the metal line at the wire bonding position on the first connection layer can compensate for the sub-signal chain at the wire bonding position.

[0078] In some embodiments, Figure 6 As shown, according to the dielectric constant of the package substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet, the compensation capacitor is used to compensate the inductance effect caused by the wire bonding with the obtained compensation capacitance value;

[0079] Specifically, the dielectric constant of the package substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet and the compensation capacitance value satisfy the following relationship:

[0080]

[0081] in, Indicates the compensation capacitance value; Represents the dielectric constant of the package substrate; Represents the area of ​​the metal sheet; Represents the gap height between the first connection layer and the second connection layer.

[0082] It is understandable that the compensation capacitance value can be adjusted by adjusting any one of the parameters of the dielectric constant of the packaging substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet.

[0083] In a specific embodiment, in actual application, since the material and geometric structure of the packaging substrate are not easy to modify after being determined, a suitable metal sheet area is selected based on the determined dielectric constant of the packaging substrate and the gap height between the first connection layer and the second connection layer so that the capacitance value of the compensation capacitor is equal to the calculated compensation capacitance value.

[0084] To ensure that the designed compensation capacitor can accurately compensate the specified sub-signal link, the metal sheet is completely arranged in the interval on the second connection layer opposite to the sub-signal link where the wire bonding position is located. That is, the setting interval of the metal sheet is determined according to the delineated sub-signal link range, and when the metal sheet is in the setting interval, it can stably compensate the sub-signal link where the wire bonding position is located.

[0085] In some embodiments, to ensure that the division of each sub-signal link is reasonable, step S1 includes:

[0086] The length of each sub-signal link is determined according to the rise time or fall time of the signal transmitted by the signal link.

[0087] In some embodiments, determining the length of each sub-signal link according to the rise time or fall time of the signal transmitted by the signal link includes:

[0088] Take half of the rise time or fall time of the signal as the average window travel time;

[0089] The average window length, that is, the length of each sub-signal link, is calculated based on the average window travel time and the signal transmission rate.

[0090] It should be noted that the concept of average window is a concept introduced by TDR measuring instruments to measure the impedance value of signal links, that is, the TDR measuring instrument will measure the impedance of the sub-signal link within each average window. In the present disclosure, since the method of obtaining the impedance of the sub-signal link is not unique, the average window travel time only represents the travel time of the signal in each sub-signal link.

[0091] In a specific embodiment, the bit rate of the signal is 2133 Mbps. Assuming that the rise time of the signal is one fifth of the bit period, the average window travel time is 1 / 2133 Mbps*1 / 5*1 / 2=46.8 ps.

[0092] Furthermore, in this embodiment, the packaging substrate adopts FR-4 PCB (a common printed circuit board whose substrate is FR-4 copper clad board). On this board, it takes about 160ps for the signal to transmit a distance of 1 inch. Under the limitation of the average window travel time, the average window length can be obtained to be about 0.3 inches, that is, the length of each sub-signal link is 0.3 inches. Starting from the starting point of the signal link, each 0.3-inch interval is divided into a sub-signal link. The wire bonding position will inevitably fall into one of the sub-signal links. The metal sheet used to compensate for the inductance effect caused by the wire bonding is limited to determine the layout range of the metal sheet by the interval corresponding to the sub-signal link interval on the second connection layer.

[0093] Some other embodiments of the present invention provide a chip packaging wire bonding compensation structure, which is formed by applying the chip packaging wire bonding compensation method described in any of the above embodiments; the chip packaging wire bonding compensation structure includes: a packaging substrate and a chip.

[0094] The packaging substrate includes a first connection layer and a second connection layer arranged in parallel, with a gap between the first connection layer and the second connection layer; the chip is electrically connected to the first connection layer using a bonding wire; a metal sheet is provided at a position on the second connection layer corresponding to the bonding point between the bonding wire and the first connection layer; the metal sheet and the bonding point constitute a compensation capacitor, and the compensation capacitor is used to compensate for the inductance effect caused by wire bonding.

[0095] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0096] Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip packaging wire bonding compensation method, wherein the wire bonding includes using bonding wires to establish an electrical connection between the chip and the packaging substrate, characterized in that: include: The signal link formed by the chip packaging wire bonding is divided into sections, and each section of the divided signal link is defined as a sub-signal link, and the length of each sub-signal link is equal; Obtain the characteristic impedance of the signal link; Measuring the inductance value of the sub-signal link where the wire bonding position is located; A compensation capacitor is provided to compensate for the inductance effect caused by wire bonding; wherein, according to the design principle that the impedance value of each sub-signal link is equal to the characteristic impedance, the inductance value of the sub-signal link where the wire bonding position is located is used to calculate the compensation capacitance value required for the sub-signal link where the wire bonding position is located, and a compensation capacitor equal to the compensation capacitance value is provided at the wire bonding position; The package substrate comprises a first connection layer and a second connection layer, the chip is connected to the metal line on the first connection layer through a bonding wire, and there is a gap between the second connection layer and the first connection layer; The compensation capacitor is provided, comprising: A metal sheet is arranged at a position corresponding to the wire bonding position on the second connection layer and the first connection layer, and a compensation capacitor is formed between the metal sheet and the metal line at the wire bonding position on the first connection layer; The metal sheet is completely arranged in a region on the second connection layer that is opposite to the sub-signal link where the wire bonding position is located.

2. The chip packaging wire bonding compensation method according to claim 1, characterized in that: The calculation method of the compensation capacitance value includes: in, Indicates the compensation capacitance value; Indicates the characteristic impedance of the signal link; Indicates the inductance value of the sub-signal chain where the wire bonding location is located.

3. The chip packaging wire bonding compensation method according to claim 2, characterized in that: According to the dielectric constant of the package substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet, the compensation capacitor compensates the inductance effect caused by the wire bonding with the compensation capacitance value obtained; The dielectric constant of the package substrate, the gap height between the first connection layer and the second connection layer, and the area of ​​the metal sheet and the compensation capacitance value satisfy the following relationship: in, Indicates the compensation capacitance value; Represents the dielectric constant of the package substrate; Indicates the area of ​​the metal sheet; Represents the gap height between the first connection layer and the second connection layer.

4. The chip packaging wire bonding compensation method according to claim 3, characterized in that: The compensation capacitor having a value equal to the compensation capacitance is arranged at the wire bonding position, comprising: According to the determined dielectric constant of the package substrate and the gap height between the first connection layer and the second connection layer, a suitable metal sheet area is selected so that the capacitance value of the compensation capacitor is equal to the calculated compensation capacitance value.

5. The chip packaging wire bonding compensation method according to claim 1, characterized in that: The segmenting of the signal link formed by chip packaging wire bonding includes: The length of each sub-signal link is determined according to the rise time or fall time of the signal transmitted by the signal link.

6. The chip packaging wire bonding compensation method according to claim 5, characterized in that: The determining the length of each sub-signal link according to the rise time or fall time of the signal transmitted by the signal link comprises: Take half of the rise time or fall time of the signal as the average window travel time; The average window length, that is, the length of each sub-signal link, is calculated based on the average window travel time and the signal transmission rate.

7. A chip packaging wire bonding compensation structure, characterized in that: Applying the chip package wire bonding compensation method according to any one of claims 1 to 6 to form the chip package wire bonding compensation structure; The chip package wire bonding compensation structure comprises: A packaging substrate, the packaging substrate comprising a first connection layer and a second connection layer arranged in parallel, with a gap being provided between the first connection layer and the second connection layer; A chip electrically connected to the first connection layer by bonding wires; A metal sheet is provided at a position on the second connection layer corresponding to the bonding point between the bonding wire and the first connection layer; the metal sheet and the bonding point form a compensation capacitor, and the compensation capacitor is used to compensate for the inductance effect caused by wire bonding.

8. The chip package wire bonding compensation structure according to claim 7, characterized in that: The second connection layer is provided with BGA solder balls.

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