Enhanced GaN transistor maintaining stable threshold voltage under irradiation and preparation method thereof

Abstract

The present invention provides an enhanced GaN transistor that maintains a stable threshold voltage under irradiation and a preparation method thereof, belonging to the field of semiconductor technology. The enhanced GaN transistor comprises a substrate layer, a gallium nitride layer and a barrier layer arranged from bottom to top, a p-GaN layer distributed in a strip shape is arranged above the barrier layer, a gate metal layer is arranged above the p-GaN layer, a source and a drain are arranged in parallel and spaced apart on both sides of the p-GaN layer, an ohmic metal layer is arranged in parallel and spaced apart on one side of the p-GaN layer close to the source, and an insulating dielectric layer is filled between the ohmic metal layer and the p-GaN layer. It can solve the technical problems of poor radiation resistance and unstable device threshold voltage caused by hole accumulation in gallium nitride power diodes in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an enhanced GaN transistor that maintains a stable threshold voltage under irradiation and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) have broad application prospects in the field of power electronics due to their advantages such as fast high-frequency response, high power density, and good high-temperature stability. In addition, due to the radiation resistance of GaN materials, power devices have important research and application potential in radiation environments such as spacecraft, satellite communications, space exploration, and nuclear energy facilities.

[0003] In the related art, the existing GaN transistors compatible with p-GaN gate technology are usually provided with a p-GaN layer close to the source side between the source and drain on their epitaxial wafers, which is used to grow a gate metal layer thereon. In a radiation environment, when GaN transistors are irradiated by radiation particles such as neutrons, protons and gamma rays, a large number of electron-hole pairs will be generated inside the device. These additional carriers may accumulate under the drain and gate, causing changes in the threshold voltage of the device, thereby affecting its safe operation. In particular, due to the presence of the p-GaN layer, the dissipation of holes will be further hindered, causing holes to accumulate on the side close to the source. In severe cases, radiation damage will occur in the diode or even device burnout.

[0004] In the device's radiation-resistant design, researchers have tried to improve the device's radiation resistance by changing the passivation layer material and thickness, but this cannot effectively reduce the electron-hole pairs inside the device, and the stability of the device's threshold voltage will still be seriously affected by radiation. Summary of the invention

[0005] The embodiment of the present invention provides an enhanced GaN transistor that maintains a stable threshold voltage under irradiation and a method for manufacturing the same. The technical problem that the GaN power diode in the prior art has poor radiation resistance and unstable device threshold voltage due to hole accumulation after irradiation is solved. The technical solution is as follows:

[0006] In a first aspect, an embodiment of the present invention provides an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation, comprising a substrate layer, a gallium nitride layer, and a barrier layer arranged from bottom to top, a p-GaN layer distributed in a strip shape is arranged above the barrier layer, a gate metal layer is arranged above the p-GaN layer, a source and a drain are arranged in parallel and at intervals on both sides of the p-GaN layer, an ohmic metal layer is arranged in parallel and at intervals on one side of the p-GaN layer close to the source, and an insulating dielectric layer is filled between the ohmic metal layer and the p-GaN layer.

[0007] Optionally, the ohmic metal layer includes a plurality of first ohmic metal layers and a plurality of second ohmic metal layers, the plurality of first ohmic metal layers are arranged at intervals along the extension direction of the p-GaN layer, and each adjacent two first ohmic metal layers are connected via a second ohmic metal layer, and in the extension direction of the p-GaN layer, the width and height of the second ohmic metal layer are both smaller than those of the first ohmic metal layer.

[0008] Optionally, in the extension direction of the p-GaN layer, the contact area between the first ohmic metal layer and the adjacent second ohmic metal layer gradually increases.

[0009] Optionally, in the extension direction of the p-GaN layer, the intervals between the first ohmic metal layers gradually increase.

[0010] Optionally, in the extension direction of the p-GaN layer, the height of the second ohmic metal layer gradually increases.

[0011] Optionally, in the extension direction of the p-GaN layer, the first ohmic metal layer has a length range of 10 to 200 μm, a width range of 5 to 200 μm, and a height range of 100 to 500 nm; the second ohmic metal layer has a length range of 5 to 300 μm, a width range of 5 to 80 μm, and a height range of 50 to 170 nm.

[0012] Optionally, the gate metal layer is disposed above the ohmic metal layer and the p-GaN layer, and the insulating dielectric layer is also filled between the ohmic metal layer and the gate metal layer.

[0013] Optionally, the thickness of the insulating dielectric layer between the ohmic metal layer and the p-GaN layer is in a range of 10 to 100 nm, and the thickness of the insulating dielectric layer between the ohmic metal layer and the gate metal layer is in a range of 20 to 120 nm.

[0014] Optionally, the gate metal layer is in a stepped shape, and the gate metal layer located above the ohmic metal layer is higher than the gate metal layer located above the p-GaN layer.

[0015] In a second aspect, an embodiment of the present invention provides a preparation method for manufacturing an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation as described in the first aspect, comprising:

[0016] Step 1: growing the substrate layer, the gallium nitride layer, the barrier layer and the p-GaN layer from bottom to top on an epitaxial wafer, and growing and etching the p-GaN layer on the barrier layer;

[0017] Step 2: depositing and etching the ohmic metal layer on the epitaxial wafer;

[0018] Step 3: growing and etching the insulating dielectric layer between the p-GaN layer and the ohmic metal layer and on the upper end;

[0019] Step 4: growing and etching the gate metal layer on the insulating dielectric layer and the p-GaN layer;

[0020] Step 5: Etching is performed on the barrier layer on both sides of the p-GaN layer and the source electrode and the drain electrode are deposited.

[0021] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0022] The enhanced GaN transistor that maintains a stable threshold voltage under irradiation provided by the embodiment of the present invention is compared with the traditional p-GaN structure GaN transistor structure in the related art. By adding an ohmic metal layer at the gate structure, that is, at the side of the gate metal layer and the p-GaN layer close to the source, the irradiation-induced carriers near the source can flow out and dissipate outside the transistor using the ohmic metal layer as a discharge channel, thereby avoiding the threshold voltage shift caused by carrier deposition. An insulating dielectric layer is grown between the ohmic metal layer and the p-GaN layer, which can effectively avoid leakage caused by direct contact between the p-GaN layer and the ohmic metal layer. It can effectively solve the technical problems of poor radiation resistance and unstable device threshold voltage of gallium nitride power diodes in the prior art due to hole accumulation after irradiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a schematic diagram of a planar structure of an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation provided in an embodiment of the present invention;

[0025] Figure 2 It is a schematic diagram of the steps of preparing a substrate layer, a gallium nitride layer, a barrier layer and a P-type gallium nitride layer for an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation in an embodiment of the present invention;

[0026] Figure 3 Schematic diagram of the steps of preparing an ohmic metal layer for an enhancement mode GaN transistor that maintains a stable threshold voltage under irradiation in an embodiment of the present invention;

[0027] Figure 4 Schematic diagram of the steps of preparing an insulating dielectric layer for an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation in an embodiment of the present invention;

[0028] Figure 5 It is a schematic diagram of the steps of preparing a gate metal layer of an enhancement mode GaN transistor that maintains a stable threshold voltage under irradiation provided by an embodiment of the present invention;

[0029] Figure 6 is a schematic diagram of the three-dimensional structure of an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation provided in an embodiment of the present invention;

[0030] Figure 7 It is a flow chart of the preparation method provided in an embodiment of the present invention.

[0031] In the figure: 1-substrate layer; 2-gallium nitride layer; 3-barrier layer; 4-p-GaN layer; 5-gate metal layer; 6-source; 7-drain; 8-ohmic metal layer; 9-insulating dielectric layer; 81-first ohmic metal layer; 82-second ohmic metal layer. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0033] Figure 1 is a schematic diagram of a planar structure of an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation provided in an embodiment of the present invention; Figure 2 It is a schematic diagram of the steps of preparing a substrate layer, a gallium nitride layer, a barrier layer and a P-type gallium nitride layer for an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation in an embodiment of the present invention; Figure 3 Schematic diagram of the steps of preparing an ohmic metal layer for an enhancement mode GaN transistor that maintains a stable threshold voltage under irradiation in an embodiment of the present invention; Figure 4 Schematic diagram of the steps of preparing an insulating dielectric layer for an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation in an embodiment of the present invention; Figure 5 It is a schematic diagram of the steps of preparing a gate metal layer of an enhancement mode GaN transistor that maintains a stable threshold voltage under irradiation provided by an embodiment of the present invention; Figure 6 Schematic diagram of the three-dimensional structure of an enhancement mode GaN transistor that maintains a stable threshold voltage under irradiation provided in an embodiment of the present invention. Figures 1 to 6As shown, based on the above defects, an embodiment of the present invention provides an enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation, comprising a substrate layer 1, a gallium nitride layer 2, and a barrier layer 3 arranged from bottom to top. A p-GaN layer 4 distributed in a strip shape is arranged above the barrier layer 3, a gate metal layer 5 is arranged above the p-GaN layer 4, and a source 6 and a drain 7 are arranged in parallel and spaced on both sides of the p-GaN layer 4. An ohmic metal layer 8 is arranged in parallel and spaced on one side of the p-GaN layer 4 close to the source 6, and an insulating dielectric layer 9 is filled between the ohmic metal layer 8 and the p-GaN layer 4.

[0034] In an embodiment of the present invention, when manufacturing the enhancement mode GaN transistor which maintains a stable threshold voltage under irradiation, Figure 2 As shown, first, a substrate layer 1, a gallium nitride layer 2, a barrier layer 3, and a whole layer of p-GaN layer 4 are grown sequentially from bottom to top on the epitaxial wafer. Then, the p-GaN layer 4 in the non-patterned area is etched away by inductively coupled plasma dry etching to obtain the p-GaN layer 4 structure arranged in strips in the embodiment of the present invention.

[0035] Afterwards, refer to Figure 3 , a whole layer of ohmic metal layer 8 is deposited on the epitaxial wafer by plasma enhanced chemical vapor deposition, and the ohmic metal layer 8 in the non-patterned area is removed by inductively coupled plasma dry etching to obtain the ohmic metal layer 8 structure which is also in the shape of a strip as a whole and is arranged in parallel and spaced on one side of the p-GaN layer 4 in the embodiment of the present invention.

[0036] Afterwards, refer to Figure 4 By using plasma enhanced chemical vapor deposition, an insulating dielectric layer 9 is grown between the p-GaN layer 4 and the ohmic metal layer 8 and on the upper end, and by using inductively coupled plasma dry etching, the insulating dielectric layer 9 in the non-patterned area is removed, thereby forming an insulating dielectric layer 9 structure for isolating the p-GaN layer 4 and the ohmic metal layer 8 from direct contact in an embodiment of the present invention.

[0037] Afterwards, refer to Figure 5 A gate metal layer 5 is grown and etched on the insulating dielectric layer 9 and the p-GaN layer 4 to be isolated from the ohmic metal layer 8 and directly contact the p-GaN layer 4 .

[0038] Finally, the barrier layer 3 on both sides of the p-GaN layer 4 is etched, and the source 6 and the drain 7 are deposited by magnetron sputtering, wherein the source 6 is isolated from one side of the p-GaN layer 4 by the ohmic metal layer 8, and the drain 7 is spaced apart from the other side of the p-GaN layer 4, thereby completing the fabrication of the transistor.

[0039] For example, in the embodiment of the present invention, the source electrode 6 and the drain electrode 7 are both prepared into a strip structure parallel to the p-GaN layer 4, and the distance between the gate metal layer 5 and the source electrode 6 is 270 μm.

[0040] The enhanced GaN transistor that maintains a stable threshold voltage under irradiation provided by the embodiment of the present invention is compared with the conventional p-GaN structure GaN transistor structure in the related art. By adding an ohmic metal layer 8 at the gate structure, that is, at the side of the gate metal layer 5 and the p-GaN layer 4 close to the source 6, the irradiation-induced carriers near the source 6 can flow out and dissipate outside the transistor using the ohmic metal layer 8 as a discharge channel, thereby avoiding the threshold voltage shift caused by carrier deposition. An insulating dielectric layer 9 is grown between the ohmic metal layer 8 and the p-GaN layer 4, which can effectively avoid leakage caused by direct contact between the p-GaN layer 4 and the ohmic metal layer 8. It can effectively solve the technical problems of poor radiation resistance and unstable device threshold voltage of gallium nitride power diodes in the prior art due to hole accumulation after irradiation.

[0041] Preferably, the ohmic metal layer 8 includes a plurality of first ohmic metal layers 81 and a plurality of second ohmic metal layers 82, wherein the plurality of first ohmic metal layers 81 are arranged at intervals along the extension direction of the p-GaN layer 4, and two adjacent first ohmic metal layers 81 are connected via a second ohmic metal layer 82, and in the extension direction of the p-GaN layer 4, the width and height of the second ohmic metal layer 82 are both smaller than the first ohmic metal layer 81. Exemplarily, in an embodiment of the present invention, the plurality of first ohmic metal layers 81 are vertical rectangular structures of the same shape and relatively large volume, and are arranged at intervals along the extension direction of the p-GaN layer 4, and a second ohmic metal layer 82 of relatively small volume and arranged in a horizontal rectangular structure is provided between adjacent first ohmic metal layers 81, and two adjacent first ohmic metal layers 81 are connected via the second ohmic metal layer 82. In the extension direction of the p-GaN layer 4, the width and height of the second ohmic metal layer 82 are smaller than the first ohmic metal layer 81, so as to reduce the contact area of ​​the connection position between the first ohmic metal layers 81. This design takes into account that the ohmic metal layer 8 with a uniform cross-sectional area may have a low contact resistance, which may cause leakage in the process of dissipating and outputting carriers. By connecting the first ohmic metal layer 81 with a second ohmic metal layer 82 with a smaller contact surface at intervals, the contact area is reduced to avoid having a high contact resistance at the connection point. Such a design can avoid the problem of excessive leakage of the ohmic metal layer.

[0042] For example, when preparing the ohmic metal layer 8, a first ohmic metal layer 81 is deposited on the epitaxial wafer, and the first ohmic metal layer 81 in the non-patterned area is removed by inductively coupled plasma dry etching, so as to form the spaced arrangement in the embodiment of the present invention. Afterwards, a second ohmic metal layer 82 is deposited between the first ohmic metal layers 81, and the second ohmic metal layer 82 in the non-patterned area is removed by inductively coupled plasma dry etching, so as to form a connection form with a smaller contact area at the connection.

[0043] Optionally, in the extension direction of the p-GaN layer 4, the contact area between the first ohmic metal layer 81 and the adjacent second ohmic metal layer 82 gradually increases. For example, in an embodiment of the present invention, on the basis of using the first ohmic metal layer 81 and the second ohmic metal layer 82 to staggeredly arrange to improve the contact resistance, it is also necessary to avoid excessive contact resistance, which will lead to higher energy loss and power loss. Therefore, in an embodiment of the present invention, the contact area between the first ohmic metal layer 81 and the adjacent second ohmic metal layer 82 is gradually increased, and an equidistantly arranged ohmic metal layer design is formed, so that the device can have both low leakage current and good energy transfer function.

[0044] Specifically, in the embodiment of the present invention, in the extension direction of the p-GaN layer 4, the spacing between the first ohmic metal layers 81 gradually increases, and the height of the second ohmic metal layer 82 gradually increases. Figure 3 As shown, in the device section of the embodiment of the present invention, the number of the first ohmic metal layers 81 is 9, and the number of the second ohmic metal layers 82 is b=8; the first ohmic metal layers 81 above the barrier layer 3 are distributed in strips, the spacing between the first ohmic metal layers 81 is not equal, and the length of the first ohmic metal layer 81 in the extension direction of the p-GaN layer 4 is 100μm; the second ohmic metal layer 82 is used to connect the first ohmic metal layer 81, and the length of the second ohmic metal layer 82 in the extension direction of the p-GaN layer 4 is 60μm, 75μm, 90μm, 105μm, 120μm, 135μm, 150μm and 165μm respectively.

[0045] The width of the first ohmic metal layer 81 in the extension direction of the p-GaN layer 4 is 100 μm; the width of the second ohmic metal layer 82 in the extension direction of the p-GaN layer 4 is 60 μm.

[0046] The height of the first ohmic metal layer 81 is 180 nm; the height of the second ohmic metal layer 82 is 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm and 65 nm respectively.

[0047] The finally formed ohmic metal layer 8 has a total length of 1800 μm in the extending direction of the p-GaN layer 4 , a maximum width of 100 μm, and a maximum height of 180 nm.

[0048] Preferably, in the extension direction of the p-GaN layer 4, the length of the first ohmic metal layer 81 is in the range of 10 to 200 μm, the width is in the range of 5 to 200 μm, and the height is in the range of 100 to 500 nm; the length of the second ohmic metal layer 82 is in the range of 5 to 300 μm, the width is in the range of 5 to 80 μm, and the height is in the range of 50 to 170 nm. According to the applicable requirements of transistors of different specifications, the actual size of the ohmic metal layer 8 can be adaptively changed within the above range, which will not be elaborated in the embodiment of the present invention.

[0049] Preferably, a gate metal layer 5 is disposed above the ohmic metal layer 8 and the p-GaN layer 4, and an insulating dielectric layer 9 is also filled between the ohmic metal layer 8 and the gate metal layer 5. By way of example, in an embodiment of the present invention, after the growth and etching of the insulating dielectric layer 9, the section above the ohmic metal layer 8 retains a certain thickness without being completely etched, and the profile of the insulating dielectric layer 9 in the extension direction of the p-GaN layer 4 is bent at a right angle as a whole. In the process of further growing and etching the gate metal layer 5, the area above the ohmic metal layer 8 can also be used as an additional growth area for the gate metal layer 5, thereby ensuring the width dimension setting requirements of the gate metal layer 5 in the transistor structure and improving transistor performance.

[0050] For example, in the embodiment of the present invention, the insulating dielectric layer 9 between the ohmic metal layer 8 and the p-GaN layer 4 has a thickness of 50 nm, a length of 1800 μm in the extension direction of the p-GaN layer 4, and a growth height of 220 nm. The thickness of the insulating dielectric layer 9 between the ohmic metal layer 8 and the gate metal layer 5 is also 50 nm to achieve complete isolation of the ohmic metal layer 8 from the upper gate metal layer 5 to avoid and reduce gate leakage current.

[0051] Optionally, the gate metal layer 5 is in a stepped shape, and the height of the gate metal layer 5 located above the ohmic metal layer 8 is higher than the gate metal layer 5 located above the p-GaN layer 4. Exemplarily, in the embodiment of the present invention, when etching the gate metal layer 5, by etching the gate metal layer 5 on the side above the p-GaN layer 4 deeper, a stepped distribution is achieved on the basis of ensuring that its thickness is the same as the thickness on the side above the ohmic metal layer 8, so that when the gate is later led out to the non-graphic area, when it is used as a control electrode and other structures are prepared, the staff can distinguish the positions of the ohmic metal layer 8 and the p-GaN layer 4 below according to their structures, thereby avoiding mistakes in subsequent manufacturing processes and improving practicality.

[0052] Figure 7Schematic diagram of the preparation method provided in the embodiment of the present invention. Figure 7 As shown, the embodiment of the present invention also provides a preparation method for preparing Figures 1 to 6 The enhanced GaN transistor shown maintains a stable threshold voltage under irradiation, and the method comprises the following steps:

[0053] S1: The epitaxial wafer grows a substrate layer 1, a gallium nitride layer 2, a barrier layer 3 and a p-GaN layer 4 from bottom to top, and grows and etches a p-GaN layer 4 on the barrier layer 3.

[0054] Specifically, a substrate layer 1, a gallium nitride layer 2, a barrier layer 3, and a whole p-GaN layer 4 are first grown on the epitaxial wafer from bottom to top. Then, the p-GaN layer 4 in the non-patterned area is etched away using an inductively coupled plasma dry etching method to obtain a p-GaN layer 4 structure arranged in strips in the embodiment of the present invention.

[0055] S2: Depositing and etching an ohmic metal layer 8 on the epitaxial wafer.

[0056] Specifically, a whole layer of the ohmic metal layer 8 is deposited on the epitaxial wafer by plasma enhanced chemical vapor deposition, and the ohmic metal layer 8 in the non-patterned area is removed by inductively coupled plasma dry etching to obtain the ohmic metal layer 8 structure which is also in the shape of a strip as a whole and is arranged in parallel and spaced apart on one side of the p-GaN layer 4 in the embodiment of the present invention.

[0057] S3: growing and etching an insulating dielectric layer 9 between the p-GaN layer 4 and the ohmic metal layer 8 and on the upper end.

[0058] Specifically, an insulating dielectric layer 9 is grown between and on the upper end of the p-GaN layer 4 and the ohmic metal layer 8 by using plasma enhanced chemical vapor deposition, and the insulating dielectric layer 9 in the non-graphic area is removed by inductively coupled plasma dry etching, thereby forming an insulating dielectric layer 9 structure for isolating the p-GaN layer 4 and the ohmic metal layer 8 to avoid direct contact in an embodiment of the present invention.

[0059] S4: growing and etching a gate metal layer 5 on the insulating dielectric layer 9 and the p-GaN layer 4 .

[0060] Specifically, a gate metal layer 5 is grown and etched on the insulating dielectric layer 9 and the p-GaN layer 4 , which is isolated from the ohmic metal layer 8 and directly contacts the p-GaN layer 4 .

[0061] S5: etching the barrier layer 3 on both sides of the p-GaN layer 4 and depositing a source electrode 6 and a drain electrode 7 .

[0062] Specifically, the barrier layer 3 on both sides of the p-GaN layer 4 is etched, and the source 6 and the drain 7 are deposited by magnetron sputtering, wherein the source 6 is isolated from one side of the p-GaN layer 4 by the ohmic metal layer 8, and the drain 7 is spaced apart from the other side of the p-GaN layer 4, thereby completing the fabrication of the transistor.

[0063] The enhanced GaN transistor that maintains a stable threshold voltage under irradiation obtained by the above-mentioned preparation method is compared with the traditional p-GaN structure GaN transistor structure in the related art. By adding an ohmic metal layer 8 at the gate structure, that is, at the side of the gate metal layer 5 and the p-GaN layer 4 close to the source 6, the irradiation-induced carriers near the source 6 can flow out and dissipate to the outside of the transistor using the ohmic metal layer 8 as a discharge channel, thereby avoiding the threshold voltage shift caused by carrier deposition. An insulating dielectric layer 9 is grown between the ohmic metal layer 8 and the p-GaN layer 4, which can effectively avoid leakage caused by direct contact between the p-GaN layer 4 and the ohmic metal layer 8. It can effectively solve the technical problems of poor radiation resistance and unstable device threshold voltage of gallium nitride power diodes in the prior art due to hole accumulation after irradiation.

[0064] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar words used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0065] The above descriptions are merely optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation, characterized in that: The invention comprises a substrate layer (1), a gallium nitride layer (2) and a barrier layer (3) arranged from bottom to top, a p-GaN layer (4) distributed in a strip shape is arranged above the barrier layer (3), a gate metal layer (5) is arranged above the p-GaN layer (4), a source electrode (6) and a drain electrode (7) are arranged in parallel and spaced apart on both sides of the p-GaN layer (4), an ohmic metal layer (8) is arranged in parallel and spaced apart on one side of the p-GaN layer (4) close to the source electrode (6), and a gap is filled between the ohmic metal layer (8) and the p-GaN layer (4). The ohmic metal layer (8) is filled with an insulating dielectric layer (9), the ohmic metal layer (8) comprising a plurality of first ohmic metal layers (81) and a plurality of second ohmic metal layers (82), the plurality of first ohmic metal layers (81) being arranged at intervals along the extension direction of the p-GaN layer (4), two adjacent first ohmic metal layers (81) being connected via a second ohmic metal layer (82), and in the extension direction of the p-GaN layer (4), the width and height of the second ohmic metal layer (82) are both smaller than those of the first ohmic metal layer (81).

2. The enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation according to claim 1, characterized in that: In the extension direction of the p-GaN layer (4), the contact area between the first ohmic metal layer (81) and the adjacent second ohmic metal layer (82) gradually increases.

3. The enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation according to claim 2, characterized in that: In the extension direction of the p-GaN layer (4), the spacing between the first ohmic metal layers (81) gradually increases.

4. The enhancement-mode GaN transistor that maintains a stable threshold voltage under irradiation according to claim 2, characterized in that: In the extension direction of the p-GaN layer (4), the height of the second ohmic metal layer (82) gradually increases.

5. The enhancement-mode GaN transistor capable of maintaining a stable threshold voltage under irradiation according to claim 2, characterized in that: In the extension direction of the p-GaN layer (4), the length of the first ohmic metal layer (81) ranges from 10 to 200 μm, the width ranges from 5 to 200 μm, and the height ranges from 100 to 500 nm; the length of the second ohmic metal layer (82) ranges from 5 to 300 μm, the width ranges from 5 to 80 μm, and the height ranges from 50 to 170 nm.

6. The enhancement-mode GaN transistor capable of maintaining a stable threshold voltage under irradiation according to any one of claims 1 to 5, characterized in that: The gate metal layer (5) is disposed above the ohmic metal layer (8) and the p-GaN layer (4), and the insulating dielectric layer (9) is also filled between the ohmic metal layer (8) and the gate metal layer (5).

7. The enhancement-mode GaN transistor capable of maintaining a stable threshold voltage under irradiation according to claim 6, characterized in that: The thickness of the insulating dielectric layer (9) between the ohmic metal layer (8) and the p-GaN layer (4) is in the range of 10 to 100 nm, and the thickness of the insulating dielectric layer (9) between the ohmic metal layer (8) and the gate metal layer (5) is in the range of 20 to 120 nm.

8. The enhancement-mode GaN transistor capable of maintaining a stable threshold voltage under irradiation according to claim 6, characterized in that: The gate metal layer (5) is in a stepped shape, and the gate metal layer (5) located above the ohmic metal layer (8) is higher than the gate metal layer (5) located above the p-GaN layer (4).

9. A preparation method for manufacturing an enhanced GaN transistor capable of maintaining a stable threshold voltage under irradiation as claimed in any one of claims 1 to 5, characterized in that: include: Step 1: growing the substrate layer (1), the gallium nitride layer (2), the barrier layer (3) and the p-GaN layer (4) on an epitaxial wafer from bottom to top, and growing and etching the p-GaN layer (4) on the barrier layer (3); Step 2: depositing and etching the ohmic metal layer (8) on the epitaxial wafer; Step 3: growing and etching the insulating dielectric layer (9) between the p-GaN layer (4) and the ohmic metal layer (8) and at the upper end; Step 4: growing and etching the gate metal layer (5) on the insulating dielectric layer (9) and the p-GaN layer (4); Step 5: Etching is performed on the barrier layer (3) on both sides of the p-GaN layer (4) to deposit the source electrode (6) and the drain electrode (7).

Images