Distributed circuit for signal pad electrostatic discharge protection

Abstract

An integrated circuit device includes a signal pad, an inductor coupled in series with the signal pad, and an electrostatic discharge (ESD) protection circuit distributed before and after the inductor, the electrostatic discharge (ESD) protection circuit providing ESD protection against ESD events on the signal pad. Other examples are disclosed and claimed.

Description

Background Art

[0001] Electrostatic discharge (ESD) can be harmful to electronic devices. During an ESD event, charge is transferred from one object to another (e.g., from a person to an integrated circuit (IC)). The transferred charge can cause a high current to pass through the IC in a short period of time, potentially damaging the device. Such ESD events can affect the IC throughout its lifetime, including during manufacturing and assembly. Electrostatic discharge (ESD) events that can damage integrated circuits can occur during the manufacturing and assembly of semiconductor devices. ICs can incorporate on-chip ESD protection structures to protect the input, output, and power pins of the IC.

[0002] Improved computing devices are currently needed to meet the growing demand for modeling complex systems, providing reduced computing time and other considerations. In some contexts, the scaling characteristics of ICs have been a driving force for such improvements. Other advances have also been made in materials, device structures, circuit layouts, etc. In particular, it has been desirable to improve ESD protection circuits for, in, or otherwise supporting the operation of ICs. It is precisely because of these and other considerations that the current improvements are needed. As the desire to increase computing efficiency becomes more prevalent, such improvements may become critical. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The materials described herein are illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals are repeated in the drawings where deemed appropriate to indicate corresponding or similar elements, e.g., having the same or similar functions. The present disclosure will be described with additional specificity and detail through the use of the accompanying drawings:

[0004] Figure 1 A block diagram of an example integrated circuit (IC) device including a distributed electrostatic discharge (ESD) network is illustrated;

[0005] Figure 2 illustrates a block diagram of another example IC device including a distributed ESD network;

[0006] Figure 3 A schematic diagram illustrating an example of an interface circuit including a distributed low capacitance ESD (LC-ESD) protection circuit;

[0007] Figure 4 A schematic diagram illustrating another example of an interface circuit including a distributed LC-ESD protection circuit;

[0008] Figure 5A block diagram of a system including a transceiver having a distributed LC-ESD protection circuit is illustrated;

[0009] Figure 6 A diagram illustrating an example data server machine employing an IC device having a distributed LC-ESD protection circuit; and

[0010] Figure 7 is a block diagram of an example computing device, all in accordance with at least some implementations of the present disclosure. DETAILED DESCRIPTION

[0011] In the following detailed description, reference is made to the accompanying drawings, which show, by way of illustration, specific examples in which the claimed subject matter may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various examples, while different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in conjunction with one example may be implemented in other examples without departing from the spirit and scope of the claimed subject matter.

[0012] References in this specification to "one example" or "an example" mean that the particular features, structures, or characteristics described in conjunction with the example are included in at least one implementation contained in this specification. Therefore, the use of the phrase "one example" or "in an example" does not necessarily refer to the same example. In addition, the position or arrangement of the various elements within each disclosed example may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be taken as limiting, and the scope of the subject matter is defined solely by the appended claims and the full scope of equivalents to which the appended claims are entitled, and is to be appropriately interpreted.

[0013] As used herein, the terms "on", "to", "between", and "over" may refer to the relative position of one layer with respect to other layers. A layer "on" or "on" another layer, or joined "to" another layer, may be in direct contact with the other layer, or may have one or more intervening layers. A layer "between" layers may be in direct contact with the layers, or may have one or more intervening layers.

[0014] The terms "coupled" and "connected" and their derivatives may be used herein to describe structural relationships between components. It is not intended that these terms are synonymous with each other. On the contrary, in particular examples, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intervening elements), and / or that two or more elements cooperate or interact with each other (e.g., causal relationship, electrical relationship, functional relationship, etc.).

[0015] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired functionality. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include the plural. The meaning of "in..." includes "in" and "on".

[0016] The vertical direction is in the z-direction, and the references "top", "bottom", "above", and "below" refer to relative positions in the z-dimension and have their usual meanings. However, the examples are not necessarily limited to the orientations or configurations illustrated in the figures. The term "aligned" (i.e., vertically or laterally) indicates that at least a portion of the components are aligned in the relevant direction, while "fully aligned" indicates that all components are aligned in the relevant direction.

[0017] The terms "substantially," "close," "approximately," "near," and "about" generally mean within + / - 10% of a target value (unless expressly specified). The term "predominantly" means more than 50% or more than half, unless otherwise specified in the specific context of use. For example, a composition that is primarily a first component means that more than half of the composition is the first component. The term "predominantly" means the most important or largest portion. For example, a composition that is primarily a first component means that the composition has more of the first component than any other component. A composition that is primarily a first and a second component means that the composition has more of the first and second components than any other component.

[0018] Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates different instances of the similar objects being referred to and is not intended to imply that the objects described must be arranged in a given sequence in time, space, ranking, or in any other manner.

[0019] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0020] The views labeled "section," "profile," and "plan" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are obtained in the xz and yz planes, and plan views are obtained in the xy plane. Typically, a profile view in the xz plane is a cross-sectional view. The accompanying drawings are labeled, where appropriate, with axes indicating the orientation of the drawing.

[0021] Some integrated circuits (ICs) may utilize diode-based electrostatic discharge (ESD) protection at pads (e.g., metallization structures associated with signals). The ESD protection circuit for the pads may consist of a metallized N+ / P-well diode (N-diode) and a separate instance of a metallized P+ / N-well diode (P-diode) coupled in series between a positive voltage source (e.g., VDD) and a reference voltage (e.g., VSS or ground), wherein the anode of the N-diode is at VSS, the cathode of the P-diode is at VDD, and the pad is connected to the node of the cathode of the N-diode and the anode of the P-diode. Two signal pads may be arranged as two instances of such a pad circuit placed adjacent to each other.

[0022] In order to provide ESD protection for human body model (HBM) type ESD stress, where a current can be forced between two adjacent pads, a relatively large size diode is used. In order to provide ESD protection for charge device model (CDM) type ESD stress, where static charge is stored in the IC itself, the ESD diode can be smaller, but may have too much capacitive loading for some applications. For example, the capacitive loading of the ESD network for a high frequency (HF) transceiver that utilizes at least one series inductor or transformer can significantly affect the HF performance. Some HF transceivers can utilize single-stage ESD diode protection directly connected at the signal pad of the integrated circuit (IC). The problem is that if the capacitive loading at the signal pad is too high, the HF performance deteriorates significantly.

[0023] Some HF transceivers can utilize matching networks built with inductors either inside the package or on the die to provide adequate ESD protection and HF performance. The problem is that the inductors add additional cost in terms of area and process / design complexity, and the matching bandwidth may be limited.

[0024] The capacitive loading can be reduced by utilizing smaller ESD diodes, but the problem is that smaller ESD LEDs may not provide adequate ESD protection at the signal pads. ESD protection can be improved by adding series resistors to smaller diodes, but there is still the problem that if the series resistance is too high, the HF performance will deteriorate.

[0025] Some ESD protection circuits for transceivers with transformer architectures rely on large primary ESD diodes connected directly at the signal pads. The capacitive load of the primary ESD diodes can vary depending on the CDM target. For an example CDM target of six amperes (6A), the capacitance can be up to about half to one picofarad (0.5-1pF), depending on the underlying silicon technology. The problem is that in order to support high-performance HF interfaces with frequencies greater than ten gigahertz (10GHz), the capacitive load of the ESD protection circuit at the signal pad may more preferably need to be in the range of about one to two hundred femtofarads (100-200fF).

[0026] Some examples can overcome one or more of the above problems. Some examples can provide technology for ESD protection for HF transceivers. In some examples, the ESD diodes of the distributed ESD protection circuit are used together with the transformer matching network to reduce or minimize the impact of capacitive load on HF performance. In some examples, the ESD network is distributed before and after the inductor coupled to the signal pad. In some examples, the capacitive load of the primary diode of the ESD network can be reduced by using fewer fingers (e.g., only two primary ESD diodes instead of four or more fingers) in a multi-finger ESD diode. In some examples, stacked diodes can be used to further reduce or minimize capacitance. Examples can be implemented using any suitable technology, including, for example, FinFet or planar technology. Advantageously, the HF performance of the signal pad is significantly improved while providing sufficient ESD protection (e.g., for CDM type stress). Another advantage is that cost and complexity are reduced relative to using an external matching network.

[0027] In some examples, the signal pads may be exposed only to CDM type stresses. In some examples, the distributed ESD protection circuitry provides protection for the signal pads from static charges stored in the IC itself (e.g., sufficient protection for CDM). For example, the distributed ESD protection circuitry may provide protection for the signal pads from discharge voltages between five volts and thirty-five volts (5-35V).

[0028] Some examples provide techniques for distributed ESD protection of differential signals where the receiver / transmitter (RX / TX) is implemented within a sensitive IC device. During assembly, the differential signal may be exposed to CDM type stress. CDM stress is evaluated as a discharge voltage of 5-35V. The CDM voltage depends on the quality of the equipment on the assembly line and the electrostatic protection level of the air ionizer. The CDM voltage can correspond to a CDM discharge current of 40mA-300mA, depending on the voltage level and die size.

[0029] Figure 1An illustrative block diagram of an illustrative IC device 100 is shown, the IC device 100 including a signal pad 110, an inductor 120 coupled in series with the signal pad, and an ESD protection circuit 130 distributed before and after the inductor 120 to provide ESD protection for ESD events on the signal pad. In some examples, the ESD protection circuit 130 can include one or more primary ESD diodes 132 coupled to the signal pad 110 and a first side of the inductor 120, and one or more secondary ESD diodes 134 coupled to a second side of the inductor 120. In some examples, the one or more secondary ESD diodes 134 can provide more ESD protection relative to the one or more primary ESD diodes 132. For example, the one or more secondary ESD diodes 134 can provide a higher capacitive load relative to the one or more primary ESD diodes 132. In some examples, one or more of primary ESD diode 132 and secondary ESD diode 134 may be coupled to signal pad 110 via implicit metallization or an explicit resistor that couples primary diode 132 and / or secondary diode 134 to signal pad 110 .

[0030] In some examples, the one or more primary ESD diodes 132 may include: one or more P diodes coupled in series with one or more N diodes (e.g., to be coupled between a positive voltage source (e.g., VDD) and a reference voltage source (e.g., VSS or ground; see Figure 3 and 4 ) between ); and resistors (see, for example, Figure 3 ), the resistor is coupled between the junction of the one or more P diodes and the one or more N diodes and the signal pad 110. For example, the one or more N diodes may include at least two stacked N diodes. In any examples herein, the signal pad 110 may be coupled to a signal having a frequency of at least five (5) GHz (e.g., as part of an HF transceiver).

[0031] Figure 2An illustrative block diagram of an example of an IC device 200 is shown, the IC device 200 including a first signal pad 210, a first inductor 220 coupled in series with the first signal pad 210, a first set of primary ESD diodes 230 coupled to the first signal pad 210 and a first side of the first inductor 220, and a first set of secondary ESD diodes 235 coupled to a second side of the first inductor 220. For example, the first set of secondary ESD diodes 235 can provide a higher capacitive load relative to the first set of primary ESD diodes 230. In some examples, the first set of primary ESD diodes 230 can include: one or more P diodes coupled in series with one or more N diodes (e.g., stacked N diodes); and a resistor coupled between a junction of the one or more P diodes and the one or more N diodes and the first signal pad 210.

[0032] In some examples, IC device 200 may further include: a first transformer 240 including a first inductor 220 and a second inductor 245; a second transformer 250 including a third inductor 255 and a fourth inductor 260; a second signal pad 270 coupled in series with fourth inductor 260; a second set of primary ESD diodes 280 coupled to the second signal pad 270 and a first side of fourth inductor 260, and a second set of secondary ESD diodes 285 coupled to a second side of fourth inductor 260. In some examples, a first side of second inductor 245 is coupled to a first side of third inductor 255 (e.g., and both are coupled to VSS), a second side of second inductor 245 is coupled to a second side of fourth inductor 260, and a second side of third inductor 255 is coupled to a second side of first inductor 220.

[0033] In some examples, the second set of secondary ESD diodes 285 provide a higher capacitive load relative to the second set of primary ESD diodes 280. In some examples, the second set of primary ESD diodes 280 can include one or more P diodes coupled in series with one or more N diodes (e.g., stacked N diodes). In some examples, the first and second pads 210, 270 can be respectively coupled to a differential pair of signals having a frequency of at least 5 GHz.

[0034] Some examples provide techniques for ESD protection for HF transceivers.In some examples, a circuit provides low capacitance ESD (LC-ESD) protection for a receiver and / or transmitter exposed to external HF signals.

[0035] Figure 3A schematic diagram of an example interface circuit 300 including LC-ESD protection for the following components coupled as shown: a connection PAD for HF signals; resistors R1, R2; an inductor L1; a capacitor C1; an inverter INV1; P-diodes P-Diode1, P-Diode2; and an N-diode stack N-Diode1, N-Diode2. In this example, the outward-facing ESD diodes P-Diode1 and N-Diode1 on the PAD side of the inductor L1 can be considered as primary ESD diodes, while the ESD diodes P-Diode2 and N-Diode 2 on the other side of the inductor L1 can be considered as secondary ESD diodes.

[0036] In this example, the ESD network is distributed before and after the inductor L1, with a reduced primary diode protection connected to the PAD via a resistor R1. Advantageously, the reduced primary diode protection has a lower capacitance value compared to the full ESD protection directly at the PAD. The resistor R1 reduces the current through the primary ESD diode to a current amount below the damage value. The size of the primary ESD diode is reduced and connected to the series resistor R1. The resistance of the inductor L1 is much smaller than the resistance of the resistor R1. For example, the inductor L1 can have an inductance of 2 nanohenries and a resistance of five ohms (2nH, 5Ω), while the resistor R1 can have a resistance of twenty-five ohms (25Ω). Therefore, the main current path from the ESD event is redirected from the primary ESD diode to the secondary ESD diode and the inductor L1. Other examples can have more or less resistance and / or inductance, which are selected to meet various design requirements while guiding most of the ESD current through the secondary ESD diode.

[0037] The primary ESD diode can reduce capacitive loading by utilizing fewer fingers (e.g., relative to full ESD protection directly at the PAD). Figure 3 In the embodiment of the present invention, the N diodes in the ESD path are stacked to reduce the capacitive load and allow a higher signal swing below the VSS voltage. In other examples, a single N diode can be used. In view of the advantages of the present specification and the accompanying drawings, those skilled in the art will appreciate that a variety of ESD protection circuits can be used together with the ESD networks distributed before and after the inductor. Other variants of the LC-ESD protection circuit can include different stacks of diodes, such as, for example, non-stacked N diodes / P diodes, stacked P diodes / non-stacked N diodes, three times (3x) or more series stacks of diodes for N diodes and / or P diodes, etc. Similarly, in different examples, the ESD victim can be decoupled via a capacitor or not via a capacitor. Figure 3The exemplary victim in may be replaced by any other suitable victim architecture.

[0038] Figure 4 Schematic diagram of an example interface circuit 400 including a pair of connection pads PAD_P and PAD_N for HF differential signals. Figure 3 Compared to the single PAD example of FIG. 4 , the circuit 400 also includes an inductive coupling network between PAD_N and PAD_P. The circuit 400 provides LC-ESD protection for a receiver and / or transmitter exposed to an external HF differential signal. In particular, the circuit 400 includes the following components coupled as shown: resistors R1, R2, R3, R4; inductors LN1, LN2, LP1, LP2; capacitors C1, C2; inverters INV_N, INV_P; P diodes P1, P2, P3, P4; N diode stacks N1, N2, N3, N4; and power clamps. In this example, P diode P1 and N diode N1 can be considered as the first set of primary ESD diodes for PAD_N, P diode P3 and N diode N3 can be considered as the second set of primary ESD diodes for PAD_P, P diode P2 and N diode N2 can be considered as the first set of secondary ESD diodes for PAD_N, and P diode P4 and N diode N4 can be considered as the second set of secondary ESD diodes for PAD_P.

[0039] In some examples, circuit 400 can be used as an architecture for ESD network differentiation for HF transmitters. The distributed ESD network utilizes reduced primary diode protection connected to the connection pads via resistors. When an ESD event occurs, the reduced CDM current flows through the small primary diodes shielded by the corresponding resistors for current limiting. In some examples, the first group of primary diodes P1, N1 and the second group of primary diodes P3, N3 can be implemented as parallel x2 finger diodes. Figure 4 As shown, large second-level ESD diodes (e.g., secondary ESD diodes P2, N2 and P4, N4) shunt approximately half of the CDM current, where the secondary ESD diodes are co-designed after the inductor for better impedance matching and before the inductor to reduce capacitive loading. In some examples, the first set of secondary diodes P2, N2 and the second set of secondary diodes P4, N4 can be implemented as parallel x4-finger diodes. The inductor provides another CDM current path (e.g., via a coil with an inductance of 2nH and a resistance of 10 ohms (2x5=10Ω)) for approximately half of the CDM current.

[0040] In some applications, the worst-case CDM discharge occurs in a negative CDM stress, where a positive current is forced to the connection pad. When a positive current is forced into PAD_N relative to VSS, an example CDM stress can have an amplitude of up to about 6 amperes (6A), and a slew rate in the range of about twenty to one hundred picoseconds (20-100ps). In the case of providing complete ESD protection directly at the connection pad, the main part of the current from the ESD event flows to VSS via the ESD diode via the power clamp. The resistance of the ESD diode is typically less than 1 ohm (<1Ω). The current path to VSS via the inductor can have a series resistance of about ten ohms (~10Ω) and therefore only drives a small part of the current from the ESD event. In the case of providing complete ESD protection directly at the connection pad, the size of the ESD diode is made to be substantially suitable for all currents from the ESD event. In some devices, the voltage at PAD_N and PAD_P can be clamped by parallel twelve-finger (x12) ESD diodes, which prevent the victim from being damaged. With full ESD protection at PAD_N and PAD_P, the capacitive loading is high and becomes problematic as the frequency of the signal on the pad increases.

[0041] Compared with the complete ESD protection at the pad, the circuit 400 includes an LC-ESD protection circuit, in which the ESD network is distributed before and after the inductor. In some examples, the high capacitive load of the primary diode at the HF PAD_N / P can be significantly reduced to two fingers (x2) from the twelve fingers (x12) of the ESD diode. The stacked diode can also be used to further reduce or minimize the capacitance. As a result, the HF performance of PAD_N and PAD_P is significantly improved. For the negative voltage signal at PAD_N and PAD_P, the 2x stacked N diode also provides an overvoltage tolerance in the range of four tenths of a volt to one half a volt (0.4-0.5V, or higher, depending on the allowable current load at the HF pad) for each diode. In some examples, PAD_N and PAD_P can be a negative one volt (-1V) overvoltage tolerance.

[0042] The primary ESD diode is decoupled from PAD_N and PAD_P by corresponding resistors R1 and R3. The size of the primary ESD diode is not made to drive most of the ESD current. On the contrary, the size of the primary ESD diode with resistors R1 and R3 is made to suppress only the overshoot at PAD_N or PAD_P. For example, the size of the primary ESD diode can also be made to drive only the remaining part of the current forced in the CDM at PAD_N or PAD_P. The resistance values ​​of resistors R1 and R3 can be selected to reduce the current through the corresponding primary ESD diode to a current amount below a predetermined amount (for example, based on preventing damage). In some examples, resistors R1 and R3 can have a resistance of approximately twenty-five ohms (25Ω), but they can have any suitable resistance value based on design requirements.

[0043] The size of the primary ESD diode is reduced and connected with a nominal series resistance (e.g., R1=25Ω). The secondary ESD diode is connected after the inductor and is sized to drive approximately half of the CDM current. The main CDM current path is redirected from the primary ESD diode to the secondary ESD diode and the inductor. For example, for an ESD event on PAD_N, approximately half of the CDM current (~3A) flows along the first ESD path through the inductor LN2 to the second-stage ESD diodes P2, N2 and is shunted to VSS via the power clamp, and approximately half of the CDM current (~3A) flows to VSS via the parallel second ESD path through both inductors LN2 and LP2 (e.g., and correspondingly, under stress on PAD_P, the secondary diodes P4, N4 drive approximately half of the CDM current, and LN1 and LP1 drive approximately half of the CDM current).

[0044] The remaining CDM current still flows along the third ESD path via the primary ESD diodes P1 and N1 decoupled by resistor R1. The size of the primary ESD diode is significantly reduced (e.g., from 12x fingers to 2x fingers). If there is no ESD protection directly at the connection pad, the overshoot at the connection pad may exceed the limit of the breakdown voltage for isolation between metal lines and cause damage driven by electrostatic overstress. The size of the series resistor R1 and the primary ESD diodes P1 and N1 can be made to clamp only the overshoot at PAD_N. Advantageously, the distributed ESD network provides the required ESD protection at the connection pad while allowing the size of the primary ESD diode to be substantially reduced.

[0045] Inductors LN1, LN2, LP1, LP2 provide functional aspects of circuit 400 and may have any suitable values ​​(e.g., in this example, each of inductors LN1, LN2, LP1, LP2 may have 5Ω and 2nH). The (transformer) matching network provides a reduced impedance level (e.g., the ~5Ω resistive portion in LN2) on the secondary side of the ESD network (e.g., the secondary ESD diodes P2, N2). Thus, the secondary ESD diodes (e.g., with increased capacitive loading) may be larger than the primary ESD diodes (e.g., P1, N1 via the ~25 ohm resistive portion of R1) without significantly affecting performance.

[0046] In some examples, the topology of circuit 400 can be used in an impedance matching network that provides an N:M impedance transformation and includes at least one direct current (DC) coupling path between the matching network input / output. The greater ESD protection of the secondary ESD diode is applied on the low impedance side (e.g., see Figure 4 25 ohm side in the ). During the worst case negative CDM stress, the positive current is driven by the p-diodes of the primary ESD diode and the secondary ESD diode, reaching the CDM charge source (VSS) at ground via the power clamp. In some examples, the N-diodes in the ESD path are stacked to reduce capacitive loading and allow higher signal swings below the VSS voltage. In other examples, a single N-diode can be utilized and / or any other suitable stacked / non-stacked arrangement of P-diodes and N-diodes can be utilized. The ESD victim can be decoupled via capacitance and can consist of a ballast inverter. Alternatively, different victims can be utilized for RX / TX and / or decoupling capacitors or no decoupling capacitors can be utilized.

[0047] An HF network incorporating full ESD protection at the pads may result in a significant reduction in return loss compared to an HF network without ESD, particularly at frequencies of 5 GHz and above. An example of an HF network incorporating an LC-ESD protection circuit with a distributed ESD network as described herein may exhibit substantially similar performance in terms of return loss and bandwidth compared to an HF network without ESD. Advantageously, the example may provide adequate ESD protection with little impact on performance at frequencies of 5 GHz and above.

[0048] Figure 5 A block diagram of an example of a system 500 is shown, which includes a power supply 510 for providing a positive voltage source and a reference voltage source and a transceiver 520 coupled to the power supply. The transceiver 520 includes a distributed LC-ESD protection circuit 530 that incorporates one or more features or aspects of the examples described herein.

[0049] For example, the transceiver 520 may include a first signal pad to be coupled to a first signal of a differential signal pair, a second signal pad to be coupled to a second signal of the differential signal pair, a transformer coupled to the first and second signal pads, and an ESD network distributed before and after the transformer, the ESD network being used to provide ESD protection for ESD events on one or more of the first signal pad and the second signal pad. In some examples, the ESD network may include: a first group of primary ESD diodes, the first group of primary ESD diodes coupled to the first signal pad through a first resistor and coupled to a first side of the transformer to provide a first ESD path for an ESD event on the first signal pad through the first group of primary ESD diodes; and a first group of secondary ESD diodes coupled to a second side of the transformer to provide a second ESD path for an ESD event on the first signal pad through the first group of secondary ESD diodes.

[0050] For example, the first set of primary ESD diodes and the first resistor may be sized to carry less than half the amount of current from an ESD event on the first signal pad (e.g., or less than one-tenth the amount of current from the ESD event). In some examples, the transformer may further provide a third ESD path for the ESD event on the first signal pad through the transformer. For example, the first set of primary ESD diodes and the first resistor may be sized to carry the remaining amount of current from the ESD event on the first signal pad that is not carried by the second and third ESD paths.

[0051] In some examples, the ESD network may further include: a second group of primary ESD diodes coupled to the second signal pad through a second resistor and coupled to the first side of the transformer to provide a fourth ESD path for an ESD event on the second signal pad through the second group of primary ESD diodes; and a second group of secondary ESD diodes coupled to the second side of the transformer to provide a fifth ESD path for an ESD event on the second signal pad through the second group of secondary ESD diodes. For example, the size of the second group of primary ESD diodes and the second resistor may be made to carry less than half the amount of current from the ESD event on the second signal pad. In some examples, the transformer may further provide a sixth ESD path for an ESD event on the second signal pad through the transformer. For example, the size of the second group of primary ESD diodes and the second resistor may be made to carry the remaining amount of current from the ESD event on the second pad that is not carried by the fifth and sixth ESD paths.

[0052] Figure 6A diagram of an example data server machine 1006 employing an IC device 1050 having a distributed LC-ESD protection circuit as described herein is shown according to some examples. The server machine 1006 can be any commercial server, for example, including any number of high performance computing platforms arranged in a rack and networked together for electronic data processing, which in the illustrative example includes one or more devices 1050 having one or more distributed LC-ESD protection circuits.

[0053] Also as shown, server machine 1006 includes a battery and / or power supply 1015 to provide power to device 1050 and, in some examples, provide power delivery functionality such as power conditioning. Device 1050 can be deployed as part of package-level integrated system 1010. Integrated system 1010 is further illustrated in expanded view 1020. In an exemplary example, device 1050 (labeled "Memory / Processor") includes at least one memory chip (e.g., RAM) and / or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or a graphics processor, etc.) having the characteristics discussed herein. In an example, device 1050 is a microprocessor including a cache memory. As shown, device 1050 can be a multi-chip module employing one or more IC devices having one or more distributed LC-ESD protection circuits, as discussed herein. The device 1050 may also be coupled to (e.g., communicatively coupled to) a board, interposer, or substrate 1060 along with one or more of a power management IC (PMIC) 1030, an RF (wireless) IC (RFIC) 1025 (including a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband and an analog front end module that also includes a power amplifier on a transmit path and a low noise amplifier on a receive path)), and a controller 1035 thereof. In some examples, the RFIC 1025, the PMIC 1030, the controller 1035, and the device 1050 include an IC device having a distributed LC-ESD protection circuit on the substrate 1060 in a multi-chip module.

[0054] Figure 7 is a block diagram of an example computing device 1100 according to some examples. For example, one or more components of the computing device 1100 may include any of the devices or structures discussed herein. Figure 71100, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some examples, some or all of the components included in computing device 1100 may be attached to one or more printed circuit boards (e.g., motherboards). In some examples, various of these components may be fabricated on a single system-on-chip (SoC) die. Additionally, in various examples, computing device 1100 may not include a processor. Figure 7 1103, but computing device 1100 may include interface circuitry for coupling to one or more of the components. For example, computing device 1100 may not include display device 1103, but may include display device interface circuitry (e.g., connector and driver circuitry), to which display device 1103 may be coupled. In another set of examples, the computing device 1100 may not include the audio output device 1104, other output devices 1105, global positioning system (GPS) device 1109, LTE device, 5G device, 6G device, 5G beamforming device, audio input device 1110, or other input device 1111, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, LTE, 5G, 6G interface circuitry, audio input device interface circuitry, or other input device interface circuitry, and the audio output device 1104, other output device 1105, GPS device 1109, audio input device 1110, or other input device 1111 may be coupled to the audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, LTE, 5G, 6G interface circuitry, audio input device interface circuitry, or other input device interface circuitry.

[0055] The computing device 1100 may include a processing device 1101 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" indicates a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1101 may include a memory 1121, a communication device 1122, a cooling device 1123, a battery / power regulation device 1124, a logic 1125, an interconnect 1126 (i.e., optionally including a redistribution layer (RDL) or a metal-insulator-metal (MIM) device), a thermal regulation device 1127, and a hardware security device 1128.

[0056] The processing device 1101 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0057] The computing device 1100 may include a memory 1102, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some examples, the memory 1102 includes memory that shares a die with the processing device 1101. The memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-M RAM).

[0058] The computing device 1100 may include a thermal conditioning / cooling device 1106. The thermal conditioning / cooling device 1106 may maintain the processing device 1101 (and / or other components of the computing device 1100) at a predetermined low temperature during operation. The predetermined low temperature may be any temperature discussed herein.

[0059] In some examples, computing device 1100 may include communication chip 1107 (e.g., one or more communication chips). For example, communication chip 1107 may be configured to manage wireless communications for transmitting data to and from computing device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some examples it may not contain any wires.

[0060] The communication chip 1107 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment)), Long Term Evolution (LTE) project and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 1107 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1107 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1107 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, 6G and higher. In other examples, the communication chip 1107 may operate according to other wireless protocols. The computing device 1100 may include an antenna 1113 to facilitate wireless communications and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0061] In some examples, the communication chip 1107 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1107 can include multiple communication chips. For example, the first communication chip 1107 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 1107 can be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, the first communication chip 1107 can be dedicated to wireless communications, while the second communication chip 1107 can be dedicated to wired communications.

[0062] Computing device 1100 may include battery / power circuitry 1108. Battery / power circuitry 1108 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 1100 to an energy source separate from computing device 1100 (e.g., AC line power).

[0063] Computing device 1100 may include a display device 1103 (or corresponding interface circuitry as discussed above). Display device 1103 may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0064] Computing device 1100 may include audio output device 1104 (or corresponding interface circuitry as discussed above). Audio output device 1104 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0065] The computing device 1100 may include an audio input device 1110 (or corresponding interface circuitry as discussed above). The audio input device 1110 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0066] Computing device 1100 may include a GPS device 1109 (or corresponding interface circuitry as discussed above). GPS device 1109 may communicate with a satellite-based system and may receive the location of computing device 1100, as is known in the art.

[0067] Computing device 1100 may include other output devices 1105 (or corresponding interface circuitry as discussed above). Examples of other output devices 1105 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0068] The computing device 1100 may include other input devices 1111 (or corresponding interface circuitry as discussed above). Examples of other input devices 1111 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0069] The computing device 1100 may include a security interface device 1112. The security interface device 1112 may include any device that provides security measures for the computing device 1100, such as intrusion detection, biometric authentication, security encoding or decoding, access list management, malware detection, or spyware detection.

[0070] Computing device 1100 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0071] The subject matter of this specification is not necessarily limited to Figure 1-7 Specific Applications Illustrated. The present subject matter may be applied to other transistor applications, as well as any suitable manufacturing application, as will be appreciated by those skilled in the art.

[0072] The following examples refer to further examples, and details in the examples may be used anywhere in one or more of the examples.

[0073] Example 1 includes an integrated circuit (IC) device, comprising: a signal pad; an inductor coupled in series with the signal pad; and an electrostatic discharge (ESD) protection circuit distributed before and after the inductor to provide ESD protection for ESD events on the signal pad.

[0074] Example 2 includes the IC device of Example 1, wherein the ESD protection circuit includes: one or more primary ESD diodes coupled to the signal pad and the first side of the inductor; and one or more secondary ESD diodes coupled to the second side of the inductor.

[0075] Example 3 includes the IC device of Example 2, wherein the one or more secondary ESD diodes provide more ESD protection relative to the one or more primary ESD diodes.

[0076] Example 4 includes the IC device of any of Examples 2-3, wherein the one or more secondary ESD diodes provide a higher capacitive load relative to the one or more primary ESD diodes.

[0077] Example 5 includes the IC device described in any one of Examples 2 to 4, wherein the one or more primary ESD diodes include: one or more P diodes coupled in series with one or more N diodes; and a resistor coupled between the signal pad and the junction of the one or more P diodes and the one or more N diodes.

[0078] Example 6 includes the IC device of Example 5, wherein the one or more N diodes include at least two stacked N diodes.

[0079] Example 7 includes the IC device of any of Examples 1 to 6, wherein the signal pad is to be coupled to a signal having a frequency of at least five gigahertz.

[0080] Example 8 includes an integrated circuit (IC) device, comprising: a first signal pad; a first inductor coupled in series with the first signal pad; a first set of primary ESD diodes coupled to the first signal pad and a first side of the first inductor; and a first set of secondary ESD diodes coupled to a second side of the first inductor.

[0081] Example 9 includes the IC device of Example 8, wherein the first set of secondary ESD diodes provides a higher capacitive load relative to the first set of primary ESD diodes.

[0082] Example 10 includes the IC device described in Example 9, wherein the first group of primary ESD diodes includes: one or more P diodes coupled in series with one or more N diodes; and a resistor coupled between the first signal pad and the junction of the one or more P diodes and the one or more N diodes.

[0083] Example 11 includes the IC device described in any one of Examples 8 to 10, further including: a first transformer, the first transformer including the first inductor and the second inductor; a second transformer, the second transformer including a third inductor and a fourth inductor; a second signal pad coupled in series with the fourth inductor; a second set of primary ESD diodes coupled to the second signal pad and the first side of the fourth inductor; and a second set of secondary ESD diodes coupled to the second side of the fourth inductor.

[0084] Example 12 includes the IC device described in Example 11, wherein the first side of the second inductor is coupled to the first side of the third inductor, the second side of the second inductor is coupled to the second side of the fourth inductor, and the second side of the third inductor is coupled to the second side of the first inductor.

[0085] Example 13 includes the IC device of any of Examples 11-12, wherein the second set of secondary ESD diodes provides a higher capacitive load relative to the second set of primary ESD diodes.

[0086] Example 14 includes the IC device of any of Examples 11 to 13, wherein the first pad and the second pad are configured to be respectively coupled to a differential pair of signals having a frequency of at least five gigahertz.

[0087] Example 15 includes a system comprising: a power supply for providing a positive voltage source and a reference voltage source; and a transceiver coupled to the power supply, the transceiver comprising: a first signal pad for coupling to a first signal of a differential signal pair; a second signal pad for coupling to a second signal of the differential signal pair; a transformer coupled to the first signal pad and the second signal pad, and an electrostatic discharge (ESD) network distributed before and after the transformer to provide ESD protection for ESD events on one or more of the first signal pad and the second signal pad.

[0088] Example 16 includes the system of Example 15, wherein the ESD network comprises: a first group of primary ESD diodes coupled to the first signal pad via a first resistor and coupled to a first side of the transformer to provide a first ESD path for the ESD event on the first signal pad via the first group of primary ESD diodes; and a first group of secondary ESD diodes coupled to a second side of the transformer to provide a second ESD path for the ESD event on the first signal pad via the first group of secondary ESD diodes.

[0089] Example 17 includes the system of Example 16, wherein the first set of primary ESD diodes and the first resistor are sized to carry less than half an amount of current from the ESD event on the first signal pad.

[0090] Example 18 includes the system of any of Examples 16-17, wherein the transformer is further configured to provide a third ESD path for the ESD event on the first signal pad through the transformer.

[0091] Example 19 includes the system of Example 18, wherein the first set of primary ESD diodes and the first resistor are sized to carry a remaining amount of current from the ESD event on the first signal pad that is not carried by the second ESD path and the third ESD path.

[0092] Example 20 includes the system described in any of Examples 16 to 19, wherein the ESD network further includes: a second group of primary ESD diodes coupled to the second signal pad via a second resistor and coupled to the first side of the transformer to provide a fourth ESD path for the ESD event on the second signal pad via the second group of primary ESD diodes; and a second group of secondary ESD diodes coupled to the second side of the transformer to provide a fifth ESD path for the ESD event on the second signal pad via the second group of secondary ESD diodes.

[0093] Example 21 includes the system of Example 20, wherein the second set of primary ESD diodes and the second resistor are sized to carry less than half an amount of current from the ESD event on the second signal pad.

[0094] Example 22 includes the system of any of Examples 20-21, wherein the transformer is further configured to provide a sixth ESD path for the ESD event on the second signal pad through the transformer.

[0095] Example 23 includes the system of Example 22, wherein the second set of primary ESD diodes and the second resistor are sized to carry a remaining amount of current from the ESD event on the second pad that is not carried by the fifth ESD path and the sixth ESD path.

[0096] Example 24 includes a method comprising: coupling an inductor in series with a signal pad; and distributing electrostatic discharge (ESD) protection circuits before and after the inductor to provide ESD protection for ESD events on the signal pad.

[0097] Example 25 includes the method of Example 24, further comprising providing one or more primary ESD diodes on a first side of the inductor and providing one or more secondary ESD diodes on a second side of the inductor.

[0098] Example 26 includes the method of Example 25, further comprising providing more ESD protection from the one or more secondary ESD diodes relative to the one or more primary ESD diodes.

[0099] Example 27 includes the method of any of Examples 25 to 26, further comprising providing a higher capacitive load from the one or more secondary ESD diodes relative to the one or more primary ESD diodes.

[0100] Example 28 includes the method of any of Examples 25 to 27, further comprising limiting an amount of ESD current directed through the one or more primary ESD diodes to less than a predetermined current amount.

[0101] Example 29 includes the method of Example 28, further comprising suppressing overshoot at the signal pad with the one or more primary ESD diodes.

[0102] Example 30 includes the method of any of Examples 25 to 29, further comprising stacking one or more of the one or more primary ESD diodes.

[0103] Example 31 includes the method of any of Examples 24 to 30, further comprising receiving a signal having a frequency of at least five gigahertz at the signal pad.

[0104] Example 32 includes an apparatus comprising: means for coupling an inductor in series with a signal pad; and means for distributing electrostatic discharge (ESD) protection circuits before and after the inductor to provide ESD protection for ESD events on the signal pad.

[0105] Example 33 includes the apparatus of Example 32, further comprising means for providing one or more primary ESD diodes on a first side of the inductor; and means for providing one or more secondary ESD diodes on a second side of the inductor.

[0106] Example 34 includes the apparatus of Example 33, further comprising means for providing more ESD protection from the one or more secondary ESD diodes relative to the one or more primary ESD diodes.

[0107] Example 35 includes the apparatus of any of Examples 33-34, further comprising means for providing a higher capacitive load from the one or more secondary ESD diodes relative to the one or more primary ESD diodes.

[0108] Example 36 includes the apparatus of any of Examples 33 to 35, further comprising means for limiting an amount of ESD current directed through the one or more primary ESD diodes to less than a predetermined current amount.

[0109] Example 37 includes the apparatus of Example 36, further comprising means for suppressing overshoot at the signal pad with the one or more primary ESD diodes.

[0110] Example 38 includes the apparatus of any of Examples 33 to 37, further comprising means for stacking one or more of the one or more primary ESD diodes.

[0111] Example 39 includes the apparatus of any of Examples 32 to 38, further comprising means for receiving a signal having a frequency of at least five gigahertz at the signal pad.

[0112] The present disclosure may be practiced through modification and alteration, and the scope of the appended claims is not limited to the examples described so far. For example, the above examples may include a specific combination of features. However, the above examples are not limited in this regard, and in various embodiments, the above examples may include taking only a subset of such features, taking a different order of such features, taking a different combination of such features, and / or taking additional features different from those features explicitly listed. Therefore, the scope of the patent right should be determined by reference to the appended claims and the entire scope of equivalents granted by these claims.

Claims

1. An integrated circuit (IC) device comprising: Signal pad; an inductor coupled in series with the signal pad; as well as Electrostatic discharge (ESD) protection circuits are distributed before and after the inductor to provide ESD protection for ESD events on the signal pad.

2. The IC device according to claim 1, wherein: The ESD protection circuit comprises: one or more primary ESD diodes coupled to the signal pad and the first side of the inductor; and One or more secondary ESD diodes are coupled to the second side of the inductor.

3. The IC device according to claim 2, wherein: The one or more secondary ESD diodes provide more ESD protection relative to the one or more primary ESD diodes.

4. The IC device according to claim 2, wherein: The one or more secondary ESD diodes provide a higher capacitive load relative to the one or more primary ESD diodes.

5. The IC device according to any one of claims 2 to 4, wherein: The one or more primary ESD diodes include: one or more P diodes coupled in series with one or more N diodes; and A resistor is coupled between the signal pad and a junction of the one or more P diodes and the one or more N diodes.

6. The IC device according to claim 5, wherein: The one or more N diodes include at least two stacked N diodes.

7. The IC device according to any one of claims 1 to 4, wherein: The signal pad is for coupling to a signal having a frequency of at least five gigahertz.

8. An integrated circuit (IC) device comprising: A first signal pad; a first inductor coupled in series with the first signal pad; a first set of primary ESD diodes coupled to the first signal pad and a first side of the first inductor; as well as A first set of secondary ESD diodes is coupled to the second side of the first inductor.

9. The IC device according to claim 8, wherein: The first set of secondary ESD diodes provides a higher capacitive load relative to the first set of primary ESD diodes.

10. The IC device according to claim 9, wherein: The first set of primary ESD diodes includes: one or more P diodes coupled in series with one or more N diodes; and A resistor is coupled between the first signal pad and a junction of the one or more P diodes and the one or more N diodes.

11. The IC device according to any one of claims 8 to 10, further comprising: a first transformer, the first transformer comprising the first inductor and a second inductor; a second transformer comprising a third inductor and a fourth inductor; a second signal pad coupled in series with the fourth inductor; a second set of primary ESD diodes coupled to the second signal pad and the first side of the fourth inductor; as well as A second set of secondary ESD diodes is coupled to the second side of the fourth inductor.

12. The IC device according to claim 11, wherein: A first side of the second inductor is coupled to a first side of the third inductor, a second side of the second inductor is coupled to the second side of the fourth inductor, and a second side of the third inductor is coupled to the second side of the first inductor.

13. The IC device according to claim 11, wherein: The second set of secondary ESD diodes provides a higher capacitive load relative to the second set of primary ESD diodes.

14. The IC device according to claim 11, wherein: The first pad and the second pad are for respectively coupling to a differential pair of signals having a frequency of at least five gigahertz.

15. A system comprising: A power supply, used for providing a positive voltage source and a reference voltage source; as well as A transceiver coupled to the power supply, the transceiver comprising: A first signal pad, used to couple to a first signal of a differential signal pair; A second signal pad, used to couple to a second signal of the differential signal pair; a transformer coupled to the first signal pad and the second signal pad; and An electrostatic discharge (ESD) network is distributed before and after the transformer to provide ESD protection against ESD events on one or more of the first signal pad and the second signal pad.

16. The system of claim 15, wherein: The ESD network includes: a first set of primary ESD diodes coupled to the first signal pad through a first resistor and to a first side of the transformer to provide a first ESD path for the ESD event on the first signal pad through the first set of primary ESD diodes; and A first set of secondary ESD diodes is coupled to the second side of the transformer to provide a second ESD path for the ESD event on the first signal pad through the first set of secondary ESD diodes.

17. The system of claim 16, wherein: The first set of primary ESD diodes and the first resistor are sized to carry less than half an amount of current from the ESD event on the first signal pad.

18. The system of claim 16, wherein: The transformer is further configured to provide a third ESD path for the ESD event on the first signal pad through the transformer.

19. The system of claim 18, wherein: The first set of primary ESD diodes and the first resistor are sized to carry a remaining amount of current from the ESD event on the first signal pad that is not carried by the second ESD path and the third ESD path.

20. A system according to any one of claims 16 to 19, wherein: The ESD network also includes: a second set of primary ESD diodes coupled to the second signal pad through a second resistor and to the first side of the transformer to provide a fourth ESD path for the ESD event on the second signal pad through the second set of primary ESD diodes; and A second set of secondary ESD diodes is coupled to the second side of the transformer to provide a fifth ESD path for the ESD event on the second signal pad through the second set of secondary ESD diodes.

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