A three-phase half-bridge circuit topology power module

Abstract

The embodiments of this specification mainly relate to the technical field of power modules, specifically a three-phase half-bridge circuit topology power module, including: an insulating board, and a first-phase half-bridge circuit structure, a second-phase half-bridge circuit structure and a third-phase half-bridge circuit structure arranged on the insulating board; the first-phase half-bridge circuit structure includes a first upper bridge arm circuit structure and a first lower bridge arm circuit structure; the first upper bridge arm circuit structure includes: a first metal layer region one, arranged on the insulating board; a first metal layer region two, arranged on the insulating board and adjacent to the first metal layer region one along the Y direction; a first metal layer region three, arranged on the insulating board and adjacent to the first metal layer region two along the Y direction. In the power module of the embodiment of this specification, the half-phase bridge circuit connection structure is folded in half on the insulating board and arranged closely, which can greatly reduce the parasitic inductance in the power module, so that the voltage spike of the power module switching transient is reduced, thereby making the switching speed of the power module faster.

Description

Technical Field

[0001] The embodiments of this specification mainly relate to the technical field of power modules, and specifically to a three-phase half-bridge circuit topology power module. Background Art

[0002] Silicon carbide chips have the characteristics of high switching frequency and low switching loss, and are widely used in power modules. For power modules with three-phase half-bridge circuit topology, if the module structure is not set reasonably, it is difficult to give full play to the performance advantages of high-speed switching and high-frequency operation of silicon carbide chips even if they are used.

[0003] How to optimize the module structure so that the power module of the three-phase half-bridge circuit structure using silicon carbide chips can fully realize the characteristics of high-speed switching and high-frequency operation is a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the problems existing in the prior art, the embodiments of this specification propose a power module, which optimizes the module structure so that the power module with a three-phase half-bridge circuit topology structure using silicon carbide chips can fully realize the performance advantages of high-speed switching and high-frequency operation.

[0005] In a first aspect, an embodiment of the present specification provides a power module, comprising: an insulating board, and a first-phase half-bridge circuit structure, a second-phase half-bridge circuit structure, and a third-phase half-bridge circuit structure arranged on the insulating board and arranged in sequence along the X direction; and a temperature-sensitive resistor arranged on the insulating board, wherein:

[0006] The first phase half-bridge circuit structure includes: a first metal layer region 1, a first input DC positive electrode pin and a first upper bridge arm power chip arranged on the first metal layer region 1, a first metal layer region 5, a first output AC electrode pin and a first lower bridge arm power chip arranged on the first metal layer region 5, a first metal layer region 4, and a first input DC negative electrode pin arranged on the first metal layer region 4, the first metal layer region 1 is adjacent to the first metal layer region 4 along the X direction, the first metal layer region 5 is adjacent to the first metal layer region 1 along the direction opposite to the X direction, and is also adjacent to the first metal layer region 4 along the Y direction.

[0007] In this way, when calculating the parasitic inductance of the main power loop of the first phase half-bridge circuit, the current flows from the first input DC positive electrode of the first metal layer area one, flows into the first lower bridge arm power chip of the first metal layer area five through the first upper bridge arm power chip, and finally flows through the first input DC negative electrode pin on the first metal layer area four. The flow path of the current of the main power loop on the insulating board is a "folded" path from top to bottom and then back to the top. The "folded" current path can form currents flowing in opposite directions and in parallel in the main power loop of the power module, and the magnetic fields generated by the current flow can offset each other, thereby reducing the parasitic inductance of the loop and achieving faster switching of the module.

[0008] Preferably, the first-phase half-bridge circuit structure further includes:

[0009] A first upper bridge arm circuit structure, a first lower bridge arm circuit structure, and a first decoupling capacitor, wherein:

[0010] The first upper bridge arm circuit structure further includes:

[0011] A first metal layer region 2, disposed on the insulating plate and adjacent to the first metal layer region 1 along the Y direction;

[0012] A first metal layer region three is disposed on the insulating plate and is adjacent to the first metal layer region two along the Y direction;

[0013] The first upper bridge arm power chip is electrically connected to the first metal layer region 2 and the first metal layer region 3 respectively through metal leads;

[0014] A first upper bridge arm power chip gate pin is arranged on the first metal layer region 2;

[0015] A first upper bridge arm power chip source pin is arranged on the first metal layer region three;

[0016] The first lower bridge arm circuit structure further includes:

[0017] The first metal layer region 2 and the first metal layer region 3 are adjacently arranged, and the first upper bridge arm power chip is also electrically connected to the first metal layer region 5 through a metal lead;

[0018] A first metal layer region 6 is disposed on the insulating plate and is adjacent to the first metal layer region 4 along the Y direction, and the first metal layer region 6 is adjacent to the first metal layer region 5 along the X direction;

[0019] A first metal layer region seven is disposed on the insulating plate and is adjacent to the first metal layer region six along the Y direction, and the first metal layer region seven is adjacent to the first metal layer region five along the X direction;

[0020] The first lower bridge arm power chip is electrically connected to the first metal layer region 4, the first metal layer region 6, and the first metal layer region 7 respectively through metal leads;

[0021] A first lower bridge arm power chip gate pin is arranged on the first metal layer region six;

[0022] A first lower bridge arm power chip source pin is arranged on the first metal layer area seven;

[0023] The first decoupling capacitor is electrically connected to the first metal layer region 1 and the first metal layer region 4, and the first decoupling capacitor, the first input DC positive electrode pin, and the first input DC negative electrode pin are on the same X-direction straight line.

[0024] In this way, by arranging the first decoupling capacitor between the first input positive and negative electrodes arranged closely at both ends of the "folded" current path, the high voltage spike of the half-bridge circuit structure during switching transients can be reduced, further increasing the switching speed.

[0025] Preferably, the first metal layer region 2 is arranged in a strip shape along the X direction, and the first metal layer region 3 is arranged in a strip shape along the X direction; or the first metal layer region 6 is arranged in a strip shape along the Y direction, and the first metal layer region 7 is arranged in a strip shape along the Y direction.

[0026] In this way, a Kelvin connection is achieved between the input side gate-source loop and the input side drain-source loop of the power module, thereby reducing the negative feedback effect caused by the output side loop coupling through the common source path when the power module is switched at high speed, and further improving the high-speed switching performance of the power module.

[0027] Preferably, the second phase half-bridge circuit structure includes a second upper bridge arm circuit structure and a second lower bridge arm circuit structure;

[0028] The second upper bridge arm circuit structure includes:

[0029] A second metal layer region 1, disposed on an insulating plate;

[0030] A second metal layer region 2 is disposed on the insulating plate and is adjacent to the second metal layer region 1 along the Y direction;

[0031] A second metal layer region three is disposed on the insulating plate and is adjacent to the second metal layer region two along the Y direction;

[0032] The second upper bridge arm power chip is arranged on the second metal layer region 1, and the second upper bridge arm power chip is electrically connected to the second metal layer region 2 and the second metal layer region 3 respectively through metal leads;

[0033] A second input DC positive electrode pin is disposed on the second metal layer region 1;

[0034] The second upper bridge arm power chip gate pin is arranged on the second metal layer area 2;

[0035] The second upper bridge arm power chip source pin is arranged on the second metal layer area three;

[0036] The second lower bridge arm circuit structure includes:

[0037] The second metal layer region 4 is disposed on the insulating plate and is adjacent to the second metal layer region 1 in the reverse direction X;

[0038] The second metal layer region five is arranged on the insulating board and is adjacent to the second metal layer region four along the Y direction, and the second metal layer region five is adjacent to the second metal layer region one, the second metal layer region two, and the second metal layer region three along the X direction, and the second upper bridge arm power chip is also electrically connected to the second metal layer region five through a metal lead;

[0039] The second metal layer region 6 is disposed on the insulating plate and is adjacent to the second metal layer region 4 along the Y direction, and the second metal layer region 6 is adjacent to the second metal layer region 5 along the X direction;

[0040] The second metal layer region seven is disposed on the insulating plate and is adjacent to the second metal layer region six along the Y direction, and the second metal layer region seven is adjacent to the second metal layer region five along the X direction;

[0041] The second lower bridge arm power chip is disposed on the second metal layer region five, and the second lower bridge arm power chip is electrically connected to the second metal layer region four, the second metal layer region six, and the second metal layer region seven through metal leads respectively;

[0042] A second input DC negative electrode pin is disposed on a second metal layer region 4;

[0043] The second lower bridge arm power chip gate pin is arranged on the second metal layer area six;

[0044] The second lower bridge arm power chip source pin is arranged on the second metal layer area seven;

[0045] The second output AC electrode pin is arranged on the second metal layer region five.

[0046] Preferably, the second phase half-bridge circuit structure further includes:

[0047] The second decoupling capacitor is electrically connected to the second metal layer region 1 and the second metal layer region 4, and the second decoupling capacitor, the second input DC positive electrode pin, and the second input DC negative electrode pin are on the same X-direction straight line.

[0048] Preferably, the second metal layer region 2 is arranged in a strip shape along the X direction, and the second metal layer region 3 is arranged in a strip shape along the X direction; or the second metal layer region 6 is arranged in a strip shape along the Y direction, and the second metal layer region 7 is arranged in a strip shape along the Y direction.

[0049] In this way, the structure of the second-phase board bridge circuit can also achieve high-speed switching while improving the performance of the two-phase circuit and the consistency of the switching action.

[0050] Preferably, the third phase half-bridge circuit structure includes a third upper bridge arm circuit structure and a third lower bridge arm circuit structure;

[0051] The third upper bridge arm circuit structure includes:

[0052] A third metal layer region 1, disposed on an insulating plate;

[0053] A third metal layer region 2 is disposed on the insulating plate and is adjacent to the third metal layer region 1 along the Y direction;

[0054] A third metal layer region three is disposed on the insulating plate and is adjacent to the third metal layer region two along the Y direction;

[0055] The third upper bridge arm power chip is arranged on the third metal layer region 1, and the third upper bridge arm power chip is electrically connected to the third metal layer region 2 and the third metal layer region 3 respectively through metal leads;

[0056] A third input DC positive electrode pin is disposed on the third metal layer region 1;

[0057] The third upper bridge arm power chip gate pin is arranged on the third metal layer region 2;

[0058] The third upper bridge arm power chip source pin is arranged on the third metal layer area three;

[0059] The third lower bridge arm circuit structure includes:

[0060] The third metal layer region 4 is disposed on the insulating plate and is adjacent to the third metal layer region 1 in the reverse direction X;

[0061] The third metal layer region five is arranged on the insulating board and is adjacent to the third metal layer region four along the Y direction, and the third metal layer region five is adjacent to the third metal layer region one, the third metal layer region two, and the third metal layer region three along the X direction, and the third upper bridge arm power chip is also electrically connected to the third metal layer region five through a metal lead;

[0062] The third metal layer region 6 is disposed on the insulating board and is adjacent to the third metal layer region 4 along the Y direction, and the third metal layer region 6 is adjacent to the third metal layer region 5 along the X direction;

[0063] The third metal layer region seven is disposed on the insulating board and is adjacent to the third metal layer region six along the Y direction, and the third metal layer region seven is adjacent to the third metal layer region five along the X direction;

[0064] The third lower bridge arm power chip is arranged on the third metal layer region five, and the third lower bridge arm power chip is electrically connected to the third metal layer region four, the third metal layer region six, and the third metal layer region seven through metal leads respectively;

[0065] A third input DC negative electrode pin is disposed on a third metal layer region 4;

[0066] The third lower bridge arm power chip gate pin is arranged on the third metal layer area six;

[0067] The third lower bridge arm power chip source pin is arranged on the third metal layer area seven;

[0068] The third output AC electrode pin is arranged on the third metal layer region five.

[0069] Preferably, the second phase half-bridge circuit structure further includes:

[0070] The third decoupling capacitor is electrically connected to the third metal layer region 1 and the third metal layer region 4, and the third decoupling capacitor, the third input DC positive electrode pin, and the third input DC negative electrode pin are on the same X-direction straight line.

[0071] Preferably, the third metal layer region 2 is arranged in a strip shape along the X direction, and the third metal layer region 3 is arranged in a strip shape along the X direction; or the third metal layer region 6 is arranged in a strip shape along the Y direction, and the third metal layer region 7 is arranged in a strip shape along the Y direction.

[0072] Preferably, the power module further comprises:

[0073] The fourth metal layer region 1 is arranged on the insulating plate between the first-phase half-bridge circuit structure and the second-phase half-bridge circuit structure, and the fourth metal layer region 1 is arranged in a long strip shape along the Y direction;

[0074] The fourth metal layer region 2 is arranged on the insulating plate between the first-phase half-bridge circuit structure and the second-phase half-bridge circuit structure, the fourth metal layer region 2 is arranged adjacent to the fourth metal layer region 1 along the Y direction, and the fourth metal layer region 2 is arranged in a long strip shape along the Y direction;

[0075] The temperature-sensitive resistor is electrically connected to the fourth metal layer region 1 and the fourth metal layer region 2.

[0076] In this way, the structure of the third-phase board bridge circuit can also achieve high-speed switching while improving the performance of the two-phase circuit and the consistency of the switching action.

[0077] Beneficial Effects

[0078] The three-phase half-bridge circuit topology power module of the embodiment of this specification, by setting the position relationship of the metal layer area corresponding to the main power circuit (i.e., the upper bridge arm power chip and the lower bridge arm power chip) of the half-bridge circuit connection structure on the insulating plate, makes a large number of currents flowing in opposite directions and in parallel in the main power circuit of the power module, and the adjacent design based on this makes the magnetic field generated by the current flow in the power module offset each other, thereby reducing the parasitic inductance of the circuit. When the parasitic inductance of the power module is reduced, the voltage spike of the power module switching transient will be reduced, thereby making the switching speed of the power module faster, and when the switching speed of the power module is faster, the loss of the power module in the switching transient is also lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 A top view of a power module provided in an embodiment of this specification;

[0080] Figure 2 A schematic diagram of a metal layer area of ​​a power module provided in an embodiment of this specification;

[0081] Figure 3 A schematic diagram of the overall structure of a power module provided in an embodiment of this specification;

[0082] Figure 4 A circuit connection structure diagram of a first upper bridge arm power chip and a first lower bridge arm power chip provided in an embodiment of this specification;

[0083] Figure 5 A circuit connection structure diagram of a second upper bridge arm power chip and a second lower bridge arm power chip provided in an embodiment of this specification;

[0084] Figure 6 A circuit connection structure diagram of the third upper bridge arm power chip and the third lower bridge arm power chip provided in an embodiment of this specification. DETAILED DESCRIPTION

[0085] Embodiments of the present specification will be described in more detail below with reference to the accompanying drawings.

[0086] Embodiment 1:

[0087] A three-phase half-bridge circuit topology power module, such as Figure 1 As shown, it includes: an insulating board 1, a first-phase half-bridge circuit structure, a second-phase half-bridge circuit structure and a third-phase half-bridge circuit structure arranged in sequence along the X direction on the insulating board 1, and a temperature-sensitive resistor 4 arranged on the insulating board 1, wherein

[0088] The first phase half-bridge circuit structure includes: a first metal layer region 110, a first input DC positive electrode pin 10 and a first upper bridge arm power chip arranged on the first metal layer region 110, a first metal layer region 5 120, a first output AC electrode pin 12 and a first lower bridge arm power chip arranged on the first metal layer region 5 120, a first metal layer region 4 130, and a first input DC negative electrode pin 11 arranged on the first metal layer region 4 130, the first metal layer region 110 is arranged adjacent to the first metal layer region 4 130 along the X direction, the first metal layer region 5 120 is arranged adjacent to the first metal layer region 110 along the direction opposite to the X direction, and is also arranged adjacent to the first metal layer region 4 130 along the Y direction;

[0089] The second-phase half-bridge circuit structure and the third-phase half-bridge circuit structure are both symmetrical to the first-phase half-bridge circuit structure.

[0090] Based on such a compact and symmetrical design, the three-phase half-bridge circuit topology power module achieves higher working efficiency. Taking the first phase half-bridge circuit structure as an example, when calculating the parasitic inductance of the main power loop of the half-bridge circuit, the current enters the first metal layer area 110 from the first input DC positive electrode pin 10, passes through the first upper bridge arm power chip MOS1 and the metal lead to enter the first metal layer area 5 120, and then passes through the first lower bridge arm power chip MOS2 and the metal lead to enter the first metal layer area 4 130, and finally flows out through the first input DC negative electrode pin 11. The main power loop is folded in half, and the currents that are parallel and opposite in direction close together cause the magnetic fields generated by the current flow to cancel each other, thereby greatly reducing the parasitic inductance of the loop. In addition, the in-situ layout of the decoupling capacitor 2 absorbs the voltage spikes of the fast switching transient, and the fast switching performance of the power module is greatly improved.

[0091] like Figure 2 As shown, the first upper bridge arm circuit structure includes: a first metal layer region 110, a first metal layer region 2 111, and a first metal layer region 3 112. Figure 1 The first upper bridge arm circuit structure also includes: a first upper bridge arm power chip MOS1, a first input DC positive electrode pin 10, a first upper bridge arm power chip gate pin 13 and a first upper bridge arm power chip source pin 14.

[0092] The first metal layer region 110 is disposed on the insulating plate 1. One side of the first metal layer region 110 is parallel to and close to the first long side of the insulating plate 1.

[0093] The second first metal layer region 111 is disposed on the insulating board 1 and is adjacent to the first metal layer region 110 along the Y direction.

[0094] The first metal layer region three 112 is disposed on the insulating plate 1 and is disposed adjacent to the first metal layer region two 111 along the Y direction. One side of the first metal layer region three 112 is parallel to and close to the second long side of the insulating plate 1 .

[0095] The first upper bridge arm power chip MOS1 is disposed on the first metal layer region 110, and the first upper bridge arm power chip MOS1 is electrically connected to the first metal layer region 2 111 and the first metal layer region 3 112 through metal leads 3. The first upper bridge arm power chip MOS1 is disposed at the first end of the first metal layer region 110 in the Y direction, and the first input DC positive electrode pin 10 is disposed at the second end of the first metal layer region 110 in the Y direction.

[0096] The first input DC positive electrode pin 10 is disposed on the first metal layer region 110 .

[0097] The first upper bridge arm power chip gate pin 13 is disposed on the first metal layer region 2 111 .

[0098] The first upper bridge arm power chip source pin 14 is disposed on the first metal layer region 3 112. The first upper bridge arm power chip gate pin 13 and the first upper bridge arm power chip source pin 14 are located on the same Y-direction straight line.

[0099] like Figure 2 As shown, the first lower bridge arm circuit structure includes: a first metal layer region four 130, a first metal layer region five 120, a first metal layer region six 122, and a first metal layer region seven 121. Figure 1 The first lower bridge arm circuit structure also includes: a first lower bridge arm power chip MOS2, a first input DC negative electrode pin 11, a first lower bridge arm power chip gate pin 16, a first lower bridge arm power chip source pin 15 and a first output AC electrode pin 12.

[0100] The first metal layer region 4 130 is disposed on the insulating plate 1 and is disposed adjacent to the first metal layer region 1 110 along the reverse direction X. One side of the first metal layer region 4 130 is parallel to and close to the first long side of the insulating plate 1.

[0101] The first metal layer region five 120 is disposed on the insulating plate 1 and is adjacent to the first metal layer region four 130 along the Y direction, and is adjacent to the first metal layer region one 110, the first metal layer region two 111, and the first metal layer region three 112 along the X direction, and the first upper bridge arm power chip MOS1 is also electrically connected to the first metal layer region five 120 through the metal lead 3. One side of the first metal layer region five 120 is parallel to and close to the second long side of the insulating plate 1.

[0102] The first metal layer region six 122 is disposed on the insulating board 1 and is adjacent to the first metal layer region four 130 along the Y direction, and the first metal layer region six 122 is adjacent to the first metal layer region five 120 along the X direction.

[0103] The first metal layer region seven 121 is disposed on the insulating board 1 and is adjacent to the first metal layer region six 122 along the Y direction, and the first metal layer region seven 121 is adjacent to the first metal layer region five 120 along the X direction.

[0104] The first lower bridge arm power chip MOS2 is disposed on the first metal layer region five 120, and the first lower bridge arm power chip MOS2 is electrically connected to the first metal layer region four 130, the first metal layer region six 122, and the first metal layer region seven 121 through the metal lead 3 respectively.

[0105] The first input DC negative electrode pin 11 is disposed on the first metal layer region 4 130 .

[0106] The first lower bridge arm power chip gate pin 16 is disposed on the first metal layer region six 122 .

[0107] The first lower bridge arm power chip source pin 15 is disposed on the first metal layer region seven 121. The first lower bridge arm power chip gate pin 16 and the first lower bridge arm power chip source pin 15 are located on the same Y-direction straight line.

[0108] The first output AC electrode pin 12 is disposed on the first metal layer region 5 120. The first input DC negative electrode pin 11 and the first output AC electrode pin 12 are located on the same Y-direction straight line. The first output AC electrode pin 12 is disposed at the first end of the first metal layer region 5 120 in the Y direction, and the first lower bridge arm power chip MOS2 is disposed at the second end of the first metal layer region 5 120 in the Y direction.

[0109] The circuit connection structure of the first upper bridge arm power chip and the first lower bridge arm power chip is as follows: Figure 4 As shown, it includes a port P1 corresponding to the first input DC positive electrode pin 10, a port N1 corresponding to the first input DC negative electrode pin 11, and a port AC1 corresponding to the first output AC electrode pin 12. Figure 1 , this embodiment is equivalent to Figure 4 The circuit connection structure of the first half-phase bridge in the circuit is folded in half and arranged closely on the insulating plate 1, which can greatly reduce the parasitic inductance in the power module. When the parasitic inductance of the power module is reduced, the voltage spike of the power module switching transient will be reduced, thereby making the switching speed of the power module faster. When the switching speed of the power module is faster, the loss of the power module in the switching transient is also lower.

[0110] In addition, if Figure 1and Figure 3 As shown, the first phase half-bridge circuit structure further includes: a first decoupling capacitor 2.

[0111] The first decoupling capacitor 2 is electrically connected to the first metal layer region 110 and the first metal layer region 4 130 , and the first decoupling capacitor 2 and the first input DC positive electrode pin 10 and the first input DC negative electrode pin 11 are on the same X-direction straight line.

[0112] In this embodiment, the first decoupling capacitor 2 is arranged close to the first input DC positive electrode pin 10 and the first input DC negative electrode pin 11. By arranging the decoupling capacitor between the DC positive and negative electrodes inside the power module, the voltage spike generated during fast switching is absorbed in situ, thereby improving the switching speed of the power module. Compared with the solution where the decoupling capacitor is arranged outside the module, the absorption effect is obvious, and the number of components on the PCB circuit board is also reduced.

[0113] In addition, if Figure 2 As shown, the first metal layer region 2 111 is arranged in a long strip shape along the X direction, the first metal layer region 3 112 is arranged in a long strip shape along the X direction, the first metal layer region 6 122 is arranged in a long strip shape along the Y direction, and the first metal layer region 7 121 is arranged in a long strip shape along the Y direction.

[0114] This setting enables Kelvin contact between the input-side gate-source and the input-side drain-source loop of the power module, thereby reducing the negative feedback effect caused by the output-side loop coupling through the common-source path during high-speed switching of the power module, and ultimately further improving the high-speed switching performance of the power module.

[0115] Furthermore, the second-phase half-bridge circuit structure includes a second upper bridge arm circuit structure and a second lower bridge arm circuit structure. The second upper bridge arm circuit structure and the second lower bridge arm circuit structure are arranged side by side in the X direction.

[0116] like Figure 2 As shown, the second upper bridge arm circuit structure includes: a second metal layer region 1 210, a second metal layer region 211, and a second metal layer region 3 212. Figure 1 The second upper bridge arm circuit structure also includes: a second upper bridge arm power chip MOS3, a second input DC positive electrode pin 20, a second upper bridge arm power chip gate pin 23 and a second upper bridge arm power chip source pin 24.

[0117] The second metal layer region 1 210 is disposed on the insulating plate 1. One side of the second metal layer region 1 210 is parallel to and close to the first long side of the insulating plate 1.

[0118] The second metal layer region 211 is disposed on the insulating board 1 and is adjacent to the second metal layer region 1 210 along the Y direction.

[0119] The second metal layer region three 212 is disposed on the insulating plate 1 and is disposed adjacent to the second metal layer region two 211 along the Y direction. One side of the second metal layer region three 212 is parallel to and close to the second long side of the insulating plate 1 .

[0120] The second upper bridge arm power chip MOS3 is disposed on the second metal layer region 1 210, and the second upper bridge arm power chip MOS3 is electrically connected to the second metal layer region 2 211 and the second metal layer region 3 212 through the metal lead 3. The second upper bridge arm power chip MOS3 is disposed at the first end of the second metal layer region 1 210 in the Y direction, and the second input DC positive electrode pin 20 is disposed at the second end of the second metal layer region 1 210 in the Y direction.

[0121] The second input DC positive electrode pin 20 is disposed on the second metal layer region 1 210 .

[0122] The second upper bridge arm power chip gate pin 23 is disposed on the second metal layer region 211 .

[0123] The second upper bridge arm power chip source pin 24 is disposed on the second metal layer region 3 212. The second upper bridge arm power chip gate pin 23 and the second upper bridge arm power chip source pin 24 are located on the same Y-direction straight line.

[0124] like Figure 2 As shown, the second lower bridge arm circuit structure includes: a second metal layer region four 230, a second metal layer region five 220, a second metal layer region six 222, and a second metal layer region seven 221. Figure 1 The second lower bridge arm circuit structure also includes: a second lower bridge arm power chip MOS4, a second input DC negative electrode pin 21, a second lower bridge arm power chip gate pin 26, a second lower bridge arm power chip source pin 25 and a second output AC electrode pin 22.

[0125] The second metal layer region 230 is disposed on the insulating plate 1 and is adjacent to the second metal layer region 1 210 along the reverse direction X. One side of the second metal layer region 230 is parallel to and close to the first long side of the insulating plate 1.

[0126] The second metal layer region five 220 is disposed on the insulating plate 1 and is adjacent to the second metal layer region four 230 along the Y direction, and is adjacent to the second metal layer region one 210, the second metal layer region two 211, and the second metal layer region three 212 along the X direction, and the second upper bridge arm power chip MOS3 is also electrically connected to the second metal layer region five 220 through the metal lead 3. One side of the second metal layer region five 220 is parallel to and close to the second long side of the insulating plate 1.

[0127] The second metal layer region six 222 is disposed on the insulating board 1 and is adjacent to the second metal layer region four 230 along the Y direction, and the second metal layer region six 222 is adjacent to the second metal layer region five 220 along the X direction.

[0128] The second metal layer region seven 221 is disposed on the insulating board 1 and is adjacent to the second metal layer region six 222 along the Y direction, and the second metal layer region seven 221 is adjacent to the second metal layer region five 220 along the X direction.

[0129] The second lower bridge arm power chip MOS4 is disposed on the second metal layer region five 220, and the second lower bridge arm power chip MOS4 is electrically connected to the second metal layer region four 230, the second metal layer region six 222, and the second metal layer region seven 221 through the metal lead 3 respectively.

[0130] The second input DC negative electrode pin 21 is disposed on the second metal layer region 4 230 .

[0131] The second lower bridge arm power chip gate pin 26 is disposed on the second metal layer region six 222 .

[0132] The second lower bridge arm power chip source pin 25 is disposed on the second metal layer region seven 221. The second lower bridge arm power chip gate pin 26 and the second lower bridge arm power chip source pin 25 are located on the same Y-direction straight line.

[0133] The second output AC electrode pin 22 is disposed on the second metal layer region 5 220. The second input DC negative electrode pin 21 and the second output AC electrode pin 22 are located on the same Y-direction straight line. The second output AC electrode pin 22 is disposed at the first end of the second metal layer region 5 220 in the Y direction, and the second lower bridge arm power chip MOS4 is disposed at the second end of the second metal layer region 5 220 in the Y direction.

[0134] The circuit connection structure of the second upper bridge arm power chip and the second lower bridge arm power chip is as follows: Figure 4 As shown, it includes a port P2 corresponding to the second input DC positive electrode pin 20, a port N2 corresponding to the second input DC negative electrode pin 21, and a port AC2 corresponding to the second output AC electrode pin 22. Figure 1 As shown, this embodiment is equivalent to Figure 4 The circuit connection structure of the second half-phase bridge in the power module is folded in half and arranged closely on the insulating plate 1, which can greatly reduce the parasitic inductance in the power module. When the parasitic inductance of the power module is reduced, the voltage spike of the power module switching transient will be reduced, thereby making the switching speed of the power module faster. When the switching speed of the power module is faster, the loss of the power module in the switching transient is also lower.

[0135] In addition, if Figure 1and Figure 3 As shown, the second phase half-bridge circuit structure further includes: a second decoupling capacitor 8.

[0136] The second decoupling capacitor 8 is electrically connected to the second metal layer region 1 210 and the second metal layer region 4 230 , and the second decoupling capacitor 8 and the second input DC positive electrode pin 20 and the second input DC negative electrode pin 21 are on the same X-direction straight line.

[0137] In this embodiment, the second decoupling capacitor 8 is arranged close to the second input DC positive electrode pin 20 and the second input DC negative electrode pin 21. By arranging the decoupling capacitor between the DC positive and negative electrodes inside the power module, the voltage spike generated during fast switching is absorbed in situ, thereby improving the switching speed of the power module. Compared with the solution where the decoupling capacitor is arranged outside the module, the absorption effect is obvious, and the number of components on the PCB circuit board is also reduced.

[0138] In addition, if Figure 2 As shown, the second metal layer region 211 is arranged in a long strip shape along the X direction, the second metal layer region 3 212 is arranged in a long strip shape along the X direction, the second metal layer region 6 222 is arranged in a long strip shape along the Y direction, and the second metal layer region 7 221 is arranged in a long strip shape along the Y direction.

[0139] This setting enables Kelvin contact between the input-side gate-source and the input-side drain-source loop of the power module, thereby reducing the negative feedback effect caused by the output-side loop coupling through the common-source path during high-speed switching of the power module, and ultimately further improving the high-speed switching performance of the power module.

[0140] Furthermore, the third phase half-bridge circuit structure includes a third upper bridge arm circuit structure and a third lower bridge arm circuit structure. The third upper bridge arm circuit structure and the third lower bridge arm circuit structure are arranged side by side in the X direction.

[0141] like Figure 2 As shown, the third upper bridge arm circuit structure includes: a third metal layer region 1 310, a third metal layer region 2 311, and a third metal layer region 312. Figure 1 The third phase half-bridge circuit structure also includes: a third upper bridge arm power chip MOS5, a third input DC positive electrode pin 30, a third upper bridge arm power chip gate pin 33 and a third upper bridge arm power chip source pin 34.

[0142] The third metal layer region 1 310 is disposed on the insulating board 1 .

[0143] The third metal layer region 2 311 is disposed on the insulating plate 1 and is adjacent to the third metal layer region 1 310 along the Y direction. One side of the third metal layer region 1 310 is parallel to and close to the first long side of the insulating plate 1 .

[0144] The third metal layer region three 312 is disposed on the insulating board 1 and is adjacent to the third metal layer region two 311 along the Y direction.

[0145] The third upper bridge arm power chip MOS5 is arranged on the third metal layer region 1 310, and the third upper bridge arm power chip MOS5 is electrically connected to the third metal layer region 2 311 and the third metal layer region 3 312 through the metal lead 3. One side of the third metal layer region 3 312 is parallel to and close to the second long side of the insulating plate 1. The third upper bridge arm power chip MOS5 is arranged at the first end of the third metal layer region 1 310 in the Y direction, and the third input DC positive electrode pin 30 is arranged at the second end of the third metal layer region 1 310 in the Y direction.

[0146] The third input DC positive electrode pin 30 is disposed on the third metal layer region 1 310 .

[0147] The third upper bridge arm power chip gate pin 33 is disposed on the third metal layer region 2 311 .

[0148] The third upper bridge arm power chip source pin 34 is arranged on the third metal layer region 312. The third upper bridge arm power chip gate pin 33 and the third upper bridge arm power chip source pin 34 are located on the same Y-direction straight line. The first upper bridge arm power chip source pin 14, the second upper bridge arm power chip source pin 24 and the third upper bridge arm power chip source pin 34 are located on the same X-direction straight line.

[0149] like Figure 2 As shown, the third lower bridge arm circuit structure includes: a third metal layer region 4 330, a third metal layer region 5 320, a third metal layer region 6 322, and a third metal layer region 7 321. Figure 1 The third lower bridge arm circuit structure also includes: a third lower bridge arm power chip MOS6, a third input DC negative electrode pin 31, a third lower bridge arm power chip gate pin 36, a third lower bridge arm power chip source pin 35 and a third output AC electrode pin 32.

[0150] The third metal layer region 4 330 is disposed on the insulating plate 1 and is adjacent to the third metal layer region 1 310 along the reverse direction X. One side of the third metal layer region 4 330 is parallel to and close to the first long side of the insulating plate 1.

[0151] The third metal layer region five 320 is disposed on the insulating plate 1 and is adjacent to the third metal layer region four 330 along the Y direction, and is adjacent to the third metal layer region one 310, the third metal layer region two 311, and the third metal layer region three 312 along the X direction, and the third upper bridge arm power chip MOS5 is also electrically connected to the third metal layer region five 320 through the metal lead 3. One side of the third metal layer region five 320 is parallel to and close to the second long side of the insulating plate 1.

[0152] The third metal layer region six 322 is disposed on the insulating board 1 and is adjacent to the third metal layer region four 330 along the Y direction, and the third metal layer region six 322 is adjacent to the third metal layer region five 320 along the X direction.

[0153] The third metal layer region seven 321 is disposed on the insulating board 1 and is adjacent to the third metal layer region six 322 along the Y direction, and the third metal layer region seven 321 is adjacent to the third metal layer region five 320 along the X direction.

[0154] The third lower bridge arm power chip MOS6 is disposed on the third metal layer region five 320, and the third lower bridge arm power chip MOS6 is electrically connected to the third metal layer region four 330, the third metal layer region six 322, and the third metal layer region seven 321 through metal leads 3 respectively.

[0155] The third input DC negative electrode pin 31 is disposed on the third metal layer region 430. The first input DC positive electrode pin 10, the first input DC negative electrode pin 11, the second input DC positive electrode pin 20, the second input DC negative electrode pin 21, the third input DC positive electrode pin 30 and the third input DC negative electrode pin 31 are located on the same X-direction straight line.

[0156] The third lower bridge arm power chip gate pin 36 is disposed on the third metal layer region six 322 .

[0157] The third lower bridge arm power chip source pin 35 is disposed on the third metal layer region seven 321. The third lower bridge arm power chip gate pin 36 and the third lower bridge arm power chip source pin 35 are located on the same Y-direction straight line.

[0158] The third output AC electrode pin 32 is arranged on the third metal layer region five 320. The third input DC negative electrode pin 31 and the third output AC electrode pin 32 are located on the same Y-direction straight line. The first output AC electrode pin 12, the first upper bridge arm power chip gate pin 13, the second output AC electrode pin 22, the second upper bridge arm power chip gate pin 23, the third output AC electrode pin 32 and the third upper bridge arm power chip gate pin 33 are located on the same X-direction straight line. The third output AC electrode pin 32 is arranged at the first end of the third metal layer region five 320 in the Y direction, and the third lower bridge arm power chip MOS6 is arranged at the second end of the third metal layer region five 320 in the Y direction.

[0159] The circuit connection structure of the third upper bridge arm power chip and the third lower bridge arm power chip is as follows: Figure 4 As shown, it includes a port P3 corresponding to the third input DC positive electrode pin 30, a port N3 corresponding to the third input DC negative electrode pin 31, and a port AC3 corresponding to the third output AC electrode pin 32. Figure 1 As shown, this embodiment is equivalent to Figure 4 The circuit connection structure of the third half-phase bridge in the circuit is folded in half on the insulating plate 1 and arranged closely, which can greatly reduce the parasitic inductance in the power module. When the parasitic inductance of the power module is reduced, the voltage spike of the power module switching transient will be reduced, thereby making the switching speed of the power module faster. When the switching speed of the power module is faster, the loss of the power module in the switching transient is also lower.

[0160] In addition, if Figure 1 and Figure 3 As shown, the second phase half-bridge circuit structure further includes: a third decoupling capacitor 9.

[0161] The third decoupling capacitor 9 is electrically connected to the third metal layer region 1 310 and the third metal layer region 4 330 , and the third decoupling capacitor 9 and the third input DC positive electrode pin 30 and the third input DC negative electrode pin 31 are on the same X-direction straight line.

[0162] In this embodiment, the third decoupling capacitor 9 is arranged close to the third input DC positive electrode pin 30 and the third input DC negative electrode pin 31. By arranging the decoupling capacitor between the DC positive and negative electrodes inside the power module, the voltage spike generated during fast switching is absorbed in situ, thereby improving the switching speed of the power module. Compared with the solution where the decoupling capacitor is arranged outside the module, the absorption effect is obvious, and the number of components on the PCB circuit board is also reduced.

[0163] In addition, if Figure 2As shown, the third metal layer region 2 311 is arranged in a strip shape along the X direction, the third metal layer region 312 is arranged in a strip shape along the X direction, the third metal layer region 6 322 is arranged in a strip shape along the Y direction, and the third metal layer region 7 321 is arranged in a strip shape along the Y direction.

[0164] This setting enables Kelvin contact between the input-side gate-source and the input-side drain-source loop of the power module, thereby reducing the negative feedback effect caused by the output-side loop coupling through the common-source path during high-speed switching of the power module, and ultimately further improving the high-speed switching performance of the power module.

[0165] Further, such as Figure 2 As shown, the power module in this embodiment further includes: a fourth metal layer region 1 7, a fourth metal layer region 2 6, and a reference Figure 1 , the power module in this embodiment also includes a temperature-sensitive resistor 4.

[0166] The fourth metal layer region 1 7 is disposed on the insulating board 1 between the first-phase half-bridge circuit structure and the second-phase half-bridge circuit structure, and the fourth metal layer region 1 7 is disposed in a long strip shape along the Y direction.

[0167] The fourth metal layer region 2 6 is arranged on the insulating plate 1 between the first phase half-bridge circuit structure and the second phase half-bridge circuit structure. The fourth metal layer region 2 6 is arranged adjacent to the fourth metal layer region 1 7 along the Y direction, and the fourth metal layer region 2 6 is arranged in a long strip shape along the Y direction.

[0168] The temperature-sensitive resistor 4 is electrically connected to the fourth metal layer region 1 7 and the fourth metal layer region 2 6 .

[0169] This arrangement makes the temperature-sensitive resistor 4 closer to the power chip, thereby improving the accuracy of measuring the temperature of the power chip inside the power module.

[0170] Although some embodiments of the present specification are shown in the drawings, it should be understood that the present specification can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein. Instead, these embodiments are provided for a more thorough and complete understanding of the present specification. It should be understood that the drawings and embodiments of the present specification are only for exemplary purposes and are not intended to limit the scope of protection of the present specification.

Claims

1. A three-phase half-bridge circuit topology power module, characterized in that: include: An insulating board (1), and a first-phase half-bridge circuit structure, a second-phase half-bridge circuit structure and a third-phase half-bridge circuit structure which are arranged on the insulating board (1) and arranged in sequence along the X direction; and a temperature-sensitive resistor (4) arranged on the insulating plate (1), wherein: The first phase half-bridge circuit structure comprises: a first metal layer region one (110), a first input DC positive electrode pin (10) and a first upper bridge arm power chip MOS1 arranged on the first metal layer region one (110), a first metal layer region five (120), a first output AC electrode pin (12) and a first lower bridge arm power chip MOS2 arranged on the first metal layer region five (120), a first metal layer region four (130), and a first input DC negative electrode pin (11) arranged on the first metal layer region four (130), the first metal layer region one (110) being arranged adjacent to the first metal layer region four (130) along the X direction, the first metal layer region five (120) being adjacent to the first metal layer region one (110) along the direction opposite to the X direction, and also being adjacent to the first metal layer region four (130) along the Y direction; The first phase half-bridge circuit structure also includes: A first upper bridge arm circuit structure, a first lower bridge arm circuit structure, and a first decoupling capacitor (2), wherein: The first upper bridge arm circuit structure further includes: A first metal layer region 2 (111), arranged on the insulating plate (1) and adjacent to the first metal layer region 1 (110) along the Y direction; A first metal layer region three (112), arranged on the insulating plate (1) and adjacent to the first metal layer region two (111) along the Y direction; The first upper bridge arm power chip MOS1 is electrically connected to the first metal layer region 2 (111) and the first metal layer region 3 (112) respectively through metal leads (3); A first upper bridge arm power chip gate pin (13) is arranged on the first metal layer region 2 (111); A first upper bridge arm power chip source pin (14) is arranged on the first metal layer region three (112); The first lower bridge arm circuit structure further includes: The first metal layer region 2 (111) and the first metal layer region 3 (112) are arranged adjacent to each other, and the first upper bridge arm power chip MOS1 is also electrically connected to the first metal layer region 5 (120) through a metal lead (3); The first metal layer region six (122) is arranged on the insulating plate (1) and is adjacent to the first metal layer region four (130) along the Y direction, and the first metal layer region six (122) is adjacent to the first metal layer region five (120) along the X direction; The first metal layer region seven (121) is arranged on the insulating plate (1) and is adjacent to the first metal layer region six (122) along the Y direction, and the first metal layer region seven (121) is adjacent to the first metal layer region five (120) along the X direction; The first lower bridge arm power chip MOS2 is electrically connected to the first metal layer region four (130), the first metal layer region six (122), and the first metal layer region seven (121) respectively through metal leads (3); A first lower bridge arm power chip gate pin (16) is arranged on the first metal layer region six (122); A first lower bridge arm power chip source pin (15) is arranged on the first metal layer area seven (121); The first decoupling capacitor (2) is electrically connected to the first metal layer region 1 (110) and the first metal layer region 4 (130), and the first decoupling capacitor (2) and the first input DC positive electrode pin (10) and the first input DC negative electrode pin (11) are on the same X-direction straight line.

2. The three-phase half-bridge circuit topology power module according to claim 1, characterized in that: The first metal layer region 2 (111) is arranged in a long strip shape along the X direction, and the first metal layer region 3 (112) is arranged in a long strip shape along the X direction; or The first metal layer region six (122) is arranged in a long strip shape along the Y direction, and the first metal layer region seven (121) is arranged in a long strip shape along the Y direction.

3. The three-phase half-bridge circuit topology power module according to claim 1, characterized in that: The second phase half-bridge circuit structure includes a second upper bridge arm circuit structure and a second lower bridge arm circuit structure; The second upper bridge arm circuit structure comprises: A second metal layer region 1 (210) is arranged on the insulating plate (1); A second metal layer region 2 (211), arranged on the insulating plate (1) and adjacent to the second metal layer region 1 (210) along the Y direction; A second metal layer region three (212), arranged on the insulating plate (1) and adjacent to the second metal layer region two (211) along the Y direction; A second upper bridge arm power chip MOS3 is arranged on the second metal layer region 1 (210), and the second upper bridge arm power chip MOS3 is electrically connected to the second metal layer region 2 (211) and the second metal layer region 3 (212) respectively through metal leads (3); A second input DC positive electrode pin (20) is arranged on the second metal layer region 1 (210); A second upper bridge arm power chip gate pin (23) is arranged on the second metal layer region 2 (211); A second upper bridge arm power chip source pin (24), arranged on the second metal layer region three (212); The second lower bridge arm circuit structure comprises: A second metal layer region four (230) is arranged on the insulating plate (1) and is arranged adjacent to the second metal layer region one (210) in the reverse direction X; The second metal layer region five (220) is arranged on the insulating plate (1) and is adjacent to the second metal layer region four (230) along the Y direction, and the second metal layer region five (220) is adjacent to the second metal layer region one (210), the second metal layer region two (211), and the second metal layer region three (212) along the X direction, and the second upper bridge arm power chip MOS3 is also electrically connected to the second metal layer region five (220) via a metal lead (3); The second metal layer region six (222) is arranged on the insulating plate (1) and is adjacent to the second metal layer region four (230) along the Y direction, and the second metal layer region six (222) is adjacent to the second metal layer region five (220) along the X direction; The second metal layer region seven (221) is arranged on the insulating plate (1) and is adjacent to the second metal layer region six (222) along the Y direction, and the second metal layer region seven (221) is adjacent to the second metal layer region five (220) along the X direction; The second lower bridge arm power chip MOS4 is arranged on the second metal layer region five (220), and the second lower bridge arm power chip MOS4 is electrically connected to the second metal layer region four (230), the second metal layer region six (222), and the second metal layer region seven (221) respectively through metal leads (3); A second input DC negative electrode pin (21), arranged on the second metal layer region four (230); A second lower bridge arm power chip gate pin (26) is arranged on the second metal layer region six (222); A second lower bridge arm power chip source pin (25), arranged on the second metal layer area seven (221); The second output AC electrode pin (22) is arranged on the second metal layer region five (220).

4. The three-phase half-bridge circuit topology power module according to claim 3, characterized in that: The second phase half-bridge circuit structure also includes: The second decoupling capacitor (8) is electrically connected to the second metal layer region one (210) and the second metal layer region four (230), and the second decoupling capacitor (8) and the second input DC positive electrode pin (20) and the second input DC negative electrode pin (21) are on the same X-direction straight line.

5. The three-phase half-bridge circuit topology power module according to claim 3, characterized in that: The second phase half-bridge circuit structure further includes: the second metal layer region 2 (211) is arranged in a long strip shape along the X direction, and the second metal layer region 3 (212) is arranged in a long strip shape along the X direction; or The second metal layer region six (222) is arranged in a long strip shape along the Y direction, and the second metal layer region seven (221) is arranged in a long strip shape along the Y direction.

6. The three-phase half-bridge circuit topology power module according to claim 1, characterized in that: The third-phase half-bridge circuit structure includes a third upper bridge arm circuit structure and a third lower bridge arm circuit structure; The third upper bridge arm circuit structure comprises: A third metal layer region 1 (310) is arranged on the insulating plate (1); A third metal layer region 2 (311), arranged on the insulating plate (1) and adjacent to the third metal layer region 1 (310) along the Y direction; A third metal layer region three (312), arranged on the insulating plate (1) and adjacent to the third metal layer region two (311) along the Y direction; A third upper bridge arm power chip MOS5 is arranged on the third metal layer region 1 (310), and the third upper bridge arm power chip MOS5 is electrically connected to the third metal layer region 2 (311) and the third metal layer region 3 (312) respectively through metal leads (3); A third input DC positive electrode pin (30) is arranged on the third metal layer region 1 (310); A third upper bridge arm power chip gate pin (33) is arranged on the third metal layer region 2 (311); A third upper bridge arm power chip source pin (34) is arranged on the third metal layer region three (312); The third lower bridge arm circuit structure comprises: A third metal layer region four (330) is arranged on the insulating plate (1) and is arranged adjacent to the third metal layer region one (310) in the reverse direction X; The third metal layer region five (320) is arranged on the insulating plate (1) and is adjacent to the third metal layer region four (330) along the Y direction, and the third metal layer region five (320) is adjacent to the third metal layer region one (310), the third metal layer region two (311), and the third metal layer region three (312) along the X direction, and the third upper bridge arm power chip MOS5 is also electrically connected to the third metal layer region five (320) through a metal lead (3); The third metal layer region six (322) is arranged on the insulating plate (1) and is adjacent to the third metal layer region four (330) along the Y direction, and the third metal layer region six (322) is adjacent to the third metal layer region five (320) along the X direction; The third metal layer region seven (321) is arranged on the insulating plate (1) and is adjacent to the third metal layer region six (322) along the Y direction, and the third metal layer region seven (321) is adjacent to the third metal layer region five (320) along the X direction; The third lower bridge arm power chip MOS6 is arranged on the third metal layer region five (320), and the third lower bridge arm power chip MOS6 is electrically connected to the third metal layer region four (330), the third metal layer region six (322), and the third metal layer region seven (321) respectively through metal leads (3); A third input DC negative electrode pin (31), arranged on the third metal layer region four (330); A third lower bridge arm power chip gate pin (36) is arranged on the third metal layer region six (322); A third lower bridge arm power chip source pin (35) is arranged on the third metal layer area seven (321); The third output AC electrode pin (32) is arranged on the third metal layer region five (320).

7. The three-phase half-bridge circuit topology power module according to claim 6, characterized in that: The third phase half-bridge circuit structure also includes: The third decoupling capacitor (9) is electrically connected to the third metal layer region one (310) and the third metal layer region four (330), and the third decoupling capacitor (9) and the third input DC positive electrode pin (30) and the third input DC negative electrode pin (31) are on the same X-direction straight line.

8. The three-phase half-bridge circuit topology power module according to claim 6, characterized in that: The third metal layer region 2 (311) is arranged in a long strip shape along the X direction, and the third metal layer region 3 (312) is arranged in a long strip shape along the X direction; or The third metal layer region six (322) is arranged in a long strip shape along the Y direction, and the third metal layer region seven (321) is arranged in a long strip shape along the Y direction.

9. The three-phase half-bridge circuit topology power module according to claim 4, characterized in that: The power module further comprises: A fourth metal layer region one (7) is arranged on the insulating plate (1) between the first phase half-bridge circuit structure and the second phase half-bridge circuit structure, and the fourth metal layer region one (7) is arranged in a long strip shape along the Y direction; A fourth metal layer region 2 (6) is arranged on the insulating plate (1) between the first phase half-bridge circuit structure and the second phase half-bridge circuit structure, the fourth metal layer region 2 (6) is arranged adjacent to the fourth metal layer region 1 (7) along the Y direction, and the fourth metal layer region 2 (6) is arranged in a long strip shape along the Y direction; The temperature-sensitive resistor (4) is electrically connected to the fourth metal layer region 1 (7) and the fourth metal layer region 2 (6).

Images