Control method for balanced power distribution of modular three-level grid-connected rectifiers in parallel

Abstract

The present application discloses a control method for balanced parallel power distribution of modular three-level grid-connected rectifiers, including: setting the module number through a dial switch, and the host computer setting the master and slave according to the module number; obtaining a given DC output voltage, starting each module separately in turn according to a double closed-loop control method and running to a steady state; sequentially closing the relay on the DC side according to the module number, and using the host's double closed loop to control the DC bus voltage of the entire system; estimating the total load output power, and realizing balanced distribution of the output power of each module through a load output power feedforward control method. The module parallel power balanced distribution method proposed in the present application has a small steady-state error and a fast dynamic response speed, avoiding the influence of sampling errors on power distribution in actual working conditions, and truly realizing the practical application needs of multi-module parallel connection under the conditions of common DC side and common AC side.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics applications, and in particular to a control method for parallel power balance distribution of modular three-level grid-connected rectifiers. Background Art

[0002] The technology of efficient, clean and stable power conversion is developing rapidly and is widely used in new energy power generation, electric vehicle charging, communication and military power supply, etc. Therefore, high-efficiency, high-reliability and large-capacity power converters have become a research hotspot.

[0003] In practical applications, the capacity of the power converter mainly depends on the power level of the key power device. In large-capacity applications, a single power device often cannot meet the power requirements, and multiple modules need to be connected in parallel, such as SVG, PCS and military high-voltage DC power supplies. When multiple SVG modules are connected in parallel, each module shares the AC side but not the DC side. Only power distribution needs to be considered between modules, and no circulation problems need to be considered. When multiple PCS modules are connected in parallel, each module shares the AC side and the DC side, but the DC side is connected to the busbar of the energy storage battery. It is necessary to consider power distribution and circulation, but it is not necessary to actively control the DC side output voltage, that is, the module works in the current source mode, and it is not necessary to consider the impact of the output voltage sampling error on the control loop. When multiple high-voltage DC power rectifier modules are connected in parallel, each module shares the AC side and the DC side, and the DC side voltage needs to be controlled by the master. The rectifier system needs to consider the impact of power distribution, circulation and sampling error on the control loop at the same time, and the control method becomes very complicated.

[0004] Therefore, how to achieve balanced power distribution when modular three-level grid-connected rectifiers are connected in parallel under the conditions of common DC side and common AC side is a technical problem that needs to be solved urgently in this field. Summary of the invention

[0005] In order to solve the above technical problems, this application proposes the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a control method for parallel power balance distribution of modular three-level grid-connected rectifiers, including:

[0007] The module number is set by the DIP switch, and the host computer sets the master and slave according to the module number;

[0008] Obtain a given DC output voltage, start each module individually in sequence according to the double closed-loop control method and run it to a steady state;

[0009] The relays on the DC side are attracted in sequence according to the module numbers, and the DC bus voltage of the entire system is controlled by the double closed loop of the host;

[0010] The total load output power is estimated, and the balanced distribution of the output power of each module is achieved through the load output power feedforward control method.

[0011] In a possible implementation, the module number is set by a DIP switch, and the host computer sets the master and slave according to the module number, including:

[0012] Manually adjust the DIP switch on the housing of each module to set the number of each module;

[0013] The host computer selects the module with the smallest number among all modules as the master, and the remaining modules are slaves.

[0014] In a possible implementation, the minimum value of the given DC output voltage satisfies that the modulation index is greater than a preset value, and the maximum value of the given DC output voltage is less than the withstand voltage of the DC side bus capacitor.

[0015] In a possible implementation, starting each module separately and in turn according to the dual closed-loop control method and running it to a steady state includes:

[0016] The voltage outer loop PI regulator calculates the current that needs to flow into the DC link capacitor to track the actual DC link voltage to the given DC link voltage;

[0017] Perform coordinate transformation on the AC input voltage and current to obtain the grid voltage and current in a two-phase stationary coordinate system;

[0018] The modulation voltage without zero-sequence voltage injection is calculated according to the current inner loop and the control equation. The current inner loop adopts DBC control and modulates the voltage u under the two-phase stationary coordinate. α and u β It is expressed as: ;

[0019] Where, L represents the inductance of the filter inductor, T s represents the control period, e α 、e β and i α 、i β are the grid voltage and current in the two-phase stationary coordinate system obtained by equal-power Clarke transformation; i α，ref 、i β,ref are the given currents in the two-phase stationary coordinate system respectively;

[0020] The three-phase grid voltages are sorted to obtain the intermediate grid voltage:

[0021] The intermediate grid voltage is denoted as e MID = mid(e A , e B , e C );

[0022] Half of the middle phase of the grid voltage is injected into the three-phase modulated voltage, so that the output DC voltage of each rectifier module can stably track the given voltage.

[0023] In a possible implementation, the relays on the DC side are sequentially attracted according to the module numbers, and the DC bus voltage of the entire system is controlled by a double closed loop of the host, including:

[0024] If the module number corresponds to a slave, after the bypass relay and the main relay are closed in sequence, the voltage outer loop of the slave is cut off, and the DC bus voltage of the entire system is controlled by the dual closed loop of the master;

[0025] If the module number corresponds to the host, after the bypass relay and the main relay are closed in sequence, the DC bus voltage of the entire system is controlled by the host's double closed loop.

[0026] In a possible implementation, the total load output power is estimated, and a load output power feedforward control method is used to achieve balanced distribution of the output power of each module, including:

[0027] The load output power of the entire system is estimated using the discretized digital controller system. The estimated load output power is expressed as:

[0028] ;

[0029] Among them, p L,ref (n+1) represents the load power estimated in the next control cycle, u d,ref (n-1) and i d,ref (n-1) respectively represent the given modulation voltage and current of the d-axis in the previous control cycle, u DC (n-1) and u DC (n-2) represents the DC side voltage sampled in the last and last two control cycles, respectively, p L (n-1) represents the load output power sampled in the previous control cycle, and C represents the capacitance of the DC side capacitor;

[0030] Substitute the historical load output power into the new load output power estimate for correction. The corrected load output power can be expressed as:

[0031] ;

[0032] in, and They represent the load power after the next control cycle and the previous control correction, respectively, L The weight factor representing the proportion of the historical load output power in the load output power after correction in the next control cycle;

[0033] The balanced distribution of the output power of each module is achieved through the load output power feedforward control method.

[0034] In a possible implementation, the control method of load output power feedforward to achieve balanced distribution of output power of each module includes:

[0035] The current of the DC side capacitor under no-load condition is obtained. The calculation formula of the DC side current is:

[0036] ;in is the given current that needs to flow into the DC link capacitor, are the proportional and integral coefficients of the PI regulator respectively, are the given and actual DC link capacitor voltages, respectively, and s represents the unit step response in the time domain;

[0037] The output power of each module rectifier is divided in detail according to the power flowing out of the rectifier DC side, the power flowing into the rectifier from the AC side and the power flowing into the DC side capacitor combined with the current of the DC side capacitor and the corrected load output power;

[0038] When there is a deviation in the sampling value of the output voltage of each module, a multi-module load feedforward power distribution method is adopted.

[0039] In a possible implementation, the power flowing out of the DC side of the rectifier is , the power flowing into the rectifier from the AC side and the power flowing into the DC capacitor Respectively expressed as:

[0040] , ,

[0041] in, Indicates the power flowing into the DC side load, Respectively represent the three-phase grid voltage; Represent the three-phase alternating current, and Respectively represent the d-axis grid voltage and current;

[0042] According to the power conversion relationship of the rectifier , get the given current of the AC input current d axis , the calculation formula is:

[0043] .

[0044] In a possible implementation, the method for distributing multi-module load feedforward power includes:

[0045] Adjust the position of the load current sensor that outputs a voltage signal from inside the module to the output end of the entire system;

[0046] delivering the output signal of the load current sensor to each module;

[0047] Power is distributed according to the master and slave devices respectively.

[0048] In a possible implementation, the performing power distribution according to the master and the slave respectively includes:

[0049] If the module is the host, it runs in voltage source mode, uses the voltage outer loop to control the DC bus output voltage of the entire system, and evenly distributes the load output power. The given current of the AC input current d axis is expressed as:

[0050] ;

[0051] Where N is the number of modules connected in parallel;

[0052] If the module is a slave, it runs in current source mode and evenly distributes the load output power. The given current of the AC input current d axis is expressed as:

[0053] .

[0054] Compared with the prior art, the beneficial effects of this application are:

[0055] When multiple three-level rectifier modules with a common DC side and a common AC side are connected in parallel, the output power of each module can be balanced, the power flow between modules introduced by the output voltage sampling error in actual working conditions can be suppressed, and the increase in loss and reduction in efficiency caused by power imbalance can be prevented.

[0056] The present application feeds forward the total load output power directly to the AC side input of each module, skipping the hysteresis of the voltage outer loop, significantly improving the response speed of the rectifier system, and being able to better handle dynamic loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A flow chart of a control method for parallel power balance distribution of modular three-level grid-connected rectifiers provided in an embodiment of the present application;

[0058] Figure 2 A main circuit diagram of a single three-level rectifier module provided in an embodiment of the present application;

[0059] Figure 3A main circuit diagram of multiple three-level rectifier modules connected in parallel provided in an embodiment of the present application;

[0060] Figure 4 A control block diagram of a host module in a rectifier system provided in an embodiment of the present application;

[0061] Figure 5 A control block diagram of a slave module in a rectifier system provided in an embodiment of the present application;

[0062] Figure 6 A power exchange relationship diagram of a rectifier system provided in an embodiment of the present application;

[0063] Figure 7 A steady-state experimental waveform diagram provided in an embodiment of the present application;

[0064] Figure 8 A dynamic experimental waveform diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0065] The present solution is described below in conjunction with the accompanying drawings and specific implementation methods.

[0066] Figure 1 A flow chart of a control method for parallel power balance distribution of modular three-level grid-connected rectifiers provided in an embodiment of the present application, see Figure 1 The control method for parallel power balance distribution of modular three-level grid-connected rectifiers in this embodiment includes:

[0067] S101, setting the module number through the DIP switch, and the host computer sets the master and slave according to the module number.

[0068] In this embodiment, the DIP switch is manually adjusted on the housing of each module to set the module number, and the host computer selects the module with the smallest number as the master among all modules, and the remaining modules are slaves. In this embodiment, the number of parallel modules is 2, module 1 is the master, and module 2 is the slave.

[0069] See also Figure 2 and Figure 3 , the main circuit diagram of a single three-level rectifier module and the main circuit diagram of multiple three-level rectifier modules in parallel provided by the embodiment of the present application, wherein the single three-level rectifier module mainly includes a three-phase power grid, an input LCL filter, an AC main bypass relay, a three-level IGBT module, a DC electrolytic capacitor and a DC main bypass relay. Multiple modules share a common AC input and a common DC output, and there is a zero-sequence circulating current loop.

[0070] S102, obtaining a given DC output voltage, and starting each module individually and sequentially according to a dual closed-loop control method and running the modules to a steady state.

[0071] In this embodiment, the given DC output voltage is obtained from the host computer, which needs to meet the operating range of the grid-connected rectifier. The minimum value of the given output voltage should meet the modulation index greater than 1.154. For example, if the input voltage on the AC side is 220V, the given DC output voltage u DC,ref satisfy:

[0072] ;

[0073] The maximum value of the given DC output voltage should be less than the withstand voltage of the DC bus capacitor. For example, in the experimental device of this embodiment, the withstand voltage of a single capacitor is 550V, and the withstand voltage of the entire DC capacitor is 1100V.

[0074] In this embodiment, the DC side output voltage set by the host computer is 800V. The host computer communicates with each sub-module in turn every 1 second. After clicking the power button, the three modules execute the soft start process on the AC side in turn. After each sub-module enters the steady state, the power-on completion flag is set to 1.

[0075] Under no-load conditions, there is only capacitance on the DC side. The actual DC side voltage u is calculated according to the voltage outer loop PI regulator. DC Tracking to the given DC side voltage u DC,ref The current i that needs to flow into the DC capacitor CAP,ref， The calculation formula is:

[0076] ;

[0077] in, is the given current that needs to flow into the DC link capacitor, are the proportional and integral coefficients of the PI regulator respectively, are the given and actual DC link capacitor voltages respectively, and s represents the unit step response in the time domain.

[0078] Transform the AC input voltage and current into coordinates, e A 、e B 、e C and i A 、i B 、i C The grid voltage e in the two-phase stationary coordinate system is obtained by equal power Clarke transformation α 、e β and current i α 、i β , under no-load conditions, i d,ref =i CAP,ref and i q,ref =0, and the reference current i in the two-phase stationary coordinate system is obtained by equal power Park inverse transformation α,ref 、i β,ref .

[0079] The modulation voltage without zero-sequence voltage injection is calculated according to the current inner loop and the control equation. In this embodiment, the current inner loop adopts DBC control, and the modulation voltage u is α and u β It is expressed as:

[0080] ;

[0081] Where, L represents the inductance of the filter inductor, T s represents the control period, e α 、e β and i α 、i β are the grid voltage and current in the two-phase stationary coordinate system obtained by equal-power Clarke transformation; u α 、u β The modulation voltage u without zero-sequence voltage injection in the three-phase stationary coordinate system is obtained by equal power Clarke inverse transformation. A 、u B 、u C .

[0082] Sort the three-phase grid voltages to get the intermediate grid voltage e MID = mid(e A , e B , e C ), half of the middle phase of the grid voltage is injected into the three-phase modulation voltage, so that the output DC voltage of each rectifier module can stably track the given voltage.

[0083] ;

[0084] Among them, u′ A , u′ B and u′ C They are the three-phase modulation voltage after zero-sequence voltage is injected. Injecting half of the middle phase of the grid voltage has two functions: one is to improve the utilization rate of DC voltage, and the other is to suppress the zero-sequence circulating current introduced by the difference in modulation voltage between multiple modules.

[0085] S103, sequentially closing the relays on the DC side according to the module numbers, and using the host's double closed loop to control the DC bus voltage of the entire system.

[0086] In this embodiment, each module sequentially attracts the bypass relay and the main relay. If the module number corresponds to the host, after the bypass relay and the main relay are attracted in sequence, the DC bus voltage of the entire system is controlled by the host's double closed loop. The control block diagram is as follows Figure 4As shown, if the module number corresponds to the slave, after the bypass relay and the main relay are attracted in sequence, the voltage outer loop of the slave is cut off, and the DC bus voltage of the entire system is controlled by the double closed loop of the host, that is, the reference of the inner loop of the slave current is zero, and the rectifier system runs in a completely no-load state. The control block diagram is as follows Figure 5 shown.

[0087] S104, estimating the total load output power, and achieving balanced distribution of the output power of each module through a load output power feedforward control method.

[0088] In this embodiment, the load output power of the entire system is estimated. In the discretized digital controller system, the estimated load power can be expressed as:

[0089] ;

[0090] Among them, p L,ref (n+1) represents the load power estimated in the next control cycle, u d,ref (n-1) and i d,ref (n-1) respectively represent the given modulation voltage and current of the d-axis in the previous control cycle, u DC (n-1) and u DC (n-2) represents the DC side voltage sampled in the last and last two control cycles, respectively, p L (n-1) represents the load output power sampled in the previous control cycle, and C represents the capacitance of the DC side capacitor.

[0091] In order to reduce the impact of sampling disturbance error, the historical load output power is substituted into the new load output power estimation for correction. The corrected load output power can be expressed as:

[0092] ;

[0093] in, and They represent the load power after the next control cycle and the previous control correction, respectively, L The weight factor that represents the proportion of the historical load output power in the corrected load output power in the next control period, and its value is between 0 and 1.

[0094] Single module load output power feedforward control algorithm. When the load on the DC side changes, there is a lag in the voltage outer loop. First, power exchange occurs between the DC side capacitor and the load, which in turn causes the DC side voltage to change. The conventional double closed-loop control algorithm only uses the DC side voltage as a feedback signal, ignoring the essential power exchange relationship of the rectifier, resulting in large fluctuations in the DC side voltage when the load changes suddenly.

[0095] See also Figure 6 , the rectifier system power exchange relationship diagram provided in this embodiment, the power input from the AC side p AC The power obtained on the DC side can be divided into p DC and power loss p LOSS , which can be divided into the power obtained by the DC capacitor p CAP and DC output power to the load p L In steady state, ignoring line losses, the AC input power is equal to the DC output power.

[0096] Power flowing out of the rectifier DC side It can be expressed as:

[0097] ;

[0098] in, Represents the power flowing into the DC side load, which can be estimated by the load power estimation formula, Indicates the power flowing into the DC side capacitor, which can be expressed as:

[0099] ;

[0100] The power flowing into the rectifier from the AC side It can be expressed as:

[0101] ;

[0102] in, and They represent the d-axis grid voltage and current respectively, which can be obtained by and After ignoring the line and switching device losses, according to the power conversion relationship of the rectifier , get the given current of the AC input current d axis , the calculation formula is:

[0103] .

[0104] The above steps divide the output power of each module rectifier in detail, where the load power feedforward algorithm is used to support the output power of the subsequent load, and the voltage outer loop PI regulator is used to offset the losses caused by sampling deviation, calculation error and line impedance.

[0105] When the sampling of each module is completely accurate, the outer loop regulators of multiple modules are the same, and the output power of each module can be evenly divided. However, in the actual system, the sampling deviation cannot be completely suppressed. When the sampling value of the output voltage of each module deviates, the above feedforward algorithm will aggravate the power flow between modules. The essential reason for the above phenomenon is that there is a coupling relationship between the output currents of multiple module loads, so it is necessary to explore the method of decoupling the output currents of multiple modules.

[0106] In this embodiment, the position of the load current sensor that outputs a voltage signal is adjusted from the inside of the module to the output end of the entire system, the output signal of the load current sensor is transmitted to each module, and then the output power is distributed according to the host and the slave respectively.

[0107] If the module is the host, it runs in voltage source mode, uses the voltage outer loop to control the DC bus output voltage of the entire system, and evenly distributes the load output power. The given current of the AC input current d axis is expressed as:

[0108] ;

[0109] Where N is the number of modules connected in parallel;

[0110] If the module is a slave, it runs in current source mode and evenly distributes the load output power. The given current of the AC input current d axis is expressed as:

[0111] .

[0112] In this embodiment, see further Figure 4 Control block diagram of the host module in the rectifier system. The given power flowing in from the AC side consists of two parts, one part is used to control the stability of the DC output voltage, and the other part is used to output to the DC load. Therefore, the given current inner loop of the host module 1 is:

[0113] .

[0114] See also Figure 5 , a control block diagram of a slave module in a rectifier system provided in an embodiment of the present application, wherein the given power flowing in from the AC side is only used to output to a DC load, and the given current inner loop of the slave module 2 is:

[0115] ;

[0116] It can be seen that the host module 1 is used to control the DC bus voltage and provide 1 / 2 of the total load power, and essentially works in the voltage source mode. The slave module 2 only provides 1 / 2 of the total load, and essentially acts in the current source mode. Secondly, the load power skips the outer loop with the capacitor voltage as the feedback signal, which significantly improves the response speed of the rectifier system. Finally, the output voltage sampling of the slave module is no longer involved in the control, which essentially solves the power flow inside the module caused by the sampling deviation.

[0117] See also Figure 7 and Figure 8 , the dynamic and steady-state experimental waveforms provided in the embodiments of the present application, wherein channel 1 is the AC current of module 1, channel 2 is the AC current of module 2, channel 3 is the DC output current of the parallel system, and channel 4 is the DC bus voltage of the parallel system. Figure 7 It can be seen that when the DC pulse load is in steady state, the DC bus voltage is relatively stable, and the output voltage ripple is about 3V, less than 0.5%; the circuit amplitudes of the two modules are almost equal, which means that the power distribution between the parallel modules is balanced. Figure 8 It can be seen that when the load changes from no-load to full-load, the average value of the DC bus voltage remains almost unchanged, and the amplitudes of the two module currents are still almost equal, which means that the proposed method is still applicable under load switching conditions.

[0118] In the embodiments of the present application, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0119] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0120] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A control method for parallel power balance distribution of modular three-level grid-connected rectifiers, characterized in that: include: The module number is set by the DIP switch, and the host computer sets the master and slave according to the module number; Obtain a given DC output voltage, start each module individually in sequence according to the double closed-loop control method and run it to a steady state; The relays on the DC side are attracted in sequence according to the module numbers, and the DC bus voltage of the entire system is controlled by the double closed loop of the host; Estimate the load output power of the entire system and achieve balanced distribution of the output power of each module through the load output power feedforward control method, including: The load output power of the entire system is estimated using the discretized digital controller system. The estimated load output power is expressed as: Among them, p L,ref (n+1) represents the load power estimated in the next control cycle, u d,ref (n-1) and i d,ref (n-1) respectively represent the given modulation voltage and current of the d-axis in the previous control cycle, u DC (n-1) and u DC (n-2) represents the DC side voltage sampled in the last and last two control cycles, respectively, p L (n-1) represents the load output power sampled in the previous control cycle, C represents the capacitance of the DC side capacitor, T s To control the cycle; Substitute the historical load output power into the new load output power estimate for correction. The corrected load output power can be expressed as: in, and They represent the load power after the next control cycle and the previous control correction, respectively, L The weight factor representing the proportion of the historical load output power in the load output power after correction in the next control cycle; The balanced distribution of the output power of each module is achieved through the load output power feedforward control method.

2. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 1, characterized in that: The module number is set by the DIP switch, and the host computer sets the master and slave according to the module number, including: Manually adjust the DIP switch on the housing of each module to set the number of each module; The host computer selects the module with the smallest number among all modules as the master, and the remaining modules are slaves.

3. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 1, characterized in that: Including, the minimum value of the given DC output voltage satisfies that the modulation index is greater than a preset value, and the maximum value of the given DC output voltage is less than the withstand voltage value of the DC side bus capacitor.

4. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 1, characterized in that: The method of starting each module separately and sequentially according to the double closed-loop control method and running it to a steady state includes: The voltage outer loop PI regulator calculates the current that needs to flow into the DC link capacitor to track the actual DC link voltage to the given DC link voltage; Perform coordinate transformation on the AC input voltage and current to obtain the grid voltage and current in a two-phase stationary coordinate system; The modulation voltage without zero-sequence voltage injection is calculated according to the current inner loop and the control equation. The current inner loop adopts DBC control and modulates the voltage u under the two-phase stationary coordinate. α and u β It is expressed as: Where, L represents the inductance of the filter inductor, T s represents the control period, e α 、e β and i α 、i β are the grid voltage and current in the two-phase stationary coordinate system obtained by equal-power Clarke transformation; i α，ref 、i β,ref are the given currents in the two-phase stationary coordinate system respectively; The three-phase grid voltages are sorted to obtain the intermediate grid voltage: The intermediate grid voltage is denoted as e MID = mid(e A , e B , e C ); Half of the middle phase of the grid voltage is injected into the three-phase modulated voltage, so that the output DC voltage of each rectifier module can stably track the given voltage.

5. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 1, characterized in that: According to the module numbers, the relays on the DC side are attracted in sequence, and the DC bus voltage of the entire system is controlled by the double closed loop of the host, including: If the module number corresponds to a slave, after the bypass relay and the main relay are closed in sequence, the voltage outer loop of the slave is cut off, and the DC bus voltage of the entire system is controlled by the dual closed loop of the master; If the module number corresponds to the host, after the bypass relay and the main relay are closed in sequence, the DC bus voltage of the entire system is controlled by the host's double closed loop.

6. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 1, characterized in that: The control method of load output power feedforward realizes balanced distribution of output power of each module, including: Obtain the given current that needs to flow into the DC side capacitor under no-load conditions. The calculation formula for the given current that needs to flow into the DC side capacitor is: where i CAP,ref k is the given current that needs to flow into the DC capacitor, p , k i are the proportional and integral coefficients of the PI regulator, u DC,ref 、u DC are the given and actual DC link capacitor voltages, respectively, and s represents the unit step response in the time domain; The output power of each module rectifier is divided in detail according to the power flowing out of the rectifier DC side, the power flowing into the rectifier from the AC side and the power flowing into the DC side capacitor combined with the current of the DC side capacitor and the corrected load output power; When there is a deviation in the sampling value of the output voltage of each module, a multi-module load feedforward power distribution method is adopted.

7. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 6, characterized in that: The power p flowing out of the rectifier DC side DC , the power p flowing into the rectifier from the AC side AC and the power p flowing into the DC capacitor CAP Respectively expressed as: p DC =p CAP +p L ,p AC =e A i A +e B i B +e C i C =e d i d ,p CAP =u DC i CAP ; Among them, p L Indicates the power flowing into the DC side load, e A 、e B 、e C Respectively represent the three-phase grid voltage; i A 、i B 、i C They represent the three-phase alternating current, e d and i d Respectively represent the d-axis grid voltage and current; According to the power conversion relationship of the rectifier p AC =p DC , get the given current i of the AC input current d axis d,ref , the calculation formula is:

8. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 6, characterized in that: The method for distributing multi-module load feedforward power includes: Adjust the position of the load current sensor that outputs a voltage signal from inside the module to the output end of the entire system; delivering the output signal of the load current sensor to each module; Power is distributed according to the master and slave devices respectively.

9. The control method for parallel power balance distribution of modular three-level grid-connected rectifiers according to claim 8, characterized in that: The power distribution is performed according to the master and the slave respectively, including: If the module is the host, it runs in voltage source mode, uses the voltage outer loop to control the DC bus output voltage of the entire system, and evenly distributes the load output power. The given current of the AC input current d axis is expressed as: Where N is the number of modules connected in parallel; If the module is a slave, it runs in current source mode and evenly distributes the load output power. The given current of the AC input current d-axis is expressed as:

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