Real-time measurement and compensation method of ADC clock jitter for high-speed data acquisition

Abstract

The present invention discloses a real-time measurement and compensation method for ADC clock jitter for high-speed data acquisition, which relates to the field of high-speed data acquisition. The method includes physically delaying the sampling clock; measuring the periodic jitter by the clock signal before and after the delay; calibrating the influence of the clock delay module on the periodic jitter measurement result; converting the periodic jitter measurement result after calibration into absolute jitter; and realizing error compensation by using absolute jitter, actual sampling result and its high-order differential. The method of the present invention utilizes the parallel processing capability and high flexibility of FPGA to realize real-time measurement and compensation of ADC clock jitter without relying on external equipment, and overcomes the problem that the traditional method is difficult to apply due to the influence of jitter size, signal type limitation and excessive calculation complexity.

Description

Technical Field

[0001] The present invention relates to the field of high-speed data acquisition, and in particular to a real-time measurement and compensation method for ADC clock jitter for high-speed data acquisition. Background Art

[0002] With the rapid development of modern electronic technology, analog-to-digital converters (ADCs) are widely used in communications, radar, measuring instruments and other fields, and are a key part of data acquisition systems. In high-frequency signal acquisition scenarios, the problem of non-uniform sampling caused by clock jitter is particularly obvious. The sampling error caused by it greatly reduces the system signal-to-noise ratio and effective number of bits, becoming one of the main noises that limit device performance.

[0003] For the problem of clock jitter, traditional solutions will reduce its impact by using clock sources with lower phase noise or improving clock circuit design, but they have problems such as high cost and weak anti-interference ability, and the effect is limited by the level of hardware development. The introduction of digital domain compensation algorithms such as iterative maximum likelihood estimation, fractional Fourier domain filtering and long-short time memory network provides a new solution to this problem, but the iteration speed is affected by the jitter size, the signal type is limited and the calculation complexity is too high, making it difficult to apply in general data acquisition systems, such as oscilloscopes, data acquisition cards, etc.

[0004] As the core of high-speed acquisition systems, field programmable gate arrays (FPGAs) have gradually become an effective tool for solving complex electronic system problems due to their parallel processing capabilities and high flexibility. Summary of the invention

[0005] The purpose of the present invention is to: In view of the above-mentioned problems, the present invention proposes a real-time measurement and compensation method for ADC clock jitter for high-speed data acquisition, which utilizes the parallel processing capability and high flexibility of FPGA to achieve real-time measurement and compensation of ADC clock jitter without relying on external devices, thereby overcoming the problems that traditional methods are difficult to apply due to the influence of jitter size, signal type limitation and excessive calculation complexity.

[0006] The technical solution adopted by the present invention is as follows:

[0007] The real-time measurement and compensation method of ADC clock jitter for high-speed data acquisition includes:

[0008] Clock delay, physically delaying the clock signal under test, and obtaining two clock signals before and after the delay of the clock signal under test;

[0009] Period jitter measurement, using a time-to-digital converter to measure the two clock signals before and after the delay to obtain a period jitter measurement result;

[0010] Jitter conversion, converting the periodic jitter measurement result into absolute jitter to obtain an absolute jitter measurement result;

[0011] Error compensation, establishing a relationship between the absolute jitter measurement result, the actual sampling result, and the high-order differentials of the absolute jitter measurement result and the actual sampling result, to obtain a compensated sampling result.

[0012] Furthermore, the clock delay includes:

[0013] A delay chain is built by cascading multiple levels of CARRY8, wherein the output port of the upper level CARRY8 in the multiple levels of CARRY8 is connected to the input port of the lower level CARRY8, and the delay amount of the measured clock signal is controlled by adjusting the number of CARRY8 cascades, and the physical delay of the measured clock signal is realized through the delay chain.

[0014] Furthermore, the period jitter measurement includes:

[0015] A tap delay chain is used to complete the construction of the delay chain, and a D flip-flop is used to latch the output of each delay unit in the delay chain to obtain a string of code values;

[0016] A decoder searches for a position code value of a highest bit in the string of code values;

[0017] The time quantity conversion converts the highest position code value into the time interval actually measured by the time digital converter, that is, the period jitter measurement result is obtained by multiplying the highest position code value by the resolution of the digital converter.

[0018] Furthermore, in the decoder, the highest position code value in a string of code values ​​is searched by binary search.

[0019] Further, the period jitter measurement also includes delay offset calibration;

[0020] The delay offset calibration is specifically to calibrate the period jitter measurement result, and the period jitter measurement result is calibrated by the following formula:

[0021] (1)

[0022] In the formula, P ( k ) is the uncalibrated period jitter measurement result obtained in the period jitter measurement, is the DC component of the period jitter measurement.

[0023] Further, the delay offset calibration includes:

[0024] The DC component is solved for the uncalibrated period jitter measurement results. P ( k) are accumulated, and the accumulated number is counted at the same time, when the accumulated number reaches a preset value, the accumulated result is latched, and the latched accumulated result is divided by the accumulated number to obtain a DC component;

[0025] FIFO buffer to store uncalibrated period jitter measurement results P ( k ) are put into FIFO for caching, the number of cached items is consistent with the accumulated number, and the DC component calculation result is read out from the FIFO cache while the DC component calculation result is latched. P ( k ), so that the uncalibrated period jitter measurement results P ( k ) is synchronized with the DC component;

[0026] Offset calibration to obtain synchronized, uncalibrated period jitter measurements P ( k ) and the DC component, the offset calibration can be achieved by taking the difference between the two with a sign, and the calibrated period jitter measurement result can be obtained. P j ( k ).

[0027] Furthermore, the jitter conversion is specifically performed by converting the absolute jitter through the following formula:

[0028] The conversion relationship between period jitter measurement results and absolute jitter measurement results is expressed as:

[0029] (2)

[0030] In the formula, and For two adjacent sampling points k and( k -1) Absolute jitter measurement results;

[0031] The absolute jitter estimate is obtained by:

[0032] (3)

[0033] In the formula, is the estimated value of period jitter, and For two adjacent sampling points k and( k -1) absolute jitter estimate, is a constant.

[0034] Furthermore, the error compensation is specifically performed by obtaining the compensated sampling result through the following formula:

[0035] (4)

[0036] In the formula, For the ideal sampling result, is the actual sampling result, Ts is the period of the sampling clock, l is the order of the series expansion.

[0037] Furthermore, the error compensation specifically includes:

[0038] Differential solution: use FIFO to cache the actual sampling results, make a difference after a delay of one beat, get the sampling difference, and amplify it by M times. M is selected according to the magnitude of the sampling difference and the jitter difference. At the same time, add the sampling difference to the periodic jitter measurement result to get the jitter difference.

[0039] The compensation value is solved by dividing the sampling difference by the jitter difference to obtain the differential of the actual sampling result, then multiplying the differential of the actual sampling result by the absolute jitter measurement result, and then reducing it by M times to obtain the sampling error compensation value, and using the obtained sampling error compensation value to complete jitter compensation.

[0040] Furthermore, the error compensation also includes synchronization compensation, which specifically includes:

[0041] The actual sampling result is cached using FIFO, and when the actual sampling result in the FIFO cache is synchronized with the compensation value, the actual sampling result is read out, and the compensated sampling result is obtained by subtracting the actual sampling result read out from the FIFO cache from the compensation value.

[0042] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0043] In the real-time measurement and compensation method for ADC clock jitter for high-speed data acquisition of the present invention, the type and frequency range of the analog-to-digital converter ADC input signal are not restricted, and the parallel processing and calculation of each data can be maintained during its operation, so that the real-time processing of the clock signal and the sampling result can be realized. Moreover, the method does not need to add additional hardware, and the jitter measurement and compensation can be realized in the FPGA of the data acquisition system. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a flow chart of the real-time measurement and compensation method of ADC clock jitter for high-speed data acquisition of the present invention;

[0045] Figure 2 It is a principle block diagram of the real-time measurement and compensation method of ADC clock jitter for high-speed data acquisition of the present invention;

[0046] Figure 3 Schematic diagram of the FPGA-TDC jitter measurement principle in the method of the present invention;

[0047] Figure 4 Schematic diagram of FPGA-TDC based on tapped delay chain architecture in the method of the present invention;

[0048] Figure 5 It is the principle diagram of the experimental system in the experimental process of the method of the present invention;

[0049] Figure 6 This is a frequency domain comparison diagram before and after compensation obtained after the experiment of the method of the present invention. DETAILED DESCRIPTION

[0050] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] The present invention provides a real-time measurement and compensation method for ADC clock jitter for high-speed data acquisition, such as Figure 1 As shown in FIG, it specifically includes five processing steps: clock delay, period jitter measurement, delay offset calibration, jitter conversion and error compensation. Figure 2 As shown, each processing process is implemented inside the FPGA. The input interface includes the sampling clock and sampling result of the ADC. The specific contents of each processing process are as follows:

[0053] Clock Delay

[0054] In this embodiment, the measured clock signal is physically delayed by 1 cycle, and the two clock signals before and after the delay need to be used as inputs for period jitter measurement; the clock delay uses the CarryChain resource CARRY8 at the bottom layer of the FPGA. Taking the Ultrasclae series of Xilinx as an example, a delay chain can be constructed by cascading multiple levels of CARRY8. The output port of the upper level CARRY8 in the delay chain is connected to the input port of the next level CARRY8. The delay value of each level of CARRY8 is the resolution of the delay chain. The delay amount is controlled by adjusting the number of cascaded CARRY8s, thereby realizing the physical delay of the measured clock signal.

[0055] Period Jitter Measurement

[0056] After delaying the clock signal by one cycle, the time-to-digital converter (TDC) is used to measure the rising edge interval of the two clock signals before and after the delay, which is the period jitter. Figure 3 shown.

[0057] Tapped delay chain, such as Figure 4As shown, this embodiment adopts FPGA-TDC based on tap delay chain architecture, builds delay chain by cascading multiple levels of CARRY8, and latches the output of each level of delay unit in the delay chain with D flip-flops, then a string of code values ​​will be obtained; the two clock signals before and after the delay are respectively input into this module as START and STOP signals. n When the interval between the rising edges of the START signal and the STOP signal after the delay unit is less than the resolution of the delay chain, the latched code value is the same as the previous one. n All bits are 1, n All bits above +1 are 0, that is, the code value jumps from 0 to 1.

[0058] The decoder can extract the number of delay units corresponding to the rising edge interval of START and STOP from the string of code values ​​output by the delay chain, which corresponds to the position of the highest bit 1 in the search code value; this embodiment uses binary search, and each round of search code value has a high half bit [2 N -1:2 N-1 ] are all 0, if not all 0, then the position code value is N -1 bit output is 1, if all are 0, then the lower half bit [2 N-1 -1:0] Repeat the search to see if all are 0 until the search is complete and the bit width is N The location code value.

[0059] Time quantity conversion, the time quantity conversion module converts the position of the highest bit 1 into the time interval actually measured by the FPGA-TDC. Here, the position code value can be converted into a time value by multiplying the TDC resolution:

[0060] (5)

[0061] In the formula P ( k ) is the uncalibrated period jitter measurement result, Bin ( k ) is the position code value, T LSB is the TDC resolution.

[0062] Performing delay offset calibration on the uncalibrated period jitter measurement result, specifically including:

[0063] This embodiment proposes an offset calibration method to alleviate the influence of the clock delay module on the period jitter measurement result. In order to avoid the situation where the rising edges of the clock signal before and after the delay are in an uncertain order, the clock delay module controls the delay amount to exceed 1 clock cycle, so that the rising edge of the clock signal after the delay is after the rising edge of the clock signal before the delay. This part of the delay excess can be considered as a DC component for the period jitter measurement result:

[0064] (1)

[0065] In the formula, is the DC component of the period jitter measurement.

[0066] The specific implementation of delay offset calibration includes:

[0067] DC component solution for uncalibrated period jitter measurement results P ( k ) are accumulated, and a counter is used to count the accumulated number. When the accumulated number reaches a preset value, the preset value is set by actual research and development, that is, a larger value is taken when the signal bit width is satisfied. When the accumulated number reaches the preset value, the accumulated result is latched, and the latched result is divided by the accumulated number to obtain the DC component.

[0068] FIFO buffer for uncalibrated period jitter measurement results per segment P ( k ) is synchronized with its corresponding DC component. In this embodiment, the uncalibrated period jitter measurement result P ( k ) are put into FIFO for cache, the cache number is consistent with the accumulated number, and the DC component calculation result is latched and read out from FIFO at the same time. P ( k ), then you can ensure P ( k ) is synchronized with the DC component.

[0069] Offset calibration, after obtaining the synchronized period jitter measurement result and the DC component, the offset calibration can be achieved by taking the difference between the two with a sign.

[0070] Jitter Conversion

[0071] like Figure 3 As shown in the figure, the conversion relationship between period jitter and absolute jitter can be expressed as:

[0072] (2)

[0073] Therefore, the estimated value of absolute jitter can be obtained by the following formula (3):

[0074] (3)

[0075] In the formula is the estimated value of period jitter, is the absolute jitter estimate, is a constant.

[0076] It can be seen from formula (2) that the conversion between period jitter and absolute jitter is carried out through an accumulator, and a counter is used to count the accumulated number. When the accumulated number reaches the set value, the accumulator is cleared and accumulated again. The setting of the accumulated number here needs to consider two factors: the signal characteristics of the absolute jitter and the cumulative error.

[0077] Error compensation

[0078] The error compensation is performed using Taylor series. It is necessary to synchronously process the absolute jitter measurement result, the actual sampling result and its high-order differential to obtain the compensated sampling result:

[0079] (4)

[0080] In the formula, For the ideal sampling result, is the actual sampling result, l is the order of the series expansion.

[0081] The specific implementation of error compensation includes, in this embodiment, taking the first-order Taylor series expansion as an example:

[0082] Differential solution, in order to synchronize the high-order differential of the actual sampling result with the jitter measurement result, the actual sampling result is cached in FIFO, and the differential is performed after a delay of one beat to obtain the sampling differential. The actual sampling result after the cache is amplified by M times, where M is selected according to the magnitude of the sampling differential and the jitter differential. At the same time, the sampling differential is added to the periodic jitter measurement result to obtain the jitter differential.

[0083] To solve the compensation value, the actual sampling difference after synchronization is divided by the jitter difference to obtain the differential of the actual sampling result, and then the differential of the actual sampling result is multiplied by the absolute jitter measurement result, and then it is reduced by M times to obtain the sampling error compensation value.

[0084] Synchronous compensation, in order to realize the corresponding point calculation of the actual sampling result and the compensation result, the actual sampling result and the compensation value must be kept synchronized. Here, FIFO is used to cache the actual sampling result. When it is synchronized with the compensation value, the actual sampling result is read out, and the difference between the two can be obtained to obtain the compensated sampling result.

[0085] Experimental verification of this embodiment:

[0086] In the verification example, a data acquisition system is built with an ADC with a sampling rate of 15MSa / s as the core to verify the effectiveness of the proposed method. The FPGA uses Xilinx's XCKU060-2FFVA1156I, and the signal source uses Keysight's 33500B arbitrary waveform generator.

[0087] like Figure 5As shown, the ADC is sampled by FPGA control, and the 240MHz signal generated by the clock circuit is divided to 15MHz by FPGA to generate the sampling clock. The sampling result is transmitted to the host computer through the online logic analyzer ILA, and then the ADC index calculation and frequency domain analysis are performed through MATLAB.

[0088] The method of this embodiment is loaded into the FPGA of the data acquisition system, and a 1 MHz sinusoidal signal is generated by a signal generator and input to the ADC. Figure 6 As shown in the frequency domain comparison diagram before and after compensation, when the sampling rate is 15MSa / s, the method of this embodiment can effectively alleviate the sidelobe noise caused by ADC clock jitter and improve the signal-to-noise ratio by about 5.25dB.

[0089] The principles and implementation methods of the present invention are described in this article using specific embodiments. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A real-time measurement and compensation method for ADC clock jitter for high-speed data acquisition, characterized in that: Specifically include: Clock delay, physically delaying the clock signal under test, and obtaining two clock signals before and after the delay of the clock signal under test; Period jitter measurement, using a time-to-digital converter to measure the two clock signals before and after the delay to obtain a period jitter measurement result; the period jitter measurement also includes delay offset calibration; The delay offset calibration is specifically to calibrate the period jitter measurement result, and the period jitter measurement result is calibrated by the following formula: （1） In the formula, P ( k ) is the uncalibrated period jitter measurement result obtained in the period jitter measurement, is the DC component of the period jitter measurement result; The delay offset calibration comprises: The DC component is solved for the uncalibrated period jitter measurement results. P ( k ) are accumulated, and the accumulated number is counted at the same time, when the accumulated number reaches a preset value, the accumulated result is latched, and the latched accumulated result is divided by the accumulated number to obtain a DC component; FIFO buffer to store uncalibrated period jitter measurement results P ( k ) are put into FIFO for caching, the number of cached items is consistent with the accumulated number, and the DC component calculation result is read out from the FIFO cache while the DC component calculation result is latched. P ( k ), so that the uncalibrated period jitter measurement results P ( k ) is synchronized with the DC component; Offset calibration to obtain synchronized, uncalibrated period jitter measurements P ( k ) and the DC component, the offset calibration can be achieved by taking the difference between the two with a sign, and the calibrated period jitter measurement result can be obtained. P j ( k ); Jitter conversion, converting the periodic jitter measurement result into absolute jitter to obtain an absolute jitter measurement result; the jitter conversion is specifically performed by converting the absolute jitter through the following formula: The conversion relationship between period jitter measurement results and absolute jitter measurement results is expressed as: （2） In the formula, For sampling point k The absolute jitter measurement result is For the sampling point k Adjacent sampling points ( k -1) Absolute jitter measurement results; The absolute jitter estimate is obtained by: （3） In the formula, is the estimated value of period jitter, is the absolute jitter estimate, is a constant; Error compensation, establishing a relationship between the absolute jitter measurement result, the actual sampling result, and the higher-order differentials of the absolute jitter measurement result and the actual sampling result, to obtain a compensated sampling result; The error compensation is specifically performed by obtaining the compensated sampling result through the following formula: （4） In the formula, For the ideal sampling result, is the actual sampling result, Ts is the period of the sampling clock, l is the order of the series expansion.

2. The method for real-time measurement and compensation of ADC clock jitter for high-speed data acquisition according to claim 1, characterized in that: The clock delay includes: A delay chain is built by cascading multiple levels of CARRY8, wherein the output port of the upper level CARRY8 in the multiple levels of CARRY8 is connected to the input port of the lower level CARRY8, and the delay amount of the measured clock signal is controlled by adjusting the number of CARRY8 cascades, and the physical delay of the measured clock signal is realized through the delay chain.

3. The method for real-time measurement and compensation of ADC clock jitter for high-speed data acquisition according to claim 2, characterized in that: The period jitter measurement includes: A tap delay chain is used to complete the construction of the delay chain, and a D flip-flop is used to latch the output of each delay unit in the delay chain to obtain a string of code values; A decoder searches for a position code value of a highest bit in the string of code values; The time quantity conversion converts the highest position code value into the time interval actually measured by the time digital converter, that is, the period jitter measurement result is obtained by multiplying the highest position code value by the resolution of the digital converter.

4. The method for real-time measurement and compensation of ADC clock jitter for high-speed data acquisition according to claim 3, characterized in that: In the decoder, the position code value of the highest bit in a string of code values ​​is searched by binary search.

5. The method for real-time measurement and compensation of ADC clock jitter for high-speed data acquisition according to claim 1, characterized in that: The error compensation specifically includes: Differential solution: use FIFO to cache the actual sampling results, perform differential calculation after one beat delay, obtain the sampling differential, and amplify the actual sampling results after the cache by M times. M is selected according to the magnitude of the sampling differential and the jitter differential. At the same time, add the sampling differential to the periodic jitter measurement result to obtain the jitter differential. The compensation value is solved by dividing the sampling difference by the jitter difference to obtain the differential of the actual sampling result, then multiplying the differential of the actual sampling result by the absolute jitter measurement result, and then reducing it by M times to obtain the sampling error compensation value, and using the obtained sampling error compensation value to complete jitter compensation.

6. The method for real-time measurement and compensation of ADC clock jitter for high-speed data acquisition according to claim 5, characterized in that: The error compensation also includes synchronous compensation, which specifically includes: The actual sampling result is cached using FIFO, and when the actual sampling result in the FIFO cache is synchronized with the compensation value, the actual sampling result is read out, and the compensated sampling result is obtained by subtracting the actual sampling result read out from the FIFO cache from the compensation value.

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