Data encoding method, device, storage medium and electronic device

Abstract

The present disclosure relates to the field of data processing technology, and in particular to a data encoding method, device, storage medium and electronic device. The method includes: obtaining encoded data, the encoded data includes multiple encoded data packets, the encoded data is obtained by encoding the data to be encoded based on a preset encoding matrix and encoding parameters, each encoding coefficient in the preset encoding matrix is ​​an extended domain element in a preset extended domain, and the preset extended domain is an extended domain determined according to the application scenario where the data to be encoded is located; based on the preset extended domain, the encoding coefficients in the preset encoding matrix are converted into a binary matrix; according to the encoding parameters and the binary matrix, a corresponding systolic array in the FPGA is constructed, so as to perform parallel encoding on multiple data packets to be encoded based on the systolic array. Through this method, the design of the encoding table lookup algorithm based on the extended domain matrix representation on the FPGA is realized, and the encoding calculation of multiple data packets to be encoded can be completed in parallel using the FPGA.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a data encoding method, device, storage medium and electronic device. Background Art

[0002] In today's digital age, the speed and efficiency of data transmission and processing have become the core concerns in the field of information technology. With the rapid development of technologies such as big data, cloud computing, and the Internet of Things, the amount of data has exploded, and the requirements for data processing systems have also increased. Especially in the fields of communications, video processing, image recognition, and high-performance computing, efficient data encoding and decoding technology has become a key factor in improving the overall performance of the system.

[0003] Traditional data encoding methods are often based on simple linear transformations or fixed algorithms, which are difficult to adapt to complex and changing application scenarios and the growing amount of data. In order to more effectively utilize resources and improve the reliability and efficiency of data transmission, researchers have begun to explore more flexible and complex encoding schemes. These encoding schemes can be customized according to the specific needs of different application scenarios, thereby enhancing the robustness and efficiency of the encoding. Summary of the invention

[0004] The main purpose of the present disclosure is to provide a data encoding method, device, storage medium and electronic device.

[0005] To achieve the above objectives, the present disclosure proposes a data encoding method, comprising:

[0006] Get the encoded data;

[0007] The coded data includes a plurality of coded data packets, the coded data is obtained by encoding the data to be coded based on a preset coding matrix and coding parameters, each coding coefficient in the preset coding matrix is ​​an extended domain element in a preset extended domain, the preset extended domain is an extended domain determined according to an application scenario of the data to be coded, and the coding parameters include an extended domain dimension of the preset extended domain, the number of data packets to be coded corresponding to the data to be coded, and the number of coded data packets corresponding to the coded data;

[0008] Based on the preset extended domain, converting the coding coefficients in the preset coding matrix into a binary matrix;

[0009] A corresponding systolic array in the FPGA is constructed according to the encoding parameters and the binary matrix, so as to perform parallel encoding on a plurality of data packets to be encoded based on the systolic array.

[0010] Optionally, constructing a corresponding systolic array in the FPGA according to the encoding parameter and the binary matrix includes:

[0011] Constructing a first operation module according to the encoding parameter and the binary matrix;

[0012] Instantiate based on the encoding parameters and the first operation module, construct a second operation module;

[0013] The systolic array is constructed by instantiating according to the encoding parameters and the second operation module.

[0014] Optionally, constructing a first operation module according to the encoding parameter and the binary matrix includes:

[0015] According to the extended domain dimension, obtaining a set of operation units;

[0016] Arranging a plurality of operation units in the operation unit set to obtain an operation unit matrix, wherein the dimension of the operation unit matrix corresponds to the dimension of the extended domain;

[0017] Determine, according to the binary matrix, a weight coefficient matrix corresponding to the operation unit matrix, wherein the weight coefficient matrix includes a weight coefficient of each operation unit in the operation unit matrix;

[0018] Based on the weight coefficient matrix, a weight is assigned to each operation unit in the operation unit matrix to obtain a first operation module, wherein each dimensional systolic array of the first operation module is a parallel operation unit.

[0019] Optionally, the instantiation based on the encoding parameter and the first operation module to construct the second operation module includes:

[0020] Determine a first operation module group according to the first operation modules and the number of the data packets to be encoded, wherein the number of the first operation modules included in the first operation module group is the same as the number of the data packets to be encoded;

[0021] Based on the first operation module group, obtaining matrix coefficients corresponding to the binary matrix;

[0022] Inputting the matrix coefficients into the first operation module group to obtain a first operation result set, wherein the first operation result set includes the operation results output by each first operation module in the first operation module group, and each first operation module in the first operation module group is a parallel operation module;

[0023] A bitwise XOR operation is performed on the first operation result set to obtain an encoded data packet corresponding to the first operation result set, thereby completing the construction of the second operation module.

[0024] Optionally, the instantiation according to the encoding parameter and the second operation module to construct the systolic array includes:

[0025] Determine a second operation module group according to the second operation modules and the number of the encoded data packets, wherein the number of the second operation modules included in the second operation module group is the same as the number of the encoded data packets;

[0026] Inputting the data packet to be encoded into the second operation module group to obtain a second operation result set, thereby completing the construction of the systolic array;

[0027] The second operation result set includes an encoded data packet output by each second operation module in the second operation module group, and each second operation module in the second operation module group is a parallel operation module.

[0028] Optionally, the obtaining of the coded data includes:

[0029] Acquire data to be encoded, wherein the data to be encoded includes a plurality of data packets to be encoded, each of which is a binary vector;

[0030] Based on a preset coding matrix, the data to be encoded is encoded to determine the product of a plurality of the data packets to be encoded and the binary matrix, thereby obtaining the encoded data packet.

[0031] Optionally, the converting, based on the preset extended domain, coding coefficients in the preset coding matrix into a binary matrix includes:

[0032] Calculate the domain operation table corresponding to the preset extended domain;

[0033] Determining a target coding coefficient according to the domain operation table, the target coding coefficient being a coding coefficient involved in a coding process of the coded data;

[0034] Traversing the domain operation table to determine the binary column vector corresponding to the target coding coefficient;

[0035] The binary matrix is ​​determined according to the binary column vector.

[0036] In addition, to achieve the above-mentioned purpose, the present disclosure also provides a data encoding device, the data encoding device comprising:

[0037] An acquisition module, used for acquiring encoded data;

[0038] The coded data includes a plurality of coded data packets, the coded data is obtained by encoding the data to be coded based on a preset coding matrix and coding parameters, each coding coefficient in the preset coding matrix is ​​an extended domain element in a preset extended domain, the preset extended domain is an extended domain determined according to an application scenario of the data to be coded, and the coding parameters include an extended domain dimension of the preset extended domain, the number of data packets to be coded corresponding to the data to be coded, and the number of coded data packets corresponding to the coded data;

[0039] A conversion module, configured to convert the coding coefficients in the preset coding matrix into a binary matrix based on the preset extended domain;

[0040] A construction module is used to construct a corresponding systolic array in the FPGA according to the encoding parameters and the binary matrix, so as to perform parallel encoding on multiple data packets to be encoded based on the systolic array.

[0041] In addition, to achieve the above objectives, the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and a processor executes the computer program to implement the above method.

[0042] In addition, to achieve the above-mentioned purpose, the present disclosure also provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-mentioned method.

[0043] In addition, to achieve the above objectives, the present disclosure also provides a computer program product, which implements the above method when executed by a processor.

[0044] Through the above technical solution, firstly, the coded data is obtained, wherein the coded data includes a plurality of coded data packets, the coded data is obtained by encoding the coded data based on the preset coding matrix and the coding parameters, each coding coefficient in the preset coding matrix is ​​an extension domain element in the preset extension domain, the preset extension domain is an extension domain determined according to the application scenario where the coded data is located, and the coding parameters include the extension domain dimension of the preset extension domain, the number of coded data packets corresponding to the coded data, and the number of coded data packets corresponding to the coded data. Then, based on the preset extension domain, the coding coefficients in the preset coding matrix are converted into a binary matrix, and then the corresponding systolic array in the FPGA is constructed according to the coding parameters and the binary matrix, so as to perform parallel encoding on the plurality of coded data packets based on the systolic array. In this way, the design of the coding lookup algorithm represented by the binary matrix of the preset extension domain on the FPGA is realized. Since the coding calculation process between each coding packet is independent of each other, and a large number of bit operations, logical operations and loop structures are involved in the coding process, the hardware logic design of the FPGA and the systolic array technology can be used to complete the calculation of the corresponding plurality of coded data packets based on the plurality of coded data packets in parallel. In addition, since FPGA is highly customizable, only small engineering modifications are required to adapt to the encoding requirements on the extended domain in different dimensions, and power consumption can be reduced through customized hardware design. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0046] Figure 1 A schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present disclosure;

[0047] Figure 2 A schematic diagram of a data encoding method according to an embodiment of the present disclosure;

[0048] Figure 3 A diagram showing the overall design structure of a systolic array involved in an embodiment of the present disclosure;

[0049] Figure 4 A PE principle diagram involved in the embodiment of the present disclosure;

[0050] Figure 5 A SA Cell starting diagram involved in the embodiment of the present disclosure;

[0051] Figure 6 It is a SA_Cell (L+3) period diagram involved in the embodiment of the present disclosure;

[0052] Figure 7 A SA_Core design schematic diagram involved in the embodiment of the present disclosure;

[0053] Figure 8 A schematic diagram of a Systolic Array design involved in the embodiment of the present disclosure;

[0054] Fig. 9 A schematic diagram of a data packet to be encoded involved in an embodiment of the present disclosure;

[0055] Fig.10 A schematic diagram of an encoded data packet involved in an embodiment of the present disclosure;

[0056] Fig.11 The present invention is a structural block diagram of a data encoding device involved in an embodiment of the present disclosure.

[0057] The realization of the objectives, functional features and advantages of the present disclosure will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0059] Reference Figure 1 , Figure 1 The figure is a schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present disclosure.

[0060] Typically, the device comprises: at least one processor 301, a memory 302, and a data encoding program stored in the memory 302 and executable on the processor 301, wherein the data encoding program is configured to implement the steps of the data encoding method as described above.

[0061] The processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 301 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. The processor 301 may also include an AI (Artificial Intelligence) processor, which is used to process operations related to the data encoding method, so that the data encoding method model can be trained and learned autonomously to improve efficiency and accuracy.

[0062] The memory 302 may include one or more storage media, which may be non-transitory. The memory 302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory storage medium in the memory 302 is used to store at least one instruction, which is used to be executed by the processor 301 to implement the data encoding method provided in the method embodiment of the present disclosure.

[0063] In some embodiments, the terminal may further optionally include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected via a bus or a signal line. Each peripheral device may be connected to the communication interface 303 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit 304, a display screen 305 and a power supply 306.

[0064] The communication interface 303 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 301 and the memory 302. In some embodiments, the processor 301, the memory 302, and the communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302, and the communication interface 303 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0065] The radio frequency circuit 304 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 304 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 304 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. Optionally, the radio frequency circuit 304 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The radio frequency circuit 304 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 304 may also include circuits related to NFC (Near Field Communication), which is not limited in the present disclosure.

[0066] The display screen 305 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 305 is a touch display screen, the display screen 305 also has the ability to collect touch signals on the surface or above the surface of the display screen 305. The touch signal can be input to the processor 301 as a control signal for processing. At this time, the display screen 305 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 305 can be one, the front panel of the electronic device; in other embodiments, the display screen 305 can be at least two, respectively arranged on different surfaces of the electronic device or in a folding design; in some embodiments, the display screen 305 can be a flexible display screen, arranged on a curved surface or a folding surface of the electronic device. Even, the display screen 305 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 305 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).

[0067] The power supply 306 is used to power various components in the electronic device. The power supply 306 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When the power supply 306 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology. Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation of the device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0068] In addition, the embodiment of the present disclosure further proposes a storage medium, on which a data encoding program is stored, and when the data encoding program is executed by a processor, the steps of the data encoding method described above are implemented. Therefore, it will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the storage medium embodiment involved in the present disclosure, please refer to the description of the method embodiment of the present disclosure. As an example, the program instructions can be deployed to be executed on one device, or on multiple devices located at one location, or on multiple devices distributed at multiple locations and interconnected by a communication network.

[0069] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the above-mentioned program can be stored in a storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the above-mentioned storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0070] First of all, it should be understood that the finite field GF(p) and its extension field GF(p L ) plays an important role in coding theory and encryption algorithms. GF ​​stands for Galois Field, p is a prime number, and L is the extended dimension of the field. In the finite field GF(p), addition and multiplication operations are both operations modulo p; the extended field GF(p L ) can be expressed as a polynomial, for example, a(x) = a 0 +a 1 x+a 2 x 2 +...+a L-1 x L-1 , where a i (0≤i≤L-1) belongs to GF(p), and the operation rules are extended by GF(p L ) The L-order primitive polynomial p(x) corresponding to GF(p) is uniquely determined. When p = 2, that is, in the binary extension field GF(2 L ) i (0≤i≤L-1) can only take values ​​of 0 or 1. This feature makes operations more convenient and faster. Addition is an XOR operation, and multiplication is an AND operation. Since the logic gate design and implementation in FPGA are good at processing bit operations, in GF(2 L ) can be well mapped to the logical structure of FPGA, giving full play to the unique advantages of FPGA.

[0071] The domain operation table can realize the expression of the coding coefficients in the coding matrix from the binary extended domain element form to the binary matrix form. After that, the coding operation is to complete the binary product operation between multiple vectors and matrices, and the calculation of multiple coding packets can be performed in parallel. Therefore, the systolic array technology in FPGA can be used to complete parallel calculations on the data stream. The data stream calculation can overlap the processing of different data units to improve the calculation throughput. While speeding up data processing and reducing latency, it can also easily adjust and optimize the hardware structure of matrix product calculation to adapt to the coding calculation tasks on different extended domains. It is very suitable for scenarios that require large-scale parallel computing and high-performance computing.

[0072] Specifically, in GF(2 L ) has a larger codeword space than the finite field GF(2), with a codeword length of L, and a total of 2 L Encoding in the extended domain can realize more complex coding technology and improve the transmission rate of the code, so that the system can better resist errors and interference in data transmission and improve the stability and reliability of the communication system.

[0073] Reference Figure 2 , Figure 2 The present invention is a flowchart of a data encoding method according to an embodiment of the present invention, comprising the following steps:

[0074] Step S11: Obtain coded data, wherein the coded data includes a plurality of coded data packets, the coded data is obtained by encoding the coded data based on a preset coding matrix and coding parameters, each coding coefficient in the preset coding matrix is ​​an extended domain element in a preset extended domain, the preset extended domain is an extended domain determined according to an application scenario where the coded data is located, and the coding parameters include an extended domain dimension of the preset extended domain, the number of coded data packets corresponding to the coded data, and the number of coded data packets corresponding to the coded data.

[0075] Step S12: Based on the preset extended domain, the coding coefficients in the preset coding matrix are converted into a binary matrix.

[0076] Step S13: constructing a corresponding systolic array in the FPGA according to the encoding parameters and the binary matrix, so as to perform parallel encoding on a plurality of data packets to be encoded based on the systolic array.

[0077] Through the above technical solution, firstly, the coded data is obtained, wherein the coded data includes a plurality of coded data packets, the coded data is obtained by encoding the coded data based on the preset coding matrix and the coding parameters, each coding coefficient in the preset coding matrix is ​​an extension domain element in the preset extension domain, the preset extension domain is an extension domain determined according to the application scenario where the coded data is located, and the coding parameters include the extension domain dimension of the preset extension domain, the number of coded data packets corresponding to the coded data, and the number of coded data packets corresponding to the coded data. Then, based on the preset extension domain, the coding coefficients in the preset coding matrix are converted into a binary matrix, and then the corresponding systolic array in the FPGA is constructed according to the coding parameters and the binary matrix, so as to perform parallel encoding on the plurality of coded data packets based on the systolic array. In this way, the design of the coding lookup algorithm represented by the binary matrix of the preset extension domain on the FPGA is realized. In this way, since the coding calculation process between each coding packet is independent of each other, and a large number of bit operations, logical operations and loop structures are involved in the coding process, the hardware logic design of the FPGA and the systolic array technology can be used to complete the calculation of the corresponding plurality of coded data packets based on the plurality of coded data packets in parallel. In addition, since FPGA is highly customizable, only small engineering modifications are required to adapt to the encoding requirements on the extended domain in different dimensions, and power consumption can be reduced through customized hardware design.

[0078] Among the possible ways to obtain the encoded data, include:

[0079] Acquire data to be encoded, the data to be encoded comprising a plurality of data packets to be encoded, each of which is a binary vector;

[0080] Based on a preset coding matrix, the data to be coded is coded to determine the product of the binary vectors and the binary matrix in a plurality of data packets to be coded, thereby obtaining a coded data packet.

[0081] It should be understood that the data to be encoded during the communication process is often in the form of a data stream generated in real time. When constructing k packets of length M to be encoded, k and M can be of any size. The k value affects the number of computing units used to construct the systolic array. Due to its design flexibility, only a small amount of engineering modification is required to adapt to different k values. The size of the M value does not affect the overall design architecture of the FPGA. It only needs to input the original data stream in real time, and it can be started and ended at any time.

[0082] For example, suppose the data to be encoded in the FPGA consists of k packets m of length M to be encoded. 1 ,m 2 ,…,m k Each data packet to be encoded contains M symbols, each symbol is an extended field GF(2 L) can be uniquely represented by an L-dimensional binary vector. The data packet to be encoded is encoded through the k×n encoding matrix G=[g ij ] k×n Get n coded data packets c of length M 1 ,c 2 ,…,c n ,Right now

[0083] [m 1 m 2 ... m k ]G=[c 1 c 2 ... c n ]

[0084] Among them, each coding coefficient g in the coding coefficient matrix G ij Both are extended domains GF(2 L ), so each encoded packet c j Can be expressed as:

[0085] c j =∑ 1≤i≤k g ij m i (1)

[0086] Among them, c j represents the jth coded data packet, j represents the number of columns of the preset coding matrix, i represents the number of rows of the preset coding matrix, k represents the number of data packets to be coded, and g ij represents the jth element in the i-th row of the preset coding matrix, m i Represents the i-th data packet to be encoded.

[0087] In a possible manner, based on a preset extended domain, the coding coefficients in the preset coding matrix are converted into a binary matrix, including:

[0088] Calculate the domain operation table corresponding to the preset extended domain;

[0089] According to the domain operation table, a target coding coefficient is determined, where the target coding coefficient is a coding coefficient involved in the coding process of the coding data;

[0090] Traverse the domain operation table to determine the binary column vector corresponding to the target coding coefficient;

[0091] Determine a binary matrix from a binary column vector.

[0092] For example, Matlab can be used to calculate the dimension of L×(2 L -1) and store it as a COE file. In Vivado, the ROM IP core is used to perform storage initialization operations through the COE file.

[0093] Specifically, let p(x) be an L-order primitive polynomial based on GF(p). If p(x) = a 0 +a 1 x+a 2 x 2 +…+a L-1 x L-1 +x L , where a 0 、a 1 …a L-1 are all elements of the finite field GF(p), then in the dimension L×(2 L -1) In the efficient coding operation table, the submatrix formed by the 1st to Lth columns is the unit matrix, and the (L+1)th column is [-a 0 -a 1 … -a L-1 ] T , column (L+2) The (L+1)th column parameters are calculated based on the following formula:

[0094]

[0095] After that, the (L+s+1)th column is recursively obtained from the (L+s)th column:

[0096]

[0097] The p in this efficient operation table L -1 columns are all different from each other and constitute exactly p in the L-dimensional linear space based on GF(p) L -1 non-zero column vector.

[0098] After the coding matrix is ​​determined, the coding coefficients g involved in the operation in formula (1) can be converted into ij (i.e., target coding coefficients) are expressed from the extended domain element form into an L×L binary matrix form (i.e., coding coefficient matrix), denoted by G ij , where the zero element can be represented by L×L zero matrix 0, and the corresponding relationship of non-zero elements can be obtained by looking up the domain operation table. ij It is fixed to the corresponding operation unit and used as the operation weight coefficient for multiplication operation. Each operation unit can complete a one-bit AND logic operation and a one-bit XOR operation. After the weight coefficient is fixed, the original data is multiplied by the coefficient and then added to the result of the previous operation unit to obtain the current operation result, and the result is input to the next operation unit for calculation, where the "previous operation unit XOR result" of the starting operation unit is input as 0.

[0099] In the specific table lookup process, due to the extended domain GF(2L ) has a unique L-dimensional binary vector corresponding to each element, so the domain operation table stored in ROM is searched by traversing the address and g ij The corresponding two-element column vector can be used.

[0100] This L-dimensional binary column vector forms the first column of the matrix G ij , and then take L-1 binary column vectors from this address, and form the second to Lth column vectors in order, finally realizing g ij The elements are represented as an L×L binary matrix G ij .

[0101] It is worth noting that when the address continuously shifts backward by L-1 bits, if it exceeds the address range of the storage domain operation table in the ROM, it will loop to the first address of the ROM and continue to shift backward to complete the construction of the matrix.

[0102] After the extended domain elements are expressed as binary matrices, since the original data packet m i There are M symbols, so for a particular i and j, we complete m i G ij The encoding calculation process requires M binary vector and matrix multiplications. For a specific j, iterate over all k independent m i G ij Then perform the addition operation to get the encoded data packet c j . By traversing the above process n times, the calculation of all encoded data packets can be completed. Due to the independence of the encoding process, the above encoding calculation process has a high degree of parallelism, and the logic gate design and implementation in the FPGA process bit operations, so the above operation process can be well mapped to the logic structure of the FPGA (such as bit multiplication is mapped to logical AND operation, bit addition is mapped to XOR operation), thereby giving play to the unique advantages of FPGA.

[0103] In the specific encoding process, the first step is to calculate each m i G ij When the product of the binary vector and the matrix can be realized by column L parallel computing; the second step is to calculate each c j When the encoding process is independent, k-way m i G ij The third step is to parallelize the calculation of all the coded data packets, and also because of the independence of the coding process, n-way c j of parallel computing.

[0104] Thus, in the FPGA hardware design, the calculation of the coding packet can be performed in parallel in a total of L×k×n parts, which greatly improves the computational efficiency of the coding algorithm.

[0105] In a possible manner, a corresponding systolic array in an FPGA is constructed according to the encoding parameters and the binary matrix, including:

[0106] Constructing a first operation module according to the encoding parameters and the binary matrix;

[0107] Based on the encoding parameters and the instantiation of the first operation module, construct a second operation module;

[0108] Instantiate according to the encoding parameters and the second operation module to construct a systolic array.

[0109] For example, in the hardware implementation process, the unique advantages of FPGA can be used to realize parallel computing of coding packets. Specifically, it is necessary to complete the design of three computing modules: the first computing module (i.e., SA_Cell module), the second computing module (i.e., SA_Core module), and the systolic array (i.e., SystolicArray module).

[0110] For example, Figure 3 This is a diagram of the overall design structure of a systolic array involved in an embodiment of the present disclosure.

[0111] Specifically, refer to Figure 3 , the corresponding systolic array SA_Cell design in FPGA can be completed based on the extended domain dimension L, the corresponding systolic array SA_Core design in FPGA can be completed based on the number of data packets to be encoded k, the corresponding systolic array SystolicArray design in FPGA can be completed based on the number of encoded data packets n, and the coded data packets can be calculated using the systolic array SystolicArray pipelined parallel encoding according to the coding coefficients and the data to be encoded.

[0112] When the extended domain dimension L, the number of data packets to be encoded k, and the number of encoded data packets n are large, the serial encoding process will bring great computational overhead. The above technical solution can realize parallel calculation of multiple encoding packets at the hardware level at the cost of extremely low storage overhead, greatly improving the computational efficiency of the encoding algorithm.

[0113] In a possible manner, a first operation module is constructed according to the encoding parameter and the binary matrix, including:

[0114] According to the extended domain dimension, a set of operation units is obtained;

[0115] Arrange multiple operation units in the operation unit set to obtain an operation unit matrix, where the dimension of the operation unit matrix corresponds to the dimension of the extended domain;

[0116] Determine a weight coefficient matrix corresponding to the operation unit matrix according to the binary matrix, wherein the weight coefficient matrix includes a weight coefficient of each operation unit in the operation unit matrix;

[0117] Based on the weight coefficient matrix, a weight is assigned to each operation unit in the operation unit matrix to obtain a first operation module, in which each dimensional systolic array of the first operation module is a parallel operation unit.

[0118] It should be understood that the systolic array is composed of multiple computing units arranged in sequence, which has good scalability and high energy efficiency, and only requires a very small area of ​​on-chip ROM to store a total of L×(2 L -1) bits, can pipeline the calculation of the original data stream, can overlap the processing of different data units, improve the calculation throughput, have a fixed delay, speed up data processing and reduce the delay, and can easily adjust and optimize the hardware structure of matrix product calculation to adapt to different binary extension domains GF(2 L ). Therefore, to obtain n coded data packets using k original data packets, a total of L×L×k×n operation units are required to be arranged in sequence.

[0119] In addition, each data packet to be encoded has M symbols, so it takes M clock cycles to complete the input of all the data symbols to be encoded. Since each symbol is represented by an L-dimensional binary vector, the systolic array has an output delay of L-1 clock cycles. Pipeline calculation can overlap the processing of different data units, so it takes M+L-1 clock cycles to complete the encoding calculation of the data stream to be encoded using the systolic array.

[0120] The simulation verification may include: using Vivado to perform simulation testing, generating the original data stream in real time through the task function $random, setting incentives and instantiating the interface.

[0121] For example, based on the above content, we can first obtain L×L processing elements (PE) to form a processing element set according to the extended domain dimension L, and then combine the L×L processing elements according to L rows and L columns to obtain a processing element matrix. Each column in the processing element matrix is ​​a separate one-dimensional systolic array, and the L columns of one-dimensional systolic arrays process data in parallel to complete each m i G ij Calculation.

[0122] Since the weight coefficient of each operation unit in the operation unit matrix is ​​constructed by the L×L binary matrix G ijTherefore, the weight coefficient matrix corresponding to the operation unit matrix can be determined according to the binary matrix, wherein the weight coefficient matrix includes the weight coefficient of each operation unit in the operation unit matrix. Based on the weight coefficient matrix, a weight is assigned to each operation unit in the operation unit matrix to obtain the first operation module, namely the SA_Cell module. The input data bit width of the SA_Cell module is L bits, the output data bit width is L bits, and the output delay is L-1 clock cycles.

[0123] In a possible manner, instantiating the first operation module based on the encoding parameter to construct the second operation module includes:

[0124] Determine a first operation module group according to the first operation modules and the number of data packets to be encoded, wherein the number of first operation modules included in the first operation module group is the same as the number of data packets to be encoded;

[0125] Based on the first operation module group, obtaining matrix coefficients corresponding to the binary matrix;

[0126] Inputting the matrix coefficients into the first operation module group to obtain a first operation result set, wherein the first operation result set includes the operation results output by each first operation module in the first operation module group, and each first operation module in the first operation module group is a parallel operation module;

[0127] A bitwise XOR operation is performed on the first operation result set to obtain an encoded data packet corresponding to the first operation result set, thereby completing the construction of the second operation module.

[0128] For example, according to the first operation module and the number of data packets to be encoded k, a first operation module group is determined, wherein the first operation module group includes k SA_Cell modules. At the same time, based on the first operation module group, the corresponding matrix coefficients in the binary matrix are obtained. In this way, for a specific j, by traversing the value of i in 1≤i≤k, the instantiation operation of k SA_Cell modules can be completed, and the m calculated by each SA_Cell is converted into i G ij The result is bitwise XOR to get the encoded data packet c j . Among them, each SA_Cell is operated in parallel, and different SA_Cells need to load different matrix coefficients. The input data width of the SA_Cell module is L×k bits, the output data width is L bits, and the output delay is L-1 clock cycles. In this way, the second operation module (i.e., SA_Core module) is constructed based on the encoding parameters and the first operation module.

[0129] In a possible manner, instantiating according to the encoding parameters and the second operation module to construct a systolic array includes:

[0130] Determine a second operation module group according to the second operation modules and the number of the encoded data packets, wherein the number of the second operation modules included in the second operation module group is the same as the number of the encoded data packets;

[0131] Inputting the data packet to be encoded into the second operation module group, obtaining a second operation result set, and completing the construction of the systolic array;

[0132] The second operation result set includes an encoded data packet output by each second operation module in the second operation module group, and each second operation module in the second operation module group is a parallel operation module.

[0133] For example, according to the second operation module and the number of coded data packets, the second operation module group is determined, wherein the second operation module group includes n second operation modules. Therefore, the value of j can be traversed in 1≤j≤n to complete n times of SA_Core module instantiation operations, and each SA_Core module completes the corresponding coded data packet c. j The calculation of n encoded data packets c is finally completed 1 ,c 2 , ..., c n Calculation. Each SA_Core performs parallel operations, and different SA_Cores need to load different matrix coefficients. The input data width of the SystolicArray module is L×k bits, the output data width is L×n bits, and the output delay is L-1 clock cycles. The FPGA design of the encoding algorithm is now complete, and simulation verification can be performed.

[0134] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, in this disclosure, the binary extended field GF(2 16 ) is used as an example to complete the coding calculation of k=5, M=65536, and n=7, and is described in detail.

[0135] (1) The 5 packets to be encoded may include m 1 , m 2 , m 3 , m 4 , m 5 , which can be specifically expressed as:

[0136] m 1 =[13604 39309 … 12050] T

[0137] m 2 =[24139 33893 … 57617] T

[0138] m 3=[54793 21010 … 58253] T

[0139] m 4 =[22115 58113 … 56069] T

[0140] m 5 =[31501 52493 … 15911] T

[0141] (2) Construct the coding coefficient matrix, that is, the coeffMatrix module matrix.

[0142] Specifically, it can be based on the input encoding matrix element g ij The value of (1≤i≤5,1≤j≤7) is searched for the same data in the ROM by traversing the address. After the search is completed, 15 data are taken continuously (each data is 16 bits) and the 16 data are arranged in columns to form a 16×16 matrix, which is the finite field g ij The matrix form corresponding to the element. After the matrix is ​​created, pull the output valid bit high and output the matrix result. Among them, the input coding matrix element g ij The bit width is L=16 bits, and the output matrix form bit width is L×L=256 bits.

[0143]

[0144] The parameters of the coeffMatrix module matrix can be shown in Table 1:

[0145] Table 1

[0146]

[0147]

[0148] (3) Constructing SA_Cell module based on encoding parameter L

[0149] Then, L = 16, so the 16×16 operation units can be used to complete the 16 rows and 16 columns in sequence. Figure 5 As shown, each row is a separate one-dimensional systolic array, 16 rows are calculated in parallel, and after the coeffMatrix module matrix is ​​constructed, as shown in Figure 4 As shown, the matrix coefficients of the coeffMatrix module matrix are input to the SA_Cell module and fixed to the corresponding operation unit as weight coefficients.

[0150] like Figure 6As shown in the figure, when the coefficient input and data input are valid at the same time, the input valid bit is pulled high. At this time, 16×16 operation units work simultaneously. After 15 clock cycles, the product of a symbol in a data packet and a matrix element is completed and the result is output. Because the data stream calculation is overlapping, a g is output every clock cycle thereafter. ij m i The calculation result of (1≤i≤5,1≤j≤7) can be specifically expressed as:

[0151]

[0152] The input data bit width is L=16 bits, and the output data bit width is L=16 bits.

[0153] The parameters of the SA_Cell module can be shown in Table 2:

[0154] Table 2

[0155]

[0156] (4) Construct SA_Core module based on encoding parameter k

[0157] Since there are 5 data packets to be encoded, the coeffMatrix module matrix and the SA_Cell module need to be instantiated 5 times.

[0158] like Figure 7 As shown, the matrix result of the coeffMatrix module matrix can be input to the SA_Cell module to instantiate the SA_Cell module 5 times. The SA_Cell module calculates 5 g when the input data is valid. ij m i (1≤i≤5,1≤j≤7), and then perform bitwise XOR operation on the 5 results to complete a coded data packet c j The calculation is performed, and the output valid bit is pulled high to output the result. Among them, the input data bit width is k×L=5×16=80 bits, and the output data bit width is L=16 bits.

[0159] Encoded packet c 1 It can be expressed as:

[0160] c 1 =g 11 m 1 +g 21 m 2 +g 31 m 3 +g 31 m 4 +g 41 m 5=[268732458…65220] T

[0161] The parameters of the SA_Core module can be shown in Table 3:

[0162] Table 3

[0163]

[0164] (5) Construct SystolicArray (i.e., systolic array) based on encoding parameter n

[0165] n = 7, generating 7 coded data packets requires instantiation of 7 SA_Cores, each of which completes the calculation of one data packet. Figure 8 As shown, 7 SA_Cores are instantiated to complete the calculation of 7 coded data packets in parallel, pull up the output valid bits, and output the coded packet results. The input data bit width is k×L=5×16=80 bits, and the output data bit width is n×L=7×16=112 bits.

[0166] The 7 coded packets can be represented as:

[0167] c 1 =g 11 m 1 +g 21 n 2 +g 31 m 3 +g 31 m 4 +g 41 m 5 =[2687 32458 … 65220] T

[0168] c 2 =g 12 m 1 +g 22 m 2 +g 32 m 3 +g 32 m 4 +g 42 m 5 =[59918 35332 … 61530] T

[0169] c 3 =g 13 m 1 +g 23 m 2 +g 33 m 3 +g 33 m4 +g 43 m 5 =[4449 6047 … 39419] T

[0170] c 4 =g 14 m 1 +g 24 m 2 +g 34 m 3 +g 34 m 4 +g 44 m 5 =[35620 2136 … 62867] T

[0171] c 5 =g 15 m 1 +g 25 m 2 +g 35 m 3 +g 35 m 4 +g 45 m 5 =[16016 8694 … 33910] T

[0172] c 6 =g 16 m 1 +g 26 m 2 +g 36 m 3 +g 36 m 4 +g 46 m 5 =[18883 1242 … 11712] T

[0173] c 7 =g 17 m 1 +g 27 m 2 +g 37 m 3 +g 37 m 4 +g 47 m 5 =[14458 50142 … 1926] T

[0174] The parameters of the SystolicArray module can be shown in Table 4:

[0175] Table 4

[0176]

[0177] For example, the data packet to be encoded is Fig. 9 As shown, the encoded data packet corresponding to the data packet to be encoded is as follows Fig.10 As shown, the FPGA design and implementation of the encoding algorithm is completed.

[0178] Reference Fig.11 , Fig.11 This is a structural block diagram of a data encoding device involved in an embodiment of the present disclosure. Based on the same inventive concept as the above embodiment, the device includes:

[0179] An acquisition module 10, used to acquire coded data;

[0180] The coded data includes a plurality of coded data packets, the coded data is obtained by encoding the data to be coded based on a preset coding matrix and coding parameters, each coding coefficient in the preset coding matrix is ​​an extended domain element in a preset extended domain, the preset extended domain is an extended domain determined according to an application scenario of the data to be coded, and the coding parameters include an extended domain dimension of the preset extended domain, the number of data packets to be coded corresponding to the data to be coded, and the number of coded data packets corresponding to the coded data;

[0181] A conversion module 20, configured to convert the coding coefficients in the preset coding matrix into a binary matrix based on the preset extended domain;

[0182] The construction module 30 is used to construct a corresponding systolic array in the FPGA according to the encoded data and the binary matrix, so as to perform parallel encoding on multiple data packets to be encoded based on the systolic array.

[0183] Optionally, the construction module 30 is used to:

[0184] Constructing a first operation module according to the encoding parameter and the binary matrix;

[0185] Instantiate based on the encoding parameters and the first operation module, construct a second operation module;

[0186] The systolic array is constructed by instantiating according to the encoding parameters and the second operation module.

[0187] Optionally, the construction module 30 is used to:

[0188] According to the extended domain dimension, obtaining a set of operation units;

[0189] Arranging a plurality of operation units in the operation unit set to obtain an operation unit matrix, wherein the dimension of the operation unit matrix corresponds to the dimension of the extended domain;

[0190] Determine, according to the binary matrix, a weight coefficient matrix corresponding to the operation unit matrix, wherein the weight coefficient matrix includes a weight coefficient of each operation unit in the operation unit matrix;

[0191] Based on the weight coefficient matrix, a weight is assigned to each operation unit in the operation unit matrix to obtain a first operation module, wherein each dimensional systolic array of the first operation module is a parallel operation unit.

[0192] Optionally, the construction module 30 is used to:

[0193] Determine a first operation module group according to the first operation modules and the number of the data packets to be encoded, wherein the number of the first operation modules included in the first operation module group is the same as the number of the data packets to be encoded;

[0194] Based on the first operation module group, obtaining matrix coefficients corresponding to the binary matrix;

[0195] Inputting the matrix coefficients into the first operation module group to obtain a first operation result set, wherein the first operation result set includes the operation results output by each first operation module in the first operation module group, and each first operation module in the first operation module group is a parallel operation module;

[0196] A bitwise XOR operation is performed on the first operation result set to obtain an encoded data packet corresponding to the first operation result set, thereby completing the construction of the second operation module.

[0197] Optionally, the construction module 30 is used to:

[0198] Determine a second operation module group according to the second operation modules and the number of the encoded data packets, wherein the number of the second operation modules included in the second operation module group is the same as the number of the encoded data packets;

[0199] Inputting the data packet to be encoded into the second operation module group to obtain a second operation result set, thereby completing the construction of the systolic array;

[0200] The second operation result set includes an encoded data packet output by each second operation module in the second operation module group, and each second operation module in the second operation module group is a parallel operation module.

[0201] Optionally, the acquisition module 10 is used to:

[0202] Acquire data to be encoded, wherein the data to be encoded includes a plurality of data packets to be encoded, each of which is a binary vector;

[0203] Based on a preset coding matrix, the data to be encoded is encoded to determine the product of the binary vectors in a plurality of the data packets to be encoded and the binary matrix, thereby obtaining the encoded data packet.

[0204] Optionally, the conversion module 20 is used to:

[0205] Calculate the domain operation table corresponding to the preset extended domain;

[0206] Determining a target coding coefficient according to the domain operation table, the target coding coefficient being a coding coefficient involved in a coding process of the coded data;

[0207] Traversing the domain operation table to determine the binary column vector corresponding to the target coding coefficient;

[0208] The binary matrix is ​​determined according to the binary column vector.

[0209] It should be noted that, since the steps executed by the device of this embodiment are the same as the steps of the aforementioned method embodiment, its specific implementation method and the technical effects that can be achieved can refer to the aforementioned embodiment and will not be repeated here.

[0210] In addition, in one embodiment, an embodiment of the present disclosure further provides an electronic device, which includes a processor, a memory, and a computer program stored in the memory, and the computer program implements the steps of the method in the aforementioned embodiment when executed by the processor.

[0211] In addition, in one embodiment, an embodiment of the present disclosure further provides a computer storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method in the aforementioned embodiment are implemented.

[0212] In some embodiments, the computer readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or various devices including one or any combination of the above memories. The computer may be various computing devices including intelligent terminals and servers.

[0213] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0214] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0215] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0216] It should be noted that, in this article, the terms "include", "may include" or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0217] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0218] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a multimedia terminal device (which can be a mobile phone, a computer, a television receiver, or a network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0219] The above descriptions are only optional embodiments of the present disclosure, and are not intended to limit the patent scope of the present disclosure. All equivalent structural transformations made using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A data encoding method, characterized in that: include: Get the encoded data; The coded data includes a plurality of coded data packets, the coded data is obtained by encoding the data to be coded based on a preset coding matrix and coding parameters, each coding coefficient in the preset coding matrix is ​​an extended domain element in a preset extended domain, the preset extended domain is an extended domain determined according to an application scenario of the data to be coded, and the coding parameters include an extended domain dimension of the preset extended domain, the number of data packets to be coded corresponding to the data to be coded, and the number of coded data packets corresponding to the coded data; Based on the preset extended domain, converting the coding coefficients in the preset coding matrix into a binary matrix; According to the encoding parameters and the binary matrix, a first operation module is constructed; based on the encoding parameters and the first operation module, a second operation module is constructed; according to the encoding parameters and the second operation module, a systolic array is constructed; so that a plurality of data packets to be encoded are encoded in parallel based on the systolic array.

2. The method according to claim 1, characterized in that: The step of constructing a first operation module according to the encoding parameter and the binary matrix includes: According to the extended domain dimension, obtaining a set of operation units; Arranging a plurality of operation units in the operation unit set to obtain an operation unit matrix, wherein the dimension of the operation unit matrix corresponds to the dimension of the extended domain; Determine, according to the binary matrix, a weight coefficient matrix corresponding to the operation unit matrix, wherein the weight coefficient matrix includes a weight coefficient of each operation unit in the operation unit matrix; Based on the weight coefficient matrix, a weight is assigned to each operation unit in the operation unit matrix to obtain a first operation module, wherein each dimensional systolic array of the first operation module is a parallel operation unit.

3. The method according to claim 1, characterized in that The instantiation based on the encoding parameter and the first operation module to construct the second operation module includes: Determine a first operation module group according to the first operation modules and the number of the data packets to be encoded, wherein the number of the first operation modules included in the first operation module group is the same as the number of the data packets to be encoded; Based on the first operation module group, obtaining matrix coefficients corresponding to the binary matrix; Inputting the matrix coefficients into the first operation module group to obtain a first operation result set, wherein the first operation result set includes the operation results output by each first operation module in the first operation module group, and each first operation module in the first operation module group is a parallel operation module; A bitwise XOR operation is performed on the first operation result set to obtain an encoded data packet corresponding to the first operation result set, thereby completing the construction of the second operation module.

4. The method according to claim 3, characterized in that The instantiation according to the encoding parameter and the second operation module to construct the systolic array includes: Determine a second operation module group according to the second operation modules and the number of the encoded data packets, wherein the number of the second operation modules included in the second operation module group is the same as the number of the encoded data packets; Inputting the data packet to be encoded into the second operation module group to obtain a second operation result set, thereby completing the construction of the systolic array; The second operation result set includes an encoded data packet output by each second operation module in the second operation module group, and each second operation module in the second operation module group is a parallel operation module.

5. The method according to claim 1, characterized in that: The obtaining of the coded data comprises: Acquire data to be encoded, wherein the data to be encoded includes a plurality of data packets to be encoded, each of which is a binary vector; Based on a preset coding matrix, the data to be encoded is encoded to determine the product of a plurality of the data packets to be encoded and the binary matrix, thereby obtaining the encoded data packet.

6. The method according to claim 1, characterized in that The converting the coding coefficients in the preset coding matrix into a binary matrix based on the preset extended domain includes: Calculate the domain operation table corresponding to the preset extended domain; Determining a target coding coefficient according to the domain operation table, the target coding coefficient being a coding coefficient involved in a coding process of the coded data; Traversing the domain operation table to determine the binary column vector corresponding to the target coding coefficient; The binary matrix is ​​determined according to the binary column vector.

7. A data encoding device, characterized in that: include: An acquisition module, used for acquiring encoded data; The coded data includes a plurality of coded data packets, the coded data is obtained by encoding the data to be coded based on a preset coding matrix and coding parameters, each coding coefficient in the preset coding matrix is ​​an extended domain element in a preset extended domain, the preset extended domain is an extended domain determined according to an application scenario of the data to be coded, and the coding parameters include an extended domain dimension of the preset extended domain, the number of data packets to be coded corresponding to the data to be coded, and the number of coded data packets corresponding to the coded data; A conversion module, configured to convert the coding coefficients in the preset coding matrix into a binary matrix based on the preset extended domain; A construction module is used to construct a first operation module according to the encoding parameters and the binary matrix; to construct a second operation module based on the encoding parameters and the first operation module; to construct a systolic array based on the encoding parameters and the second operation module; so as to perform parallel encoding on multiple data packets to be encoded based on the systolic array.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the processor executes the computer program to implement the method according to any one of claims 1 to 6.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method according to any one of claims 1 to 6.

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