FPGA-based real-time system for multi-channel visible light communication across water surface

Abstract

The application discloses a kind of real-time systems of cross water surface multi-channel visible light communication based on FPGA, using FPGA as real-time signal processing unit, while processing signal transmission and reception.Integrating low-density parity-check (LDPC) codes from 5G new radio, the system significantly improves its detection capability for dynamic W2A-OWC scenarios.The system also optimizes the use of FPGA resources through time multiplexing of the IP core of the LDPC decoder.The system not only supports single-color light transmission, but also supports multi-color light transmission, covering LEDs of different wavelengths to meet various service needs and adapt to complex environments.Using a light source array as the transmitting end and a detector array as the receiving end, a multi-channel transmission and reception module is realized, which can improve the rate of the communication system, promote the simultaneous transmission of multiple data streams and improve the overall throughput.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of cross-water surface visible light communication and FPGA real-time system, and particularly relates to a cross-water surface multi-channel visible light communication real-time system based on FPGA. BACKGROUND

[0002] In recent years, underwater activities and related wireless communication have attracted great interest from academia and industry. In order to efficiently and safely explore and obtain marine data, it is necessary to establish a communication link between underwater platforms (such as underwater unmanned vehicles (UUV) and sensors) and terrestrial platforms (such as unmanned aerial vehicles (UAV) and base stations). Cross-water surface reliable communication plays an important role in various applications such as underwater monitoring and underwater rescue missions.

[0003] Radio frequency waves, sound waves and light waves are three existing wireless carriers for transmission in air and water. Although radio frequency signals can propagate for a long distance (up to tens of kilometers) and achieve a high transmission rate (up to hundreds of Mbps) in air, they can only propagate a few meters in water due to high absorption and attenuation. Sound waves can propagate several kilometers in water and have always been the first choice for underwater communication. However, the transmission rate of acoustic communication systems is only on the order of kilobits per second, which cannot meet the requirements of potential applications. In addition, most of the sound waves are reflected by the water surface and greatly attenuated in air. In summary, neither radio frequency nor sound waves can be used alone for communication across dynamic water surfaces.

[0004] Recent advances in optical wireless communication (OWC) have promoted the use of light waves as an alternative solution for communication across dynamic water surfaces. It has been proven that water exhibits acceptable attenuation to the blue-green window (from 450 nm to 570 nm), which lays the foundation for underwater optical wireless communication. Compared with radio frequency waves and sound waves, light waves have several obvious advantages: first, the propagation attenuation of light waves in water and air media is acceptable; second, according to the Fresnel formula, most of the light energy can pass through the W2A interface for small incident angles; third, OWC can provide high transmission rates at relatively low cost. These attractive features make OWC a promising communication technology across the W2A interface.

[0005] In actual communication scenarios, communication systems are required to have high rates, high precision, real-time processing, good system stability, and a large number of channels. Under these conditions, FPGA becomes the preferred choice for performing real-time high-speed data acquisition and processing in communication systems due to its high clock frequency, small internal delay, pure hardware parallel control, fast operation speed, flexible programming configuration, short development cycle, strong anti-interference ability, and rich internal resources. SUMMARY

[0006] Therefore, the application provides a FPGA-based cross-water multi-channel visible light communication real-time system, which can effectively improve communication efficiency.

[0007] In order to achieve the above object, the technical scheme adopted by the application is as follows:

[0008] A FPGA-based cross-water multi-channel visible light communication real-time system, the system comprises a sending end development board, a biasing device, a light source array, a cross-water channel system, a detector array and a receiving end development board arranged in sequence along a communication link.

[0009] The sending end development board is used for receiving data sent by an upper computer and pre-processing the data as an alternating current signal of the biasing device and a direct current signal from a direct current power supply, and coupling the signals to drive the light source array to emit light signals.

[0010] The light signals are received by the receiving end development board after passing through the cross-water channel system.

[0011] The sending end development board and the receiving end development board both use FPGA as a real-time signal processing unit to perform real-time signal sending and receiving, and the receiving end development board uses a time division manner to use an IP core of an LDPC decoder.

[0012] Further, the light source array is an LED array, the detector array is a photodetector array, the number of LED light sources in the LED array is the same as that of photodetectors in the photodetector array, both are n, n is greater than or equal to 3, and they are placed one by one.

[0013] Further, the sending end development board receives data of FPGA sent by the upper computer, and sequentially adds address information, adds CRC check bits, LDPC encoding, adds a synchronization header and frames, and outputs n channels of the data after OOK modulation through a digital-to-analog converter of an expansion board of the FPGA, wherein the address information of the n channels of the output data is different.

[0014] Further, the n channels of data output by the sending end development board are not emitted at the same time, and the subsequent data is delayed relative to the previous data, so that the n channels of data received by the receiving end development board are used together in series using one LDPC decoder IP core.

[0015] Further, the receiving end development board converts the electrical signals from the detector array into digital signals, and the digital signals are sent into an LDPC decoding IP core after passing through an initialization module, merging, downsampling, synchronization, channel estimation and log-likelihood ratio mapping, and the decoded data is subjected to CRC check and address information check, and if the address information of the received data frame is the same as that of the sent data frame, the data is uploaded to the upper computer and displayed.

[0016] The application has the advantages that:

[0017] The application provides an FPGA-based real-time system for multi-channel visible light communication across water surface, which can improve the speed of the communication system; the system not only supports monochromatic light transmission, but also supports polychromatic light transmission, covers LEDs of different wavelengths, and meets various service requirements and adapts to complex environments; the hardware logic of the FPGA can directly process signals, reducing the delay of software processing, which is crucial for communication systems that require fast response; in addition, the received 3-way data is serially used with one LDPC decoder, realizing efficient use of FPGA resources. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a FPGA-based multi-channel visible light communication real-time system diagram across water surface;

[0019] Figure 2 It is a schematic diagram of the communication principle of each component of the transmitting end;

[0020] Figure 3 It is a schematic diagram of the physical layer link transmission data frame structure of the transmitting end;

[0021] Figure 4 It is a schematic diagram of the 3-way data sending timing of the transmitting end;

[0022] Figure 5 It is a schematic diagram of the communication principle of each component of the receiving end. DETAILED DESCRIPTION

[0023] The application will be further described below in combination with the drawings and examples.

[0024] The application provides a FPGA-based multi-channel visible light communication real-time system across water surface, which has a simple structure, can effectively improve the speed of the communication system, reduce the delay of software processing, and realize efficient use of FPGA resources.

[0025] Specifically, as shown in the drawings, Figure 1 It is a FPGA-based multi-channel visible light communication real-time system diagram across water surface, which includes a transmitting end development board, a biasing device, a light source array, a cross-water channel system, a detector array, and a receiving end development board arranged in sequence along the communication link. The transmitting end development board is an AX7021 development board, and the receiving end development board is an AX7325 development board. The light source array uses an LED array as the transmitting end, and the detector array uses an APD array as the receiving end, realizing a multi-channel transmission and reception module. The transmitting end development board and the receiving end development board both use an FPGA as a real-time signal processing unit for real-time signal sending and receiving, and use an IP core of an LDPC decoder through time division, realizing efficient use of FPGA resources.

[0026] It should be noted that the wavelength range of the LED array can be arbitrarily selected, including but not limited to blue-green light sources. The wavelength range needs to be selected according to actual needs.

[0027] In one embodiment, the LED array is n (n≥3) LEDs with wavelengths between 450nm and 570nm, where n is preferably 3. The light emitted by the LED array under water reaches the effective detection surface of the detector array through the water-atmosphere interface of the cross-water channel system.

[0028] It should be noted that when the LED array is n, the APD array is also n, the data emitted by the sender development board is n, and the data received by the receiver development board is also n.

[0029] Among them, the wavelength of the LED array is in the blue-green window of 450nm-570nm, which is used to reduce the attenuation of light in the underwater channel and ensure the transmission distance of the communication system.

[0030] In the experiment, the water tank is 3 meters long, 1 meter wide, and 0.6 meters high. Three LEDs are placed underwater in a triangular shape, with a distance of 1m between each other and a distance of 0.2m from the bottom of the water tank. The water depth in the water tank is kept at 0.27m. The receiving end of the three APDs is installed on a shelf 0.8m away from the water surface, corresponding to the three LEDs, and placed facing up in the air.

[0031] Specifically, the main function of the transmitting end is to receive the FPGA data sent by the host computer through the serial port. After the data reaches the FPGA, it is stored in the first-in-first-out (FIFO) queue. When the data in the FIFO accumulates to a specified bit length, it is read out and added with address information, CRC check bits, LDPC encoding, synchronization header and framing, OOK modulation. Finally, the signal is output through the three channels of the expansion board digital-to-analog converter (DAC) on the FPGA. After that, the three signals are coupled with the DC signal from the DC power supply as the AC signal of the bias tee, driving the three LEDs (CREE XHP70) for controlling the LED light emission. The light signal emitted by the LED array passes through the water body, passes through the fluctuating water surface, and then passes through the atmospheric channel to finally reach the receiving end. Among them, the address information of the three data is different, which is convenient for the receiving end to distinguish the three data.

[0032] At the receiving end, first, the light signal emitted by the LED array reaches the light-sensitive surface of the APD through the water-air interface, and the light signal is received by the three APDs and converted into corresponding three-way electrical signals. Then, the receiving end FPGA (ALINX AX7325B) uses a 3-channel analog-to-digital converter (ADC) to convert the electrical signals from the three APDs into digital signals respectively. At the receiving end FPGA, the digital signal is sent to the LDPC decoding IP core after passing through the initialization module, merging, downsampling, synchronization, channel estimation and Log Likelihood Ratio (LLR) mapping. And the decoded data is CRC checked and address information checked, if the received data frame address is the same as the sending address, the data is uploaded to the host computer and displayed.

[0033] Embodiment

[0034] Figure 2 For the detailed schematic diagram of the transmitting end, the USB of the host computer transmits the uncoded file data to the FPGA (ALINX AX7021) through the USB to TTL module. FIFO is used as a buffer to handle the mismatch of data rate between the host computer and the FPGA. The baud rate of the host computer is 1953250 bps, to prevent FIFO overflow caused by rate mismatch, hardware flow control RTS / CTS is used for write rate control: the development board monitors the remaining space of FIFO in real time, when the remaining space is less than a certain value, the development board pulls up the CTS pin, after the host computer sends the content of the buffer, it will stop sending, the total size of FIFO is 2048 Bytes. Then, when the data in the FIFO accumulates to a specified bit length, it is read out, and the data is added with address information, CRC check bit, LDPC encoding, synchronization header and framing, OOK modulation, after being output by the DAC, it is coupled with the AC signal and DC signal of the bias as the driving signal of the LED.

[0035] As shown in Figure 3 the physical layer link transmission data frame structure, the data physical layer transmission adopts LDPC encoding of (2176, 1280), which is the standard channel coding adopted by 5G communication, and the encoding and decoding are realized by the LDPC IP core in vivado.

[0036] It should be noted that due to the limited resources of the receiving end FPGA, when processing 3-way data, if 3 LDPC decoder IP cores are used at the same time, the resources of the receiving end FPGA are insufficient. Therefore, the data frames of the 3-way data sent by the sending end are not sent at the same time, but the second way is delayed by 80 microseconds relative to the first way, and the third way is delayed by 80 microseconds relative to the second way, so as to ensure that the received 3-way data is used together in series using one LDPC decoder IP core, and the FPGA resources are used efficiently. The 3-way data sending timing is as follows Figure 4 .

[0037] Figure 5 The receiving end is shown in the schematic diagram. After the optical signal is received by the three APDs and converted into corresponding three-way electrical signals, it is sent to the receiving end FPGA for processing. After the digital signal is processed by the initialization module, merging, downsampling, synchronization, channel estimation, and Log Likelihood Ratio (LLR) mapping, it is sent to the LDPC decoding IP core for decision decoding. Then, the address information of the decoded output data is extracted. If the received data frame address matches the sending address, the decoded data from the three channels is separated, and then CRC check is performed. According to the CRC check result, the count of successfully decoded data frames in the register is updated. The number of received data frames can be determined by the synchronized frame count. Among them, the initialization module is different from the photon counting method, which selects the received pulse signal by threshold selection; the synchronization module makes a decision based on the correlation value and energy value of the synchronization header. In order to save resources, the 3-way data is serialized during LDPC decoding. After decoding, the 3-way data is separated by address information, and then CRC check and error frame statistics are performed.

[0038] In order to simulate the dynamic underwater environment, a wave generator is placed in the underwater channel to make the channel dynamic. The system performance is tested under calm water surface conditions and wave water surface conditions.

[0039] Table 1 shows the number of frames sent by the receiving end under calm water surface conditions, the number of received frames, and the number of frames with correct CRC check. It can be seen that under calm water surface conditions, the data frame transmission accuracy is 100%;

[0040] Table 2 shows the number of frames sent by the receiving end under wave water surface conditions, the number of received frames, and the number of frames with correct CRC check. It can be seen that under wave water surface conditions, the data frame transmission accuracy is 99.932%;

[0041] Table 1

[0042]

[0043] Table 2

[0044]

[0045] Therefore, it is illustrated that the scheme can realize real-time communication of multi-channel visible light communication facing dynamic cross-water surface channel with lower complexity.

[0046] The above-described specific embodiments further illustrate the purpose, technical scheme and beneficial effects of the present application. It should be understood that the above-described specific embodiments are only for the specific embodiments of the present application and are not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. An FPGA-based real-time system for multi-channel underwater visible light communication across water surface, characterized in that, The system comprises a sending development board, a biaser, a light source array, a cross-water channel system, a detector array and a receiving development board arranged in sequence along a communication link. The sending development board is configured to receive data sent by an upper computer and pre-process the data as AC signals coupled with DC signals from a DC power supply to drive the light source array to emit light signals. The light signals are transmitted to the detector array through the cross-water channel system and received by the receiving development board. The sending development board and the receiving development board both use FPGA as real-time signal processing units to send and receive real-time signals, and the receiving development board uses an IP core of an LDPC decoder in a time-division manner, specifically, the n pieces of data output by the sending development board are not sent at the same time, and the data of a subsequent piece of data is delayed relative to the data of a previous piece of data, so that the n pieces of data received by the receiving development board are used together in series using one LDPC decoder IP core. The light source array is an LED array, and the wavelength is located in the blue-green window of 450nm-570nm, the detector array is a photodetector array, the number of LED light sources in the LED array is the same as the number of photodetectors in the photodetector array, both are n, n≥3, and are placed one-to-one. The sending development board receives data of FPGA sent by the upper computer, and adds address information, adds CRC check bits, LDPC encoding, adds a synchronization header and frames the data in sequence, and then outputs the data through n channels of a D / A converter of an expansion board of the FPGA after OOK modulation, wherein the address information of the n pieces of output data is different. 2.The FPGA-based real-time system for multi-channel visible light communication across water surface according to claim 1, wherein, The receiving development board converts electrical signals from the detector array into digital signals, and the digital signals are sent into an LDPC decoding IP core after being processed by an initialization module, merging, downsampling, synchronization, channel estimation and log-likelihood ratio mapping, and the decoded data is subjected to CRC check and address information check, and if the address information of the received data frame is the same as the address information of the sent data frame, the data is uploaded to the upper computer and displayed.

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