Wireless receiver equipment, data processing method thereof and wireless communication system
By using non-idle symbols in the wireless receiver device for memory access and entering an idle state during the idle symbol, the problem of inefficiency of the processor when waiting for memory write events is solved, and the power consumption and efficiency improvement are achieved.
Patent Information
- Application Number
- CN202310768501.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-27
- Publication Date
- 2024-12-27
AI Technical Summary
In wireless communication, the processor is unable to perform other tasks while waiting for memory write events, resulting in reduced work efficiency and increased power consumption.
A wireless receiver device is designed, including a decoder, memory unit and processor, to avoid unnecessary memory access by accessing memory during non-idle symbols for data analysis and processing, and to enter an idle state during idle symbols.
It effectively reduces the power consumption of wireless communication devices during packet reception and processing, and improves the working efficiency of the processor.
Smart Images
Figure CN119210643A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to receiving packet decoding and analysis processing, and in particular to a wireless receiver device and a data processing method thereof and a wireless communication system. Background Art
[0002] In wireless communication, the transmitting end usually encodes the raw data to form a packet, and then the receiving end decodes the packet to restore it to the original data. When receiving a packet, the decoder usually decodes the packet to obtain the original data and writes the original data to the memory. The processor then accesses the memory to obtain the original data and performs data analysis on the original data. Since it is impossible to predict when the memory write event will occur, the processor needs to continuously access the memory to obtain the decoded raw data and cannot perform other tasks, resulting in reduced work efficiency and significant energy consumption. Therefore, how to optimize the power consumption performance of wireless communication equipment in the processing of received packets is one of the main goals of the related industry. Summary of the invention
[0003] The present disclosure provides a wireless receiver device, which includes a decoder, a memory unit and a processor. The decoder is used to decode a packet during a plurality of symbols to obtain original data. The memory unit is used to temporarily store the original data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among the symbols according to the number of data bits per symbol and the number of symbols of the corresponding packet, and access the memory unit during the period of at least one non-idle symbol to perform data analysis and processing on the original data, but enter an idle state during the period of at least one idle symbol without accessing the memory unit.
[0004] The present disclosure further proposes a data processing method, which is applicable to a wireless receiver device and includes: decoding a packet during a plurality of symbols to obtain original data; temporarily storing the original data in a memory unit; and determining at least one non-idle symbol and at least one idle symbol among these symbols based on the number of data bits per symbol and the number of symbols of the corresponding packet, and accessing the memory unit during at least one non-idle symbol to perform data analysis and processing on the original data, but entering an idle state without accessing the memory unit during at least one idle symbol.
[0005] The present disclosure further proposes a wireless receiver device, which includes a wireless transmitter device and a wireless receiver device, wherein the wireless transmitter device is configured to transmit packets, and the wireless receiver device is configured to receive packets via a wireless channel. The wireless receiver device includes a decoder, a memory unit, and a processor. The decoder is used to decode packets during a plurality of symbols to obtain original data. The memory unit is used to temporarily store the original data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among these symbols based on the number of data bits per symbol and the number of symbols of the corresponding packet, and access the memory unit during at least one non-idle symbol to perform data analysis and processing on the original data, but enter an idle state during at least one idle symbol without accessing the memory unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] For a more complete understanding of the embodiments and their advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:
[0007] Figure 1 is a schematic diagram of a wireless communication system according to an embodiment of the present disclosure;
[0008] Figure 2 is a circuit block diagram of a wireless receiver device according to an embodiment of the present disclosure;
[0009] Figure 3 For use Figure 2 An example of a wireless receiver device decoding a packet;
[0010] Figure 4 Schematic diagram of a flow chart of a method for determining a symbol status according to an embodiment of the present disclosure;
[0011] Figure 5 and Figure 6 are examples of processor states at different numbers of data bits per symbol and the same number of symbols; and
[0012] Figure 7 It is a flowchart of the data processing method of the embodiment of the present disclosure. DETAILED DESCRIPTION
[0013] The following is a detailed discussion of the embodiments of the present disclosure. However, it is understood that the embodiments provide many applicable concepts that can be implemented in a variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the present disclosure.
[0014] According to current Wi-Fi system specifications, the transmission modes used by the Wi-Fi system may include, for example, orthogonal frequency division multiplexing (OFDM) transmission mode, high throughput (HT) mode, very high throughput (VHT) mode, high efficiency (HE) mode, etc., wherein the high throughput mode, very high throughput mode, and high efficiency mode correspond to wireless local area network (WLAN) standards of different communication generations such as Wi-Fi 4, Wi-Fi 5, and Wi-Fi 6, respectively. The better the hardware specifications of the wireless transceiver device and the more advanced the supported Wi-Fi system, the more transmission modes can be used. The disclosed embodiments may also support other wired and / or wireless communication technologies such as cellular networks, Bluetooth, local area networks (LAN), and / or Universal Serial Bus (USB).
[0015] Please refer to Figure 1 , Figure 1 Schematic diagram of a wireless communication system 100 of an embodiment of the present disclosure. The communication technology adopted by the wireless communication system 100 may be, for example, a wireless local area network communication technology that complies with the IEEE 802.11 standard (including IEEE 802.11ac, IEEE 802.11ax, etc.) and / or other applicable wireless communication technologies. The wireless communication system 100 includes wireless transceiver devices 110 and 120, which are connected via a wireless channel. The wireless transceiver devices 110 and 120 may have the functions of packet transmission and reception at the same time. For example, in a scenario where the wireless transceiver device 110 transmits a packet to the wireless transceiver device 120 via a wireless channel, the wireless transceiver devices 110 and 120 may also be referred to as a wireless transmitter device and a wireless receiver device, respectively.
[0016] The wireless channel in the wireless communication system 100 can support multiple-input multiple-output (MIMO) transmission, multiple-input single-output (MISO) transmission, single-input multiple-output (SIMO) transmission and / or single-input single-output (SISO) transmission between the wireless transceiver devices 110 and 120. Each of the wireless transceiver devices 110 and 120 can represent a variety of different implementations, including but not limited to mobile wireless transceiver devices such as stations (STA), notebook computers, mobile phones, tablet computers, and / or fixed wireless transceiver devices such as access points (AP), routers, switches, computer devices, server devices, and workstations.
[0017] Figure 2 FIG. 2 is a block diagram of a wireless receiver device 200 according to an embodiment of the present disclosure. The wireless receiver device 200 may be Figure 1 The wireless transceiver device 110 and / or the wireless transceiver device 120. The wireless receiver device 200 includes a decoder 210, a memory unit 220 and a processor 230. The decoder 210 is used to decode the received packet to obtain raw data. According to the coding technology used in the wireless communication system, the decoder 210 can be, for example, a convolutional decoder, a trellis decoder, a Viterbi decoder and / or a turbo decoder, but is not limited thereto. For example, if the wireless receiver device 200 is used in a wireless local area network communication system, the decoder 210 can be a Viterbi decoder.
[0018] The memory unit 220 is coupled to the decoder 210 and can be used to temporarily store the original data obtained after the decoder 210 decodes the packet. The memory unit 220 can be a data memory (DMEM), a static random access memory (SRAM) or other memory suitable for temporarily storing the original data.
[0019] The processor 230 is coupled to the memory unit 220, and can access the memory unit 220 to obtain the raw data temporarily stored in the memory unit 220, and perform data analysis (parsing) on the obtained raw data. The processor 230 can be, for example, a conventional processor, a multi-core processor, a digital signal processor (DSP), a microprocessor, or an application-specific integrated circuit (ASIC), but is not limited thereto.
[0020] The decoder 210 decodes the packet during a plurality of symbols to obtain the original data. Specifically, during each symbol, the decoder 210 decodes the corresponding segment in the packet to obtain N bits of data per symbol. DBPS When the number of remaining bits rest_bits of the original data after the decoder 210 decodes the packet and has not been written into the memory unit 220 is greater than the threshold bit number T bits , the decoder 210 may write part of the original data to the memory unit 220 for the processor 230 to perform data analysis and processing. In particular, according to the performance characteristics of the processor 230, such as the clock frequency, when the number of remaining bits of the original data rest_bits is greater than the threshold bit number T for the first time, bits , the decoder 210 writes a K-bit original data string to the memory unit 220. Then, before the last symbol, as long as the number of remaining bits of the original data rest_bits increases to a value greater than the threshold bit number T for a non-first time, bits , the decoder 210 writes two K-bit original data strings into the memory unit 220. During the last symbol, the decoder 210 writes all the original data that have not been written into the memory unit 220 into the memory unit 220.
[0021] Furthermore, when the decoder 210 decodes the packet during a plurality of symbols to obtain the original data and temporarily stores the original data in the memory unit, the processor 230 generates a corresponding packet according to the number of data bits per symbol N. DBPS The processor 230 accesses the memory unit 220 to perform data analysis on the original data during the non-idle symbol period. On the contrary, during the idle symbol period, the processor 230 enters an idle state without accessing the memory unit 220.
[0022] Figure 3 For use Figure 2An example of a wireless receiver device 200 decoding a packet. In this example, the wireless receiver device 200 receives and decodes a packet having a high efficiency multi-user (MU) physical layer protocol data unit (PPDU) format (also known as HE MUPPDU) and a modulation and coding scheme (MCS) index value of 5 in an IEEE 802.11ax wireless local area network, and the decoder 210 performs Viterbi decoding on the HE-SIG-B field in the received packet and writes a 64-bit string to the memory unit 220, and the HE-SIG-B field corresponds to 4 orthogonal frequency division multiplexing (OFDM) symbols (hereinafter referred to as OFDM symbols). During the first OFDM symbol, the decoder 210 decodes the first segment of the HE-SIG-B field in the packet. Since the number of remaining bits of the original data, rest_bits, is only 208 bits and does not exceed 256 bits, the decoder 210 does not write any 64-bit original data string to the memory unit 220, that is, there is no data writing event in the memory unit 220. During the second OFDM symbol, the decoder 210 decodes the second segment of the HE-SIG-B field in the packet, so that the number of remaining bits, rest_bits, increases to 416 bits and exceeds 256 bits, so the decoder 210 writes 1 64-bit original data string to the memory unit 220 (i.e., 1 arrow in block B1). After writing 1 64-bit string, the number of remaining bits, rest_bits, is still 352 bits and exceeds 256 bits, so the decoder 210 then writes 2 more 64-bit original data strings to the memory unit 220 (i.e., 2 arrows in block B2). During the third OFDM symbol, the decoder 210 decodes the third segment of the HE-SIG-B field in the packet, so that the number of remaining bits rest_bits accumulates to 432 bits and exceeds 256 bits, so the decoder 210 writes two 64-bit original data strings to the memory unit 220 (i.e., the two arrows in block B3). After writing the two 64-bit original data strings, the received bit count still has 304 bits and exceeds 256 bits, so the decoder 210 then writes two more 64-bit original data strings to the memory unit 220 (i.e., the two arrows in block B4). During the fourth OFDM symbol, the decoder 210 decodes the fourth segment of the HE-SIG-B field in the packet, and then divides the original data with the number of remaining bits rest_bits of 384 into six 64-bit original data strings and writes them to the memory unit 220 (i.e., the six arrows in block B5).
[0023] Figure 4 4 is a flow chart of a symbol state determination method 400 according to an embodiment of the present disclosure. The symbol state determination method 400 can be used to Figure 2 For example, in the example of the wireless receiver device 200 , the symbol state determination method 400 may be performed by the processor 230 .
[0024] In the symbol status determination method 400, operation S402 is first performed to obtain the number of data bits per symbol N. DBPS And the number of symbols N symbol , and initialize the number of remaining bits of the original data rest_bits to 0 and the symbol number i to 1. Then, operation S404 is performed to increase the number of remaining bits of the original data rest_bits by the number of bits per symbol data N DBPS Then, operation S406 is performed to determine whether the current symbol is the last symbol, that is, to determine whether the symbol number i is equal to the symbol number N. symbol If yes, then operation S408 is performed to record the current symbol (i.e., the i-th symbol) as a non-idle symbol, and the symbol status determination method 400 is terminated. Otherwise, if the current symbol is not the last symbol, then operation S410 is performed to determine whether the number of remaining bits of the original data rest_bits is greater than the threshold bit number T bits If the result of operation S410 is that the number of remaining bits of the original data, rest_bits, is greater than the threshold number of bits T bits , then operation S412 is performed to record the current symbol (i.e., the i-th symbol) as a non-idle symbol, and then operation S414 is performed to determine whether the number of remaining bits of the original data rest_bits is greater than the threshold bit number T for the first time. bits On the contrary, if the result of operation S410 is that the number of remaining bits of the original data, rest_bits, is not greater than the threshold number of bits T bits , then operation S416 is performed to record the current symbol (ie, the i-th symbol) as an idle symbol, and then operation S418 is performed to enter the next symbol (ie, the symbol number i increases by 1), and return to operation S404 to process the next symbol.
[0025] If the result of operation S414 is that the number of remaining bits of the original data rest_bits is greater than the threshold number of bits T for the first time bits , then operation S420 is performed to subtract the number of bits K of the original data string from the number of remaining bits rest_bits of the original data (i.e., perform rest_bits-K). On the contrary, if the result of operation S414 is that the number of remaining bits rest_bits of the original data is not greater than the threshold bit number T for the first time, bits, then proceed to operation S422, subtract the number of bits K of the two original data strings from the number of remaining bits rest_bits of the original data (i.e., perform rest_bits-2K). After operation S420 or operation S422 is completed, proceed to operation S424, and determine whether the number of remaining bits rest_bits of the original data is greater than the threshold number of bits T bits If the number of remaining bits of the original data, rest_bits, is greater than the threshold bit number T bits , then perform operation S422; otherwise, perform operation S418.
[0026] The threshold bit number T in the symbol state determination method 400 bits The bit number K of the original data string can be adjusted according to the hardware and software specifications and / or communication system specifications. In some embodiments, the threshold bit number T bits The number of bits K of the original data string needs to be greater than or equal to twice, that is, T bits ≥2K. In some embodiments, the threshold bit number T bits and the number of bits K of the original data string are 256 and 64, respectively. In addition, some operations in the symbol state determination method 400 also correspond to the operations of the decoder and the memory unit. Operation S404 corresponds to the decoder decoding the i-th HE-SIG-B packet, operation S408 corresponds to the event that the decoder writes all remaining data to the memory unit at the end of the period of the last symbol, operation S420 corresponds to the event that the decoder writes 1 K-bit original data string to the memory unit, and operation S422 corresponds to the event that the decoder writes 2 K-bit original data strings to the memory unit.
[0027] Figure 5 and Figure 6 For the number of data bits per symbol N DBPS and the same number of symbols N symbol An example of the following processor state, where the threshold bit number T bits The number of bits K of the original data string is 256 and 64 respectively. Figure 5 In the example, the number of data bits per symbol is N DBPS and the number of symbols N symbol 208 and 8 respectively. Figure 5 As shown in the figure, the decoder does not write any 64-bit original data string to the memory unit during the first symbol, so the processor is awakened during each symbol from the second to the eighth symbol to enter the working state. Figure 6 In the example, the number of data bits per symbol is N DBPS and the number of symbols N symbol 28 and 8 respectively. Figure 6It can be seen from the shown content that the decoder does not write any 64-bit original data string to the memory unit during the period from the 1st to the 7th symbol. Until the period of the 8th symbol, the decoder writes all the bit original data strings that have not yet been written to the memory unit, so the processor is awakened only during the 8th symbol to enter the working state.
[0028] Table 1 and Table 2 are the threshold bit number T bits The number of bits K of the original data string is 256 and 64 respectively. The number of bits per symbol N DBPS 13, 26, 52, 78, 104, 156, 208 and the number of symbols N symbol The table below shows the number of idle symbols and the proportion of idle symbols corresponding to 1 to 20. symbol At least 2, there will be at least 1 idle symbol, and at the same symbol number N symbol The smaller the number of data bits per symbol N is, the DBPS It may correspond to more idle symbols. In addition, it can be seen from Table 2 that the larger the number of symbols N symbol The smaller the number of symbols N symbol The larger the corresponding idle symbol ratio is, the more it can reduce power consumption and increase processor efficiency. DBPS 13 or 26 and the number of symbols N symbol For a system configuration of at least 2, the proportion of idle symbols is at least 50% and can be as high as 80% to 95%, indicating that the processor is idle as much as 80% to 95% of the time.
[0029] Table 1
[0030]
[0031]
[0032] Table 2
[0033]
[0034]
[0035] Figure 7 FIG. 7 is a flow chart of a data processing method 700 according to an embodiment of the present disclosure. The data processing method 700 can be used to Figure 2 For example, in the example of the wireless receiver device 200 , the data processing method 700 may be performed by the processor 230 .
[0036] In the data processing method 700, operation S702 is first performed, according to the number of data bits per symbol NDBPS And the number of symbols N symbol Generate a symbol status list. The symbol status list includes status information of whether each symbol is an idle symbol. In addition, the symbol status list can be generated by performing the symbol status determination method 400. In the process of performing the symbol status determination method 400, each symbol will be determined whether it is an idle symbol (i.e., an idle symbol or a non-idle symbol). For example, if the number of data bits per symbol is N DBPS and the number of symbols N symbol are 208 and 8 respectively. By performing the symbol status determination method 400, it can be determined that the first symbol is an idle symbol and the second to eighth symbols are all non-idle symbols. Therefore, the obtained symbol status list can be shown in the following Table 3.
[0037] Table 3
[0038]
[0039] Next, operation S704 is performed to determine whether the current symbol is an idle symbol according to the symbol status list. If so, operation S706 is performed to enter the idle state without accessing the memory unit, and the wake-up timer is set to determine the time when the processor wakes up from the idle state according to the order in which the next non-idle symbol appears, and when the wake-up timer ends, operation S708 is performed, the processor enters the wake-up state, and then operation S710 is performed to access the memory unit to obtain the original data string for data analysis and processing. On the contrary, if the judgment result of operation S704 is that the current symbol is a non-idle symbol, operation S710 is directly performed. After operation S710 is completed, operation S712 is then performed to determine whether the current symbol is the last symbol according to the symbol status list. If the current symbol is determined to be the last symbol, operation S714 is performed, and the processor completes the data analysis and processing. On the contrary, if the current symbol is determined not to be the last symbol, operation S716 is performed to enter the next symbol and return to operation S704.
[0040] As can be seen from the above description, the disclosed embodiment can predict whether there is an event of a decoded bit data string being written to the memory unit during each symbol, and decide whether the processor enters the awake state to perform data analysis and processing on the bit data string stored in the memory unit or enters the idle state based on the prediction result. Therefore, compared with the conventional processing method, the disclosed embodiment can make the processor enter the idle state when there is no event of writing to the memory unit and not access the memory unit until the decoded original data is written to the memory unit and then access the memory unit for data analysis and processing, thereby achieving the effect of saving power consumption.
[0041] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.
[0042]
Explanation of symbols
[0043] 100: Wireless communication system
[0044] 110,120: Wireless transceiver equipment
[0045] 200: Wireless receiver equipment
[0046] 210:Decoder
[0047] 220: memory unit
[0048] 230: Processor
[0049] 400: Symbol status determination method
[0050] 700: Data processing method
[0051] B1-B5: Blocks
[0052] S402-S424, S702-S716: operation.
Claims
1. A wireless receiver device, comprising: A decoder, for decoding a packet during a plurality of symbols to obtain an original data; a memory unit for temporarily storing the original data; and A processor is configured to determine at least one non-idle symbol and at least one idle symbol among the multiple symbols based on a number of data bits per symbol and a number of symbols corresponding to the packet, and access the memory unit during the at least one non-idle symbol to perform data analysis processing on the original data, but enter an idle state without accessing the memory unit during the at least one idle symbol.
2. The wireless receiver apparatus of claim 1, wherein the decoder is a Viterbi decoder.
3. The wireless receiver device of claim 1 , wherein the decoder is configured to perform the following processing on the original data: When a remaining number of bits of the original data is greater than a threshold number of bits for the first time, writing an original data string of the original data into the memory unit; When the number of remaining bits of the original data is greater than the threshold number of bits for a non-first time, writing two original data strings in the original data into the memory unit; and During a last symbol among the plurality of symbols, original data that has not been written into the memory cell among the original data is written into the memory cell. 4 . The wireless receiver device as claimed in claim 3 , wherein a bit number of each of the plurality of the original data strings is 64, and the threshold bit number is 256.
5. The wireless receiver device as claimed in claim 1, wherein the number of data bits per symbol is 13 or 26.
6. The wireless receiver device as claimed in claim 1, wherein the processor is configured to generate a symbol status list according to the number of data bits per symbol and the number of symbols, the symbol status list comprising status information of whether each of the plurality of symbols is an idle symbol. 7 . The wireless receiver device as claimed in claim 6 , wherein the processor is configured to set a wake-up timer according to the symbol state list when entering the idle state, and enter an awake state when the wake-up timer expires.
8. A data processing method, applicable to a wireless receiver device, the data processing method comprising: Decoding a packet during a plurality of symbols to obtain an original data; temporarily storing the original data in a memory unit; and At least one non-idle symbol and at least one idle symbol among the multiple symbols are determined according to a number of data bits per symbol and a number of symbols corresponding to the packet, and the memory unit is accessed during the at least one non-idle symbol to perform data analysis processing on the original data, but an idle state is entered during the at least one idle symbol without accessing the memory unit.
9. The data processing method as claimed in claim 8, wherein temporarily storing the original data in the memory unit comprises: When a remaining number of bits of the original data is greater than a threshold number of bits for the first time, writing an original data string of the original data into the memory unit; When the number of remaining bits of the original data is greater than the threshold number of bits for a non-first time, writing two original data strings in the original data into the memory unit; and During a last symbol among the plurality of symbols, original data that has not been written into the memory cell among the original data is written into the memory cell.
10. A wireless communication system, comprising: a wireless transmitter device configured to transmit a packet; and A wireless receiver device configured to receive the packet via a wireless channel, the wireless receiver device comprising: A decoder, for decoding the packet during a plurality of symbols to obtain an original data; a memory unit for temporarily storing the original data; and A processor is configured to determine at least one non-idle symbol and at least one idle symbol among the multiple symbols based on a number of data bits per symbol and a number of symbols corresponding to the packet, and access the memory unit during the at least one non-idle symbol to perform data analysis processing on the original data, but enter an idle state without accessing the memory unit during the at least one idle symbol.