Wireless receiver equipment, data processing method thereof and wireless communication system
By managing non-idle and idle symbols based on the symbol number and processor performance characteristics in wireless receiver devices, the problem of inefficiency when the processor waits for memory write events is solved, and more efficient power consumption management is achieved.
Patent Information
- Application Number
- CN202310770945.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-27
- Publication Date
- 2024-12-27
AI Technical Summary
In wireless communication, the processor cannot perform other tasks while waiting for memory write events, resulting in reduced work efficiency and significant energy consumption, and unable to achieve optimal power consumption performance.
Design a wireless receiver device that includes a decoder, memory unit and processor to decode aggregated packets during multiple symbols and determine non-idle and idle symbols based on the number of symbols and processor performance characteristics, only during non-idle symbols Access memory for data analysis and processing, and enters idle state at other times.
Through this method, the processor efficiently processes data during non-idle symbols and enters a low-power idle state at other times, significantly improving the power consumption performance of wireless communication devices.
Smart Images
Figure CN119210645A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to receiving packet decoding and analysis processing, and in particular to a wireless receiver device and a data processing method thereof and a wireless communication system. Background Art
[0002] In wireless communication, the transmitting end usually encodes the raw data to form a packet, and then the receiving end decodes the packet to restore it to the original data. When receiving a packet, the decoder usually decodes the packet to obtain the raw data and writes the raw data to the memory. The processor then accesses the memory to obtain the raw data and performs data analysis on the raw data. Since it is impossible to predict when the memory write event will occur, the processor needs to continuously access the memory to obtain the decoded raw data and cannot perform other tasks, resulting in reduced work efficiency and significant energy consumption. Therefore, how to optimize the power consumption performance of wireless communication equipment in the processing of received packets is one of the main goals of the related industry. Summary of the invention
[0003] The present disclosure provides a wireless receiver device, which includes a decoder, a memory unit and a processor. The decoder is used to decode an aggregated packet during a plurality of symbols to obtain original data, and the aggregated packet has a plurality of sub-blocks. The memory unit is used to temporarily store the original data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among the symbols according to the number of symbols, the number of data bits per symbol corresponding to the sub-blocks, and the performance characteristics of the processor, and access the memory unit during the period of at least one non-idle symbol to perform data analysis and processing on the original data, but enter an idle state during the period of at least one idle symbol without accessing the memory unit.
[0004] The present disclosure further proposes a data processing method, which is applicable to a wireless receiver device and includes: decoding an aggregate packet during a plurality of symbols to obtain original data, wherein the aggregate packet has a plurality of sub-blocks; temporarily storing the original data in a memory unit; and determining at least one non-idle symbol and at least one idle symbol among the symbols based on the number of symbols, the number of data bits per symbol corresponding to the sub-blocks, and the performance characteristics of the processor, and accessing the memory unit during the period of at least one non-idle symbol to perform data analysis and processing on the original data, but entering an idle state without accessing the memory unit during the period of at least one idle symbol.
[0005] The present disclosure further proposes a wireless receiver device, which includes a wireless transmitter device and a wireless receiver device, wherein the wireless transmitter device is configured to transmit an aggregate packet, and the wireless receiver device is configured to receive the aggregate packet via a wireless channel, wherein the aggregate packet has multiple sub-blocks. The wireless receiver device includes a decoder, a memory unit, and a processor. The decoder is used to decode the aggregate packet during multiple symbols to obtain original data. The memory unit is used to temporarily store the original data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol among the symbols based on the number of symbols, the number of data bits per symbol corresponding to the sub-blocks, and the performance characteristics of the processor, and access the memory unit during the period of at least one non-idle symbol to perform data analysis and processing on the original data, but enter an idle state during the period of at least one idle symbol without accessing the memory unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] For a more complete understanding of the embodiments and their advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:
[0007] Figure 1 is a schematic diagram of a wireless communication system according to an embodiment of the present disclosure;
[0008] Figure 2 is a circuit block diagram of a wireless receiver device according to an embodiment of the present disclosure;
[0009] Figure 3 For use Figure 2 An example of a wireless receiver device performing packet decoding processing;
[0010] Figure 4 It is a flowchart of a method for counting the number of original data strings in a symbol according to an embodiment of the present disclosure;
[0011] Figure 5A and Figure 5B is an example of processor states at different numbers of data bits per symbol and the same number of symbols;
[0012] Figure 6 A statistical table showing the number of original data strings with a specific number of symbols and the number of data bits per symbol;
[0013] Figure 7 Schematic diagram of the flow of the method for determining the category of an aggregation symbol according to an embodiment of the present disclosure;
[0014] Fig. 8A and Figure 8B They are respectively a list of aggregate symbol categories under different processor performances of an example of the present disclosure;
[0015] Fig. 9 A flowchart of a data processing method according to an embodiment of the present disclosure;
[0016] Fig. 10A and Fig. 10B A list of aggregation symbol categories under different processor performances of the first comparative example; and
[0017] Fig.11A and Fig. 11B They are respectively a list of aggregation symbol categories under different processor performances of the second comparative example. DETAILED DESCRIPTION
[0018] The following is a detailed discussion of the embodiments of the present disclosure. However, it is understood that the embodiments provide many applicable concepts that can be implemented in a variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the present disclosure.
[0019] According to current Wi-Fi system specifications, the transmission modes used by Wi-Fi systems may include, for example, orthogonal frequency division multiplexing (OFDM) transmission mode, high throughput (HT) mode, very high throughput (VHT) mode, high efficiency (HE) mode, and extremely high throughput (EHT) mode, among which the high throughput mode, very high throughput mode, high efficiency mode, and extremely high throughput mode correspond to wireless local area network (WLAN) standards of different communication generations, such as Wi-Fi 4, Wi-Fi 5, Wi-Fi 6, and Wi-Fi 7. The better the hardware specifications of the wireless transceiver and the more advanced the Wi-Fi system it supports, the more transmission modes that can be used. The disclosed embodiments may also support other wired and / or wireless communication technologies such as cellular network, Bluetooth, local area network (LAN) and / or Universal Serial Bus (USB).
[0020] Please refer to Figure 1 , Figure 1Schematic diagram of a wireless communication system 100 of an embodiment of the present disclosure. The communication technology adopted by the wireless communication system 100 may be, for example, a wireless local area network communication technology that complies with the IEEE 802.11 standard (including IEEE 802.11ac, IEEE 802.11ax, IEEE 802.11be, etc.) and / or other applicable wireless communication technologies. The wireless communication system 100 includes wireless transceiver devices 110 and 120, which are connected via a wireless channel. The wireless transceiver devices 110 and 120 may have the functions of packet transmission and reception at the same time. For example, in a scenario where the wireless transceiver device 110 transmits a packet to the wireless transceiver device 120 via a wireless channel, the wireless transceiver devices 110 and 120 may also be referred to as a wireless transmitter device and a wireless receiver device, respectively.
[0021] The wireless channel in the wireless communication system 100 can support multiple-input multiple-output (MIMO) transmission, multiple-input single-output (MISO) transmission, single-input multiple-output (SIMO) transmission and / or single-input single-output (SISO) transmission between the wireless transceiver devices 110 and 120. Each of the wireless transceiver devices 110 and 120 can represent a variety of different implementations, including but not limited to mobile wireless transceiver devices such as stations (STA), notebook computers, mobile phones, tablet computers, and / or fixed wireless transceiver devices such as access points (AP), routers, switches, computer devices, server devices, and workstations.
[0022] Figure 2 FIG. 2 is a block diagram of a wireless receiver device 200 according to an embodiment of the present disclosure. The wireless receiver device 200 may be Figure 1The wireless transceiver device 110 and / or the wireless transceiver device 120. The wireless receiver device 200 includes a decoder 210, a memory unit 220 and a processor 230. The decoder 210 is used to decode the received packet to obtain the original data (rawdata). According to the coding technology used in the wireless communication system, the decoder 210 can be, for example, a convolutional decoder, a trellis decoder, a Viterbi decoder and / or a turbo decoder, but is not limited thereto. For example, if the wireless receiver device 200 is used in a wireless local area network communication system, the decoder 210 can be a Viterbi decoder.
[0023] The memory unit 220 is coupled to the decoder 210 and can be used to temporarily store the original data obtained after the decoder 210 decodes the packet. The memory unit 220 can be a data memory (DMEM), a static random access memory (SRAM) or other memory suitable for temporarily storing the original data.
[0024] The processor 230 is coupled to the memory unit 220, and can access the memory unit 220 to obtain the original data temporarily stored in the memory unit 220, and perform data analysis (parsing) on the obtained original data. The processor 230 can be, for example, a conventional processor, a multi-core processor, a digital signal processor (DSP), a microprocessor, or an application-specific integrated circuit (ASIC), but is not limited thereto.
[0025] The decoder 210 decodes the packet during a plurality of symbols to obtain the original data. Specifically, during each symbol, the decoder 210 decodes the corresponding segment in the packet to obtain N bits of data per symbol. DBPS When the number of remaining bits rest_bits of the original data after the decoder 210 decodes the packet and has not been written into the memory unit 220 is greater than the threshold bit number T bits , the decoder 210 may write part of the original data to the memory unit 220 for the processor 230 to perform data analysis and processing. In particular, according to the performance characteristics of the processor 230, such as the clock frequency, when the number of remaining bits of the original data rest_bits is greater than the threshold bit number T for the first time,bits , the decoder 210 writes 1 K-bit original data string to the memory unit 220. Then, before the last symbol, as long as the number of remaining bits of the original data rest_bits increases to a value greater than the threshold bit number T for a non-first time, bits , the decoder 210 writes 2K-bit original data strings into the memory unit 220. During the last symbol, the decoder 210 writes all original data that have not been written into the memory unit 220 into the memory unit 220.
[0026] Figure 3 For use Figure 2An example of a wireless receiver device 200 decoding a packet. In this example, the wireless receiver device 200 receives and decodes a packet having a high efficiency multi-user physical layer protocol data unit (also known as HE MU PPDU) format and a modulation and coding scheme (MCS) index value of 5 in an IEEE 802.11ax wireless local area network. The decoder 210 performs Viterbi decoding on the HE-SIG-B field in the received packet and writes it to the memory unit 220 as a 64-bit string, and the HE-SIG-B field corresponds to 4 orthogonal frequency division multiplexing (OFDM) symbols (hereinafter referred to as OFDM symbols). During the first OFDM symbol, the decoder 210 decodes the first segment of the HE-SIG-B field in the packet. Since the number of remaining bits of the original data, rest_bits, is only 208 bits and does not exceed 256 bits, the decoder 210 does not write any 64-bit original data string to the memory unit 220, that is, there is no data writing event in the memory unit 220. During the second OFDM symbol, the decoder 210 decodes the second segment of the HE-SIG-B field in the packet, so that the number of remaining bits, rest_bits, increases to 416 bits and exceeds 256 bits, so the decoder 210 writes 1 64-bit original data string to the memory unit 220 (i.e., 1 arrow in block B1). After writing 1 64-bit string, the number of remaining bits, rest_bits, is still 352 bits and exceeds 256 bits, so the decoder 210 then writes 2 more 64-bit original data strings to the memory unit 220 (i.e., 2 arrows in block B2). During the third OFDM symbol, the decoder 210 decodes the third segment of the HE-SIG-B field in the packet, so that the remaining bit number rest_bits accumulates to 432 bits and exceeds 256 bits, so the decoder 210 writes two 64-bit original data strings to the memory unit 220 (i.e., the two arrows in block B3). After writing the two 64-bit original data strings, the remaining bit number rest_bits is still 304 bits and exceeds 256 bits, so the decoder 210 then writes two more 64-bit original data strings to the memory unit 220 (i.e., the two arrows in block B4). During the fourth OFDM symbol, the decoder 210 decodes the fourth segment of the HE-SIG-B field in the packet, and then divides the original data with the remaining bit number rest_bits of 384 into 6 64-bit original data strings and writes them to the memory unit 220 (i.e., the 6 arrows in block B5).
[0027] Figure 44 is a flow chart of a method 400 for counting the number of original data strings in a symbol according to an embodiment of the present disclosure. The method 400 for counting the number of original data strings in a symbol can be used to Figure 2 For example, in the example of the wireless receiver device 200 , the method 400 for counting the number of original data strings in a symbol may be performed by the processor 230 .
[0028] In the method 400 for counting the number of original data strings in a symbol, operation S402 is first performed to obtain the number of data bits per symbol N. DBPS And the number of symbols N symbol , and the number of remaining bits of the original data is initialized to 0, corresponding to the 1st to the Nth symbol The number of original data strings of the symbol DB(1)-DB(N symbol ) are all 0 and the symbol number i is 1. Then, operation S404 is performed to increase the number of remaining bits of the original data rest_bits by the number of bits per symbol data N DBPS Then, operation S406 is performed to determine whether the i-th symbol (ie, the current symbol) is the last symbol, that is, to determine whether the symbol number i is equal to the symbol number N. symbol If yes, then proceed to operation S408, record the number of original data strings DB(i) corresponding to the i-th symbol as A method 400 for counting the number of original data strings in the end symbol, wherein represents a ceiling function operation. Otherwise, if the current symbol is not the last symbol, operation S410 is performed to determine whether the number of remaining bits of the original data rest_bits is greater than the threshold bit number T bits If the result of operation S410 is that the number of remaining bits of the original data, rest_bits, is greater than the threshold number of bits T bits , then operation S412 is performed to further determine whether the number of remaining bits of the original data rest_bits is greater than the threshold bit number T for the first time bits On the contrary, if the result of operation S410 is that the number of remaining bits of the original data, rest_bits, is not greater than the threshold number of bits T bits , then operation S414 is performed to enter the next symbol (ie, the symbol number i is increased by 1), and the process returns to operation S404 to process the next symbol.
[0029] If the result of operation S412 is that the number of remaining bits of the original data rest_bits is greater than the threshold number of bits T for the first time bits, then operation S416 is performed to subtract the number of bits K of one original data string from the number of remaining bits rest_bits of the original data (i.e., perform rest_bits-K), and increase the number of original data strings DB(i) corresponding to the i-th symbol by 1. On the contrary, if the judgment result of operation S412 is that the number of remaining bits rest_bits of the original data is not greater than the threshold bit number T for the first time, bits , then operation S418 is performed to subtract the number of bits K of the two original data strings from the number of remaining bits rest_bits of the original data (i.e., rest_bits-2K), and the number of original data strings DB(i) corresponding to the i-th symbol is increased by 2. After operation S416 or operation S418 is completed, operation S420 is performed to determine whether the number of remaining bits rest_bits of the original data is greater than the threshold bit number T bits If the number of remaining bits of the original data, rest_bits, is greater than the threshold bit number T bits , then proceed to operation S418. Otherwise, if it is determined that the number of remaining bits of the original data rest_bits is not greater than the threshold number of bits T bits , then perform operation S414.
[0030] The threshold bit number T in the method 400 for counting the number of original data strings in a symbol bits The bit number K of the original data string can be adjusted according to the hardware and software specifications and / or communication system specifications. In some embodiments, the threshold bit number T bits Should be greater than or equal to twice the number of bits K of the original data string, that is, T bits ≥2K. In some embodiments, the threshold bit number T bits and the number of bits K of the original data string are 256 and 64, respectively. In addition, some operations in the method 400 for counting the number of original data strings in a symbol also correspond to the operations of the decoder and the memory unit. Operation S404 corresponds to the decoder decoding the i-th HE-SIG-B packet, operation S408 corresponds to the event that the decoder writes all remaining data to the memory unit at the end of the period of the last symbol, operation S416 corresponds to the event that the decoder writes 1 K-bit original data string to the memory unit, and operation S418 corresponds to the event that the decoder writes 2 K-bit original data strings to the memory unit.
[0031] Figure 5A and Figure 5B is the number of data bits per symbol N DBPS and the same number of symbols N symbol An example of the following processor state, where the threshold bit number T bits The number of bits K of the original data string is 256 and 64 respectively. Figure 5A In the example, the number of data bits per symbol is N DBPSand the number of symbols N symbol 208 and 8 respectively. Figure 5A As shown in the figure, the decoder does not write any 64-bit original data string to the memory unit during the first symbol, so the processor is awakened during each symbol from the second to the eighth symbol to enter the awakened state (e.g., working state) and work. Figure 5B In the example, the number of data bits per symbol is N DBPS and the number of symbols N symbol 28 and 8 respectively. Figure 5B As can be seen from the shown content, the decoder did not write any 64-bit original data string to the memory unit during the period from the 1st to the 7th symbol. Until the period of the 8th symbol, the decoder wrote all the original data strings that have not yet been written to the memory unit, so the processor is awakened only during the 8th symbol to enter the awakened state.
[0032] Figure 6 Shows the number of symbols N symbol is 20 and the number of data bits per symbol is N DBPS The original data string number statistics table TB is 13, 26, 52, 78, 104, 156, 208. The original data string number statistics table TB can be generated by performing the original data string number statistics method 400 in the symbol. DBPS Taking 104 as an example, the numbers of original data strings during the 3rd and 4th symbols are 1 and 2 respectively, which means that the decoder writes 1 and 2 original data strings into the memory unit during the 3rd and 4th symbols respectively.
[0033] In the IEEE 802.11be wireless local area network, multiple EHT-SIG content channels and multiple sub-blocks can be used for aggregated downlink transmission. For example, a channel with a bandwidth of 320MHz has 4 sub-blocks, and each sub-block has N data bits per symbol. DBPS , which is determined by the modulation and coding scheme (MCS) index value (hereinafter referred to as MCS index value) and the dual-channel modulation (DCM) setting value (hereinafter referred to as DCM setting value). The MCS index value and DCM setting value corresponding to each sub-block can be obtained from the U-SIG field in the extremely high throughput multi-user protocol data unit (also known as EHT MU PPDU) format.
[0034] Table 1 shows the MCS index value, DCM setting value and number of data bits per symbol N for each EHT-SIG field in the VHT MU PPDU. DBPSAccording to the content shown in Table 1, if the MCS index value is 0, the corresponding number of data bits per symbol when the DCM setting value is 0 (i.e., dual carrier modulation is not used) and 1 (i.e., dual carrier modulation is used) is N. DBPS 13 and 26 respectively. The number of data bits per symbol corresponding to other MCS index values and DCM setting values is N DBPS It can be obtained from the content shown in Table 1.
[0035] Table 1
[0036]
[0037]
[0038] Furthermore, the processor may select a corresponding MCS index value and a DCM setting value (ie, the number of data bits per symbol N corresponding to each sub-block) according to its performance characteristics and the MCS index value and DCM setting value corresponding to each sub-block. DBPS ) etc. to determine the status of each aggregated symbol (the symbol after aggregating multiple sub-blocks).
[0039] Figure 7 FIG. 7 is a flow chart of a method 700 for determining the category of an aggregation symbol according to an embodiment of the present disclosure. The method 700 for determining the category of an aggregation symbol can be used to Figure 2 For example, in the example of the wireless receiver device 200 , the aggregation symbol category determination method 700 may be performed by the processor 230 .
[0040] In the method 700 for determining the type of aggregated symbol, operation S702 is first performed to aggregate the number of original data strings output by each sub-block in each symbol to generate a list of the number of aggregated original data strings output by each aggregated symbol (the number of aggregated original data strings CDB(i) is the sum of the number of original data strings DB(i) of each sub-block), and initialize the remaining number of aggregated original data strings rest_CDB to 0 and the symbol number i to 1. Figure 6 Taking the original data string number statistics table TB as an example, if the number of data bits per symbol N is used DBPS The four sub-blocks of 26, 52, 78 and 104 are aggregated for downlink transmission. The original data string number lists of these sub-blocks are the corresponding data bit numbers N per symbol in the original data string number statistics table TB. DBPS The columns are 26, 52, 78 and 104, and the list of the number of aggregated original data strings is the sum of the above columns (for example, the number of original data strings DB(5) of these four sub-blocks are 0, 1, 2, 2 respectively, and the number of aggregated original data strings CDB(5) in the list of the number of aggregated original data strings is 0+1+2+2=5).
[0041] Next, operation S704 is performed, and the number of remaining aggregated original data strings rest_CDB is increased by the number of aggregated original data strings CDB(i) of the current symbol (i.e., the i-th symbol). After that, operation S706 is performed to determine whether the current symbol is the last symbol, i.e., whether the symbol number i is equal to the symbol number N symbol If yes, then proceed to operation S708 to make the number of symbols N symbol Plus Where M is the maximum number of raw data strings that the processor can process per symbol, and records the next symbol to the last symbol (the Symbol) is a non-idle symbol, and then the aggregate symbol category determination method 700 ends. On the contrary, if the current symbol is not the last symbol, operation S710 is performed to determine whether the number of remaining aggregated original data strings rest_CDB is greater than or equal to the maximum number of original data strings processed per symbol of the processor M. If the determination result of operation S710 is that the number of remaining aggregated original data strings rest_CDB is greater than or equal to the maximum number of original data strings processed per symbol of the processor M, operation S712 is performed to record the next symbol (i.e., the i+1th symbol) as a non-idle symbol, and operation S714 is performed to subtract the maximum number of original data strings processed per symbol of the processor M from the number of remaining aggregated original data strings rest_CDB. On the contrary, if the judgment result of operation S710 is that the remaining number of aggregated original data strings rest_CDB is less than the maximum number of original data strings M that can be processed per symbol of the processor, operation S716 is performed to determine whether the sum of the remaining number of aggregated original data strings rest_CDB and the number of aggregated original data strings CDB(i+1) of the next symbol (i.e., the i+1th symbol) is greater than the maximum number of original data strings M that can be processed per symbol of the processor. If it is determined that the sum of the number of remaining aggregated original data strings rest_CDB and the number of aggregated original data strings CDB(i+1) of the next symbol (i.e., the i+1 symbol) is greater than the maximum number of original data strings M processed per symbol by the processor, operations S712 and S714 are performed; conversely, if it is determined that the sum of the number of remaining aggregated original data strings rest_CDB and the number of aggregated original data strings CDB(i+1) of the next symbol (i.e., the i+1 symbol) is not greater than the maximum number of original data strings M processed per symbol by the processor, operation S718 is performed to record the next symbol (i.e., the i+1 symbol) as an idle symbol. After operation S714 or operation S718 is completed, operation S720 is performed to enter the next symbol (i.e., the symbol number i increases by 1), and return to operation S704 to process the next symbol.
[0042] According to the present disclosure, the wireless receiver device 200 uses the aggregate symbol category determination method 700 to obtain the category of each aggregate symbol, and determines whether the processor 230 enters or maintains the idle state during the idle symbol, and enters or maintains the awake state during the non-idle symbol. Therefore, it can be ensured that the processor 230, which can process a maximum number of original data strings per symbol of M, obtains a maximum of M aggregated original data strings from the memory unit 220 during each non-idle symbol when in the awake state, so as to process the original data in the shortest time, thereby achieving the optimization of processing performance.
[0043] Fig. 8A and Figure 8B The maximum number of original data strings M processed by the processor of an example of the present disclosure per symbol is 6 and 8, and the number of data bits per symbol of the 1st to 4th sub-blocks is N. DBPS They are 26, 52, 104, 52 respectively, and the number of symbols is N symbol is 20, and the threshold bit number T bits The aggregate symbol category lists CTB1 and CTB2 are respectively 256 and 64 when the number of bits K of the original data string is 256 and 64. The number of the original data strings output from the first to the fourth sub-blocks can be obtained by performing the original data string number counting method 400 in the symbol, and the total number of the output original data strings is the number of aggregate original data strings per symbol, and the symbol category can be obtained by performing the aggregate symbol category determination method 700. Fig. 8A and Figure 8B As shown, under the condition of receiving the same aggregated packet, in the aggregated symbol category list CTB1, 10 symbols out of 23 symbols are idle symbols, and in the aggregated symbol category list CTB2, 13 symbols out of 23 symbols are idle symbols. That is to say, the processor whose maximum number of processed original data strings per symbol is 6 is in an idle state in 10 idle symbols, and the processor whose maximum number of processed original data strings per symbol is 8 is in an idle state in 13 idle symbols. Therefore, under the condition of better processor performance (larger maximum number of processed original data strings per symbol M), the processor can have more idle states (i.e., longer total time in idle state), so it has better power consumption performance.
[0044] Fig. 9 FIG. 9 is a flow chart of a data processing method 900 according to an embodiment of the present disclosure. The data processing method 900 can be used to Figure 2 For example, in the example of the wireless receiver device 200 , the data processing method 900 may be performed by the processor 230 .
[0045] In the data processing method 900, operation S902 is first performed, based on the processor performance, the number of symbols N symboland the number of data bits per symbol of all sub-blocks N DBPS Generate an aggregate symbol category list. The aggregate symbol category list may include category information of whether each symbol is an idle symbol (i.e., an idle symbol or a non-idle symbol). The aggregate symbol category list may be Fig. 8A Aggregate symbol category list CTB1 or Figure 8B The aggregate symbol category list CTB2 is shown, and it can be obtained by performing the original data string number counting method 400 in the symbol and the aggregate symbol category determination method 700.
[0046] Next, operation S904 is performed to determine whether the current symbol is an idle symbol according to the aggregate symbol category list. If so, operation S906 is performed to enter the idle state, and a wake-up timer is set according to the aggregate symbol category list (the time when the processor wakes up from the idle state is determined according to the order in which the next non-idle symbol appears), and when the wake-up timer ends, operation S908 is performed, the processor enters the wake-up state, and then operation S910 is performed to obtain the original data string from the memory unit for data analysis processing. On the contrary, if the judgment result of operation S904 is that the current symbol is a non-idle symbol, operation S910 is directly performed. After operation S910 is completed, operation S912 is entered to determine whether the current symbol is the last symbol according to the aggregate symbol category list. If the current symbol is determined to be the last symbol, operation S914 is performed, and the processor completes the data analysis processing. On the contrary, if the current symbol is determined not to be the last symbol, operation S916 is performed to enter the next symbol and return to operation S904.
[0047] Fig. 10A and Fig. 10B The maximum number of original data strings M processed by the processor in each symbol of the first comparative example is 6 and 8, and the number of data bits per symbol of the first to fourth sub-blocks is N. DBPS They are 26, 52, 104, 52, and the number of symbols N. symbol is 20, and the threshold bit number T bits The aggregate symbol category lists RTB1 and RTB2 are respectively 256 and 64 bits of the original data string. The processor polls the memory unit during each symbol to obtain the original data temporarily stored in the memory unit. Fig. 10A and Fig. 10B As shown, in the polling mode, each symbol is a non-idle symbol, so no matter whether there is original data temporarily stored in the memory unit and no matter what the performance of the processor is, the processor remains in the awake state during each symbol, which does not have any effect of reducing power consumption.
[0048] Fig.11A and Fig. 11BThe maximum number of original data strings M processed by the processor of the second comparative example per symbol is 6 and 8, and the number of data bits per symbol of the first to fourth sub-blocks is N. DBPS They are 26, 52, 104, 52, and the number of symbols N. symbol is 20, and the threshold bit number T bits and the aggregation symbol category lists RTB3 and RTB4 when the number of bits K of the original data string is 256 and 64 respectively. In the second comparative example, as long as any sub-block from the 1st to the 4th sub-block outputs any original data string during the current symbol, the next symbol is a non-idle symbol. On the contrary, if none of the 1st to the 4th sub-blocks outputs any original data string during the current symbol, the next symbol is an idle symbol. In other words, the processor decides whether to enter the awake state or the idle state based on whether there is original data written to the memory unit during each symbol. For example, if Fig.11A As shown, the number of original data strings written to the memory cell during the 8th symbol is 0, so the processor is in an idle state during the 9th symbol. The number of original data strings written to the memory cell during the 9th symbol is 4 instead of 0, so the processor is in an awake state during the 10th symbol. Fig. 8A , Figure 8B , Fig.11A and Fig. 11B It can be seen that the processor of the embodiment of the present disclosure can have more idle time, thereby achieving better power consumption performance.
[0049] From the above description, it can be seen that the present disclosure improves power consumption performance by causing the processor to enter a wake-up state to access the memory unit and obtain the original data for data analysis and processing when the memory unit accumulates a considerable number of decoded original data strings, and causing the processor to enter an idle state at other times.
[0050] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.
[0051]
Explanation of symbols
[0052] 100: Wireless communication system
[0053] 110,120: Wireless transceiver equipment
[0054] 200: Wireless receiver equipment
[0055] 210:Decoder
[0056] 220: memory unit
[0057] 230: Processor
[0058] 400: Method for counting the number of original data strings in a symbol
[0059] 700: Aggregation symbol category determination method
[0060] 900: Data processing method
[0061] B1-B5: Blocks
[0062] CTB1-CTB2,RTB1-RTB4: Aggregation symbol category list
[0063] S402-S420, S702-S720, S902-S916: Operation
[0064] TB: Statistics table of the number of original data strings.
Claims
1. A wireless receiver device, comprising: a decoder for decoding an aggregate packet during a plurality of symbols to obtain original data, wherein the aggregate packet has a plurality of sub-blocks; a memory unit for temporarily storing the original data; and A processor is configured to determine at least one non-idle symbol and at least one idle symbol among the multiple symbols based on a symbol number, a plurality of data bit numbers per symbol respectively corresponding to the multiple sub-blocks, and a performance characteristic of the processor, and access the memory unit during a period of the at least one non-idle symbol to perform data analysis processing on the original data, but enter an idle state without accessing the memory unit during a period of the at least one idle symbol.
2. The wireless receiver apparatus of claim 1, wherein the decoder is a Viterbi decoder.
3. A wireless receiver device as described in claim 1, wherein the processor is configured to obtain a maximum of M aggregated original data strings of the original data from the memory unit during each of the at least one non-idle symbol, wherein M is a maximum number of original data strings that can be processed per symbol by the processor.
4. The wireless receiver device as claimed in claim 3, wherein the maximum number of processed original data strings per symbol is 6 or 8. The wireless receiver device as claimed in claim 1 , wherein the plurality of sub-blocks is 4 sub-blocks.
6. The wireless receiver device of claim 1, wherein the processor is configured to generate an aggregate symbol category list according to the performance characteristic, the plurality of data bits per symbol and the number of symbols, the aggregate symbol category list comprising category information of whether each of the plurality of symbols is an idle symbol. 7 . The wireless receiver device as claimed in claim 6 , wherein the processor is configured to, when entering the idle state, set a wake-up timer according to the aggregated symbol category list, and enter an awake state when the wake-up timer expires.
8. A data processing method, applicable to a wireless receiver device, the data processing method comprising: Decoding an aggregate packet during a plurality of symbols to obtain original data, the aggregate packet having a plurality of sub-blocks; temporarily storing the original data in a memory unit; and At least one non-idle symbol and at least one idle symbol among the multiple symbols are determined based on a symbol number, a plurality of data bit numbers per symbol respectively corresponding to the plurality of sub-blocks, and a performance characteristic of a processor, and during a period of the at least one non-idle symbol, a processor accesses the memory unit to perform data analysis processing on the original data, but during a period of the at least one idle symbol, the processor enters an idle state without accessing the memory unit.
9. A wireless communication system, comprising: A wireless transmitter device configured to transmit an aggregate packet having a plurality of sub-blocks; and A wireless receiver device configured to receive the aggregated packet via a wireless channel, the wireless receiver device comprising: a decoder for decoding the aggregated packet during a plurality of symbols to obtain an original data; a memory unit for temporarily storing the original data; and A processor is configured to determine at least one non-idle symbol and at least one idle symbol among the multiple symbols based on a symbol number, a plurality of data bit numbers per symbol respectively corresponding to the multiple sub-blocks, and a performance characteristic of the processor, and access the memory unit during a period of the at least one non-idle symbol to perform data analysis processing on the original data, but enter an idle state without accessing the memory unit during a period of the at least one idle symbol.
10. The wireless communication system of claim 9, wherein the aggregate packet is a packet in a very high throughput multi-user physical layer protocol data cell format.