A message processing method and device of a switch chip

Abstract

The application provides a message processing method and device of a switching chip, the method comprising: dividing each module inside the switching chip into multiple partitions, setting an independent time-to-live timer for each partition, and synchronously timing the multiple time-to-live timers in response to a same enable signal; when an ingress port of the switching chip receives a message, recording an entry time of the message by using a time-to-live timer of a partition where the ingress port is located, and when the message enters another partition, obtaining a current timestamp by using a time-to-live timer of the corresponding partition, and determining a message time-to-live according to the current timestamp and the entry time; and if the message time-to-live exceeds a preset threshold, discarding the message as timed out. The technical solution of the application improves the stability, efficiency and data processing accuracy of the switching chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of network transmission, and particularly relates to a message processing method and device of a switching chip. BACKGROUND

[0002] Timestamping of data packets has a wide range of applications in chips. Timestamping in network switching chips is used for traffic monitoring, delay measurement, fault diagnosis, QoS management, intrusion detection, event correlation, and audit tracing, helping to identify abnormal behavior and attack patterns. Network interface controllers also have built-in timestamping to support the Precision Time Protocol or improve the performance monitoring capabilities of applications. In high-performance computing interconnect chips, timestamping is used for time synchronization and packet delay measurement, which is crucial for maintaining efficient data transmission and task scheduling. Special-purpose integrated circuits (ASICs) designed for network monitoring and data analysis use timestamps to accurately record the arrival and departure times of data packets for deep packet inspection, traffic analysis, and compliance checks.

[0003] To implement timestamping in a chip, first, a uniform and unbiased clock source is needed to ensure that the clock information seen by each module in the entire chip is uniform; second, a timing function module is needed in each data processing module to calculate the time information of the packet entering and leaving the module; finally, the timestamp can be calculated by a hardware scheme, the time information is transmitted with the packet, and the actual time of the data packet entering and leaving the chip is calculated by hardware implementation or software method.

[0004] Taking an InfiniBand (IB) network switching chip as an example, the performance of a network switching chip is mainly measured by its transmission bandwidth and transmission delay. Transmission bandwidth refers to the amount of data that a switching chip can process per second, usually expressed in bits per second (bps) or gigabits per second (Gbps). Transmission delay refers to the time it takes for a data packet to enter and leave the switching chip, usually measured in microseconds or nanoseconds. High transmission bandwidth ensures that the switching chip can handle a large amount of data flow, while low transmission delay means that data packets can quickly pass through the switching chip, thereby reducing network latency.

[0005] In network communication, congestion control is used to prevent network overload and maintain network stability. In a switching chip, if some data packets are delayed due to network congestion or too long transmission time within the switching chip, these data packets may be discarded. This mechanism prevents network resources from being occupied by outdated or invalid data packets, thereby ensuring subsequent bandwidth usage. For example, the IB protocol relies on the "Switch life time" mechanism to handle data packets that have been in the switching chip for too long. If the survival time of a data packet in the switching chip exceeds a certain threshold, the data packet will be discarded. SUMMARY

[0006] The present application aims to provide a packet processing method and device of a switch chip, and aims to realize a simple packet time-to-live calculation and timeout discard scheme.

[0007] According to a first aspect of the present application, a packet processing method of a switch chip is provided, comprising:

[0008] dividing each module inside the switch chip into multiple partitions, setting an independent time-to-live timer for each partition, and synchronously timing the multiple time-to-live timers in response to a same enable signal;

[0009] when an ingress port of the switch chip receives a packet, recording an entry time of the packet by using a time-to-live timer of a partition where the ingress port is located, and when the packet enters another partition, obtaining a current timestamp by using a time-to-live timer of the corresponding partition, and determining a packet time-to-live according to the current timestamp and the entry time;

[0010] if the packet time-to-live exceeds a preset threshold, discarding the packet as timeout.

[0011] In an optional implementation, the multiple time-to-live timers are synchronously timed in response to a same enable signal, and the method further comprises:

[0012] sending an enable signal to the multiple time-to-live timers simultaneously by using a 1-bit enable bit inside a chip center module, so as to enable the multiple time-to-live timers simultaneously, and realize global precise synchronous timing.

[0013] In an optional implementation, after the current timestamp is obtained, the method further comprises:

[0014] storing the timestamp information in an unused field or a reserved field of the packet during packet transmission, so as to synchronously transmit the timestamp information with the packet.

[0015] In an optional implementation, the packet is discarded as timeout, and the method further comprises:

[0016] for a packet whose time-to-live exceeds a preset threshold, discarding the packet from both sides of a FIFO buffer simultaneously.

[0017] In an optional implementation, the packet is discarded as timeout, and the method further comprises:

[0018] for a packet whose time-to-live exceeds a preset threshold, first releasing a descriptor corresponding to the packet, removing the descriptor from a linked list, and then releasing a cache space occupied by the packet, and returning the cache space to a free list.

[0019] According to a second aspect of the present application, a packet processing device of a switch chip is provided, comprising:

[0020] a synchronization timing unit, configured to divide each module inside the switch chip into a plurality of partitions, and set an independent time-to-live timer for each partition, and the plurality of time-to-live timers are synchronized in response to a same enable signal;

[0021] a packet tracking unit, configured to, when a packet is received by an ingress port of the switch chip, record an entry time of the packet by using a time-to-live timer of a partition where the ingress port is located, and when the packet enters another partition, acquire a current timestamp by using a time-to-live timer of the corresponding partition, and determine a time-to-live of the packet according to the current timestamp and the entry time;

[0022] a timeout discarding unit, configured to discard the packet when the time-to-live of the packet exceeds a preset threshold.

[0023] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0024] The partition-synchronized Life Timer design reduces the risk of congestion and central wiring of the switch chip, and provides a simple and efficient global synchronization timing mechanism. This design not only optimizes the physical implementation and resource utilization, but also improves the timing accuracy and reliability of the system, and meets the needs of high-performance network switch chips. While achieving simplicity and not requiring each path module to perform cumulative calculation of the time-to-live, the useless VCRC field is transmitted with the timestamp, without additional wiring and hardware overhead. In addition, this scheme can conveniently realize delay statistics of each module and the entire chip, thereby providing strong support for system performance optimization, and significantly improving the design efficiency, performance and maintainability of the switch chip. Through the simple and efficient discarding implementation scheme based on FIFO and linked list structure, the system can efficiently manage and discard packets that cannot be sent for a long time, ensuring effective utilization of Buffer resources. At the same time, the system maintains high performance while reducing implementation cost and complexity, and enhances the stability and efficiency of the switch chip, ensuring smooth transmission of subsequent packets.

[0025] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and attained by the structure and processes particularly pointed out in the description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without any creative effort on the basis of these drawings.

[0027] Figure 1 is a schematic diagram of a timing mechanism of a switching chip according to the related art.

[0028] Figure 2 is a flowchart of a packet processing method of a switching chip according to an exemplary embodiment of the present application.

[0029] Figure 3 is a schematic diagram of a timing mechanism according to an exemplary embodiment of the present application.

[0030] Figure 4 is a schematic diagram of a partition synchronization timing structure according to an exemplary embodiment of the present application.

[0031] Figure 5 is a flowchart of a partition synchronization timing process according to an exemplary embodiment of the present application.

[0032] Figure 6 is a flowchart of a packet time-to-live calculation according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort belong to the scope of protection of the present application.

[0034] As shown in Figure 1 , a data packet enters the switching chip from port-m, and a time stamp is added before the data enters the FIFO processing. The time stamp information will go to the downstream switching scheduling module with the packet. The switching scheduling module also has its own timing module. When the data packet is scheduled to port-n, the latest time stamp will be added. After the data packet enters port-n, before the data packet is sent out from the chip, the total transmission time of the data packet in the chip is obtained according to the time stamp calculation module. This information can be used to solve network congestion or optimize network topology.

[0035] Therefore, the traditional scheme faces significant challenges in implementing the timing of the packet full transmission path's lifetime and the timeout discard in the switch chip. With the increasing changes in the area, transmission bandwidth, and chip frequency of the switch chip, the traditional scheme brings great challenges to the implementation of the chip physical backend for the clock wiring and time stamp information signal wiring of the whole chip. In order to realize the lifetime timing of the packet full transmission path, time accumulation needs to be performed in each switch chip and the module through which the packet passes. This means that the packet needs to record the time it has consumed at each switch node and continue to accumulate when it reaches the next node. This full-path time tracking mechanism is extremely complex because the packet can pass through multiple switch chips and different modules, and each node needs to accurately record and update the time. On the other hand, in order to realize the above full-path timing, a separate timer needs to be maintained for each packet. In a high-performance network, millions of packets can be transmitted in the network at the same time. Allocating a timer for each packet is not feasible in hardware because it will consume a large amount of hardware resources (such as timer registers and logic units) and significantly increase the complexity and cost of the switch chip. In hardware implementation, dynamically allocating and managing timers for each packet is extremely challenging. Hardware logic needs to handle high-speed data streams and needs to complete timer update and accumulation operations in a very short time. This not only increases the complexity of hardware design, but also can cause performance bottlenecks, affecting the overall performance of the switch chip.

[0036] In addition, cut-through switching is a high-performance packet forwarding mode that allows the switch chip to start forwarding immediately after receiving the first few bytes of the packet without waiting for the entire packet to be received. Although this mode can significantly reduce transmission latency, it also brings many difficulties when designing the packet discard mechanism:

[0037] 1) Early forwarding challenge: In cut-through mode, the packet starts to be forwarded before it is completely received. Therefore, if it is found that the packet needs to be discarded (for example, due to congestion or error) before the packet is completely received, the switch chip must take immediate action. However, at this time, the packet may have been partially forwarded to the next node, making the discard operation complex.

[0038] 2) Error detection delay: Since the cut-through mode starts forwarding before the packet is completely received, error detection (such as checksum error, format error, etc.) may be delayed until the second half of the packet is received. In this case, the partially forwarded packet needs to be recovered or notified to the next node to discard, which increases the complexity of the discard mechanism.

[0039] 3) Resource management: In cut-through mode, the switch chip needs to effectively manage its buffer resources. If a packet is determined to be discarded after partial reception, the chip must ensure that the allocated buffer resources can be recovered in time and will not affect other packets being processed. This resource management requires delicate control logic and fast response capabilities.

[0040] 4) Flow control and congestion handling: Cut-through mode requires the switch chip to make forwarding decisions in a very short time and handle flow control and congestion. If congestion occurs in the network, the switch chip needs to respond quickly and discard some packets. However, since the packet may have been partially forwarded, how to effectively perform the discard operation and notify the relevant nodes is a complex problem.

[0041] In summary, whether it is the survival time timing of the entire packet transmission path or the design of the packet discard mechanism in cut-through mode, there are significant technical challenges.

[0042] Based on the above analysis, the present application proposes a packet processing method and device for a switch chip, which implements a Life Timer with partitioned implementation and global synchronous timing, and a survival time calculation based on timestamp and survival timeout packet discard function, systematically solving the difficulties of survival time timing of the entire packet transmission path and the complex design of the packet discard mechanism in cut-through mode, thereby improving the stability, efficiency and accuracy of data processing of the switch chip.

[0043] For the problem of survival time timing of the entire packet transmission path in the switch chip, a Life Timer mechanism with partitioned implementation and global synchronous timing is adopted. In partitioned implementation, the switch chip divides the network into multiple independent regions, and the timers in each region run independently, avoiding the difficulty of hardware implementation of maintaining timers for each packet individually. At the same time, through the global synchronous timing mechanism, the timing between each partition remains consistent, ensuring that the survival time of the packet on the entire transmission path can be accurately calculated. In this way, the system can effectively determine whether the packet has timed out, thereby implementing the discard of the packet timeout. Based on the distance of the physical distribution of the internal modules of the chip, the partitioning scheme can reduce the consumption of internal routing and hardware resources of the chip, and the global synchronous timing ensures that the clock modules of each partition will not produce large errors due to different physical routing and physical implementation locations of the chip.

[0044] In view of the difficulty in designing the packet discarding mechanism in the Cut-through mode, the application provides a survival time calculation based on a timestamp and a survival timeout packet discarding mechanism. When a packet enters a switching chip, the system embeds a timestamp in each packet to record the generation time of the packet. By reading and comparing the timestamps, the survival time of the packet on the transmission path is calculated in real time. When the survival time of the packet exceeds a preset threshold, an automatic discarding mechanism is triggered to discard the timeout packet, thereby ensuring the timeliness of packet processing and the effective use of system resources.

[0045] Referring to Figure 2 the flowchart, the packet processing method of the switching chip provided by the application exemplarily comprises the following steps.

[0046] Step 201: Dividing each module inside the switching chip into multiple partitions, setting an independent survival time timer for each partition, and synchronously timing the multiple survival time timers in response to the same enable signal.

[0047] In order to achieve more accurate timing, the delay of each path must be consistent, which requires complex path adjustment. Such path differences and adjustment requirements increase the complexity of system design and implementation, and restrict the improvement of overall performance and accuracy. As shown in Figure 3 , the application independently sets a Life Timer in each partition. The configuration parameters (such as time accuracy) of each Life Timer can be independently configured, but by placing a 1-bit enable bit in the chip center module, the synchronization timing of each partition at the same time can be ensured, thereby realizing global accurate synchronization timing. Specifically, the chip center module can be the chip top_crg module to reduce the line delay deviation of the global_ctrl control signal sent to each partition.

[0048] Since the Life Timer is independently set in each partition, the problem of length difference of the path from the central timer to each port is eliminated, and complex path adjustment is no longer required, thereby simplifying the system design and improving the timing accuracy and reliability. The Life Timer schematic diagram of partition synchronization timing is as shown in Figure 4 .

[0049] The partition division method mainly depends on the chip back-end implementation. For example, physically adjacent ports as a partition can reduce the wiring and path delay, ensure the synchronization of the time timer of the partition, and reduce the error.

[0050] Exemplarily, the Life Timer configuration process is as shown in Figure 5 . First, configure the Life Timer parameters of each partition, and then enable multiple Life Timers at the same time to start synchronous timing.

[0051] Step 202: When the ingress port of the switch chip receives a packet, record the ingress time of the packet using the time-to-live timer of the partition in which the ingress port is located, and when the packet enters other partitions, obtain the current timestamp using the time-to-live timer of the corresponding partition, and determine the packet time-to-live according to the current timestamp and the ingress time.

[0052] When the packet enters the system, it needs to be time-stamped, denoted as T_stamp_in. Specifically, a variety of marking methods can be used.

[0053] In a preferred embodiment, a signal can be attached to the packet during transmission to carry the timestamp information. This method ensures that the timestamp can be transmitted synchronously with the packet, facilitating the reading and use of the subsequent processing module.

[0054] In yet another preferred embodiment, the timestamp information can be stored in the unused field or reserved field of the packet. The unused field may, for example, be a variable cyclic redundancy check (VCRC) field that is not used when transmitting across the switch chip. This method takes advantage of the redundant space in the packet, does not increase the additional transmission burden, and at the same time ensures that the timestamp information can be transmitted with the packet.

[0055] The calculation method of the packet time-to-live is the difference between the current timestamp and the ingress time:

[0056] switch_life_time = T_stamp_cur - T_stamp_in

[0057] Exemplarily, a packet time-to-live calculation schematic diagram is shown in Figure 6 Based on the timestamp, accurate performance evaluation of each module transmission delay, chip transmission delay, etc. can be completed, and the calculation of the packet time-to-live can be completed, and the mean, maximum, and minimum delay can be calculated.

[0058] Step 203: If the packet time-to-live exceeds a predetermined threshold, the packet is discarded.

[0059] The packet discard implementation can be divided into the following two types:

[0060] 1) For the packet that exceeds the time, it is discarded from both the read / write sides of the FIFO Buffer. This means that the packet will not be read for subsequent processing, and will not occupy the write space. In this way, the Buffer space is returned and reused.

[0061] 2) For the expired packet, first release its corresponding descriptor, remove it from the linked list. Then release the buffer space occupied by the packet, and return it to the idle list. In this way, the memory resources are recycled and reused efficiently.

[0062] The internal data flow mode of the network chip is divided into cut-through and store_forward:

[0063] Cut-through data transmission mode: the internal module of the chip does not need to receive a complete data packet, and can send the data packet to the downstream module, and the data transmission delay in the chip is small;

[0064] Store_forward data transmission mode: it needs to receive a complete data packet before sending the data packet to the downstream;

[0065] In the cut-through mode, the timestamp of the packet is recommended to be placed in the packet header, and when the timeout is detected, the packet can be discarded at the entrance as soon as possible to avoid the complex scenario that part of the data packet has been sent to the downstream module;

[0066] In the store-forward mode, the timestamp of the packet can be placed at any position of the data, and when the timeout is detected, the complete packet is stored in the buffer, and the whole packet can be easily discarded;

[0067] It can be seen that the packet processing method of the switching chip provided by the present application has at least the following advantages compared with the related art: the partition synchronization Life Timer design reduces the risk of congestion and congestion of the switching chip center, and provides a simple and efficient global synchronization timing mechanism. This design not only optimizes the physical implementation and resource utilization, but also improves the timing accuracy and reliability of the system, and meets the needs of high-performance network switching chips. While being simple to implement and not requiring each path module to accumulate and calculate the survival time, the useless VCRC field is transmitted with the timestamp, without additional wiring and hardware overhead. In addition, the scheme can conveniently realize the delay statistics of each module and the whole chip, thereby providing strong support for system performance optimization, and significantly improving the design efficiency, performance and maintainability of the switching chip. Through the simple and efficient discard implementation scheme based on FIFO and linked list structure, the system can efficiently manage and discard the packets that cannot be sent for a long time, ensuring the effective use of Buffer resources. At the same time, the system maintains high performance while reducing implementation cost and complexity, and enhances the stability and efficiency of the switching chip, ensuring smooth transmission of subsequent packets.

[0068] Correspondingly, the present application provides a packet processing device of a switching chip in a second aspect, comprising:

[0069] a synchronization timing unit, configured to divide each module inside the switch chip into multiple partitions, and set an independent time-to-live timer for each partition, and the multiple time-to-live timers are synchronized in response to a same enable signal;

[0070] a packet tracking unit, configured to, when a packet is received by an ingress port of the switch chip, record an entry time of the packet by using a time-to-live timer of a partition where the ingress port is located, and when the packet enters another partition, obtain a current timestamp by using a time-to-live timer of the corresponding partition, and determine a time-to-live of the packet according to the current timestamp and the entry time;

[0071] a timeout discarding unit, configured to discard the packet when the time-to-live of the packet exceeds a preset threshold.

[0072] The apparatus can be implemented by using the packet processing method of the switch chip provided in the embodiments of the first aspect, and the specific implementation manners can refer to the description in the embodiments of the first aspect, which will not be repeated here.

[0073] It can be understood that the structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also combine and adjust the structural features of the above multiple embodiments according to the needs of use, and the concept of the present application should not be limited to the specific details of the above examples.

[0074] Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for processing a packet of a switch chip, characterized in that, include: The internal modules of the switching chip are divided into multiple partitions, and an independent lifetime timer is set for each partition. The multiple lifetime timers respond to the same enable signal and perform synchronous timing. When the ingress port of the switching chip receives a packet, the ingress time of the packet is recorded using the time-to-live timer of the partition where the ingress port is located. When the packet enters another partition, the current timestamp is obtained using the time-to-live timer of the corresponding partition. The packet's lifespan is determined based on the current timestamp and the ingress time. The message lifespan is the difference between the current timestamp and the entry time; After obtaining the current timestamp, the method further includes: storing the timestamp information in an unused field or a reserved field of the message during message transmission, so as to transmit the timestamp information synchronously with the message; If the message's lifespan exceeds a preset threshold, the message will be discarded after the timeout.

2. The packet processing method of a switch chip according to claim 1, characterized in that, The plurality of survival time timers synchronize in response to the same enable signal, further comprising: The chip's central module sends an enable signal to multiple time-to-live timers simultaneously, enabling all time-to-live timers to be enabled at the same time and achieving global precise synchronous timing.

3. The packet processing method of claim 1, wherein, The step of discarding the message after a timeout further includes: For messages whose lifespan exceeds a preset threshold, the message is discarded from both the read and write sides of the FIFO cache simultaneously.

4. The packet processing method of a switch chip according to claim 1, characterized in that, The step of discarding the message after a timeout further includes: For messages whose lifespan exceeds a preset threshold, first release the descriptor corresponding to the message, remove the descriptor from the linked list, then release the cache space occupied by the message, and return the cache space to the free list.

5. A packet processing apparatus of a switch chip, characterized by, include: The synchronization timing unit is used to divide the internal modules of the switching chip into multiple partitions, set an independent lifetime timer for each partition, and the multiple lifetime timers respond to the same enable signal to perform synchronous timing. The message tracking unit is used to record the entry time of the message using the lifetime timer of the partition where the entry port is located when the ingress port of the switching chip receives the message, and to obtain the current timestamp using the lifetime timer of the corresponding partition when the message enters other partitions, and to determine the message lifetime based on the current timestamp and the entry time. The message lifespan is the difference between the current timestamp and the entry time; After obtaining the current timestamp, the timestamp information is stored in an unused field or a reserved field of the message during message transmission, so as to transmit the timestamp information synchronously with the message; The timeout discard unit is used to discard the message when the message lifespan exceeds a preset threshold.

6. The message processing apparatus for the switching chip according to claim 5, characterized in that, The synchronization timing unit is further used for: The chip's central module sends an enable signal to multiple time-to-live timers simultaneously, enabling all time-to-live timers to be enabled at the same time and achieving global precise synchronous timing.

7. The message processing apparatus for the switching chip according to claim 5, characterized in that, The timeout discard unit is further used for: For messages whose lifespan exceeds a preset threshold, the message is discarded from both the read and write sides of the FIFO cache simultaneously.

8. The message processing apparatus for the switching chip according to claim 5, characterized in that, The timeout discard unit is further used for: For messages whose lifespan exceeds a preset threshold, first release the descriptor corresponding to the message, remove the descriptor from the linked list, then release the cache space occupied by the message, and return the cache space to the free list.

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