Dynamic reconfigurable wireless communication receiving end synchronization method
Through the dynamic reconfigurable digital FIR filter and pulsating array design, the problems of FIR filter calculation delay and resource consumption in wireless communication receiving end synchronization are solved, low resource consumption and fast synchronization are achieved, and multiple communication protocols are adapted to.
Patent Information
- Application Number
- CN202411234496.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2024-12-27
AI Technical Summary
The existing wireless communication end-sync technology cannot process FIR filtering calculations online in real time, resource consumption and delay cannot meet engineering needs, and it is difficult to adapt to multiple communication protocols.
Design a dynamic reconfigurable digital FIR filter, adopts a complex FIR filter based on a pulsating array, calculates the PSS sequence mutual correlation coefficient and energy of the signal through FIR low-pass filtering and downsampling processing, and marks the signal position using the timing marking module, dynamically Configure filter frequency response and synchronization sequence.
It reduces the resource consumption of downlink synchronization algorithms, reduces computing delay, supports multiple communication standards, adapts to future communication protocols, and achieves low resource consumption and fast synchronization.
Smart Images
Figure CN119212069A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a technology in the field of wireless communication, in particular to a dynamically reconfigurable wireless communication receiving end synchronization method. Background Art
[0002] With the continuous evolution of mobile communication technology, the complexity of mobile communication systems continues to increase, and the cost of implementation also rises accordingly. Orthogonal frequency division multiplexing (OFDM) technology plays a vital role in modern mobile communication systems. This technology uses orthogonal phases to effectively avoid mutual interference between carriers. In order to maintain the orthogonality of the carriers between the signal transmitter and the receiver, the received signal must be synchronized in time and frequency. Receiving devices that support multiple communication protocols need to design various synchronization solutions for different receiving ends in the communication system, which undoubtedly leads to huge resource consumption. In addition, communication devices that adopt such solutions are often difficult to adapt to future communication protocols. Summary of the invention
[0003] In view of the fact that the prior art cannot process the FIR filtering calculation of the received signal online in real time in the wireless communication receiving end synchronization scenario, and the resource consumption and delay cannot meet the needs of the existing engineering, the present invention proposes a dynamically reconfigurable wireless communication receiving end synchronization method, designs a dynamically reconfigurable digital FIR filter using a systolic array, and applies it to the receiving end synchronization of the wireless communication system. It is compatible with multiple communication standards while greatly reducing the resource consumption of implementing the downlink synchronization algorithm.
[0004] The present invention is achieved through the following technical solutions:
[0005] The present invention relates to a dynamically reconfigurable wireless communication receiving end synchronization method. After performing FIR low-pass filtering and down-sampling processing on a received signal, the PSS sequence mutual correlation coefficient of the signal, the signal energy and the distance between the signal and the synchronization sequence are calculated, and then the relative position of the PSS sequence with a distance exceeding a threshold is marked as timing information in the input signal.
[0006] The FIR low-pass filtering is implemented by using a complex FIR filter based on a systolic array and a Winogard algorithm.
[0007] The complex FIR filter controls the filter coefficients, order and power consumption through a data bus.
[0008] The present invention relates to a system for implementing the above method, comprising: a preprocessing module, a PSS detection module and a timing marking module, wherein: the preprocessing module performs low-pass filtering and downsampling processing on a received signal and then outputs it to the PSS detection module; the PSS detection module determines the position of the PSS sequence in the received signal based on the cosine distance between the downsampled received signal and the PSS sequence; the timing marking module marks the position of the next PSS in the received signal according to the position where the peak value appears and the calculated delay of the PSS detection module.
[0009] The PSS detection module includes: three groups of complex FIR filters, one group of real FIR filters and a peak detector, wherein: the three groups of complex FIR filters calculate the cross-correlation between the downsampled received signal and three PSS sequences in parallel, and one group of real FIR filters is used to calculate the energy of the downsampled received signal; the peak detector calculates the cosine distance according to the cross-correlation and the signal energy, and determines whether the cosine distance may be the peak of the cosine distance according to the relationship between the cosine distance and the threshold. Technical Effects
[0010] The present invention designs a dynamically reconfigurable FIR filter so that the low-pass filter and cross-correlation modules in the receiving end synchronization scheme can be dynamically configured; the timing mark module does not need to store the received signal after low-pass filtering in RAM and then read it out, thereby compensating for the calculation delay of the PSS synchronization detection module. Instead, the periodic characteristics of the PSS signal are used to mark the position where the next PSS appears in the received signal. Compared with the prior art, the present invention can dynamically adjust the frequency response of the low-pass filter; can dynamically adjust the synchronization sequence, support the cross-correlation calculation of multiple synchronization sequences, and thus support multiple synchronization signal detection; reduce the overall delay of downlink synchronization detection, and reduce the resource consumption of the timing module. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a flow chart of the present invention;
[0012] Figure 2 It is a schematic diagram of FIR low-pass filtering;
[0013] In the figure: (a) FIR filter based on systolic array; (b) PE of systolic array; (c) final PE;
[0014] Figure 3 This is a schematic diagram of the implementation architecture of the complex FIR filter;
[0015] Figure 4 This is a schematic diagram of the cosine distance MATLAB simulation results of the synchronization sequence;
[0016] Figure 5 Schematic diagram showing the misalignment between the synchronization peak and the synchronization sequence caused by the computational delay introduced into the synchronization algorithm; Figure 6 It is a schematic diagram of the effect of the embodiment. DETAILED DESCRIPTION
[0017] like Figure 1 As shown, this embodiment involves a dynamically reconfigurable wireless communication receiving end synchronization method, which first performs FIR low-pass filtering and downsampling processing on the received signal, calculates the PSS sequence correlation coefficient of the signal, the signal energy and its distance from the synchronization sequence, and then marks the relative position of the PSS sequence whose distance exceeds the threshold in the input signal as timing information.
[0018] The FIR low-pass filtering is performed as follows. Figure 2 (a) shows a systolic array implementation, which includes: a data bus unit, such as Figure 2 (b) The processing unit PE shown in FIG. Figure 2 (c) shows the final processing unit PEn, wherein: in the initialization stage, the FIR filter tap coefficients are written into the corresponding processing unit and the final processing unit through the data bus. After initialization, if the frequency response of the FIR filter needs to be adjusted, the new FIR filter tap coefficients can be re-written into the corresponding processing unit and the final processing unit through the data bus.
[0019] like Figure 2 As shown in (b), the processing unit PE includes: a multiplier, an adder, a plurality of delay units and a storage unit, wherein: in each clock cycle, the input data in the delay unit is multiplied by the corresponding filter tap coefficient according to the time sequence of the signal input, and the product is added to the product of the previous stage and output to the next stage PE.
[0020] like Figure 2 As shown in (c), the final processing unit PEn includes: a multiplier, an adder, an accumulator, a plurality of delay units and a storage unit, wherein: in each clock cycle, the input data in the delay unit is multiplied by the corresponding filter tap coefficient according to the time sequence of the signal input, the product is added to the previous stage product and then output to the accumulator, the accumulator adds the stored accumulated value to the input multi-stage PE product sum to obtain the FIR filtering result and periodically outputs the FIR filtering result.
[0021] The periodicity mentioned is: Figure 2 The value of clkrate in (a) is shown in the cycle.
[0022] The output described above, the accumulator clears the accumulated result after outputting the FIR filtering result.
[0023] like Figure 3As shown, the complex FIR filter adds the real part sequence of the received signal to the imaginary part sequence and performs FIR filtering with the real part of the PSS sequence to obtain the first filtered signal FIR0. The real part sequence of the received signal is subtracted from the imaginary part sequence and the imaginary part of the PSS sequence to obtain the second filtered signal FIR1. The real part of the received signal and the sum of the real part and the imaginary part of the PSS sequence are FIR filtered to obtain the third filtered signal FIR2; then the first filtered signal FIR0 is subtracted from the third filtered signal FIR2, i.e. the imaginary part of the complex FIR calculation, and the second filtered signal FIR1 is subtracted from the third filtered signal FIR2, i.e. the real part of the complex FIR calculation.
[0024] The distance, i.e., the relative position of the synchronization sequence in the input signal is determined by the cosine distance, is specifically: Where: x is the input signal, y is the synchronization sequence, y * is the conjugate of y, ε is the cosine distance, is the energy of the synchronization sequence, is a fixed value, and N is the length of the synchronization sequence.
[0025] The distance exceeding the threshold value means: when the cosine distance ε is greater than the set threshold ε th , then the position of the cosine distance peak is considered to be the relative position of the synchronization sequence in the input signal, that is, the synchronization peak, specifically: in: Calculate on the software side and write to the corresponding register through the data bus. , it is again implemented using a complex FIR filter based on a systolic array.
[0026] like Figure 4 The figure shows the Matlab simulation result of the distance exceeding threshold judgment. The horizontal axis is the sampling time, the vertical axis is the cosine distance, and the simulation test signal is the base station signal sampled by the ADC. The cosine distance of the synchronization sequence is significantly larger than the cosine distance of other signals.
[0027] The marking timing information, i.e. the frame header of the marking input signal, is specifically: T1+T2 position, where: T1 is the delay of the PSS detection module, and T2 is the delay between the start position of the synchronization sequence and the frame header after baseband processing. T1 is determined by simulation, and after the circuit is implemented, T1 remains unchanged. T2 is obtained by baseband demodulation from the received signal.
[0028] After specific practical experiments, the SoC scheduling receiving end synchronization module has been implemented in the FPGA environment in the dedicated processor deployed in the communication field, which can realize the communication between 5G base stations and FPGA. Figure 6The FPGA measurement results show that the three signals from top to bottom are the fixed-point cosine distances of PSS0, PSS1, and PSS2. The maximum value of the fixed-point cosine distance is 16383, which means the cosine distance is 1. Depend on Figure 6 It can be seen that only PSS0 appears in the received signal, and the cosine distance peak is 0.98.
[0029] Compared with the prior art, the present invention uses the structure of the FIR IP core and the simple associative law of multiplication to complete the related calculation of complex numbers, realizes the effect of pipeline operation, avoids the complex timing structure, and can run at 245.76MHz and higher frequencies. The FIR filter is designed using a systolic array, and the filter coefficients and orders can be dynamically configured after the hardware circuit is implemented, so that the design is suitable for a variety of wireless communication scenarios. The Winogard algorithm is used to reduce the computing resource overhead. When the filter order is less than the maximum configurable order, the system clock frequency can be reduced to reduce power consumption. The present invention determines the relative position of the synchronization sequence according to the peak value of the cosine distance. When the cosine distance is greater than the threshold configured from the bus, it will be judged as a peak value, eliminating the RAM memory overhead required for traversing the cosine distance. The present invention uses a timing module based on the periodicity of the cross-correlation sequence, so that the delay of calculating the synchronization peak is not included in the entire receiving end synchronization design.
[0030] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.
Claims
1. A dynamically reconfigurable wireless communication receiving end synchronization method, characterized in that: After the received signal is subjected to FIR low-pass filtering and downsampling, the PSS sequence cross-correlation coefficient, signal energy and distance to the synchronization sequence of the signal are calculated, and then the relative position of the PSS sequence with a distance exceeding the threshold is marked as timing information in the input signal; The FIR low-pass filtering is implemented by using a complex FIR filter based on a systolic array and a Winogard algorithm.
2. The dynamically reconfigurable wireless communication receiving end synchronization method according to claim 1, characterized in that: The FIR low-pass filtering is implemented by a systolic array, which includes: a data bus unit, a processing unit PE and a final processing unit PEn, wherein: in the initialization stage, the FIR filter tap coefficients are written into the corresponding processing unit and the final processing unit through the data bus, and after initialization, if the frequency response of the FIR filter needs to be adjusted, the new FIR filter tap coefficients can be re-written into the corresponding processing unit and the final processing unit through the data bus.
3. The dynamically reconfigurable wireless communication receiving end synchronization method according to claim 2, characterized in that: The processing unit PE includes: a multiplier, an adder, a plurality of delay units and a storage unit, wherein: in each clock cycle, the input data in the delay unit is multiplied by the corresponding filter tap coefficient according to the time sequence of the signal input, and the product is added to the previous stage product and then output to the next stage PE; The final processing unit PEn comprises: a multiplier, an adder, an accumulator, a plurality of delay units and a storage unit, wherein: in each clock cycle, the input data in the delay unit is multiplied by the corresponding filter tap coefficient according to the time sequence of the signal input, the product is added to the previous stage product and then output to the accumulator, the accumulator adds the stored accumulated value to the input multi-stage PE product sum to obtain the FIR filtering result and periodically outputs the FIR filtering result.
4. The dynamically reconfigurable wireless communication receiving end synchronization method according to claim 1, characterized in that: The complex FIR filter adds the real part sequence of the received signal to the imaginary part sequence and performs FIR filtering with the real part of the PSS sequence to obtain the first filtered signal FIR0; subtracts the imaginary part sequence from the real part sequence of the received signal and performs FIR filtering with the imaginary part of the PSS sequence to obtain the second filtered signal FIR1; performs FIR filtering on the real part of the received signal and the sum of the real part and the imaginary part of the PSS sequence to obtain the third filtered signal FIR2; then subtracts the third filtered signal FIR2, i.e. the imaginary part calculated by the complex FIR, from the first filtered signal FIR0, and subtracts the third filtered signal FIR2, i.e. the real part calculated by the complex FIR, from the second filtered signal FIR1.
5. The dynamically reconfigurable wireless communication receiving end synchronization method according to claim 1, characterized in that: The distance, i.e., the relative position of the synchronization sequence in the input signal is determined by the cosine distance, is specifically: Where: x is the input signal, y is the synchronization sequence, y * is the conjugate of y, ε is the cosine distance, is the energy of the synchronization sequence, which is a fixed value, and N is the length of the synchronization sequence; The distance exceeding the threshold value means: when the cosine distance ε is greater than the set threshold ε th , then the position of the cosine distance peak is considered to be the relative position of the synchronization sequence in the input signal, that is, the synchronization peak, specifically: in: Calculate on the software side and write to the corresponding register through the data bus. , it is again implemented using a complex FIR filter based on a systolic array.
6. The dynamically reconfigurable wireless communication receiving end synchronization method according to claim 1, characterized in that: The marking timing information, i.e. marking the frame header of the input signal, is specifically: T1+T2 position, wherein: T1 is the delay of the PSS detection module, T2 is the delay between the starting position of the synchronization sequence and the frame header obtained after baseband processing, wherein T1 is determined by simulation, after the circuit is implemented, T1 remains unchanged, and T2 is obtained by baseband demodulation from the received signal.
7. A dynamically reconfigurable wireless communication receiving end synchronization system implementing the method described in any one of claims 1 to 6, characterized in that: include: A preprocessing module, a PSS detection module and a timing marking module, wherein: the preprocessing module performs low-pass filtering and downsampling on the received signal and then outputs it to the PSS detection module, and the PSS detection module determines the position of the PSS sequence in the received signal based on the cosine distance between the downsampled received signal and the PSS sequence; The timing marking module marks the position of the next PSS in the received signal according to the position where the peak value appears and the calculated delay of the PSS detection module.
8. The wireless communication receiving end synchronization system according to claim 7, characterized in that: The PSS detection module includes: three groups of complex FIR filters, one group of real FIR filters and a peak detector, wherein: the three groups of complex FIR filters calculate the cross-correlation between the downsampled received signal and three PSS sequences in parallel, and one group of real FIR filters is used to calculate the energy of the downsampled received signal; the peak detector calculates the cosine distance according to the cross-correlation and the signal energy, and determines whether the cosine distance may be the peak of the cosine distance according to the relationship between the cosine distance and the threshold.