Displayer based on silicon-based tiled display drive and manufacturing method and driving method thereof

Abstract

The invention discloses a display based on a silicon-based tiled display drive and a manufacturing method and a driving method thereof, the display based on the silicon-based tiled display drive comprises a top chip and a bottom chip which are arranged in a laminated manner, and the top chip and the bottom chip are interconnected through metal; the top chip comprises an array formed by a plurality of top subunits, and each top subunit comprises a pixel array; the bottom chip comprises an array formed by a plurality of bottom subunits, each bottom subunit at least comprises one driving unit, and the bottom subunit array partitions display data according to a corresponding pixel array; the top subunits and the bottom subunits are interconnected in a one-to-one correspondence manner, and the bottom subunits are used for controlling the display of the pixel arrays in the correspondingly interconnected top subunits. According to the display based on the silicon-based tiled display drive, degradation interference noise caused by line-by-line scanning is reduced, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of silicon-based OLED displays, and in particular to a display based on silicon-based splicing display drive and a manufacturing method and a driving method thereof. Background Art

[0002] Microdisplay technology has been widely used in near-eye display terminal products, including Micro OLED, Micro LED, high-resolution LCD, liquid crystal on silicon (LCOS) and digital light processing (DLP). Microdisplay chips generally include pixel circuits and peripheral drive circuits. Pixel circuits are repeated pixel circuit arrays used to drive optical structures and display images; peripheral drive circuits include row drive circuits, column drive circuits, storage circuits (SRAM), logic operation circuits (logic), analog-to-digital / digital-to-analog conversion modules (ADC / DAC), control IO circuits, power management modules, etc., which are used to process and analyze input video signals and output them to pixel circuits so that the pixel circuits display images. The existing display drive methods range from interlaceddriving in the CRT era to progressive driving in the LCD era, with refresh rates ranging from 30 frames, 60 frames, 90 frames, 120 frames, 144 frames to 240 frames. From the LCD era to the AMOLED era, all display products use progressive scanning. This design balances image quality and cost and ensures mass production, but the image quality is not ideal.

[0003] Thanks to the silicon-based backplane technology, Stack type CIS has taken the lead in realizing the mass production of driving technology that simultaneously senses and acquires images frame by frame. However, the current silicon-based OLED displays on the market still use the line-by-line scanning drive handed down from the LCD / AMOLED era, which cannot achieve the mass production process of full-pixel direct drive for the theoretically best display effect.

[0004] Therefore, a new display based on silicon-based splicing display drive and a manufacturing method and a driving method thereof are needed. Summary of the invention

[0005] In order to solve the above-mentioned product performance problem, the present invention provides a display based on silicon-based splicing display drive and a manufacturing method and a driving method thereof.

[0006] The present invention provides a display based on silicon-based splicing display drive, comprising: a top chip and a bottom chip in a stacked structure, the top chip and the bottom chip are interconnected by metal; the top chip comprises an array formed by a plurality of top sub-units, each of which comprises a pixel array; the bottom chip comprises an array formed by a plurality of bottom sub-units, each of which comprises at least one driving unit, and the bottom sub-unit array partitions display data according to its corresponding pixel array; the top sub-units and the bottom sub-units are interconnected one by one, and the bottom sub-units are used to control the display of the pixel array in the corresponding interconnected top sub-units.

[0007] In some embodiments, the top chip and the bottom chip are conductively interconnected via copper interconnect plugs.

[0008] In some embodiments, the top chip and / or the bottom chip is a silicon-based chip.

[0009] In some embodiments, the bottom silicon-based chip also includes bottom logic circuits and flexible circuit board leads.

[0010] In some embodiments, the top sub-unit further includes a top scanning circuit and a top interconnection region interconnected with the pixel array, and the top scanning circuit controls the gating of the pixel array in the top sub-unit where it is located.

[0011] In some embodiments, the bottom sub-unit further includes a bottom scanning circuit and a bottom interconnection region, the bottom sub-unit includes a driving unit array, and the bottom scanning circuit controls the gating of the driving unit array in the bottom sub-unit where the bottom scanning circuit is located.

[0012] In some embodiments, a top interconnection region of a top subunit and a bottom interconnection region of a bottom subunit are conductively interconnected via a copper interconnection plug.

[0013] In some embodiments, a driving unit in a bottom sub-unit controls the display of a pixel array in its corresponding top sub-unit.

[0014] In some embodiments, the top chip has tungsten vias on a side facing away from the bottom chip.

[0015] The present invention also provides a method for manufacturing a display based on silicon-based splicing display drive, comprising: providing a bottom chip, each bottom chip comprising a bottom sub-unit array composed of a plurality of bottom sub-units, at least one driving unit being formed in each bottom sub-unit, and the bottom sub-unit array partitioning display data according to its corresponding pixel array; providing a top chip, each top chip comprising a top sub-unit array composed of a plurality of top sub-units, and a pixel array being formed in each top sub-unit; interconnecting the top sub-units of the top chip and the bottom sub-units of the bottom chip one by one, and the bottom sub-units are used to control the display of the pixel array in the corresponding interconnected top sub-units.

[0016] In some embodiments, the top chip and the bottom chip are conductively interconnected via copper interconnect plugs.

[0017] In some embodiments, the material of the top chip and / or the bottom chip is silicon.

[0018] In some embodiments, the manufacturing method further includes: forming a bottom logic circuit and a flexible circuit board lead on each bottom chip.

[0019] In some embodiments, the manufacturing method further includes: forming a top scanning circuit and a top interconnection area interconnected with the pixel array on each top sub-unit, wherein the top scanning circuit controls the gating of the pixel array in the top sub-unit where the top scanning circuit is located.

[0020] In some embodiments, the manufacturing method further comprises: forming a bottom scanning circuit and a bottom interconnection region on each bottom sub-unit, wherein the bottom sub-unit comprises a driving unit array, and the bottom scanning circuit controls the gating of the driving unit array in the bottom sub-unit where the bottom scanning circuit is located.

[0021] In some embodiments, the conductive interconnection between the top chip and the bottom chip through the copper interconnection plug includes: conductively interconnecting a top interconnection region of a top subunit and a bottom interconnection region of a bottom subunit one by one through a copper interconnection plug.

[0022] In some embodiments, a driving unit in a bottom sub-unit controls the display of a pixel array in its corresponding top sub-unit.

[0023] In some embodiments, the manufacturing method further includes: forming a tungsten via on a surface of the top chip facing away from the bottom chip.

[0024] The present invention also provides a driving method for a display based on silicon-based splicing display drive, comprising: the bottom sub-unit divides the image data according to the top sub-unit; controlling the gating of the pixel array in the top sub-unit by controlling the top scanning circuit; controlling the gating in the bottom chip and the top chip to realize the image display of the corresponding bottom sub-unit and the top sub-unit.

[0025] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following beneficial effects:

[0026] The embodiment of the present disclosure provides a display based on silicon-based splicing display drive, which realizes the simultaneous display of partitions in the entire display panel instead of line-by-line scanning by dividing the pixel unit into multiple sub-units on the top chip and setting the drive unit into multiple sub-units on the bottom chip. At the same time, the silicon-based stacking packaging process is adopted, and the corresponding drive module is integrated on the bottom surface of the original display pixel array to realize the architecture of splicing display drive in a single screen body, changing the original single screen display line-by-line scanning into multiple sub-screen display integrated splicing drive, thereby reducing the degradation interference noise of line-by-line scanning and improving the display effect.

[0027] Furthermore, a manufacturing method of a display based on a silicon-based splicing display driver provided in an embodiment of the present disclosure divides the pixel units into different sub-units, so that in the entire display panel, the partitions start displaying at the same time, rather than scanning line by line, thereby improving the refresh rate; the pixels and the driver are divided into different chip settings, and the corresponding driver module is integrated on the bottom surface of the original display pixel array, thereby realizing the architecture of splicing display driver in a single screen body, greatly reducing the driving load. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of the structure of a display based on silicon-based splicing display drive according to an embodiment of the present disclosure;

[0030] Figure 2 A schematic diagram of a functional module of a top chip subunit of a display based on silicon-based splicing display drive according to an embodiment of the present disclosure;

[0031] Figure 3 A schematic diagram of a functional module of a top subunit of a display based on silicon-based splicing display drive according to an embodiment of the present disclosure;

[0032] Figure 4 It is a functional module schematic diagram of a bottom chip of a display based on silicon-based splicing display drive according to an embodiment of the present disclosure;

[0033] Figure 5 It is a functional module schematic diagram of a bottom subunit of a display based on silicon-based splicing display drive according to an embodiment of the present disclosure;

[0034] Figure 6A digital data driven block diagram formed by interconnecting a top subunit and a bottom subunit in an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of a process of manufacturing a display based on silicon-based splicing display drive according to an embodiment of the present disclosure;

[0036] Figure 8 This is a timing diagram of a driving method of a display based on silicon-based splicing display driving according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0038] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In the present invention, it is an electrical device, so connection and interconnection both refer to conductive interconnection. Since the accompanying drawings are descriptions of the same device, the same numbers in the drawings represent the same components.

[0039] The embodiment of the present disclosure provides a display based on silicon-based splicing display drive, including: a top chip and a bottom chip in a stacked structure, the top chip and the bottom chip are interconnected by metal; the top chip includes an array formed by a plurality of top sub-units, each top sub-unit includes a pixel array; the bottom chip includes an array formed by a plurality of bottom sub-units, each bottom sub-unit includes at least one driving unit, and the bottom sub-unit array partitions display data according to its corresponding pixel array; the top sub-units and the bottom sub-units are interconnected one-to-one, and the bottom sub-units are used to control the display of the pixel array in the corresponding interconnected top sub-units.

[0040] The specific examples of the present invention are further described in detail below with reference to the accompanying drawings.

[0041] In the embodiment of the present disclosure, the top chip and the bottom chip are both silicon-based chips. Figure 1The display 10 based on silicon-based splicing display driver includes a top silicon-based chip 20 and a bottom silicon-based chip 30, and the top silicon-based chip 20 and the bottom silicon-based chip 30 are electrically connected to each other through a copper interconnect plug. In addition, other metals can also be used to connect through chip-to-chip plug interconnection, which is not limited in the present disclosure.

[0042] In the embodiment of the present disclosure, Figure 2 and Figure 3 The top silicon-based chip 20 includes a top sub-unit array composed of a plurality of top sub-units 210, each of which includes a pixel array 220, a top scanning circuit 230 interconnected with the pixel array 220, and a top interconnection area 240. The top scanning circuit 230 is used to control the gating of the pixel array 220 in the top sub-unit 210 where it is located.

[0043] In conventional backplanes, a row-by-row scanning method is usually adopted to control the display of pixel units row by row. In the present invention, the pixels of the top silicon-based chip 20 are divided into multiple regions, namely multiple top sub-units 210, and each top sub-unit 210 includes a pixel array 220, so that the operation of the top sub-unit 210 is controlled by a top scanning circuit 230 arranged on one side of the pixel display region inside the top sub-unit. Specifically, by controlling the selection of the pixel array 220, for example, different top sub-units 210 are started to work at the same time, that is, the pixel arrays 220 in different sub-units 210 are started to display at the same time. Specifically, the pixel array in each top sub-unit 210 can adopt a row scanning method, so that the partitions in the entire display panel start to display at the same time, instead of row-by-row scanning. Taking the top sub-units divided into 4 as an example, the row scanning time can be increased by 4 times because the partition resolution is reduced by 1 / 4, and the amount of electrical coupling interference noise caused by row-by-row scanning can be reduced in the same proportion.

[0044] In this embodiment, reference Figure 3 A top interconnection region 240 is also provided at the edge of the pixel display region within the top sub-unit 210, so that each top sub-unit 210 in the top silicon-based chip 20 and the driving circuit in the bottom silicon-based chip 30 can be directly interconnected by means of interconnection metal plugs or interconnection metals provided in this region.

[0045] In the embodiment of the present disclosure, Figure 4 and Figure 5The bottom silicon-based chip 30 includes a bottom subunit array composed of a plurality of bottom subunits 310, and the bottom subunit array is used to partition the display data according to the corresponding pixel array. Each bottom subunit 310 includes a driving unit array 320 composed of a plurality of driving units, a bottom scanning circuit 330 and a bottom interconnection area 340. Among them, the bottom scanning circuit 330 controls the gating of the driving unit array 320 in the bottom subunit where it is located. The top subunit and the bottom subunit are interconnected one by one, and the bottom subunit is used to control the display of the pixel array in the corresponding interconnected top subunit. Specifically, in the embodiment of the present disclosure, the top interconnection area 240 of a top subunit 210 and the bottom interconnection area 340 of a bottom subunit 310 are conductively interconnected through a copper interconnection plug.

[0046] In a conventional display backplane, the driver is usually set on one side of the pixel display area to drive the pixel for display. In the present invention, the pixel and the driver are divided into different chip settings, wherein the pixel unit is set on the top silicon-based chip 20, and the driver unit is set on the bottom silicon-based chip 30. In the present invention, the driver unit is divided into zones, and an independent driver unit array 320 is set in each bottom sub-unit 310, wherein the bottom sub-unit corresponds to the top sub-unit, and the driver unit array 320 in the bottom sub-unit provides display drive to the pixel array 220 in the corresponding top sub-unit. Further, each bottom sub-unit 310 controls the driver unit array 320 through a bottom scanning circuit 330 set on one side thereof, for example, strobes the driver unit in the driver unit array. Further, each bottom sub-unit is set on one side thereof through a bottom interconnection area 340, thereby realizing direct interconnection between each top sub-unit 210 unit in the top silicon-based chip 20 and the driver circuit in the bottom silicon-based chip 30 through an interconnection metal plug or interconnection metal set in this area. In the embodiment of the present disclosure, the driving unit array 320 within each bottom sub-unit 310 controls the display of the pixel array 220 within its corresponding top sub-unit 210. By integrating the corresponding driving module on the bottom surface of the original display pixel array, an architecture of splicing display drivers in a single screen is realized.

[0047] In the embodiment of the present disclosure, the driving unit array 320 in each bottom subunit 310 controls the display of the pixel array 220 in its corresponding top subunit 210, referring to Figure 6In the interconnected structure of a top sub-unit and a bottom sub-unit, the driving unit in the bottom sub-unit 310 includes: a memory (8-bit SRAM), a clock counter (ClockCount), a pulse width modulation module (PWM), etc. During operation, the image data Vdata is input into the memory, and the memory receives and stores Vdata for subsequent processing; the clock counter module controls the data reading and processing timing according to the clock signal; the pulse signal is generated through the information of the counter and then through pulse width modulation to control the brightness of each sub-unit. Afterwards, the signal after pulse width modulation is transmitted to the pixel in the top sub-unit 210 through the sub-unit interface (Sub cell I / F), driving the light-emitting element to display the corresponding color and brightness.

[0048] Furthermore, in the present embodiment, the bottom silicon-based chip 30 is also provided with a bottom logic circuit 350, through which the driving data of the pixel display is distributed to the driving array 320 according to the positional relationship between the driving array and the pixel array, so that the display driving data of the entire pixel area can be transmitted in parallel to the driving array 320, and then transmitted in parallel to each top sub-unit 210 in the top silicon-based chip 20, so as to solve the problem of overall coordinated image display from driving data to controlling pixel switches. Since the driving data is also partitioned, the refresh frequency can be improved as a whole.

[0049] Furthermore, in the present embodiment, the bottom silicon-based chip 30 is also provided with a flexible circuit board lead 360. Since the top silicon-based chip 20 is connected to the bottom silicon-based chip 30 through metal, the bottom silicon-based chip is conductively interconnected with other chips or structures of the display device through the provided flexible circuit board lead 360. Since the bottom silicon-based chip 30 and the top silicon-based chip 20 are separated, the interconnection area does not occupy the pixel display area, thereby further increasing and improving the display area and display efficiency.

[0050] In some embodiments, the flexible circuit board lead may be composed of a flexible substrate and a conductive copper foil. The flexible substrate may be a polyester film or a polyimide film.

[0051] In the disclosed embodiment, the top silicon chip has a tungsten via 201 on the side facing away from the bottom silicon chip. In some embodiments, signals, power supplies or ground lines between different layers of the circuit board can be effectively connected through the tungsten vias to achieve normal operation of the circuit.

[0052] The embodiment of the present disclosure provides a display based on silicon-based splicing display drive, which realizes the simultaneous display of partitions in the entire display panel instead of line-by-line scanning by dividing the pixel unit into multiple sub-units in the top chip and setting the drive unit into multiple sub-units on the bottom chip. At the same time, the silicon-based stacking packaging process is adopted, and the corresponding drive module is integrated on the bottom surface of the original display pixel array to realize the architecture of splicing display drive in a single screen body, changing the original single screen display line-by-line scanning into multiple sub-screen display integrated splicing drive, thereby reducing the degradation interference noise of line-by-line scanning and improving the display effect.

[0053] The present disclosure also provides a method for manufacturing a display based on silicon-based splicing display drive. Figure 7 The manufacturing method of the present invention is shown in the flowchart of the embodiment of the present invention. Figure 1-7 The manufacturing method of the display based on silicon-based splicing display driver comprises the following steps:

[0054] S1: Provide a bottom chip, each bottom chip includes a bottom sub-unit array composed of a plurality of bottom sub-units, at least one driving unit is formed in each bottom sub-unit, and the bottom sub-unit array partitions display data according to its corresponding pixel array.

[0055] S3: providing a top chip, each top chip comprising a top sub-unit array composed of a plurality of top sub-units, and a pixel array is formed in each top sub-unit.

[0056] In the embodiment of the present disclosure, the top chip and the bottom chip are silicon-based chips.

[0057] In the embodiment of the present disclosure, the structural schematic diagram of each top chip is as follows: Figure 2 , refer to Figure 2 and Figure 3 Each top chip 20 includes a top sub-unit array composed of a plurality of top sub-units 210 , and a pixel array 220 is formed in each top sub-unit 210 .

[0058] Specifically, forming the top chip 20 further includes forming a top scanning circuit 230 and a top interconnection area 240 interconnected with the pixel array 220 in each top subunit 210, thereby obtaining the top chip 20. The top scanning circuit 230 controls the gating of the pixel array 220 in the top subunit 210 where it is located.

[0059] By dividing the pixels of the top silicon-based chip 20 into a plurality of pixel arrays 220 disposed in a plurality of top sub-units 210, the top scanning circuit 230 disposed on one side of the pixel display area inside the top sub-unit is used to control the operation of the top sub-unit 210. Specifically, by controlling the selection of the pixel array 220, the pixel arrays 220 in different top sub-units 210 can be made to start displaying at the same time. In this way, it is achieved that the partitions in the entire display panel start displaying at the same time, rather than scanning line by line. Taking the top sub-units 210 divided into 4 as an example, the refresh frequency is increased to 4 times the original.

[0060] In the embodiment of the present disclosure, the structural schematic diagram of each bottom chip is as follows: Figure 4 , refer to Figure 4 and Figure 5 A bottom sub-unit array consisting of a plurality of bottom sub-units 310 is formed on the bottom chip 30, and the bottom sub-unit array is used to partition the display data according to its corresponding pixel array. A driving unit array 320 is formed in each bottom sub-unit 310, and the driving unit array 320 includes at least one driving unit.

[0061] Specifically, forming the bottom chip 30 further includes forming a bottom scanning circuit 330 and a bottom interconnection region 340 on each bottom sub-unit 310 , wherein the bottom scanning circuit 330 controls the gating of the driving unit array 320 in the bottom sub-unit 310 where it is located.

[0062] Since the pixels and the drivers are divided into different chip settings, the driver units are partitioned in the present invention, and an independent driver unit array 320 is set in each bottom sub-unit 310, so that the driver unit array 320 in each bottom sub-unit provides display drive to the pixel array 220 in the corresponding top sub-unit. Further, each bottom sub-unit 310 controls the driver unit array 320 through a bottom scanning circuit 330 set on one side thereof. In the embodiment of the present disclosure, the driver unit array 320 in each bottom sub-unit 310 controls the display of the pixel array 220 in its corresponding top sub-unit 210, and the corresponding driver module is integrated on the bottom surface of the original display pixel array, so as to realize the architecture of splicing display drive in a single screen body.

[0063] In the embodiment of the present disclosure, the forming of the bottom chip 30 further includes: forming a bottom logic circuit 350 and a flexible circuit board lead 360 on the bottom chip 30 , thereby obtaining the bottom chip 30 .

[0064] Furthermore, in this embodiment, the bottom logic circuit 350 is used to distribute the driving data of the pixel display to the driving array according to the positional relationship between the driving array and the pixel array, so that the display driving data of the entire pixel area can be transmitted in parallel to the driving array, and then transmitted in parallel to the top sub-unit in the top silicon-based chip, thereby solving the problem of overall coordination from driving data to controlling pixel switches for image display. Since the driving data is also partitioned, the refresh frequency can be improved as a whole.

[0065] In some embodiments, the flexible circuit board lead may be composed of a flexible substrate and a conductive copper foil. The flexible substrate may be a polyester film or a polyimide film.

[0066] S5: interconnecting the top sub-units of the top chip and the bottom sub-units of the bottom chip in a one-to-one correspondence, wherein the bottom sub-units are used to control the display of the pixel arrays in the corresponding interconnected top sub-units.

[0067] In the embodiment of the present disclosure, the top chip and the bottom chip are conductively interconnected through copper interconnect plugs, so that the top sub-units on the top chip and the bottom sub-units on the bottom chip are interconnected one by one. In some other embodiments, other metals can also be used to connect through chip-to-chip plug interconnection, which is not limited by the present disclosure.

[0068] Specifically, each bottom sub-unit 310 is provided with a bottom interconnection area 340 on one side thereof, so that each top sub-unit 210 unit in the top silicon-based chip 20 and the driving circuit in the bottom silicon-based chip 30 are directly interconnected by means of an interconnection metal plug or interconnection metal provided in the area, so that the driving unit in each bottom sub-unit controls the display of the pixel array in its corresponding top sub-unit.

[0069] exist Figure 1 In the embodiment, the method for manufacturing a display based on silicon-based splicing display driver further includes forming a tungsten via 201 on the opposite side of the top chip 20 relative to the bottom chip 30. Through the tungsten via 201, signals, power supplies or ground lines between different layers of the circuit board can be effectively connected to achieve normal operation of the circuit.

[0070] In another embodiment, after forming the bottom chip, an OSFET device may be integrated on the bottom chip and used as the top chip to realize the function of the top chip.

[0071] In a specific embodiment, the preparation process of the OSFET device includes: forming a back gate electrode and depositing a gate insulating layer, the back gate electrode is used to support the subsequent thin film; forming a CAAC-IGZO island on the gate electrode, then depositing an insulating layer and performing chemical mechanical polishing (CMP) to ensure a smooth surface in preparation for the next step. Next, a source / drain (S / D) pattern is formed on the surface of the film using a self-aligned technique; a top gate insulating layer and a gate electrode are deposited; a passivation layer and contact points are formed to protect the transistor and ensure that the signal can be effectively transmitted; after the main structure is completed, a metal layer is formed to provide connection and support.

[0072] The method for preparing a display based on a silicon-based splicing display driver provided in the embodiment of the present disclosure divides the pixel units into different sub-units, so that in the entire display panel, the partitions start displaying at the same time, rather than scanning line by line, thereby improving the refresh rate; the pixels and the driver are divided into different chip settings, and the corresponding driver module is integrated on the bottom surface of the original display pixel array, thereby realizing the architecture of splicing display driver in a single screen body, greatly reducing the driving load.

[0073] The present invention can realize a low-latency driving method. Specifically, a lamination process is used on a silicon-based chip to realize partition splicing driving. Because the number of line scans of each sub-spliced ​​screen is greatly reduced, the degradation interference noise of progressive scanning is significantly reduced, and the screen itself can easily achieve an ultra-high frame rate, which improves the grayscale dynamic response time (from milliseconds to microseconds). In addition, the driving load (Source loading) is greatly reduced under this circuit structure, which means that dynamic power consumption can be reduced. Because of the splicing drive, independent EM dimming of each sub-spliced ​​screen becomes possible.

[0074] This can increase the scanning circuit and driving circuit units of the traditional single backplane by 1 to 2 orders of magnitude, distribute the added scanning and driving units to the corresponding top chip and bottom chip, and integrate them through silicon-based packaging technology. Through the splicing display drive architecture, the advantages of low latency, ultra-high refresh, independent partition EM dimming and other display effect improvements can be achieved.

[0075] The present invention also provides a driving method for a display based on silicon-based splicing display drive, comprising: the bottom sub-unit divides the image data according to the top sub-unit; controlling the gating of the pixel array in the top sub-unit by controlling the top scanning circuit; controlling the gating in the bottom chip and the top chip to realize the image display of the corresponding bottom sub-unit and the top sub-unit.

[0076] like Figure 8As shown, specifically, firstly, the line-by-line scanned image input from the whole system end is cut into image data according to the resolution of the top sub-unit; a frame start pulse signal STV is issued, and the frequency of the pulse signal is the same as the frame rate; a row scan clock signal CKV is issued, and the number in a frame period is approximately equal to the vertical resolution, the number of top sub-units in each column; the digital image data is converted into the analog potential Data of the top sub-units of 1-m rows.

[0077] The following are some examples:

[0078] When the vertical resolution is 4K and the frame rate is 60 Hz, the Line time is 1 / 60 / 4000, which is approximately equal to 4.16 us; when the frame rate is 240 Hz, the Line time = 1.04 us.

[0079] The following is an example 2:

[0080] When the number of rows n of the top subunit is 40 and the frame rate is 60 Hz, the Line time (row scanning time) is 1 / 60 / 40, which is approximately equal to 416 us; and when the frame rate is 240 Hz, the Line time = 104 us.

[0081] The limitation of high refresh rate is the requirement of pixel circuit writing time, which is related to Line Time, load and horizontal multiplexing ratio (MUX). When Line Time is released by an order of magnitude, the bottleneck of the whole design will not be on the screen side. In the present invention, the bottom scanning circuit 330 (Logic) generates a row scanning circuit control signal, the driving unit array 320 (Video Data Driving) converts the digital image data into analog potential, and the bottom interconnection area 340 (Connection) is connected to the top sub-unit through Cu-Cu process. When the horizontal multiplexing ratio Mux=1, the number of Data channels is m, and Mux=2, the number of Data channels is m / 2, and the number of connections can be flexibly adjusted by adjusting Mux; the top sub-unit converts the received digital image signal into a PWM pulse signal corresponding to the grayscale, thereby realizing the control of 8-bit grayscale brightness.

[0082] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display based on silicon-based splicing display driver, characterized in that: include: A top chip and a bottom chip in a stacked structure, wherein the top chip and the bottom chip are interconnected by metal; The top chip includes an array formed by a plurality of top sub-units, each top sub-unit including a pixel array; The bottom chip includes an array formed by a plurality of bottom sub-units, each bottom sub-unit includes at least one driving unit, and the bottom sub-unit array partitions display data according to its corresponding pixel array; The top sub-units and the bottom sub-units are interconnected one by one, and the bottom sub-units are used to control the display of the pixel array in the corresponding interconnected top sub-units.

2. The display based on silicon-based splicing display driver according to claim 1, characterized in that: The top chip and the bottom chip are conductively interconnected via copper interconnect plugs.

3. The display based on silicon-based splicing display driver according to claim 2, characterized in that: The top chip and / or the bottom chip are silicon-based chips.

4. The display based on silicon-based splicing display driver according to claim 3, characterized in that: The bottom silicon-based chip also includes bottom logic circuits and flexible circuit board leads.

5. The display based on silicon-based splicing display driver according to claim 1, characterized in that: The top subunit further comprises a top scanning circuit and a top interconnection area interconnected with the pixel array. The top scanning circuit controls the gating of the pixel array in the top subunit where the top scanning circuit is located.

6. The display based on silicon-based splicing display driver according to claim 5, characterized in that: The bottom subunit further comprises a bottom scanning circuit and a bottom interconnection area. The bottom subunit comprises a driving unit array. The bottom scanning circuit controls the gating of the driving unit array in the bottom subunit where the bottom scanning circuit is located.

7. The display based on silicon-based splicing display driver according to claim 6, characterized in that: A top interconnection region of a top subunit and a bottom interconnection region of a bottom subunit are conductively interconnected via a copper interconnection plug.

8. The display based on silicon-based splicing display driver according to claim 7, characterized in that: The driving unit in the bottom subunit controls the display of the pixel array in its corresponding top subunit.

9. The display based on silicon-based splicing display driver according to claim 1, characterized in that: The top chip has tungsten vias on the side facing away from the bottom chip.

10. A method for manufacturing a display based on silicon-based splicing display driver according to claim 1, characterized in that: include: Providing a bottom chip, each bottom chip comprising a bottom sub-unit array composed of a plurality of bottom sub-units, at least one driving unit being formed in each bottom sub-unit, and the bottom sub-unit array partitioning display data according to its corresponding pixel array; Providing a top chip, each top chip comprising a top sub-unit array consisting of a plurality of top sub-units, each top sub-unit forming a pixel array; The top sub-units of the top chip and the bottom sub-units of the bottom chip are interconnected in a one-to-one correspondence, and the bottom sub-units are used to control the display of the pixel arrays in the corresponding interconnected top sub-units.

11. The manufacturing method according to claim 10, characterized in that: The top chip and the bottom chip are conductively interconnected via copper interconnect plugs.

12. The manufacturing method according to claim 10, characterized in that: The material of the top chip and / or the bottom chip is silicon.

13. The manufacturing method according to claim 10, characterized in that: Also includes: Bottom logic circuits and flexible circuit board leads are formed on each bottom chip.

14. The manufacturing method according to claim 11, characterized in that: Also includes: A top scanning circuit and a top interconnection area interconnected with the pixel array are formed on each top sub-unit, and the top scanning circuit controls the gating of the pixel array in the top sub-unit where the top scanning circuit is located.

15. The manufacturing method according to claim 14, characterized in that: Also includes: A bottom scanning circuit and a bottom interconnection region are formed on each bottom sub-unit, wherein the bottom sub-unit includes a driving unit array, and the bottom scanning circuit controls the gating of the driving unit array in the bottom sub-unit where the bottom scanning circuit is located.

16. The manufacturing method according to claim 15, characterized in that: The conductive interconnection between the top chip and the bottom chip through the copper interconnection plug includes: conductively interconnecting a top interconnection area of ​​a top subunit and a bottom interconnection area of ​​a bottom subunit in a one-to-one correspondence through a copper interconnection plug.

17. The manufacturing method according to claim 16, characterized in that: The driving unit in the bottom subunit controls the display of the pixel array in its corresponding top subunit.

18. The manufacturing method according to claim 10, characterized in that: Also includes: Tungsten vias are formed on the side of the top chip facing away from the bottom chip.

19. A method for driving a display based on silicon-based splicing display drive according to claim 1, characterized in that: include: The bottom subunit divides the image data according to the top subunit; Controlling the gating of the pixel array in the top subunit where the top scanning circuit is located by controlling the top scanning circuit; Control the strobe in the bottom chip and the top chip to realize the image display of the corresponding bottom subunit and top subunit.

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