Path-based layer stack connectivity checking for plasma-induced damage avoidance

Abstract

A computing system implementing a reliability verification tool is disclosed to identify a portion of a layout design describing an integrated circuit, the integrated circuit including a victim transistor and an aggressor transistor, the victim transistor having a gate connected to the aggressor transistor. The reliability verification tool can extract a resistor network for the connection between the victim transistor and the aggressor transistor and simulate the resistor network to determine that the connection between the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 364,884, filed on May 18, 2022, which is incorporated herein by reference. Technical Field

[0003] The present application relates generally to electronic design automation and, more particularly, to path-based layer stack connectivity checking for plasma-induced damage avoidance. Background Art

[0004] In the design process for manufacturing integrated circuits, the physical design of an integrated circuit describes specific geometric elements and is often referred to as a layout design. These geometric elements, typically polygons, define the shapes that will be produced in various materials to manufacture the integrated circuit. Typically, the designer will select a group of geometric elements representing circuit device components, such as contacts, gates, and place them in the design area. These groups of geometric elements can be custom-designed, selected from a previously created design library, or some combination of the two. Once the groups of geometric elements representing the circuit device components have been placed, geometric elements representing connecting lines are then placed between these geometric elements according to a predetermined route. These lines will form the wiring used to interconnect the electronic devices.

[0005] Descriptions of the physical design of integrated circuits can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transmitting and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it contains a hierarchy of structures, each of which includes layout elements (such as polygons, paths or polylines, circles, and text boxes). Other formats include open source formats called Open Access, Milkyway, EDDM, and the Open Artwork System Interchange Standard (OASIS). These various industry formats are used to define geometric information in the layout design used to manufacture integrated circuits. Once the design is completed, the layout portion of the design can be used by manufacturing tools to manufacture the circuit using photolithography processes.

[0006] There are many different fabrication processes for making circuits, but most processes involve a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch away the exposed (or unexposed) portions of the layer. For example, a simple semiconductor device component can be made by the following steps. First, a positive epitaxial layer is grown on a silicon substrate by chemical vapor deposition. Next, a nitride layer is deposited on the epitaxial layer. Specific areas of the nitride layer are then exposed to radiation, and the exposed areas are etched away, leaving exposed areas on the epitaxial layer (i.e., areas no longer covered by the nitride layer). The exposed areas are then subjected to a diffusion or ion implantation process, which allows dopants (e.g., phosphorus) to enter the exposed epitaxial layer and form charged wells. This process of depositing a layer or subsequent layers of material on a substrate, then exposing a specific pattern to radiation, etching, and dopants or other diffused materials is repeated multiple times, allowing the manufacture of different physical layers of a circuit.

[0007] During the manufacture of integrated circuits, transistors may have gate dielectrics that are thin enough, such as only a few molecules thick, to be damaged when the transistor gate receives a higher voltage than expected. For example, an aggressor transistor may be designed to provide a voltage to the gate of a victim transistor. To avoid damaging the gate dielectric of the victim transistor during manufacturing, foundries will typically manufacture the transistors by making a connection between the well of the aggressor transistor and the well of the victim transistor, and then making a connection from the aggressor transistor to the gate of the victim transistor.

[0008] Many foundries generate connection rules that can be used to ensure that a layout design with an attack transistor and a victim transistor pair will make a connection between the well of the attack transistor and the well of the victim transistor before making a connection from the attack transistor to the gate of the victim transistor. Traditional verification tools apply these connection rules in a step-by-step manner by analyzing the layers of the layout design from the substrate up to the metal layer. However, the victim transistor well and the attack transistor well are often not directly connected in the layout design, but include intermediate circuits such as current pumps, intermediate wells, etc. This lack of a direct connection between the victim transistor well and the attack transistor well will inhibit traditional verification tools and cause this part of the layout design to not be checked by the connection rules. Summary of the Invention

[0009] The present application discloses a computing system that implements a reliability verification tool to identify a portion of a layout design describing an integrated circuit that includes a victim transistor and an aggressor transistor, the victim transistor having a gate connected to the aggressor transistor. The reliability verification tool can extract a resistor network for the connection between the victim transistor and the aggressor transistor and simulate the resistor network to determine whether the connection between the victim transistor and the well of the aggressor transistor occurs before the victim transistor has a gate connected to the aggressor transistor. Embodiments are described in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 and Figure 2 Illustrated are examples of the types of computer systems that may be used to implement various embodiments.

[0011] Figure 3 An example of a physical verification system including a reliability verification system that performs path-based layer stack connectivity checking for plasma-induced damage avoidance according to various embodiments is illustrated.

[0012] Figure 4 A flow chart showing an example path-based layer stack connectivity check for plasma-induced damage avoidance, according to various examples, is illustrated.

[0013] Figure 5 An example layout design with an aggressor transistor, a victim transistor, and an intermediate circuit according to various embodiments is illustrated.

[0014] Figures 6A to 6C Illustrated for Figure 5 An example of path-based layer stack connectivity checking for plasma-induced damage avoidance in the layout design described in

[15] . DETAILED DESCRIPTION

[0015] Illustrative operating environment

[0016] Various examples may be implemented by executing software instructions by a computing device (e.g., a programmable computer). Figure 1 An illustrative example of a computing device 101 is shown. As seen in the figure, computing device 101 includes a computing unit 103 having a processing unit 105 and a system memory 107. Processing unit 105 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. System memory 107 can include read-only memory (ROM) 109 and random access memory (RAM) 111. As will be understood by one of ordinary skill in the art, both read-only memory (ROM) 109 and random access memory (RAM) 111 can store software instructions for execution by processing unit 105.

[0017] The processing unit 105 and system memory 107 are connected directly or indirectly via bus 113 or an alternative communication structure to one or more peripheral devices 115-123. For example, the processing unit 105 or system memory 107 can be directly or indirectly connected to one or more additional storage devices, such as a magnetic and / or removable hard drive 117, a removable optical drive 119, and / or a flash memory card. The processing unit 105 and system memory 107 can also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. Input devices 121 can include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. Output devices 123 can include, for example, a monitor display, a printer, and speakers. For various examples of computing device 101, one or more peripheral devices 115-123 can be housed internally with the computing unit 103. Alternatively, one or more peripheral devices 115-123 can be external to the housing of the computing unit 103 and connected to the bus 113 via, for example, a universal serial bus (USB) connection.

[0018] For some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 to communicate with other devices comprising the network. The network interface 115 may convert data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). Furthermore, the network interface 115 may utilize any suitable connection agent (or combination of agents) to connect to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and, therefore, will not be discussed in further detail herein.

[0019] It should be understood that computing device 101 is illustrated only as an example and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices including Figure 1 The components of the computing device 101 illustrated in FIG. 1 include only Figure 1 A subset of the components illustrated in, or an alternative combination of components, including Figure 1 For example, various embodiments may be implemented using a multi-processor computer, multiple single-processor and / or multi-processor computers arranged in a network, or some combination of the two.

[0020] For some implementations, processor unit 105 may have more than one processor core. Figure 2The example of a multi-core processor unit 105 that can be used with various embodiments is illustrated. As seen in the figure, the processor unit 105 includes multiple processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B and a memory cache 205A and 205B respectively. As known to those of ordinary skill in the art, the computing engine 203A and 203B may include logic devices for performing various computing functions (e.g., obtaining software instructions and then performing the actions specified in the obtained instructions). These actions may include, for example, adding, subtracting, multiplying and comparing numbers, performing logical operations (e.g., AND, OR, NOR and XOR) and retrieving data. Each computing engine 203A and 203B can then use its corresponding memory cache 205A and 205B to quickly store and retrieve data and / or instructions for execution.

[0021] Each processor core 201A and 201B is connected to an interconnect 207. The specific configuration of the interconnect 207 may vary depending on the architecture of the processor unit 105. For some processor cores 201A and 201B (e.g., the Cell microprocessor created by Sony Corporation, Toshiba Corporation, and IBM Corporation), the interconnect 207 may be implemented as an interconnect bus. However, for other processor cores 201A and 201B (e.g., the Opteron microprocessor available from Advanced Micro Devices, Inc. of Sunnyvale, California), the interconnect 207 may be implemented as a bus. TM and Athlon TM In some implementations, the processor unit 105 may include additional components, such as a shared high-level cache memory accessible by the processor cores 201A and 201B. It should also be understood that Figure 1 and Figure 2 The description of the illustrated computer network is provided by way of example only and is not intended to suggest any limitation as to the scope of use or functionality of the alternative embodiments.

[0022] Path-based layer stack connectivity checking for plasma-induced damage avoidance

[0023] Figure 3 An example of a physical verification system 300 including a reliability verification system 320 that performs path-based layer stack connectivity checking for plasma-induced damage avoidance is illustrated according to various embodiments. Figure 4A flow chart illustrating an example path-based layer stack connectivity check for plasma-induced damage avoidance according to various examples is illustrated. Figure 3 and Figure 4 , a physical verification system 300 may receive a layout design 301 for an electronic system. The layout design 301 may define geometric information that can be used to manufacture an integrated circuit (e.g., an electronic system), and may be specified in a Graphic Data System II (GDSII) format, an open access format, a Milkyway format, an EDDM format, an Open Artwork System Interchange Standard (OASIS) format, etc. The physical verification system 300 may also receive connection rules 302, for example from a foundry or integrated circuit manufacturer, to identify valid types of connections and a manufacturing order for circuit device connections in the layout design 301.

[0024] In some embodiments, the physical verification system 300 may include a design rule checking system 310 that analyzes the layout design 301 to determine whether the circuits within the layout design 301 comply with design rules from a foundry capable of manufacturing the integrated circuit described by the layout design 301. When determining whether the layout design 301 complies with the connection rules 302, the design rule checking system 310 may perform a layer-by-layer check of the order of electrical connections of the integrated circuit. The design rule checking system 310 may identify connections on different layers of the integrated circuit in the order in which they are manufactured (e.g., starting with the substrate layer, then moving to the diffusion layer, and then moving to the various stacked metal layers).

[0025] The design rule checking system 310 can utilize the identified connections on different layers to perform a connection check based on the connection rules 302. In some embodiments, when the design rule checking system 310 identifies that a pair of transistors does not comply with the connection rules 302, for example, because there is no connection between the wells of the transistors before connecting the gate region of at least one of the transistors, the design rule checking system 310 can generate one or more connection errors 303. In some cases, the connection errors 303 generated by the design rule checking system 310 can be false, for example, because the transistor pair can have their wells connected to a common voltage potential through a shared intermediate circuit (e.g., a current pump circuit or an intermediate well).

[0026] Physical verification system 300 may include reliability verification system 320 that determines whether layout design 301 complies with connection rules 302. In some embodiments, reliability verification system 320 may receive connection errors 303 from design rule checking system 310. Reliability verification system 320 may analyze portions of layout design 301 that may be associated with connection errors 303 to determine whether a transistor pair can connect their wells to a common voltage potential, directly or through shared intermediate circuitry (e.g., a current pump circuit or an intermediate well), and further determine whether this connection allows the transistor pair to comply with connection rules 302. In some embodiments, reliability verification system 320 may determine whether layout design 301 complies with connection rules 302 independent of any connection errors 303 generated by design rule checking system 310 and / or without design rule checking system 310 performing a check of layout design 301 against connection rules 302.

[0027] The reliability verification system 320 may include a connection system 321 that identifies circuit devices and their connections described in the layout design 301. For example, the connection system 321 may analyze geometric information in the layout design 301 to identify circuit devices and their connections. In some embodiments, in block 401, the connection system 321 may identify a portion of the layout design that describes an integrated circuit, the integrated circuit including a victim transistor and an aggressor transistor having a well. In some embodiments, the wells of the victim transistor and the aggressor transistor may be coupled to a shared intermediate circuit. Figure 5 Embodiments of aggressor transistors, victim transistors, and intermediate circuits in a layout design are described in more detail.

[0028] Figure 5 An example layout design with an aggressor transistor, a victim transistor, and an intermediate circuit according to various embodiments is illustrated. Figure 5, a portion of integrated circuit 500 may include transistors 501-504. Transistors 501 and 503 may be P-type channel metal oxide semiconductor (PMOS) transistors, while transistors 502 and 504 may be N-type channel metal oxide semiconductor (NMOS) transistors. Transistors 501 and 502 may be formed as switches, with their drain regions coupled to the gate regions of transistors 503 and 504. The source regions of transistors 502 and 504 may be connected via an intermediate circuit 505, which may include at least one current pump, an intermediate well, other circuitry coupled between the wells of transistors 502 and 504, or a combination thereof. During fabrication, the connection of the source regions of transistors 502 and 504 via intermediate circuit 505 should be made before the connection between the drain regions of transistors 501 and 502 and the gate regions of transistors 503 and 504 is made to avoid any plasma-induced damage to the dielectrics of the gate regions of transistors 503 and 504.

[0029] Return Reference Figure 3 and Figure 4 , the reliability verification system 320 may include a parasitic extraction system 322 that determines the resistive electrical characteristics of the circuits identified by the connection system 321 in the layout design 301, for example, by converting polygons on a layer of the layout design 301 into equivalent resistance representations. The parasitic extraction system 322 may aggregate the resistive electrical characteristics into a resistive network, which may be an equivalent resistance representation of the circuits identified by the connection system 321. In some embodiments, in block 402, the parasitic extraction system 322 may extract the resistive network for connections between the victim transistor, the attack transistor, and any shared intermediate circuits coupled between the wells of the victim transistor and the attack transistor. Reference will be made below to Figure 6A Embodiments of a resistive network for connections between the victim transistor, the aggressor transistor, and the shared intermediate circuit are described in more detail.

[0030] Figures 6A to 6C Illustrated for Figure 5 Example of path-based layer stack connectivity checking for plasma-induced damage avoidance in the layout design described in . Figure 6A , the resistor network 610 can be Figure 5 5. The resistor network 610 may include a pair of transistors 602 and 604, which may correspond to Figure 5 Transistors 502 and 504 in. Transistors 602 and 604 can be connected to a resistor intermediate circuit 605, which can correspond to Figure 5 The resistance representation may also include resistors R, which represent the various connections between transistors 602 and 604 and the resistance intermediate circuit 605 and their locations within the different metal layers of the integrated circuit.

[0031] Return Reference Figure 3 and Figure 4 , the reliability verification system 320 may include a layer condition system 323 that sets various conditions for the integrated circuit described in the layout design 301 at different manufacturing stages based at least in part on the connection rules 302. Conditions such as a condition when the top metal layer has not yet been manufactured, but other layers below the top metal layer have been manufactured, may indicate that the top metal layer is an open circuit and, therefore, blocks current from flowing through the portion of the resistor network corresponding to the top metal layer. In some embodiments, the layer condition system 323 may set the layers to be open circuits by setting the resistance values ​​of these layers to have an infinite resistance value or some other very high resistance value that blocks current from flowing through the resistor network. In some embodiments, in box 403, the layer condition system 323 may set the resistance value of the connection between the gate of the victim transistor and the attacking transistor to block current from flowing through the connection.

[0032] The reliability verification system 320 may include a simulator 324 that simulates the conditions of the resistor network set by the layer condition system 323. In some embodiments, the simulator 324 may inject current into the node of the attacking transistor and then use numerical simulation (e.g., using Kirchhoff's current law) to determine whether the injected current reaches the victim transistor. In some embodiments, in block 404, the simulator 324 may simulate the resistor network using the resistance values ​​set for the connection to determine the connection between the victim transistor and the well of the attacking transistor. Figure 6B Embodiments of simulating a resistor network with blocked current flowing through a connection between the gate of a victim transistor and an aggressor transistor are described in greater detail.

[0033] Figures 6A to 6C Illustrated for Figure 5 Example of path-based layer stack connectivity checking for plasma-induced damage avoidance in the layout design described in . Figure 6B , the resistor network 620 can be configured to block current from flowing through the Metal 3 layer, which will include the connection between the drain region of transistor 602 and the gate region of transistor 604. This condition can correspond to a situation where the substrate layer, diffusion layer, Metal 1 layer, and Metal 2 layer have been fabricated, but the Metal 3 layer has not yet been fabricated. The simulator can apply an injected current 621 to the source region of transistor 602 and detect whether the source region of transistor 604 receives a current 622. The presence of a received current 622 on the source region of transistor 604 indicates that the source regions of the two transistors 602 and 604 are connected to each other via the resistor intermediate circuit 605, and indicates that the connection between the drain region of transistor 602 and the gate region of transistor 604 has been made before the connection between them is made.

[0034] Return Reference Figure 3 and Figure 4 In some embodiments, in block 405, the layer condition system 323 may set the resistance value of the connection between the gate of the victim transistor and the attacking transistor so as not to block current from flowing through the connection. The condition set by the layer condition system 323 may correspond to when the connection between the gate of the victim transistor and the attacking transistor has already been fabricated. In some embodiments, in block 406, the connection system 324 may simulate a resistor network using the resistance value set for the connection to determine the electrical connection of the connection between the gate of the victim transistor and the attacking transistor. Although the simulation of the layer conditions has been shown as being performed serially, in some embodiments, the layer condition system 323 may generate a matrix with different conditions and their corresponding resistance values ​​in various layers, and the simulator 324 may simulate the resistor network across the different conditions in parallel. The matrix and the different conditions may correspond to different connection paths through different layers and polygons in the layout design 301, which may be associated with the connection rules 302. In some embodiments, the matrix may be populated with different conditions determined by the connection system 324 or received by the reliability verification system 320 via user input. The ability to allow user-based control over whether an entire layer or specific polygons within a layer form a path between a victim transistor and an aggressor transistor can increase flexibility for analyzing layout designs 301 with different construction requirements, such as in multi-chip modules for three-dimensional integrated circuits (3DICs). Figure 6C An embodiment of simulating a resistor network using unblocked current flowing through a connection between the gate of a victim transistor and an aggressor transistor is described in further detail.

[0035] Figures 6A to 6C Illustrated for Figure 5 Example of path-based layer stack connectivity checking for plasma-induced damage avoidance in the layout design described in . Figure 6C , the resistor network 630 can be set to not block current flow through the Metal 3 layer, which will include the connection between the drain region of transistor 602 and the gate region of transistor 604. This condition can correspond to a situation where all layers - substrate to Metal 3 - have been fabricated. The simulator can apply an injected current 631 to the drain region of transistor 602 and detect whether the gate region of transistor 604 receives the current 632. The presence of the received current 632 on the gate region of transistor 604 indicates that the connection to the gate region of transistor 604 has been fabricated.

[0036] Return Reference Figure 3 and Figure 4, the reliability verification system 320 may include a reporting system 325 that applies one or more connection rules to the connections determined during the one or more simulations in block 407 to determine whether the portion of the layout design can be manufactured to avoid plasma-induced damage to the gate dielectric of the victim transistor. The reporting system 325 may analyze the intermediate circuits in the portion of the layout design 301 to determine whether connections have been made through intermediate wells, which are often referred to as soft connections between the aggressor transistor and the victim transistor. The reporting system 325 may generate a connection report 303 based on the results determined from applying the connection rules 302 to the connections determined during the one or more simulations. The connection report 303 may identify which portions of the layout design 301 comply or do not comply with the connection rules 302 and / or whether any connections have been made through soft connections via intermediate wells.

[0037] The above-described systems and devices may use a dedicated processor system, a microcontroller, a programmable logic device, a microprocessor, or any combination thereof to perform some or all of the operations described herein. Some of the above-described operations may be implemented in software, while other operations may be implemented in hardware. Any operations, processes, and / or methods described herein may be performed by devices, equipment, and / or systems substantially similar to the devices, equipment, and / or systems described herein and with reference to the illustrated figures.

[0038] The processing device can execute instructions or "code" stored in the memory. The memory can also store data. The processing device can include, but is not limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The processing device can be part of an integrated control system or system manager, or can be provided as a portable electronic device configured to interface with a networked system locally or remotely via wireless transmission.

[0039] The processor memory can be integrated with the processing device, for example, RAM or flash memory arranged within an integrated circuit microprocessor or the like. In other examples, the memory can include a separate device, such as an external disk drive, a storage array, a portable flash key fob, or the like. The memory and the processing device can be operably coupled together or communicate with each other, for example, via an I / O port, a network connection, or the like, and the processing device can read files stored on the memory. Depending on the permission settings, the associated memory can be designed to be "read-only" (ROM) or not. Other examples of memory can include, but are not limited to, WORM, EPROM, EEPROM, flash memory, etc., which can be implemented in solid-state semiconductor devices. Other memories can include moving parts, such as known rotating disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0040] The operating instructions or commands may be implemented or embodied in the tangible form of stored computer software (also referred to as a "computer program" or "code"). The program or code may be stored in a digital memory and may be read by a processing device. "Computer-readable storage media" (or alternatively, "machine-readable storage media") may include all of the aforementioned types of memory as well as new technologies of the future, as long as the memory is capable of storing digital information having the properties of a computer program or other data at least temporarily, and as long as the stored information can be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical use of "computer" to imply a complete mainframe, minicomputer, desktop or even laptop computer. On the contrary, "computer-readable" may include storage media that can be read by a processor, a processing device or any computing system. Such media may be any available media that can be accessed locally and / or remotely by a computer or processor, and may include volatile and non-volatile media, removable and non-removable media, or any combination thereof.

[0041] A program stored in a computer-readable storage medium may include a computer program product. For example, a storage medium may be used as a convenient means for storing or transmitting a computer program. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logical device, program, or operation without clear boundaries.

[0042] in conclusion

[0043] Although this application describes specific examples of implementing embodiments of the present invention, those skilled in the art will appreciate that there are many variations and permutations of the above-described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, although specific terminology has been employed above to refer to electronic design automation processes, it will be understood that any desired combination of electronic design automation processes may be used to implement the various examples of the present invention.

[0044] Those skilled in the art will also recognize that the concepts taught herein can be adapted to specific applications in many other ways. In particular, those skilled in the art will recognize that the illustrated example is only one of many alternative implementations that will become clear upon reading this disclosure.

[0045] Although the specification may refer to "one," "another," or "some" examples in several places, this does not necessarily mean that each such reference is to the same example or examples or that the feature applies to only a single example.

Claims

1. A method for path-based layer stack connectivity inspection for plasma-induced damage avoidance, comprising: identifying, by a computing system, a portion of a layout design describing an integrated circuit, the integrated circuit including a victim transistor and an aggressor transistor, the victim transistor having a gate connected to the aggressor transistor, wherein the victim transistor and the aggressor transistor have wells; extracting, by the computing system, a resistor network for connection between the victim transistor and the attack transistor; and simulating, by the computing system, the resistor network to determine that connection between the well of the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor; Wherein, simulating the resistor network further comprises: setting a resistance value of a connection between the gate of the victim transistor and the aggressor transistor to block current from flowing through the connection; injecting current at a source region of the attack transistor in the resistor network; and Receipt of the injected current at a source region of the victim transistor in the resistor network is detected to confirm the connection between the well of the victim transistor and the well of the aggressor transistor.

2. The method according to claim 1, further comprising: setting a resistance value of the connection between the gate of the victim transistor and the aggressor transistor so as not to block current from flowing through the connection; injecting a current at a drain region of the aggressor transistor in the resistor network toward the gate of the victim transistor; as well as Receipt of the injected current at the gate of the victim transistor in the resistor network is detected to confirm the connection between the aggressor transistor and the gate of the victim transistor.

3. The method according to claim 1, wherein Extracting the resistive network for the connection between the victim transistor and the aggressor transistor includes extracting a shared intermediate circuit coupled to the well of the victim transistor and the well of the aggressor transistor.

4. The method according to claim 3, wherein: The shared intermediate circuit includes at least one of a current pump circuit coupled between the source region of the attacking transistor and the source region of the victim transistor or a different well in the substrate coupled as a soft connection between the source region of the attacking transistor and the source region of the victim transistor.

5. The method of claim 1 , further comprising applying, by the computing system, one or more connection rules to the connections determined during the simulation to determine whether fabrication of the portion of the layout design avoids plasma-induced damage.

6. The method according to claim 1, further comprising: detecting, by the computing system through a design rule checking process, that the layout design includes connection errors corresponding to one or more design rules; as well as The connection error is discarded by the computing system based on a determination that the connection between the well of the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor.

7. A system for path-based layer stack connectivity inspection for plasma-induced damage avoidance, comprising: a storage system configured to store computer-executable instructions; as well as A computing system, which, in response to executing the computer-executable instructions, is configured to: identifying a portion of a layout design describing an integrated circuit, the integrated circuit including a victim transistor and an aggressor transistor, the victim transistor having a gate connected to the aggressor transistor, wherein the victim transistor and the aggressor transistor have wells; extracting a resistor network for connection between the victim transistor and the aggressor transistor; and simulating the resistor network to determine that connection between the well of the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor; Wherein, simulating the resistor network further comprises: setting a resistance value of a connection between the gate of the victim transistor and the aggressor transistor to block current from flowing through the connection; injecting current at a source region of the attack transistor in the resistor network; and Receipt of the injected current at a source region of the victim transistor in the resistor network is detected to confirm the connection between the well of the victim transistor and the well of the aggressor transistor.

8. The system according to claim 7, wherein: Simulating the resistor network further includes: setting a resistance value of the connection between the gate of the victim transistor and the aggressor transistor so as not to block current from flowing through the connection; injecting current at a drain region of the aggressor transistor in the resistor network toward the gate of the victim transistor; and Receipt of the injected current at the gate of the victim transistor in the resistor network is detected to confirm the connection between the aggressor transistor and the gate of the victim transistor.

9. The system according to claim 7, wherein: Extracting the resistive network for the connection between the victim transistor and the aggressor transistor includes extracting a shared intermediate circuit coupled to the well of the victim transistor and the well of the aggressor transistor.

10. The system according to claim 9, wherein: The shared intermediate circuit includes at least one of a current pump circuit coupled between the source region of the attacking transistor and the source region of the victim transistor or a different well in the substrate coupled as a soft connection between the source region of the attacking transistor and the source region of the victim transistor.

11. The system according to claim 7, wherein: The computing system, in response to executing the computer-executable instructions, is further configured to: detecting, by a design rule checking process, that the layout design includes connection errors corresponding to one or more design rules; as well as The connection error is discarded based on a determination that the connection between the well of the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor.

12. An apparatus for path-based layer stack connectivity checking for plasma-induced damage avoidance, comprising at least one computer-readable storage device for storing instructions, the instructions configured to cause one or more processing devices to perform operations comprising: identifying a portion of a layout design describing an integrated circuit, the integrated circuit including a victim transistor and an aggressor transistor, the victim transistor having a gate connected to the aggressor transistor, wherein the victim transistor and the aggressor transistor have wells; extracting a resistor network for connection between the victim transistor and the aggressor transistor; and simulating the resistor network to determine that connection between the well of the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor; Wherein, simulating the resistor network further comprises: setting a resistance value of a connection between the gate of the victim transistor and the aggressor transistor to block current from flowing through the connection; injecting current at a source region of the attack transistor in the resistor network; and Receipt of the injected current at a source region of the victim transistor in the resistor network is detected to confirm the connection between the well of the victim transistor and the well of the aggressor transistor.

13. The device according to claim 12, wherein Simulating the resistor network further includes: setting a resistance value of the connection between the gate of the victim transistor and the aggressor transistor so as not to block current from flowing through the connection; injecting current at a drain region of the aggressor transistor in the resistor network toward the gate of the victim transistor; and Receipt of the injected current at the gate of the victim transistor in the resistor network is detected to confirm the connection between the aggressor transistor and the gate of the victim transistor.

14. The device according to claim 12, wherein Extracting the resistive network for the connection between the victim transistor and the aggressor transistor includes extracting a shared intermediate circuit coupled to the well of the victim transistor and the well of the aggressor transistor.

15. The device according to claim 14, wherein The shared intermediate circuit includes at least one of a current pump circuit coupled between the source region of the attacking transistor and the source region of the victim transistor or a different well in the substrate coupled as a soft connection between the source region of the attacking transistor and the source region of the victim transistor.

16. The device according to claim 12, wherein The instructions are further configured to cause the one or more processing devices to perform operations including applying one or more connectivity rules to the connectivity determined during the simulation to determine whether fabrication of the portion of the layout design avoids plasma-induced damage.

17. The device according to claim 12, wherein The instructions are further configured to cause the one or more processing devices to perform operations comprising: detecting, by a design rule checking process, that the layout design includes connection errors corresponding to one or more design rules; and The connection error is discarded based on a determination that the connection between the well of the victim transistor and the well of the aggressor transistor occurs before the gate of the victim transistor is connected to the aggressor transistor.

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