Array substrate, liquid crystal lens and display device

Abstract

The application provides an array substrate, a liquid crystal lens and a display device, and relates to the technical field of display. The array substrate comprises a substrate and a first conductive layer on one side of the substrate. The first conductive layer comprises a plurality of first signal lines. The first signal lines comprise a first slope area, a flat area and a second slope area which are arranged in sequence along a second direction and extend along a first direction. The width of the first slope area and the second slope area along the second direction is greater than or equal to one fourth of the width of the first signal line along the second direction. The first signal line in the array substrate has a relatively gentle surface, so that the probability of breakage of other signal lines when crossing above the first signal line can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a liquid crystal lens, and a display device. Background Technology

[0002] Liquid crystal lenses, as novel optical devices, are widely used in various fields. They utilize the property that liquid crystal materials change their refractive index under the influence of an electric field to focus and disperse light. When an electric field is applied to a liquid crystal lens, the orientation of the liquid crystal molecules changes, thereby altering the refractive index distribution of the lens and modulating the light.

[0003] Currently, there are technical difficulties in the fabrication process of liquid crystal lenses, which can cause circuit breaks in the array substrate of the liquid crystal lens. Summary of the Invention

[0004] Embodiments of this application provide an array substrate, a liquid crystal lens, and a display device. The first signal line in the array substrate has a relatively flat surface, thereby reducing the probability of other signal lines breaking when crossing the first signal line.

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide an array substrate, comprising:

[0007] Substrate;

[0008] A first conductive layer located on one side of the substrate, the first conductive layer including a plurality of first signal lines, the first signal lines including a first slope region, a flat region and a second slope region extending along a first direction and arranged sequentially along a second direction;

[0009] Wherein, the width of the first slope area and the second slope area along the second direction is greater than or equal to one-quarter of the width of the first signal line along the second direction.

[0010] In some array substrates provided in embodiments of this application, the portion of the surface of the first signal line on the side away from the substrate located in the flat region is substantially parallel to the substrate;

[0011] The portion of the surface of the first signal line on the side away from the substrate located in the first slope region has a first angle with the substrate, and the portion of the surface of the first signal line on the side away from the substrate located in the second slope region has a second angle with the substrate. The angle range of the first angle and the second angle is 5° to 50°.

[0012] In some array substrates provided in embodiments of this application, the width of the first ramp region along the second direction is approximately equal to the width of the second ramp region along the second direction, and the first included angle is approximately equal to the second included angle.

[0013] In some array substrates provided in embodiments of this application, the array substrate further includes:

[0014] A second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes multiple second signal lines, which overlap with the first signal lines.

[0015] A first insulating layer is located between the first conductive layer and the second conductive layer and has a plurality of first through holes;

[0016] The second signal line includes a first segment and a second segment. The first segment extends in the same direction as the first signal line, and the second segment intersects the extension direction of the first signal line. The first segment is electrically connected to the first signal line through the first through hole. At least a portion of the orthographic projection of the first through hole onto the first signal line falls into the slope area.

[0017] In some array substrates provided in embodiments of this application, along the second direction, the distance between the center of the first through hole and one side of the first line segment is not equal to the distance between the center of the first through hole and the other side of the first line segment.

[0018] In some array substrates provided in embodiments of this application, the orthographic projection of the first via onto the first signal line falls into the first ramp region.

[0019] In some array substrates provided in embodiments of this application, a portion of the orthographic projection of the first via on the first signal line falls into the first ramp region, and another portion of the orthographic projection of the first via on the first signal line falls into the flat region.

[0020] In some array substrates provided in embodiments of this application, the orthographic projection of the first via onto the first signal line falls into the second ramp region.

[0021] In some array substrates provided in embodiments of this application, the orthographic projection of the first via on the first signal line falls into the second ramp region, and another portion of the orthographic projection of the first via on the first signal line falls into the flat region.

[0022] In some array substrates provided in the embodiments of this application, the plurality of second signal lines include a plurality of driving electrode line groups, and the driving electrode line groups include a plurality of driving electrode lines that do not transmit signals that are not completely identical;

[0023] The plurality of first signal lines include a plurality of parallel traces; the parallel traces are used to electrically connect the drive electrode lines with the same transmission signal in different drive electrode line groups together.

[0024] In some array substrates provided in the embodiments of this application, the array substrate includes a display area, a first hub area and a second hub area located on opposite sides of the display area, and a signal introduction area located on the side of the first hub area away from the display area;

[0025] The multiple parallel routing lines include a first parallel routing line and a second parallel routing line. The first hub area is provided with multiple first parallel routing lines, and the second hub area is provided with multiple second parallel routing lines.

[0026] The display area is provided with a plurality of driving electrode line groups; the plurality of driving electrode lines extend from the display area to the first hub area and the second hub area respectively, and are electrically connected to the first parallel line and the second parallel line respectively;

[0027] The number of the first parallel traces, the number of the second parallel traces, and the number of the drive electrode lines in the same drive electrode line group are equal.

[0028] In some array substrates provided in embodiments of this application, the signal introduction area includes:

[0029] Multiple overlapping traces are located on the second conductive layer; the multiple overlapping traces extend from the signal introduction area to the first hub area, and a portion of the overlapping traces overlap with the orthographic projection of the first parallel traces on the substrate;

[0030] Multiple signal lead-in lines are located on the first conductive layer; the first insulating layer has multiple second through holes, and the overlapping traces are electrically connected to the signal lead-in lines through the second through holes;

[0031] The number of the multiple overlapping wirings is the same as the number of the multiple first parallel wirings.

[0032] In some array substrates provided in embodiments of this application, the first insulating layer further includes a plurality of virtual vias disposed in the signal introduction area.

[0033] In some array substrates provided in embodiments of this application, the total area of ​​the plurality of virtual vias and the plurality of second vias in the signal introduction area is approximately the same as the area of ​​the first via.

[0034] Secondly, embodiments of this application provide a liquid crystal lens, including an array substrate as described in any one of the first aspects, and further including an opposing substrate and a liquid crystal layer located between the array substrate and the opposing substrate.

[0035] Thirdly, embodiments of this application provide a display device, including a display panel and a liquid crystal lens as described in the second aspect; the liquid crystal lens is disposed on the light-emitting side of the display panel.

[0036] Embodiments of this application provide an array substrate, a liquid crystal lens, and a display device. The array substrate includes a substrate and a first conductive layer located on one side of the substrate. The first conductive layer includes a plurality of first signal lines. The first signal lines include a first ramp region, a flat region, and a second ramp region that extend along a first direction and are arranged sequentially along a second direction. The width of the first ramp region and the second ramp region along the second direction is greater than or equal to one-quarter of the width of the first signal line along the second direction.

[0037] In the array substrate provided in the embodiments of this application, the first signal line is provided with a first ramp area, a flat area and a second ramp area extending along a first direction and arranged sequentially along a second direction, and the width of the first ramp area and the second ramp area along the second direction is greater than or equal to one-quarter of the width of the first signal line along the second direction. Since the width of the two ramp areas (including the first ramp area and the second ramp area) along the second direction is greater than or equal to half the width of the first signal line along the second direction, the first signal line has a relatively gentle surface. When other signal lines are subsequently fabricated on the first signal line, the probability of other signal lines breaking when crossing the first signal line can be reduced, thereby improving the yield of the array substrate.

[0038] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A schematic diagram of a broken signal line structure on an array substrate in a related art, provided for an embodiment of this application;

[0041] Figure 2 A scanning electron microscope (SEM) image of a broken signal line on an array substrate in a related art, provided as an embodiment of this application;

[0042] Figure 3 A top view of an array substrate provided for an embodiment of this application;

[0043] Figure 4 Figures (a) and (b) are microscope images of over-etched signal lines in two related technologies provided in the embodiments of this application;

[0044] Figure 5 A schematic diagram of a cross-sectional structure of a first signal line provided for an embodiment of this application;

[0045] Figure 6 and Figure 7 Scanning electron microscope images of two first signal lines provided for embodiments of this application;

[0046] Figure 8 Etching speed analysis diagram of signal lines provided for embodiments of this application and signal lines in related technologies;

[0047] Figure 9 A top view of a partial area of ​​an array substrate provided for an embodiment of this application;

[0048] Figure 10 Analysis table of improvement in signal line breakage issues after changes to design parameters or manufacturing process parameters provided for embodiments of this application;

[0049] Figure 11 A top view of another array substrate provided for an embodiment of this application;

[0050] Figures 12-15 A schematic cross-sectional view of an array substrate with four different locations for the first through-hole provided in an embodiment of this application;

[0051] Figures 16-20 An intermediate structural diagram of the fabrication process of an array substrate with a first via at a first location provided for an embodiment of this application;

[0052] Figures 21-23 An intermediate structural diagram of the fabrication process of an array substrate with a second location for the first through-hole provided in an embodiment of this application;

[0053] Figures 24-26 An intermediate structural diagram of the array substrate in the fabrication process of the third setting position of the first through hole provided in the embodiments of this application;

[0054] Figures 27-29An intermediate structural diagram of the fabrication process of an array substrate with a fourth setting position of the first through hole provided in an embodiment of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0057] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0059] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0060] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of said value.

[0061] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0062] The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0063] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0064] In related technologies, the space requirements for wiring design on array substrates are becoming increasingly stringent. To improve design space, this is typically achieved by reducing trace width or the distance between traces. For example... Figure 1 As shown, the linewidth of a trace (e.g., an ITO electrode) is L (also called Line), and the distance between two adjacent traces is S (also called Space). The sum of L and S is the trace pitch. In practical applications, as the linewidth (L) of traces becomes smaller, the risk of trace breakage is lower when fabricating traces on relatively flat surfaces. However, for example... Figure 1 In the area where ITO bridges the gate, the risk of trace breakage is significantly increased when fabricating finer traces on a sloping surface. Combined with... Figure 2 The scanning electron microscope (SEM) image shown reveals that the ITO electrode fractures at the ramp location. Furthermore, due to limitations in wiring space and exposure machine resolution, it is impossible to compensate for this by widening the ITO electrode at the ramp location.

[0065] Therefore, a new design is urgently needed to improve the above problems.

[0066] The embodiments of this application provide the following technical solution: the first signal line in the array substrate has a relatively flat surface, thereby reducing the probability of other signal lines breaking when crossing the first signal line.

[0067] The array substrate provided in the embodiments of this application will be explained and described below with reference to the accompanying drawings.

[0068] Embodiments of this application provide an array substrate, the array substrate comprising:

[0069] Substrate 1;

[0070] A first conductive layer 2 is located on one side of the substrate 1. The first conductive layer 2 includes multiple first signal lines 21, combined with... Figure 3 and Figure 5 As shown, the first signal line 21 includes lines along a first direction (e.g., Figure 3 Extending in the X direction and along the second direction (e.g.) Figure 3 The first slope region X1, the flat region P, and the second slope region X2 are arranged sequentially in the Y direction; among them, Figure 5 for Figure 3 A schematic diagram of the cross-sectional structure of the first signal line 21 along the second direction (Y direction);

[0071] like Figure 5 As shown, the widths (D1 and D2) of the first ramp region X1 and the second ramp region X2 along the second direction (Y direction) are both greater than or equal to one-quarter of the width D of the first signal line 21 along the second direction (Y direction).

[0072] like Figure 5 As shown, the width of the first signal line 21 is D, the width of the left slope (first slope region X1) projected in the direction perpendicular to the substrate 1 is D1, the width of the right slope (second slope region X2) projected in the direction perpendicular to the substrate 1 is D2, and the width of the middle part (flat region P) is D3, where D = D1 + D2 + D3.

[0073] For example, D1 = D2 > ≥ one-quarter of D.

[0074] For example, the substrate 1 described above can be a rigid substrate, such as a glass substrate or a silicon substrate.

[0075] The material of the first conductive layer 2 can be a metal or a metal oxide.

[0076] For example, the material of the first conductive layer 2 is molybdenum (Mo).

[0077] In an exemplary embodiment, the first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular.

[0078] Since the widths (D1 and D2) of the first ramp region X1 and the second ramp region X2 along the second direction (Y direction) are both greater than or equal to one-quarter of the width D of the first signal line 21 along the second direction (Y direction), the sum of the widths D1 and D2 of the first ramp region X1 and the second ramp region X2 along the second direction (Y direction) is greater than or equal to half of the width D of the first signal line 21 along the second direction (Y direction). Thus, the ramp region in the first signal line 21 occupies at least half the width, resulting in a relatively gentle surface for the first signal line 21. This reduces the probability of other signal lines breaking when crossing the first signal line 21 during subsequent fabrication, thereby improving the yield of the array substrate.

[0079] In some array substrates provided in the embodiments of this application, such as Figure 5 As shown, the portion of the surface of the first signal line 21 on the side away from the substrate 1 located in the flat region P is approximately parallel to the substrate 1;

[0080] The portion of the surface of the first signal line 21 on the side away from the substrate 1 located in the first slope region X1 has a first included angle α with the substrate 1, and the portion of the surface of the first signal line 21 on the side away from the substrate 1 located in the second slope region X2 has a second included angle β with the substrate 1. The angle range of the first included angle α and the second included angle β is 5° to 50°.

[0081] For example, such as Figure 6 As shown, the first included angle α is 8.26° and the second included angle is 8.54°. The first included angle and the second included angle are approximately equal.

[0082] For example, such as Figure 7 As shown, the first included angle α is 19.41°, and the second included angle β is 18.01°.

[0083] It should be noted that, in this specification, taking into account the measurement and the tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), "approximately" means within an acceptable range of deviations for a particular value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of said value.

[0084] In practical applications, the first signal line 21 is fabricated using a chemical liquid wet etching method. For details, please refer to... Figure 6 or Figure 7As shown, a patterned photoresist (PR) is formed on the first conductive layer 2. Using the patterned photoresist as a mask, the first conductive layer 2 is etched. By adjusting the composition ratio of the etching solution of the first conductive layer 2 (Mo), the phosphoric acid content in the etching solution is reduced, that is, the viscosity of the etching solution is reduced, making it easier for the etching solution to drill laterally. This can result in a slope region with a wider size (e.g., D2 and D2), and at the same time, it is also easy to make the slope angle (profile) of the first signal line 21 very small.

[0085] The etching solution is formulated with the following proportions: 16% acetic acid, 2.5% nitric acid, 45-60% phosphoric acid, and the remainder consisting of additives and water.

[0086] In some array substrates provided in embodiments of this application, combined with Figure 6 The SEM image of the cross-section of the first signal line 21 shows that the width D1 of the first ramp region X1 along the second direction (Y direction) is approximately equal to the width D2 of the second ramp region X2 along the second direction (Y direction), and the first included angle α is approximately equal to the second included angle β.

[0087] Among them, Figure 6 and Figure 7 In the SEM image shown, the dimension marked 1 is the width of the patterned photoresist (PR resist), the dimension marked 2 is the width of the first signal line 21 obtained after actual etching, the dimension marked 3 is the first included angle α, and the dimension marked 4 is the second included angle β; the relevant values ​​are shown in the upper left corner of the SEM image.

[0088] exist Figure 6 In the process, the width of the patterned photoresist (PR resist) is 6.6777 μm, and the width of the first signal line 21 obtained after actual etching is 4.8874 μm, the first included angle α is 8.26°, and the second included angle β is 8.54°.

[0089] exist Figure 7 In the process, the width of the patterned photoresist (PR resist) is 4.8503 μm, and the width of the first signal line 21 obtained after actual etching is 3.5685 μm, the first included angle α is 19.41°, and the second included angle β is 18.01°.

[0090] Additionally, when applying an array substrate to a liquid crystal lens, such as Figure 3As shown, due to the large number of second signal lines 51 in display area A, the via density in the hub area (including B1 and B2) is much greater than the via density in signal introduction area B3. As a result, during the process of forming vias in the insulating material using dry etching, the plasma consumption rate in signal introduction area B3 is slower than that in the hub area, and the plasma density is larger than that in the hub area. This can easily lead to a faster etching rate of the insulating material in signal introduction area B3, resulting in over-etching of the conductive structure below the insulating material (such as the signal introduction line in the first conductive layer 2), or even complete etching of the metal material below the via.

[0091] Dry etching is a process that uses plasma gas to react with the material physically or chemically to remove the material.

[0092] like Figure 4 Figures (a) and (b) provide schematic diagrams of over-etching of the signal lead-in lines below the vias, showing that light is etched through certain areas. Furthermore, to achieve better optical performance, liquid crystal lenses typically use low-reflectivity metals, such as molybdenum (Mo), for the traces. However, Molybdenum (Mo) is more easily etched using dry etching, making it more prone to over-etching.

[0093] To improve the above problems, the inventors tested various solutions, such as... Figure 10 As shown, adjustments can be made by changing the design or process parameters in two directions: either the first signal line (Gate, first conductive layer) or the second signal line (ITO, second conductive layer). For the first signal line (Gate), adjustments can be made by either reducing the film thickness (from 2200nm to 800nm) or changing the profile (reducing the profile). Figure 10 As observed, both methods improve the over-etching problem, but modifying the profile (reducing the profile) shows a significantly better improvement. For the second signal line (ITO), the film thickness can be reduced by changing the Target Life (ITO THK, from 700nm to 400nm), the cleaning process of the mask for the second signal line 51 can be changed (the cleaning solution can be changed from water to TMAH), and the thickness of the PR adhesive on the second signal line 51 can be increased (from 1.5μm to 2.2μm). In summary, it can be seen that modifying the outer profile of the first signal line 21 provides the best improvement to the above-mentioned problems.

[0094] Based on this, embodiments of this application fabricate the entire via pattern on the slope of the first signal line 21 of the hub area; or, a portion of the via pattern is fabricated on the slope of the first signal line 21 of the hub area. This improves the aforementioned via problem, as explained in detail below.

[0095] In some array substrates provided in embodiments of this application, combined with Figure 3 , Figure 9 ,as well as Figures 12-15 As shown, the array substrate also includes:

[0096] The second conductive layer 5 is located on the side of the first conductive layer 2 away from the substrate 1. The second conductive layer 5 includes multiple second signal lines 51, and the second signal lines 51 overlap with the first signal lines 21.

[0097] The first insulating layer 3 is located between the first conductive layer 2 and the second conductive layer 5, and has a plurality of first through holes 31;

[0098] Among them, such as Figure 9 As shown, the second signal line 51 includes a first segment XD1 and a second segment XD2. The first segment XD1 extends in the same direction as the first signal line 21 (e.g., both extend along the X direction), and the second segment XD2 (e.g., extends along the Y direction) intersects with the extension direction of the first signal line 21. The first segment XD1 is electrically connected to the first signal line 21 through the first through hole 31.

[0099] like Figures 12-15 As shown, at least a portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 falls into the ramp area (first ramp area X1 or second ramp area X2).

[0100] In an exemplary embodiment, the material of the second conductive layer 5 includes a metal or a metal oxide.

[0101] For example, the material of the second conductive layer 5 includes metal oxides. In this specification, the material of the second conductive layer 5 is indium tin oxide (ITO) as an example.

[0102] Wherein, at least a portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 falls into the slope region (first slope region X1 or second slope region X2), including the following cases:

[0103] For example, such as Figure 14 and Figure 15 As shown, a portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 falls into the slope area (first slope area X1 or second slope area X2).

[0104] For example, such as Figure 12 and Figure 13 As shown, the entire area of ​​the orthographic projection of the first through hole 31 onto the first signal line 21 falls into the slope area (first slope area X1 or second slope area X2).

[0105] In the embodiments of this application, by setting at least a portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 to fall into the slope area, due to the leveling effect of the material of the first insulating layer 3, such as Figure 8 As shown, the thickness d1 of the first insulating layer 3 in the slope region (region B) is less than the thickness d of the first insulating layer 3 in region C in the related art. In this way, during the dry etching process, the plasma concentration consumption rate in the hub region where the first signal line 21 is located is reduced, thereby making it more consistent with the plasma concentration in the signal introduction region B3. This improves the problem of over-etching of the signal introduction region traces caused by the inconsistent via density and plasma concentration difference mentioned above.

[0106] Specifically, in combination Figure 8 As shown, assuming the length of the orthographic projection of region B of the first insulating layer 3 on the slope of the first signal line 21 in the hub region is L, and the length of the slope of the first insulating layer 3 on the signal introduction line 22 in the corresponding signal introduction region of the same length L is L1, and the thickness of the first insulating layer 1 in region B is d1; assuming the thickness of regions B and C along the direction perpendicular to the cross section is 1, and the thickness of the first insulating layer 3 in region C is d, it is easy to know that the thickness of the first insulating layer 3 at the non-slope position on the first signal line 21 in the hub region is also d; according to the PECVD film formation principle, for the same time period, the volume of the insulating layer in regions B and C is equal, that is: L1×d1×1=L×d×1. Assuming that the first included angle α of the first signal line 21 in the hub region is 30° at this time, it is easy to know that:

[0107]

[0108] Therefore, it can be seen that the thickness d1 of the first insulating layer 3 in region B is less than the thickness d of the first insulating layer 3 on the signal introduction line 22 in the signal introduction region B3. It can be seen that the first insulating layer 3 on the slope of the first signal line 21 in the hub area will be etched to the bottom faster. In addition, combined with the difference in via density in the two regions, the plasma concentration is balanced during the etching process, so that the etching rate in the two regions is consistent, which improves the problem of over-etching of the signal introduction area traces caused by the inconsistency of via density and the difference in plasma concentration mentioned above.

[0109] In some array substrates provided in the embodiments of this application, such as Figure 9 As shown, along the second direction (Y direction), the distance H1 between the center of the first through hole 31 and one side of the first line segment XD1 is not equal to the distance H2 between the center of the first through hole 31 and the other side of the first line segment XD1.

[0110] For example, such as Figure 9As shown, the first through hole 31 is located near the lower side of the first line segment XD1.

[0111] For example, the first through hole 31 can be located near the upper side of the first line segment XD1.

[0112] in, Figures 12-14 Four cross-sectional structural diagrams of array substrates are provided.

[0113] In some array substrates provided in the embodiments of this application, such as Figure 13 As shown, the orthographic projection of the first through hole 31 onto the first signal line 21 falls into the first ramp area X1.

[0114] In some array substrates provided in the embodiments of this application, such as Figure 15 As shown, a portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 falls into the first slope region X1, and another portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 falls into the flat region P.

[0115] In some array substrates provided in the embodiments of this application, such as Figure 12 As shown, the orthographic projection of the first through hole 31 onto the first signal line 21 falls into the second ramp area X2.

[0116] In some array substrates provided in the embodiments of this application, such as Figure 14 As shown, the orthographic projection of the first through hole 31 onto the first signal line 21 falls into the second slope region X2, and another part of the orthographic projection of the first through hole 31 onto the first signal line 21 falls into the flat region P.

[0117] In the array substrate provided in the embodiments of this application, by setting at least a portion of the orthographic projection of the first through-hole 31 onto the first signal line 21 to fall into the ramp region (first ramp region X1 or second ramp region X2), the leveling effect of the material of the first insulating layer 3 is achieved, such as Figure 8 As shown, the thickness d1 of the first insulating layer 3 in the slope region (region B) is less than the thickness d of the first insulating layer 3 in region C in the related art. In this way, during the dry etching process, the plasma concentration consumption rate in the hub region where the first signal line 21 is located is reduced, thereby making it more consistent with the plasma concentration in the signal introduction region B3. This improves the problem of over-etching of the signal introduction region traces caused by the inconsistent via density and plasma concentration difference mentioned above.

[0118] It should be noted that, in combination Figure 9 and Figure 12 As shown, the first through-hole 31 is positioned offset from the axis of the first signal line 21 by its orthogonal projection onto the first signal line 21, while the second through-hole 31 is still positioned on the axis of the signal input line 22. Wherein, Figure 12 for Figure 9 A schematic diagram of the cross-sectional structure along the AA' direction.

[0119] In some array substrates provided in the embodiments of this application, such as Figure 3 As shown, the multiple second signal lines 51 include multiple drive electrode line groups G, and the drive electrode line group G includes multiple drive electrode lines that do not transmit signals that are not completely the same.

[0120] The multiple first signal lines 21 include multiple parallel lines; the parallel lines are used to electrically connect the drive electrode lines with the same transmission signal in different drive electrode line groups G together.

[0121] For example, such as Figure 3 As shown, the drive electrode line group G includes eight drive electrode lines that transmit signals that are not completely identical, such as the first drive electrode line, the second drive electrode line, the third drive electrode line, the fourth drive electrode line, the fifth drive electrode line, the sixth drive electrode line, the seventh drive electrode line, and the eighth drive electrode line.

[0122] For example, a first type of parallel routing is used to electrically connect the first driving electrode lines in different driving electrode line groups G together; a second type of parallel routing is used to electrically connect the second driving electrode lines in different driving electrode line groups G together; a third type of parallel routing is used to electrically connect the third driving electrode lines in different driving electrode line groups G together; a fourth type of parallel routing is used to electrically connect the fourth driving electrode lines in different driving electrode line groups G together; a fifth type of parallel routing is used to electrically connect the fifth driving electrode lines in different driving electrode line groups G together; a sixth type of parallel routing is used to electrically connect the sixth driving electrode lines in different driving electrode line groups G together; a seventh type of parallel routing is used to electrically connect the seventh driving electrode lines in different driving electrode line groups G together; and an eighth type of parallel routing is used to electrically connect the eighth driving electrode lines in different driving electrode line groups G together. Each type of parallel routing may include a first parallel routing line disposed in a first busbar area B1 and a second parallel routing line disposed in a second busbar area B2.

[0123] In some array substrates provided in the embodiments of this application, such as Figure 3 As shown, the array substrate includes a display area A, a first hub area B1 and a second hub area B2 located on opposite sides of the display area A, and a signal introduction area B3 located on the side of the first hub area B1 away from the display area A.

[0124] The multiple parallel routing lines include the first parallel routing line and the second parallel routing line. The first hub area B1 is equipped with multiple first parallel routing lines, and the second hub area B2 is equipped with multiple second parallel routing lines.

[0125] Multiple drive electrode line groups G are provided in the display area A; multiple drive electrode lines extend from the display area A to the first hub area B1 and the second hub area B2 respectively, and are electrically connected to the first parallel line and the second parallel line respectively.

[0126] The number of first parallel lines (e.g., the first horizontal signal line 21 in the first hub area B1), the number of second parallel lines (e.g., the first horizontal signal line 21 in the second hub area B2), and the number of drive electrode lines in the same drive electrode line group G (e.g., the second vertical signal line 51 in the display area A) are equal.

[0127] In some array substrates provided in embodiments of this application, combined with Figure 3 and Figure 9 As shown, the signal introduction area B3 includes:

[0128] Multiple overlapping traces 52 located on the second conductive layer 5; such as Figure 3 As shown, multiple overlapping traces 52 extend from the signal introduction area B3 to the first hub area B1, and some of the overlapping traces 52 overlap with the orthographic projection of the first parallel trace (e.g., the first signal line 21 in the horizontal direction in the first hub area B1) on the substrate 1.

[0129] Multiple signal lead-in lines 22 are located on the first conductive layer 2; the first insulating layer 3 has multiple second through holes 32, and the overlapping wiring 52 is electrically connected to the signal lead-in lines 22 through the second through holes 32.

[0130] The number of multiple overlapping cables 52 is the same as the number of multiple first parallel cables (e.g., the first signal line 21 in the horizontal direction in the first hub area B1).

[0131] The following section, in conjunction with the fabrication process of the array substrate, explains how... Figures 12-15 The differences between the four array substrates.

[0132] by Figure 12 Taking the array substrate shown as an example, its fabrication process is illustrated:

[0133] Step 1, as follows Figure 16 As shown, a conductive pattern for the first conductive layer 2 is fabricated on substrate 1 through exposure, development, and wet etching. The first conductive layer 2 is typically made of molybdenum (Mo). The conductive pattern of the first conductive layer 2 includes a signal introduction line 22 in the signal introduction region B3 and a first signal line 21 (e.g., parallel wiring) in the hub region. The conductive pattern of the first conductive layer 2 is fabricated using the optimized etching solution described earlier. The first signal line 21 and the signal introduction line 22 in the first conductive layer 2 have the same cross-sectional structure, i.e., the signal introduction line 22 also has... Figure 5 The structure shown is a similar cross-section.

[0134] Step 2, as follows Figure 17 As shown, the first insulating layer 3 is prepared by PECVD. The material of the first insulating layer 3 includes inorganic materials, such as SiNx, SiO2, or SiNxO. y .

[0135] Step 3, as follows Figure 18 As shown, a photoresist film layer 4 (PR resist) is formed, and a via mask is used to expose and develop the photoresist film layer, forming vias 41 located in the first hub region B1 and vias 42 located in the signal introduction region B3 on the photoresist film layer 4. Specifically, during exposure using the via mask, the mask is moved along the... Figure 9 As shown, by moving a certain distance downward in the vertical direction, the via 41 of the hub area can be made on the slope to the right of the first signal line 21 of the hub area; and since the extension direction of the signal lead-in line 22 is originally in the vertical direction, the via 42 of the signal lead-in area B3 is still located in the middle position of the signal lead-in line 22.

[0136] Step 4, as follows Figure 19 As shown, using a dry etching method with the aforementioned photoresist pattern as a mask, via etching is performed to fabricate the second via 32 of the signal introduction region B3 and the first via 31 of the hub region on the first insulating layer 3. At this time, as... Figure 19 As shown, the via 31 of the hub area is made on the slope to the right of the first signal line 21 of the hub area, while the second via 32 of the signal introduction area B3 is still located in the middle of the signal introduction line 22 of the signal introduction area B3.

[0137] Step 5, as follows Figure 20 As shown, an indium tin oxide (ITO) thin film is formed by magnetron sputtering. After processes such as exposure, development, and etching, a film like the one shown is prepared. Figure 9 The second signal line 51 and the overlapping wiring 52 are shown in the diagram.

[0138] Step 6: Planarize the above-mentioned driving array substrate using organic layer 6 to obtain the following... Figure 12 The structure shown is such that the display area A completely covers the organic layer 6, and the area in the signal introduction area B3 used for bonding with external circuits is hollowed out for bonding external circuits. The main function of the organic layer 6 is to make the driving electric field of the liquid crystal lens driving panel more uniform; the thickness of the organic layer 6 ranges from 2.0 to 5.0 μm.

[0139] For example Figure 14 The structure of the array substrate shown is fabricated using the same process as described above. Figure 12 The fabrication process of the array substrate shown is similar, the main difference being in step 3, where the mask is placed along... Figure 9When the vertical direction shown in the figure moves a certain distance downwards, Figure 14 The structure shown moves the mask down by a distance less than [a certain amount]. Figure 12 The structure shown shifts the mask downwards by a certain distance, thus obtaining... Figure 24 , Figure 25 and Figure 26 The first via 31 is simultaneously set on the slope and the flat area to the right of the first signal line 21.

[0140] For example Figure 13 The structure of the array substrate shown is fabricated using the same process as described above. Figure 12 The fabrication process of the array substrate shown is similar, the main difference being in step 3, where the mask is placed along... Figure 9 As shown, moving a certain distance upwards in the vertical direction results in the following: Figure 21 , Figure 22 and Figure 23 The first via 31 is set on the slope to the left of the first signal line 21.

[0141] For example Figure 15 The structure of the array substrate shown is fabricated using the same process as described above. Figure 13 The fabrication process of the array substrate shown is similar, the main difference being in step 3, where the mask is placed along... Figure 9 When the vertical direction shown in the figure moves a certain distance downwards, Figure 15 The structure shown moves the mask down by a distance less than [a certain amount]. Figure 13 The structure shown shifts the mask downwards by a certain distance, thus obtaining... Figure 27 , Figure 28 and Figure 29 The first via 31 is simultaneously set on the slope and the flat area to the left of the first signal line 21.

[0142] It should be noted that the solutions mentioned above are all improvements made by adjusting the fabrication process without changing the existing photomask, which improves the over-etching problem and has a low cost.

[0143] The embodiments of this application provide a solution to improve the over-etching problem by changing the design of the photomask.

[0144] In this case, by changing the design of the mask, the first via 31 of the hub area can be directly fabricated in the slope area of ​​the first signal line 21. In this case, when the fabrication process involves step 3 mentioned above, it is not necessary to move the mask for exposure.

[0145] Alternatively, by changing the mask design, dummy vias can be added around the second via 32 in the signal introduction area B3, so that the via density in the signal introduction area B3 is comparable to the via density in the hub area.

[0146] In some array substrates provided in the embodiments of this application, such as Figure 11 As shown, the first insulating layer 3 also includes a plurality of dummy vias disposed in the signal introduction area B3.

[0147] It should be noted that the aforementioned dummy via is an isolated via (an opening in the first insulating layer) and has no electrical connection with other conductive structures.

[0148] It should be noted that a first insulating layer 3 is provided at the location of the aforementioned virtual via, and a second conductive layer 5 is also provided covering the virtual via to better mimic the structure of the second via 32.

[0149] In some array substrates provided in embodiments of this application, the total area of ​​the plurality of dummy vias and the plurality of second vias 32 in the signal introduction area B3 is approximately the same as the area of ​​the first via 31.

[0150] In some embodiments, when the dimensions of the dummy via, the second via 32, and the first via 31 are the same, the total density of the dummy via and the second via 32 located in the signal introduction area B3 can be set to be comparable to the total density of the first via 31 in the hub area.

[0151] The term "equivalent" as used above includes, but is not limited to, being equal, and may have a fluctuation of 3% to 5% on the basis of equality.

[0152] It should be noted that the array substrate provided in the embodiments of this application may also include other structures and components. This specification only describes the structures and designs related to the inventive points. Other structures and components that the array substrate may also include can be found in related art.

[0153] Embodiments of this application provide a liquid crystal lens, including an array substrate as described in any of the preceding descriptions, an opposing substrate, and a liquid crystal layer located between the array substrate and the opposing substrate.

[0154] Liquid crystal lenses regulate the alignment of liquid crystal molecules by applying an electric field or changing other external conditions, thereby altering their refractive index and phase for incident light, thus controlling the transmission of light. The basic structure of a liquid crystal lens consists of a face-down substrate, a liquid crystal layer, and an array substrate. Transparent electrodes (such as the second signal line 51 mentioned earlier) are disposed on both the face-down substrate and the array substrate, and a driving circuit is also disposed on the array substrate. The transparent electrodes are used to apply the electric field, the liquid crystal layer is used to accommodate the liquid crystal molecules, and the driving circuit is used to control the magnitude and direction of the electric field.

[0155] It should be noted that the liquid crystal lens also includes other components and structures. This description focuses only on the structures related to the invention. Other components and structures included in the liquid crystal lens can be found in relevant technologies and will not be elaborated here.

[0156] Those skilled in the art will understand that the liquid crystal lens provided in this application has the advantages of the array substrate of any of the above embodiments.

[0157] An embodiment of this application provides a display device, including a display panel and a liquid crystal lens as described above; the liquid crystal lens is disposed on the light-emitting side of the display panel.

[0158] For example, the above-mentioned display device can be a 3D display device, such as a glasses-free 3D display device.

[0159] The display device provided in the embodiments of this application has the characteristics of high manufacturing yield, stable performance, and good product quality.

[0160] The display device provided in this application can be any product or component with display function, such as a display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc.

[0161] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A first conductive layer located on one side of the substrate, the first conductive layer including a plurality of first signal lines, the first signal lines including a first slope region, a flat region and a second slope region extending along a first direction and arranged sequentially along a second direction; Wherein, the width of the first ramp area and the second ramp area along the second direction is greater than or equal to one-quarter of the width of the first signal line along the second direction; The array substrate further includes: A second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes multiple second signal lines, which overlap with the first signal lines. A first insulating layer is located between the first conductive layer and the second conductive layer and has a plurality of first through holes; The second signal line includes a first segment and a second segment. The first segment extends in the same direction as the first signal line, and the second segment intersects the extension direction of the first signal line. The first segment is electrically connected to the first signal line through the first through hole. At least a portion of the orthographic projection of the first through hole onto the first signal line falls into the slope area.

2. The array substrate according to claim 1, characterized in that, The portion of the surface of the first signal line on the side away from the substrate located in the flat region is substantially parallel to the substrate; The portion of the surface of the first signal line on the side away from the substrate located in the first slope region has a first angle with the substrate, and the portion of the surface of the first signal line on the side away from the substrate located in the second slope region has a second angle with the substrate. The angles of the first angle and the second angle range from 5° to 50°.

3. The array substrate according to claim 2, characterized in that, The relative deviation between the width of the first slope area along the second direction and the width of the second slope area along the second direction is no greater than 5%, and the relative deviation between the angles of the first included angle and the second included angle is no greater than 5%.

4. The array substrate according to claim 1, characterized in that, Along the second direction, the distance between the center of the first through hole and one side of the first line segment is not equal to the distance between the center of the first through hole and the other side of the first line segment.

5. The array substrate according to claim 4, characterized in that, The orthographic projection of the first through hole onto the first signal line falls into the first slope area.

6. The array substrate according to claim 4, characterized in that, A portion of the orthographic projection of the first through-hole onto the first signal line falls into the first slope region, and another portion of the orthographic projection of the first through-hole onto the first signal line falls into the flat region.

7. The array substrate according to claim 4, characterized in that, The orthographic projection of the first through hole onto the first signal line falls into the second slope area.

8. The array substrate according to claim 4, characterized in that, A portion of the orthographic projection of the first through-hole onto the first signal line falls into the second slope region, and another portion of the orthographic projection of the first through-hole onto the first signal line falls into the flat region.

9. The array substrate according to any one of claims 4 to 8, characterized in that, The plurality of second signal lines include a plurality of drive electrode line groups, and the drive electrode line groups include a plurality of drive electrode lines that transmit signals that are not entirely the same; The plurality of first signal lines include a plurality of parallel traces; the parallel traces are used to electrically connect the drive electrode lines with the same transmission signal in different drive electrode line groups together.

10. The array substrate according to claim 9, characterized in that, The array substrate includes a display area, a first hub area and a second hub area located on opposite sides of the display area, and a signal introduction area located on the side of the first hub area away from the display area. The multiple parallel routing lines include a first parallel routing line and a second parallel routing line. The first hub area is provided with multiple first parallel routing lines, and the second hub area is provided with multiple second parallel routing lines. The display area is provided with a plurality of driving electrode line groups; the plurality of driving electrode lines extend from the display area to the first hub area and the second hub area respectively, and are electrically connected to the first parallel line and the second parallel line respectively; The number of the first parallel traces, the number of the second parallel traces, and the number of the drive electrode lines in the same drive electrode line group are equal.

11. The array substrate according to claim 10, characterized in that, The signal introduction area includes: Multiple overlapping traces are located on the second conductive layer; the multiple overlapping traces extend from the signal introduction area to the first hub area, and a portion of the overlapping traces overlap with the orthographic projection of the first parallel traces on the substrate; Multiple signal lead-in lines are located on the first conductive layer; the first insulating layer has multiple second through holes, and the overlapping traces are electrically connected to the signal lead-in lines through the second through holes; The number of the multiple overlapping wirings is the same as the number of the multiple first parallel wirings.

12. The array substrate according to claim 11, characterized in that, The first insulating layer also includes a plurality of virtual vias disposed in the signal introduction area.

13. The array substrate according to claim 12, characterized in that, The relative deviation between the total area of ​​the plurality of virtual vias and the plurality of second vias in the signal introduction area and the area of ​​the first via is no greater than 5%.

14. A liquid crystal lens, characterized in that, The array substrate as described in any one of claims 1 to 13 further includes a counter substrate and a liquid crystal layer located between the array substrate and the counter substrate.

15. A display device, characterized in that, It includes a display panel and a liquid crystal lens as described in claim 14; the liquid crystal lens is disposed on the light-emitting side of the display panel.

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