Control methods for memory systems, memory systems and electronic devices

Abstract

This application provides a control method for a memory system, a memory system, and an electronic device. When hard decoding of hard data read from the memory fails, the control method can read soft data from the memory and perform soft decoding on the obtained soft data using the LLR value in an initial lookup table. If soft decoding fails, the LLR value in the initial lookup table is shifted, and soft decoding is performed based on the LLR value after each shift, thereby improving the efficiency of soft decoding.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a control method for a memory system, a memory system, and an electronic device. Background Technology

[0002] Memory and its systems are storage devices used to preserve information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production costs, suitable erasure speed, and retention characteristics. To improve the error correction capability of memory, a combination of hard decoding and soft decoding is typically used to decode the data read from the memory. However, current soft decoding methods generally suffer from low decoding efficiency. Summary of the Invention

[0003] The embodiments of this application provide a control method for a memory system, a memory system, and an electronic device, which aim to solve the problem of low decoding efficiency caused by the high latency of the current memory software decoding process.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] Firstly, a control method for a memory system is provided. During execution, this method first acquires first soft data corresponding to hard data read from the memory and a first lookup table. The first lookup table includes a first log-likelihood ratio determined based on a first reference read voltage of the memory. Then, a first soft decoding operation is performed based on the first log-likelihood ratio and the first soft data. Finally, if the first soft decoding operation fails, the first log-likelihood ratio is shifted at least once, and a second soft decoding operation is performed based on the log-likelihood ratio after each shift and the first soft data. Through this method, when the first soft decoding operation fails, the log-likelihood ratio can be directly shifted before soft decoding, instead of changing the lookup table or offsetting the reference read voltage before multiple soft decoding operations. This reduces the number of soft decoding iterations, lowers the soft decoding latency, and improves the efficiency of soft decoding.

[0006] In one possible implementation, when performing at least one shift on the first log-likelihood ratio and executing the second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, the first log-likelihood ratio can be forward-shifted at least once, and soft decoding can be performed based on the log-likelihood ratio after each shift and the first soft bit data. This method allows for multiple forward shifts based on the first log-likelihood ratio, thereby improving decoding efficiency.

[0007] In one possible implementation, the first log-likelihood ratio is shifted positively at least once. If software decoding fails based on the shifted log-likelihood ratio and the first soft-bit data, the first log-likelihood ratio can be shifted negatively at least once, and software decoding can be performed based on the shifted log-likelihood ratio and the first soft-bit data. By using this method, when positive shifting of the first log-likelihood ratio fails to decode successfully, negative shifting is chosen, further improving the efficiency of successful decoding.

[0008] In one possible implementation, when performing at least one shift on the first log-likelihood ratio and executing the second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, the first log-likelihood ratio can also be negatively shifted at least once, and soft decoding can be performed based on the log-likelihood ratio after each shift and the first soft bit data. By using this method, multiple negative shifts can be performed on the first log-likelihood ratio, thereby improving the efficiency of successful decoding.

[0009] In one possible implementation, the first log-likelihood ratio is negatively shifted at least once. If software decoding fails based on the shifted log-likelihood ratio and the first soft-bit data, the first log-likelihood ratio can be positively shifted at least once, and software decoding can be performed based on the shifted log-likelihood ratio and the first soft-bit data. By using this method, when negative shifting of the first log-likelihood ratio fails to decode successfully, a positive shift is chosen, further improving the efficiency of successful decoding.

[0010] In one possible implementation, when performing at least one shift on the first log-likelihood ratio and executing the second soft decoding operation based on the log-likelihood ratio after each shift and the first soft data, the first log-likelihood ratio can also be cross-shifted, and soft decoding can be performed based on the log-likelihood ratio after each shift and the first soft data. By using cross-shifting, the latency of soft decoding can be further reduced, and the efficiency of successful soft decoding can be improved.

[0011] In one possible implementation, when the first log-likelihood ratio is shifted at least once, the value of each shift is the same.

[0012] In one possible implementation, when the first log-likelihood ratio is shifted at least once, the value of each shift is different.

[0013] In one possible implementation, after stopping the second soft decoding operation when the number of shifts of the first log-likelihood ratio reaches a preset value, the method further includes: obtaining a second lookup table; the second lookup table includes a second log-likelihood ratio determined based on a second reference read voltage of the memory. Then, the first reference read voltage is shifted to the second reference read voltage. Finally, the second soft bit data of the memory is read according to the second reference read voltage, and a third soft decoding operation is performed according to the second soft bit data and the second log-likelihood ratio.

[0014] By using the above method, when software decoding fails using the first lookup table, a second lookup table can be used instead, and then software decoding can be performed by reading the voltage with an offset reference, thereby improving the efficiency of successful decoding.

[0015] In one possible implementation, after stopping the second soft decoding operation when the number of shifts of the first log-likelihood ratio reaches a preset value, the method further includes: obtaining a third lookup table, the third lookup table including a third log-likelihood ratio determined based on a third reference read voltage; and performing a fourth soft decoding operation based on the third log-likelihood ratio and the first soft bit data.

[0016] By using the above method, when software decoding fails using the first lookup table, a third lookup table can be used instead, and software decoding can be performed in the same way as the first lookup table, thereby improving the efficiency of successful decoding.

[0017] In one possible implementation, the step of obtaining the first soft data corresponding to the hard data read from the memory and the first lookup table is performed after the hard decoding operation of the hard data fails.

[0018] In a second aspect, a computer-readable storage medium is provided that stores computer program instructions. When executed by a processor, the computer program instructions implement the method in any of the possible implementations of the first aspect described above.

[0019] Thirdly, a memory system is provided. This memory system includes one or more memories; a memory controller coupled to the memories and configured to control the memories; the memory controller includes decoding circuitry. The decoding circuitry is configured to implement the method of any possible implementation of the first aspect described above.

[0020] Fourthly, a memory controller is provided, comprising a bus and decoding circuitry coupled to the bus. The decoding circuitry is configured to implement the method of any possible implementation of the first aspect described above.

[0021] Fifthly, an electronic device is provided, comprising an interface circuit and a memory system coupled to the interface circuit.

[0022] Understandably, the beneficial effects that can be achieved by the second to fifth aspects of this application can be referred to the beneficial effects of the first aspect above, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 The following diagram illustrates the structure of a memory provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of a memory card provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the structure of a solid-state drive provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the structure of a memory controller provided in an embodiment of this application;

[0029] Figure 6 This is a schematic diagram illustrating a method for acquiring soft bit data and hard bit data, provided in an embodiment of this application.

[0030] Figure 7 A schematic diagram illustrating the confidence interval distribution when reading soft bit data, provided in an embodiment of this application;

[0031] Figure 8 A trend chart of LLR value changes in a confidence interval is provided for an embodiment of this application;

[0032] Figure 9 This is a schematic flowchart of a control method for a memory system provided in an embodiment of this application;

[0033] Figure 10 This application provides a schematic diagram of an LLR value shifting process.

[0034] Figure 11 A schematic diagram illustrating another LLR value shifting process provided in this application embodiment;

[0035] Figure 12 This application provides a schematic diagram of a process following a second software decoding failure.

[0036] Figure 13 This is a schematic diagram illustrating another process after a second software decoding failure, provided in an embodiment of this application.

[0037] Figure 14 This is a schematic diagram of a software decoding circuit provided in an embodiment of this application;

[0038] Figure 15 This is a schematic diagram of a decoding circuit provided in an embodiment of this application;

[0039] Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0040] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0042] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0043] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the terms "coupled" or "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" and "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0044] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0045] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0047] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0048] like Figure 1 As shown, many electronic devices incorporate a memory system 100. The memory system 100 includes one or more memories 120 and a memory controller 110.

[0049] In some implementations, the memory controller 110 is designed to operate in low duty cycle environments, such as secure digital memory cards (SD cards), compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0050] In some implementations, the memory controller 110 is designed to operate in a high duty cycle environment in a solid-state disk (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0051] The memory controller 110 can be configured to control the operation of the memory 120, such as read, erase, and program operations. The memory controller 110 can also be configured to manage various functions relating to data stored or to be stored in the memory 120, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 110 is also configured to process error correcting codes (ECCs) relating to data read from or written to the memory 120.

[0052] The memory controller 110 can also perform any other suitable function, such as formatting the memory 120. The memory controller 110 can communicate with external devices (e.g., the host 110) according to a specific communication protocol. For example, the memory controller 110 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0053] The memory controller 110 and one or more memories 120 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package).

[0054] In such Figure 2 In one example shown, the memory controller 110 and a single memory 120 can be integrated into the memory card 200. The memory card 200 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage card (UFS), etc. The memory card 200 may also include a connection between the memory card 200 and a host computer (e.g., Figure 1 The memory card connector 210 is coupled to the host 110 in the host.

[0055] In such Figure 3 In another example shown, the memory controller 110 and multiple memories 120 may be integrated into a solid-state drive (SSD) 300. The SSD 300 may also include a connection between the SSD 300 and a host computer (e.g., Figure 1 The solid-state drive connector 310 is coupled to the host 110. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 300 is greater than the storage capacity and / or operating speed of the memory card 200.

[0056] like Figure 4 As shown, the memory 120 includes a memory array 128 and peripheral circuitry. The peripheral circuitry includes terminal blocks 121, control logic circuitry 122, registers 123, a voltage generator 124, row drivers 125, column drivers 126, and page buffers 127. Terminal blocks 121 are primarily used to receive read and program commands from the memory controller 300, and to send read data back to the memory controller 300. Control logic circuitry 122 is primarily used to control the row drivers 125, column drivers 126, and page buffers 127 to perform read, program, erase, and verification operations based on commands sent by the memory controller 110. Registers 123 can store control commands sent by the memory controller 110.

[0057] In one example, such as Figure 5As shown, the memory controller 110 includes a bus 113; and a host interface 115, a memory interface 116, a processor 111, internal memory 112, and an error correction and verification (ECC) circuit 114 coupled to the bus 113. The host interface 115 is used to connect to a host computer; the memory interface 116 is used to connect to one or more memories. The processor 111 can receive request instructions sent by the host computer via the bus 113, and send control instructions to the memories connected to the memory interface 116 according to the request instructions, thereby controlling the memories to perform read / program operations. The internal memory 112 may include read-only memory (ROM) and random access memory (RAM). The processor 111 may be a microcontroller unit (MCU). The ROM can store fixed instructions that the processor needs to execute, such as the address of the initial log likelihood ratio (LLR) lookup table and the address of the fixed program to be run after the MCU starts. The RAM can store data that the MCU interacts with the host computer and the memories. The error correction and verification circuit 114 includes a software decoding circuit 1142 and a hardware decoding circuit 1141. The hardware decoding circuit 1141 performs hardware decoding on hard-bit data read from memory. The software decoding circuit 1142 performs software decoding on soft-bit data read from memory. Hardware decoding can be performed using low-density parity check (LDPC) codes, etc. For example, hardware decoding may include parity checking operations to generate a syndrome, and bit-flipping algorithms, min-sum algorithms, and / or sum-product algorithms to determine erroneous bits, etc. Software decoding can also be performed using low-density parity check (LDPC) codes, etc. For example, software decoding may further include operations involving information such as log likelihood ratio (LLR) values. Furthermore, software decoding may include decoding operations that are at least partly the same as or different from those in hardware decoding.

[0058] Next, refer to Figure 6 This section provides specific examples of hard bit (HB) and soft bit (SB) data. Figure 6 This is a schematic diagram showing the distribution of memory cells and the relationship between hard-bit data and soft-bit data, representing the threshold voltages of the "B" and "A" programming states.

[0059] like Figure 6 As shown, due to read disturbances or data retention, the width of the threshold voltage distribution in each programming state sometimes expands, and the lower part of adjacent threshold voltage distributions overlaps with each other. Figure 6 (The slanted area). In such a case, if a read operation is performed, the memory cell corresponding to the overlapping area at the lower end is more likely to become a invalid bit. More specifically, for example, at a read voltage V... A When performing a read operation corresponding to the "B" programming state, the read voltage V is... A The above threshold voltage for the "A" programmed state memory cell and the memory cell with a read voltage less than V A The memory cell in the "B" programmed state with the threshold voltage becomes a faulty bit. If the number of faulty bits exceeds the number of bits that the ECC circuit can correct for errors, then it becomes difficult to read the data correctly.

[0060] Therefore, in this embodiment, during a read operation in one programming state, two read voltages are set, located in the region where the lower ends of the threshold voltage distribution overlap. More specifically, for the "B" programming state, two read voltages V are set. AL and V AH Read voltage V AL Less than the reading voltage V A The voltage. Read the voltage V. AH For a voltage higher than the reading voltage V A The voltage. The area where the "A" programming state and the "B" programming state overlap is located at the read voltage V. AL With reading voltage V AH Between. In addition, read the voltage V. AL With reading voltage V A The magnitude of the voltage difference can be compared with the reading voltage V. A With reading voltage V AH The voltage difference can be the same or different.

[0061] For example, when using the reading voltage V AL During the read operation, the threshold voltage is less than the read voltage V. AL The data in the storage cell is "1". The threshold voltage is the read voltage V. AL The data in the above storage units is "0".

[0062] Additionally, when using the reading voltage V AH During the read operation, the threshold voltage is less than the read voltage V. AH The data in the storage cell is "1". The threshold voltage is the read voltage V. AH The data in the above storage units is "0".

[0063] In this embodiment, among the two read voltages corresponding to one programming state, the read data based on the lower read voltage is defined as hard bit data.

[0064] Soft bits are calculated through logical operations on two read data (e.g., XOR). Figure 6 In the example, the threshold voltage is less than the read voltage V. AL The soft-bit data in the storage cell is "0". The threshold voltage is the read voltage V. AL Above and below the reading voltage V AH The soft bit data of the storage cell is "1". The threshold voltage is the read voltage V. AH The soft data in the above memory cells is "0". Furthermore, soft data operations are not limited to XOR operations. Soft data operations can be set based on the definition of soft data. For example, when the threshold voltage is the read voltage V... AL Above and below the reading voltage V AH When the soft bit data of the storage cell is defined as "0", the soft bit data can also be calculated using the XNOR (exclusive NOT) operation.

[0065] Therefore, soft bit data indicates whether the threshold voltage is located near the boundary between two adjacent threshold voltage distributions. By referring to hard bit data and soft bit data, information can be obtained as to whether the threshold voltage is located in the lower part of the threshold voltage distribution in the object's programming state.

[0066] Furthermore, if software decoding fails during the process, the typical solutions mainly include the following three types:

[0067] 1) Based on the reference read voltage, perform more read offset to obtain more soft bit data for decoding.

[0068] 2) Offset the reference reading voltage, and then use the offset reference level as the basis to obtain soft bit data for soft decoding.

[0069] 3) Set up lookup tables for multiple scenarios. If software decoding fails when using a certain lookup table, use other LLR lookup tables for software decoding.

[0070] However, adjusting the software decoding strategy in the above way will increase the number of decoding processes, thereby increasing the latency of software decoding and reducing its efficiency.

[0071] like Figure 7As shown, when reading soft bit data from the overlapping area of ​​two adjacent programming states in a memory cell, the reference read voltage RV can be offset multiple times with positive and negative voltages to obtain multiple soft bit data. For example, taking eight offset voltages (±0.07V, ±0.14V, ±0.21V, and ±0.28V) as an example, when reading soft bit data using these eight offset voltages, the overlapping area can be divided into eight confidence intervals (Z1 to Z8). Table 1 shows the changes in the LLR values ​​of the above eight confidence intervals when reading soft bit data with four offset voltages (±0.07V and ±0.14V). When the LLR value is positive, the larger the value, the greater the probability of the data being 0. When the LLR value is negative, the smaller the value, the greater the probability of the data being 1.

[0072] Table 1

[0073] RV-0.14 63 63 57 39 23 10 -8 -59 RV-0.07 63 57 39 23 10 -8 -26 -63 RV 63 39 23 10 -8 -26 -49 -63 RV+0.07 63 23 10 -8 -26 -49 -53 -63 RV+0.14 54 10 -8 -26 -49 -53 -63 -63

[0074] As shown in Table 1, the LLR values ​​in the confidence intervals Z2-Z7 change when reading soft-bit data with four offset voltages, including ±0.07V and ±0.14V. To more intuitively illustrate the trend of LLR value changes, a trend graph of the LLR values ​​for each confidence interval can be plotted based on Table 1. The trend graph of LLR values ​​is shown below. Figure 8 As shown. From Figure 8 It can be seen that there is a very good linear relationship between the LLR values ​​in the confidence interval Z2-Z7 and the positive and negative offset voltages when reading soft-bit data. Therefore, it is feasible to perform soft decoding by shifting the LLR values ​​based on this linear relationship.

[0075] Therefore, in order to solve the above problems, such as Figure 9 As shown in the figure, this application provides a control method for a memory system, which can be executed by a memory controller. The specific implementation process is as follows.

[0076] S901. Read hard-bit data from memory and perform hard decoding operation.

[0077] For example, the memory controller can send control commands to the control logic circuitry in the memory to instruct the control logic circuitry to read the corresponding programmed hard data from the memory cell according to a first reference read voltage. The first reference read voltage can be the optimal read voltage for the memory (e.g., NAND flash memory) under certain scenarios. This optimal read voltage can be obtained by testing the memory device under a set scenario. The set scenario can be set according to the actual usage environment of the memory. For example, the set scenario can include environmental factors of the memory and parameters of the memory itself, such as ambient temperature, ambient humidity, the memory's power supply voltage, and the number of erase / write cycles. In the above implementation process, if the hard decoding operation successfully obtains the decoded data, the decoded data is output and decoding stops; otherwise, execution continues in step S902.

[0078] S902. Repeatedly read hard data multiple times and perform hard decoding operation on each read hard data.

[0079] During the execution of the above method, if the first hard decoding fails, the memory controller can continue to send control commands to the control logic circuit in the memory to repeatedly read the hard bit data of the corresponding programmed state in the memory cell. The control logic circuit can use the same reference read voltage for repeated readings, or it can use reference read voltages from different scenarios; this application embodiment does not impose specific limitations on this.

[0080] In the above implementation process, if the hardware decoding operation successfully obtains the decoded data, the decoded data is output and decoding stops; otherwise, S903 continues to be executed.

[0081] S903. Obtain the first soft data and the first lookup table corresponding to the hard data read from the memory.

[0082] The first lookup table includes a first log-likelihood ratio determined based on a first reference read voltage of the memory. The user can select the optimal read voltage for certain scenarios as the first reference read voltage, and then perform testing and calculation to obtain the first log-likelihood ratio. The first soft bit data can be read by applying one or more positive and negative voltage offsets to the first reference read voltage. The first reference read voltage and the offset voltage values ​​for each offset can be set according to actual scenario requirements; this embodiment does not impose specific limitations on this.

[0083] For example, after a hard decoding operation fails, the memory controller can send a control command to the logic control circuitry within the memory to instruct the control logic circuitry to read the first soft bit data in the memory cell.

[0084] In the above implementation, the first lookup table can be stored in the internal memory of the memory controller or in a memory coupled to the memory controller. When the first lookup table is stored in the internal memory of the memory controller, it can be stored in ROM. If the memory controller fails to perform a hardware decoding operation, it can read the first lookup table from the ROM. When the first lookup table is stored in a memory coupled to the memory controller, the address information of the first lookup table can be stored in the ROM so that the first lookup table can be read from the corresponding address in the memory during a software decoding operation.

[0085] S904. Perform a first soft decoding operation based on the first log-likelihood ratio and the first soft bit data.

[0086] For example, after the memory controller acquires the first soft bit data, it can perform soft decoding on the first soft bit data based on the first log-likelihood ratio using a soft decoding circuit (which may include an LDPC decoder). If decoding is successful, the decoded data is output. Otherwise, execution continues to S905. The first soft bit data may include soft bit data read after one or more positive and negative offsets of the first reference read voltage. Correspondingly, the first soft decoding operation includes at least one soft decoding operation, i.e., each soft bit data corresponds to one soft decoding operation. Furthermore, the process of performing soft decoding based on the log-likelihood ratio in the above implementation is a process well-known to those skilled in the art, and will not be described in detail here.

[0087] S905. When it is determined that the first soft decoding operation fails, perform at least one shift on the first log-likelihood ratio, and perform a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data.

[0088] In one possible implementation, if the first soft decoding operation fails, the soft decoding circuit within the memory controller can perform at least one shift on the first log-likelihood ratio and perform a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data. The second soft decoding operation includes at least one soft decoding operation, meaning that soft decoding is performed based on the shifted log-likelihood ratio and the first soft bit data after each shift of the first log-likelihood ratio.

[0089] For example, the first log-likelihood ratio can be shifted positively at least once, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. If decoding still fails, the first log-likelihood ratio can be shifted negatively at least once, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. The specific execution process is as follows: Figure 10 As shown.

[0090] S1001. The first software decoding operation has failed.

[0091] If the software decoding fails to obtain the correct data based on the first log-likelihood ratio and the first soft bit data, it indicates that the first software decoding operation has failed.

[0092] S1002. Shift the first log-likelihood ratio positively.

[0093] In one example, as shown in Table 2, assuming the overlapping region of two adjacent programmed states in a certain memory cell is divided into multiple confidence intervals (Z1, Z2, Z3, ...), and the initial LLR values ​​corresponding to each confidence interval are (a, b, c, ...), then when the first log-likelihood ratio is positively shifted, the value of each positive shift can be the same (i.e., the value of each shift is a fixed value). In Table 2, m represents the value of the shift. This value can be set according to actual needs, and this embodiment does not impose specific limitations on it.

[0094] Table 2

[0095] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift a+m b+m c+m ... Second shift a+2m b+2m c+2m ... ... ... ... ... ...

[0096] In another example, as shown in Table 3, when the first log-likelihood ratio is positively shifted, the shift value can be different each time (i.e., the shift value is not fixed). In Table 3, m and n represent two different numerical values. These two values ​​can be set according to actual needs, and this application embodiment does not impose specific limitations on them.

[0097] Table 3

[0098] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift a+m b+m c+m ... Second shift a+m+n b+m+n c+m+n ... ... ... ... ... ...

[0099] S1003. Perform soft decoding based on the shifted log-likelihood ratio and the first soft bit data.

[0100] Each shift of the log-likelihood ratio allows for one soft decoding operation with the first soft bit data. If decoding is successful, the decoded data is output. Otherwise, execution continues to S1004.

[0101] S1004. Determine whether the number of positive shifts of the first log-likelihood ratio has reached the set threshold.

[0102] If the number of positive shifts of the first log-likelihood ratio reaches a set threshold, then S1005 to S1007 are executed. If the number of positive shifts of the first log-likelihood ratio does not reach the set threshold, then S1002 to S1003 are executed.

[0103] S1005. Negatively shift the first log-likelihood ratio.

[0104] In one example, as shown in Table 4, when the first log-likelihood ratio is positively shifted, the shift value can be the same each time (i.e., the shift value is fixed each time). In Table 4, m represents the value of each positive shift. This value can be set according to actual needs, and this embodiment does not impose specific limitations on it.

[0105] Table 4

[0106] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift am bm cm ... Second shift a-2m b-2m c-2m ... ... ... ... ... ...

[0107] In another example, as shown in Table 5, when negatively shifting the first log-likelihood ratio, the value of each positive shift can be different (i.e., the value of each shift is not fixed). In Table 5, m and n represent two different numerical values. These two values ​​can be set according to actual needs, and this application embodiment does not impose specific limitations on them.

[0108] Table 5

[0109] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift am bm cm ... Second shift amn bmn cmn ... ... ... ... ... ...

[0110] S1006. Perform soft decoding based on the shifted log-likelihood ratio and the first soft bit data.

[0111] Each shift of the log-likelihood ratio allows for one soft decoding operation with the first soft bit data. If decoding is successful, the decoded data is output. Otherwise, execution continues to step S1007.

[0112] S1007. Determine whether the number of negative shifts of the first log-likelihood ratio has reached the set threshold.

[0113] If the number of positive shifts of the first log-likelihood ratio reaches a set threshold, the second soft decoding operation ends. If the number of positive shifts of the first log-likelihood ratio does not reach the set threshold, S1005 to S1006 are executed.

[0114] In another possible implementation, the first log-likelihood ratio can be negatively shifted at least once, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. If decoding still fails, the first log-likelihood ratio is positively shifted at least once, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. The specific execution process is as follows: Figure 11 As shown.

[0115] S1101. The first software decoding operation has failed.

[0116] If the software decoding fails to obtain the correct data based on the first log-likelihood ratio and the first soft bit data, it indicates that the first software decoding operation has failed.

[0117] S1102. Negatively shift the first log-likelihood ratio.

[0118] The first log-likelihood ratio can be negatively shifted by referring to Table 4 or Table 5, which will not be elaborated here in the embodiments of this application.

[0119] S1103. Perform soft decoding based on the shifted log-likelihood ratio and the first soft bit data.

[0120] Each shift of the log-likelihood ratio allows for one soft decoding operation with the first soft bit data. If decoding is successful, the decoded data is output. Otherwise, execution continues to step S1104.

[0121] S1104. Determine whether the number of negative shifts of the first log-likelihood ratio has reached the set threshold.

[0122] If the number of negative shifts of the first log-likelihood ratio reaches a set threshold, then S1105 to S1107 are executed. If the number of negative shifts of the first log-likelihood ratio does not reach the set threshold, then S1102 to S1103 are executed.

[0123] S1105. Shift the first log-likelihood ratio positively.

[0124] The first log-likelihood ratio can be positively shifted by referring to Table 2 or Table 3, which will not be elaborated here in the embodiments of this application.

[0125] S1106. Perform soft decoding based on the shifted log-likelihood ratio and the first soft bit data.

[0126] Each shift of the log-likelihood ratio allows for one soft decoding operation with the first soft bit data. If decoding is successful, the decoded data is output. Otherwise, execution continues to step S1107.

[0127] S1107. Determine whether the number of negative shifts of the first log-likelihood ratio has reached the set threshold.

[0128] If the number of positive shifts of the first log-likelihood ratio reaches a set threshold, the second soft decoding operation ends. If the number of positive shifts of the first log-likelihood ratio does not reach the set threshold, then S1105 to S1106 continue to be executed.

[0129] In another possible implementation, the first log-likelihood ratio can be cross-shifted, and soft decoding can be performed based on the log-likelihood ratio after each shift and the first soft bit data. Here, cross-shifting means that positive and negative shifts are performed alternately, but the number of positive or negative shifts after each cross is not limited.

[0130] In one example, the first log-likelihood ratio can be shifted positively at least once, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. Next, the first log-likelihood ratio is shifted negatively at least once, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. Then, the first log-likelihood ratio is shifted positively at least once again, and software decoding can be performed based on the log-likelihood ratio after each shift and the first soft-bit data. This process is repeated until decoding is successful or the number of shifts of the first log-likelihood ratio reaches a set maximum value. The values ​​shifted each time can be the same or different.

[0131] For example, as shown in Table 6, suppose the overlapping region of two adjacent programming states in a certain memory cell is divided into multiple confidence intervals (Z1, Z2, Z3, ...), and the initial LLR values ​​corresponding to each confidence interval are (a, b, c, ...). The first shift can be performed by positively shifting the first log-likelihood ratio (i.e., adding m). The second shift can be performed by negatively shifting the first log-likelihood ratio for the first time (i.e., subtracting m). The third shift can be performed by positively shifting the first log-likelihood ratio for the second time (i.e., adding m+n). The fourth shift can be performed by negatively shifting the first log-likelihood ratio for the second time (i.e., subtracting 2m). The values ​​of m and n can be set according to actual needs, and this embodiment does not impose specific limitations on them.

[0132] Table 6

[0133] Confidence interval Z1 Z2 Z3 ... Initial LLR value a b c ... First shift a+m b+m c+m ... Second shift am bm cm ... Third shift a+m+n b+m+n c+m+n ... Fourth shift a-2m a-2m a-2m ... ... ... ... ... ...

[0134] In the above implementation process, when performing cross shifting, the value of each positive or negative shift can be set according to actual needs, and is not limited to the method in Table 6.

[0135] In one possible implementation, such as Figure 12 As shown, when the number of shifts of the first log-likelihood ratio reaches a preset value, the second soft decoding operation ends. After that, the soft decoding circuit can also replace the second lookup table to continue soft decoding of the first soft bit data, as detailed below.

[0136] S1201. Obtain the second lookup table.

[0137] The second lookup table includes a second log-likelihood ratio determined based on a second reference reading voltage, and the second lookup table corresponds to a different scenario than the first lookup table.

[0138] Specifically, the reference read voltage may shift in certain scenarios. Therefore, the user can shift the reference read voltage in certain scenarios to obtain a second reference read voltage, and then perform testing and calculation to obtain a second log-likelihood ratio that can be successfully decoded. The second lookup table can also be stored in the internal memory of the memory controller, or in memory coupled to the memory controller.

[0139] S1202. Shift the first reference read voltage to the second reference read voltage.

[0140] The offset of the reading voltage can be set according to actual needs, and this application embodiment does not impose specific restrictions on it.

[0141] S1203. Read the second soft bit data of the memory according to the second reference read voltage, and perform a third soft decoding operation according to the second soft bit data and the second log-likelihood ratio.

[0142] The third software decoding operation can be performed in the same manner as the second software decoding operation, and will not be described in detail in this embodiment.

[0143] In the above manner, the reference reading voltage can be offset first, and then the LLR value can be shifted based on the second lookup table and then software decoding can be performed, thereby improving the efficiency of software decoding.

[0144] In one possible implementation, such as Figure 13 As shown, when the number of shifts of the first log-likelihood ratio reaches a preset value, after the second soft decoding operation ends, the soft decoding circuit can also replace the third lookup table to continue soft decoding of the first soft bit data, as detailed below.

[0145] S1301. Obtain the third lookup table.

[0146] The third lookup table includes a third log-likelihood ratio determined based on a third reference reading voltage. The scenarios corresponding to the third lookup table are different from those corresponding to the first lookup table.

[0147] S1302. Perform the fourth soft decoding operation based on the third log-likelihood ratio and the first soft bit data.

[0148] Once the third lookup table is obtained, software decoding can be performed directly based on the third lookup table. This improves the efficiency of software decoding by changing the lookup table.

[0149] In the above implementation process, Figure 10 and Figure 11The corresponding software decoding method can be selectively executed after software decoding based on shifting the LLR value using the first lookup table fails. This application does not impose specific limitations on this method.

[0150] In one possible implementation, the steps of shifting and soft decoding the log-likelihood ratio in all the above possible implementations can be implemented by a soft decoding circuit.

[0151] For example, such as Figure 14 As shown, the soft decoding circuit 1142 may include a register circuit 1410 coupled to the bus 113; and a decoding circuit 1420 coupled to the register circuit 1410. Wherein, as Figure 15 As shown, the decoding circuit 1420 may include a processor 1421 coupled to a register circuit 1410; a decoder 1422 coupled to the processor 1421; and a main controller 1423 coupled to both the decoder 1422 and the processor 1421. The register circuit 1410 may store a lookup table read from memory and soft-bit data read from memory. The processor 1421 may send the LLR value from the lookup table and the soft-bit data to the decoder 1422 for soft decoding. If decoding is successful, the decoder 1422 sends the decoded data to the register circuit 1410 for buffering. If decoding fails, the decoder 1422 sends a flag signal to the main controller 1423. Upon receiving the flag signal, the main controller 1423 may send an indication signal to the processor 1421. This indication signal instructs the processor 1421 to shift the LLR value in the lookup table before transmitting the LLR value to the decoder 1422 for soft decoding. The decoder 1422 may be an LDPC decoder. The aforementioned main controller 1423 and processor 1422 may include, but are not limited to, a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), or a general-purpose processor.

[0152] In the above implementation process, the main controller 1423 and the processor 1422 can also be the same device, and this application embodiment does not impose specific limitations on this. In addition, the above-mentioned software decoding circuit 1142 can be disposed on a circuit board as an independent chip for sale or use, or it can be sold or used as part of a memory controller.

[0153] In one possible implementation, this application also provides a computer-readable storage medium. This computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the steps corresponding to the method in any of the possible implementations described above.

[0154] In some embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory, flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), a UFS, a CF card, a memory stick, etc.

[0155] In one possible implementation, such as Figure 16As shown in the illustration, this application embodiment also provides an electronic device 1600, which includes a host 1610 and a memory system 100 coupled to the host. A memory controller 110 in the memory system 100 is coupled to the host 1610. The memory controller 110 can manage data stored in a memory 120 and communicate with the host 1610. The host 1610 can be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of the electronic device 1600. The host 1610 can be configured to send data to the memory 120. Alternatively, the host 1610 can be configured to receive data from the memory 120. In other words, the memory system 100 can be applied to and packaged into different types of electronic devices 1600, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0156] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A control method for a memory system, characterized in that, include: Obtain the first soft bit data and the first lookup table corresponding to the hard bit data read from the memory; The first lookup table includes a first log-likelihood ratio determined based on a first reference read voltage of the memory; Perform a first soft decoding operation based on the first log-likelihood ratio and the first soft bit data; When it is determined that the first soft decoding operation fails, the first log-likelihood ratio is shifted at least once, and a second soft decoding operation is performed based on the log-likelihood ratio after each shift and the first soft bit data.

2. The method according to claim 1, characterized in that, Perform at least one shift on the first log-likelihood ratio, and perform a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, including: The first log-likelihood ratio is shifted positive at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

3. The method according to claim 2, characterized in that, When the method fails to perform soft decoding based on the first log-likelihood ratio and the first soft bit data after each shift by shifting the first log-likelihood ratio at least once, the method includes: The first log-likelihood ratio is negatively shifted at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

4. The method according to claim 1, characterized in that, Perform at least one shift on the first log-likelihood ratio, and perform a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, including: The first log-likelihood ratio is negatively shifted at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

5. The method according to claim 4, characterized in that, When the method fails to perform soft decoding based on the first log-likelihood ratio and the first soft bit data after each shift by shifting the first log-likelihood ratio at least once, the method includes: The first log-likelihood ratio is shifted positive at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

6. The method according to claim 1, characterized in that, Perform at least one shift on the first log-likelihood ratio, and perform a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, including: The first log-likelihood ratio is cross-shifted, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

7. The method according to claim 1, characterized in that, When the first log-likelihood ratio is shifted at least once, the value of each shift is the same.

8. The method according to claim 1, characterized in that, When the first log-likelihood ratio is shifted at least once, the value of each shift is different.

9. The method according to claim 1, characterized in that, The method further includes: If the second soft decoding operation is successful, the corresponding decoded data is output; otherwise, the second soft decoding operation is stopped when the number of shifts of the first log-likelihood ratio reaches a preset value.

10. The method according to claim 9, characterized in that, After stopping the second soft decoding operation when the number of shifts of the first log-likelihood ratio reaches a preset value, the method further includes: Obtain a second lookup table, the second lookup table including a second log-likelihood ratio determined based on a second reference read voltage of the memory; Shift the first reference read voltage to the second reference read voltage; The second soft bit data of the memory is read according to the second reference read voltage, and a third soft decoding operation is performed according to the second soft bit data and the second log-likelihood ratio.

11. The method according to claim 9, characterized in that, After stopping the second soft decoding operation when the number of shifts of the first log-likelihood ratio reaches a preset value, the method further includes: Obtain a third lookup table, which includes a third log-likelihood ratio determined based on a third reference read voltage of the memory; A fourth soft decoding operation is performed based on the third log-likelihood ratio and the first soft bit data.

12. The method according to any one of claims 1-11, characterized in that, The step of obtaining the first soft data corresponding to the hard data read from the memory and the first lookup table is performed after the hard decoding operation of the hard data fails.

13. A computer-readable storage medium, characterized in that, The system stores computer program instructions; when the computer program instructions are executed by a processor, they implement the method described in any one of claims 1-12.

14. A memory system, characterized in that, Includes one or more memories; a memory controller coupled to the memories and configured to control the memories; the memory controller includes decoding circuitry; The decoding circuit is configured as follows: Obtain first soft data corresponding to hard data read from memory and a first lookup table; the first lookup table includes a first log-likelihood ratio determined based on a first reference read voltage of memory; Perform a first soft decoding operation based on the first log-likelihood ratio and the first soft bit data; When it is determined that the first soft decoding operation fails, the first log-likelihood ratio is shifted at least once, and a second soft decoding operation is performed based on the log-likelihood ratio after each shift and the first soft bit data.

15. The memory system according to claim 14, characterized in that, When performing at least one shift on the first log-likelihood ratio and performing a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, the decoding circuit is configured as follows: The first log-likelihood ratio is shifted positive at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

16. The memory system according to claim 15, characterized in that, When the first log-likelihood ratio is shifted positive at least once, and soft decoding fails based on the log-likelihood ratio after each shift and the first soft bit data, the decoding circuit is further configured to: The first log-likelihood ratio is negatively shifted at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

17. The memory system according to claim 14, characterized in that, When performing at least one shift on the first log-likelihood ratio and performing a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, the decoding circuit is configured as follows: The first log-likelihood ratio is negatively shifted at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

18. The memory system according to claim 17, characterized in that, When the first log-likelihood ratio is negatively shifted at least once, and soft decoding fails based on the log-likelihood ratio after each shift and the first soft bit data, the decoding circuit is further configured to: The first log-likelihood ratio is shifted positive at least once, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

19. The memory system according to claim 14, characterized in that, Perform at least one shift on the first log-likelihood ratio, and perform a second soft decoding operation based on the log-likelihood ratio after each shift and the first soft bit data, including: The first log-likelihood ratio is cross-shifted, and soft decoding is performed based on the log-likelihood ratio after each shift and the first soft bit data.

20. The memory system according to claim 14, characterized in that, When the first log-likelihood ratio is shifted at least once, the value of each shift is the same.

21. The memory system according to claim 14, characterized in that, When the first log-likelihood ratio is shifted at least once, the value of each shift is different.

22. A memory controller, characterized in that, Includes a bus and a decoding circuit coupled to the bus; The decoding circuit is configured as follows: Obtain first soft data corresponding to hard data read from memory and a first lookup table; the first lookup table includes a first log-likelihood ratio determined based on the memory's reference read voltage; Perform a first soft decoding operation based on the first log-likelihood ratio and the first soft bit data; When it is determined that the first soft decoding operation fails, the first log-likelihood ratio is shifted at least once, and a second soft decoding operation is performed based on the log-likelihood ratio after each shift and the first soft bit data.

23. An electronic device, characterized in that, It includes an interface circuit and a memory system coupled to the interface circuit as described in any one of claims 14-21.

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