Data writing method, storage device, and data writing system

Abstract

The embodiment of the present application discloses a data writing method, a storage device and a data writing system. The control unit of the storage device of the embodiment of the present application temporarily stores the data to be written into a source buffer area, controls the source buffer area to transmit the data to be written into a target buffer area, and releases the source buffer area after the transmission of the data to be written is completed, and then controls the target buffer area to write the data to be written into a storage medium of the storage device. The embodiment of the present application releases the source buffer area after the data transmission is completed, thereby reducing the occupation time of the source buffer area, and thus improving the data writing efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to a data writing method, a storage device, and a data writing system. Background Technology

[0002] Data writing efficiency is limited by write bandwidth, which is affected by the capacity of the storage device's buffer memory (i.e., cache). However, due to manufacturing costs and other reasons, the cache capacity of existing storage devices is limited. Therefore, when the data volume is large, the cache will be occupied for a long time, resulting in low data writing efficiency. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a data writing method, a storage device, and a data writing system to reduce the time occupied by the source buffer after data transmission is completed, thereby improving data writing efficiency.

[0004] In a first aspect, embodiments of the present invention provide a data writing method, applicable to a control unit of a storage device, the method comprising:

[0005] The data to be written is temporarily stored in the source cache.

[0006] The source buffer is controlled to transfer the data to be written to the target buffer.

[0007] Upon completion of the data transmission to be written, the source buffer is released.

[0008] The target cache is controlled to write the data to be written to the storage medium of the storage device.

[0009] Optionally, the method further includes:

[0010] Receive data write request;

[0011] The data write request is parsed to obtain the data to be written from the data write request.

[0012] Optionally, the data to be written is input / output data, the source buffer is the input / output data buffer in the static random access memory of the control unit, and the target buffer is the internal buffer of the storage medium.

[0013] Optionally, controlling the source buffer to transfer the data to be written to the target buffer includes:

[0014] The source cache is controlled to transfer the data to be written to the target cache via direct memory access.

[0015] Optionally, releasing the source buffer in response to the completion of the data transmission to be written includes:

[0016] In response to receiving a transmission completion signal for the data to be written, the availability status of the source buffer is changed to available.

[0017] Optionally, the method further includes:

[0018] Receive data write request;

[0019] The data write request is parsed to obtain the target data in the data write request;

[0020] The target data is verified to obtain the verification data of the target data;

[0021] The verification data is determined as the data to be written.

[0022] Optionally, the data to be written is the verification data of the input / output data, the source buffer is the verification data buffer in the static random access memory of the control unit, and the target buffer is the verification data buffer in the dynamic random access memory of the control unit.

[0023] Optionally, the step of controlling the target cache to write the data to be written to the storage medium of the storage device includes:

[0024] The target cache is controlled to transfer the data to be written to the internal cache of the storage medium;

[0025] The internal cache is controlled to write the data to be written to the storage medium.

[0026] In a second aspect, embodiments of the present invention provide a storage device, the storage device comprising:

[0027] Storage medium;

[0028] Multiple caches, including a source cache and a destination cache for the data to be written;

[0029] The control unit is configured to temporarily store the data to be written in a source buffer, send a data transmission instruction to the source buffer to control the source buffer to transmit the data to be written to a target buffer, release the source buffer in response to the completion of the data transmission, and send a data write request to the target buffer to control the target buffer to write the data to be written to the storage medium.

[0030] Thirdly, embodiments of the present invention provide a data writing system, the data writing system comprising:

[0031] The storage device as described in the second aspect;

[0032] The host is configured to send a data write request to the storage device.

[0033] Fourthly, embodiments of the present invention provide a data writing device, suitable for a control unit of a storage device, the device comprising:

[0034] The data temporary storage module is used to temporarily store the data to be written to the source cache area;

[0035] The data transmission module is used to control the source buffer to transmit the data to be written to the target buffer;

[0036] The release module is used to release the source buffer in response to the completion of the data transmission to be written;

[0037] The data writing module is used to control the target cache to write the data to be written to the storage medium of the storage device.

[0038] Fifthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any one of the first aspects.

[0039] In a sixth aspect, embodiments of the present invention provide a computer program product that, when run on a computer, causes the computer to perform the method as described in any one of the first aspects.

[0040] In this embodiment of the invention, the control unit of the storage device temporarily stores the data to be written in the source cache, controls the source cache to transfer the data to be written to the target cache, and releases the source cache after the data transfer is complete, thereby controlling the target cache to write the data to be written to the storage medium of the storage device. This embodiment of the invention reduces the time the source cache is occupied by releasing it after data transfer is complete, thus improving data writing efficiency. Attached Figure Description

[0041] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0042] Figure 1 This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention;

[0043] Figure 2 This is a flowchart of the data writing method according to an embodiment of the present invention;

[0044] Figure 3This is a flowchart of the data writing method according to an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of the existing data writing process;

[0046] Figure 5 This is a schematic diagram of the data writing process according to an embodiment of the present invention;

[0047] Figure 6 This is a flowchart of the data writing method according to an embodiment of the present invention;

[0048] Figure 7 This is a schematic diagram of the existing data writing process;

[0049] Figure 8 This is a schematic diagram of the data writing process according to an embodiment of the present invention;

[0050] Figure 9 This is a schematic diagram of a data writing device according to an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of a data access system according to an embodiment of the present invention. Detailed Implementation

[0052] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0053] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0054] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0055] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0056] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0057] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium. Flash memory can include NOR flash memory and NAND flash memory, and can perform operations such as reading, programming (i.e., writing), and erasing. NAND flash memory comprises multiple blocks, each block consisting of a number of pages, each page consisting of a number of bit lines, and each bit line consisting of a number of memory cells. This allows NAND flash memory to store data in memory cells in the form of bits. Therefore, NAND flash memory can perform erase operations at the block level and programming or reading operations at the page level. This invention primarily describes an SSD (Solid State Disk) storage device using NAND flash memory as the storage medium. It should be understood that this embodiment is not limited to this; existing storage devices that support corresponding functions, or storage devices that will support corresponding functions with future technological developments, are all within the protection scope of this invention.

[0058] Data write bandwidth refers to the amount of data that can be written to a storage device per unit of time. Data write efficiency is limited by write bandwidth; the higher the write bandwidth, the higher the write efficiency. Therefore, in order to improve the write bandwidth of a storage device and thus improve its data write efficiency, the control unit of the storage device is usually equipped with an internal cache, such as a Static Random-Access Memory (SRAM) cache, a Dynamic Random Access Memory (DRAM) cache, or a Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM or DDR, a type of DRAM) cache.

[0059] Figure 1 This is a schematic diagram of the structure of a storage device according to an embodiment of the present invention. Figure 1As shown, the storage device 10 of this embodiment includes a control unit 11 and a NAND storage medium 12. The control unit 11 includes a front-end (FE) module 111, a flash translation layer (FTL) module 112, a back-end (BE) module 113, an SRAM cache 114, and a DDR cache 115. The NAND storage medium 12 includes a cache area 121 and a storage area 122.

[0060] The FE module 111 is mainly responsible for interface communication and data transmission with the host, including receiving data write requests from the host, performing preliminary parsing and processing of the data write requests, obtaining various information including the logical block address (LBA) of the data to be written and passing it to the FTL module 112, and temporarily storing the data to be written carried in the data write request in the SRAM cache 114 or the DDR cache 115.

[0061] The FTL module 112 is primarily responsible for mapping the logical block address of the data to be written to the physical block address (PBA) on the NAND storage medium 12, which is the actual storage location of the data to be written in the storage area 122. It then transmits this information, including the physical block address of the data to be written, to the BE module 113. Simultaneously, the FTL module is also responsible for managing tasks on the NAND storage medium 12, such as garbage collection, wear leveling, and recovery from abnormal power outages.

[0062] The BE module 113 is connected to the NAND storage medium 12 and performs corresponding data writing operations according to the information transmitted by the FTL module 112. That is, it controls the SRAM cache 114 or DDR cache 115 to transmit the data to be written to the NAND storage medium 12 and to release the SRAM cache 114 or DDR cache 115 so that the SRAM cache 114 or DDR cache 115 can store new data to be written.

[0063] During the data writing process, the BE module 113 will temporarily store the data to be written in the buffer 121. The buffer 121 is the internal buffer of the NAND storage medium 12. Therefore, after the data to be written is transferred, the NAND storage medium 12 can write the data to be written into the corresponding storage cell in the storage area 122 according to the physical block address of the data to be written.

[0064] However, the manufacturing cost of the internal cache of the control unit is usually high, and in order to reasonably control the manufacturing cost of the storage device, the capacity of the internal cache of the control unit is limited. In the existing technology, the storage unit of the storage device will only release the internal cache after the data has been written to the storage medium. Therefore, when the data volume is large, the cache will be occupied for a long time, resulting in low data writing efficiency.

[0065] Based on this, embodiments of the present invention provide a data writing method, a storage device, and a data writing system to reduce the time occupied by the source buffer after data transmission is completed, thereby improving data writing efficiency.

[0066] Figure 2 This is a flowchart of a data writing method according to an embodiment of the present invention. Figure 2 As shown, the method in this embodiment includes the following steps:

[0067] Step S201: Temporarily store the data to be written in the source cache.

[0068] After acquiring the data to be written, in this step, the control unit of the storage device can temporarily store the data to be written in the internal cache area of ​​the control unit according to actual needs, and determine the internal cache area where the data to be written is temporarily stored as the source cache area.

[0069] by Figure 1 Taking the storage device shown as an example, the control unit of the storage device can temporarily store the data to be written in the SRAM cache 114 or in the DDR cache. This embodiment does not impose any restrictions.

[0070] Step S202: Control the source buffer to transfer the data to be written to the target buffer.

[0071] The actual capacity of the source cache affects the write bandwidth of the data to be written, thus limiting the write efficiency. Therefore, to prevent the source cache from being occupied for a long time, in this step, the control unit of the storage device can control the source cache to transfer the data to be written to the target cache. Furthermore, the control unit of the storage device can determine the transmission method of the data to be written based on the source cache and the target cache, and control the source cache to transfer the data to be written to the target cache according to the corresponding transmission method.

[0072] Still with Figure 1 Taking the storage device shown as an example, when the source cache is SRAM cache 114, the target cache can be DDR cache 115 or NAND storage medium 12 cache 121; when the source cache is DDR cache 115, the target cache can be NAND storage medium 12 cache 121.

[0073] When the source cache is SRAM cache 114 or DDR cache 115, and the target cache is cache 121 of NAND storage medium 12, the control unit 11 of storage device 10 can control SRAM cache 114 or DDR cache 115 to transfer the data to be written to cache 121 of NAND storage medium 12 via the internal data bus of storage device 10, i.e., the bus connected to NAND storage medium 12, using Direct Memory Access (DMA). DMA is a hardware technology that allows direct data exchange between devices, chips, etc., without the intervention of the central processing unit (CPU), thus saving CPU computing resources and improving the transmission efficiency of the data to be written.

[0074] When the source cache is SRAM cache 114 and the target cache is DDR cache 115, the control unit 11 of the storage device 10 can control the SRAM cache 114 to transmit the data to be written to the DDR cache 115 through the internal data bus of the storage device 10, that is, the bus connected to the DDR cache 115, so as to ensure the transmission efficiency of the data to be written.

[0075] Step S203: In response to the completion of the data transmission to be written, the source buffer is released.

[0076] When data to be written is temporarily stored in the source buffer, the storage device's control unit changes the availability status of the source buffer to unavailable to prevent new data to be written from being temporarily stored in the source buffer and overwriting the existing data. Therefore, in this step, the storage device's control unit can change the availability status of the source buffer back to available after the data to be written has been transferred, thereby releasing the source buffer.

[0077] Furthermore, the control unit of the storage device can obtain the transmission status of the data to be written according to the source buffer and the target buffer in an appropriate manner, thereby modifying the availability status of the source buffer.

[0078] Still with Figure 1 Taking the storage device shown as an example, when the source cache is SRAM cache 114 or DDR cache 115, and the target cache is cache 121 of NAND storage medium 12, the DMA data transfer mechanism sends a transfer completion signal to the control unit 11 of storage device 10 after the data transfer is completed. Specifically, this signal can be DMA Done. Therefore, upon receiving the transfer completion signal from NAND storage medium 12, the control unit 11 of storage device 10 can determine that the data to be written has been transferred.

[0079] When the source cache is SRAM cache 114 and the target cache is DDR cache 115, in one possible scenario, the control unit 11 of the storage device 10 may maintain internal status flags to track the status of SRAM cache 114 and DDR cache 115, and update the status flags of SRAM cache 114 or DDR cache 115 after the data to be written has been transferred. Therefore, the control unit 11 of the storage device 10 can determine that the data to be written has been transferred by reading the status flags of SRAM cache 114 or DDR cache 115.

[0080] In one possible scenario, there might be a specific handshake protocol or completion signal between the SRAM cache 114 and the DDR cache 115. Therefore, after data transfer is complete, the DDR cache 115 will send a data transfer completion signal to the SRAM cache 114. Thus, the control unit 11 of the storage device 10 can determine that the data to be written has been transferred by monitoring this data transfer completion signal.

[0081] In one possible scenario, to ensure the integrity and correctness of data transmission, the control unit 11 of the storage device 10 can perform a verification operation on the data to be written. After determining that the data to be written has been transmitted successfully via the aforementioned status flag or transmission completion signal, the control unit 11 of the storage device 10 can perform a verification operation on the data to be written in the DDR cache 115 to verify whether the data to be written in the DDR cache 115 is consistent with the original data to be written in the SRAM cache 114. If the verification passes, the control unit 11 of the storage device 10 can determine that the data to be written has been transmitted successfully.

[0082] Step S204: Control the target cache to write the data to be written to the storage medium of the storage device.

[0083] In this step, the control unit of the storage device can control the target cache to write the data to be written into the corresponding storage cell in the storage medium based on the physical block address of the data to be written. Specifically, if the target cache is the internal cache of the control unit of the storage device, the control unit of the storage device can control the target cache to transfer the data to be written to the internal cache of the storage medium, and control the storage medium of the storage device to write the data to be written into the corresponding storage cell.

[0084] Still with Figure 1Taking the storage device shown as an example, when the target cache is DDR cache 115, the control unit 11 of the storage device 10 can control the DDR cache 115 to transfer the data to be written to the cache 121 of the NAND storage medium 12, and control the NAND storage medium 12 to write the data to be written in the cache 121 of the NAND storage medium 12 to the corresponding storage cell in the storage area 122.

[0085] If the target cache is the internal cache of the storage medium of the storage device, the control unit of the storage device can control the internal cache of the storage medium to write the data to be written to the corresponding storage unit in the storage medium of the storage device.

[0086] It is easy to understand that in this embodiment, steps S203 and S204 can be executed simultaneously or sequentially, and this embodiment does not impose any restrictions.

[0087] Writing data from the internal cache of the storage medium to the corresponding storage unit takes time. Therefore, according to existing technology, even after the data has been transferred to the target cache, the source cache is not released until the data is completely written. This increases the occupancy time of the source cache, thus reducing the write bandwidth. However, the method of this invention allows the source cache to be released earlier, thereby increasing the write bandwidth and improving the write efficiency.

[0088] In this embodiment of the invention, the control unit of the storage device temporarily stores the data to be written in the source cache, controls the source cache to transfer the data to be written to the target cache, and releases the source cache after the data transfer is complete, thereby controlling the target cache to write the data to be written to the storage medium of the storage device. This embodiment of the invention reduces the time the source cache is occupied by releasing it after data transfer is complete, thus improving data writing efficiency.

[0089] Figure 3 This is a flowchart of a data writing method according to an embodiment of the present invention. Figure 3 As shown, the method in this embodiment includes the following steps:

[0090] Step S301: Receive data write request.

[0091] In this embodiment, the host can send a data write request to the control unit of the storage device via the bus. Therefore, in this step, the control unit of the storage device can receive the data write request.

[0092] Step S302: Parse the data write request and obtain the data to be written in the data write request.

[0093] In this step, the control unit of the storage device can parse the data write request and determine the input / output data carried in the data write request, i.e., the I / O (Input / Output) data, as the data to be written.

[0094] The parsing process of a data write request requires high data processing bandwidth. Therefore, the control unit of the storage device can use a cache to complete the parsing process and obtain the input and output data in the data write request. In practical applications, SRAM has higher data processing performance than DDR. Therefore, in this embodiment, the control unit of the storage device can use an SRAM cache to parse the data write request.

[0095] In one possible scenario, the SRAM cache is divided into multiple data caches, including input / output data caches, depending on actual needs. Therefore, in this step, the control unit of the storage device can use the input / output data caches in the SRAM to parse data write requests.

[0096] Step S303: The data to be written is temporarily stored in the source cache.

[0097] After acquiring the input / output data from the data write request, the control unit of the storage device can directly and temporarily store the input / output data in the internal cache of the control unit, specifically, the high-speed cache of the control unit. In this embodiment, the high-speed cache can be an SRAM cache. Furthermore, the control unit of the storage device can temporarily store the input / output data in the input / output data cache area of ​​the control unit's SRAM.

[0098] Step S304: Control the source buffer to transfer the data to be written to the target buffer.

[0099] To reduce the time that input / output data occupies the source buffer and to avoid placing an excessive data processing burden on the control unit of the storage device, the control unit of the storage device can designate the internal buffer of the storage medium of the storage device as the target buffer for input / output data and control the internal buffer of the control unit, specifically the input / output data buffer in the SRAM, to transfer the input / output data to the internal buffer of the storage medium of the storage device.

[0100] In this step, the control unit of the storage device can control the input / output data buffer in the SRAM to transfer input / output data to the internal buffer of the storage medium of the storage device via DMA.

[0101] Step S305: In response to the completion of the data transmission to be written, the source buffer is released.

[0102] In this step, the control unit of the storage device can determine that the input / output data transmission is complete after receiving the input / output data transmission completion signal, and then change the availability status of the internal buffer of the control unit to available, thereby releasing the internal buffer of the control unit. Specifically, the storage device can change the availability status of the input / output data buffer in the SRAM to available.

[0103] Step S306: Control the target cache to write the data to be written to the storage medium of the storage device.

[0104] In this step, the control unit of the storage device can control the internal buffer of the storage medium to write the data to be written into the corresponding storage cell in the storage medium of the storage device, thus completing the input and output data writing process.

[0105] Figure 4 This is a schematic diagram of the existing data writing process. For example... Figure 4 As shown, in step S41, the FE module 111 can receive a data write request sent by the host 40 and parse the data write request. Then, in step S42, the I / O data carried in the data write request is temporarily stored in the SRAM 114, specifically the I / O data buffer 1141 of the SRAM. In step S43, the I / O data buffer 1141 of the SRAM is controlled to transfer the I / O data to the buffer 121 of the NAND storage medium 12. In step S44, after the I / O data transfer is completed, the NAND storage medium 12 can send an I / O data transfer completion signal, i.e., DMA Done, to the BE module 113. In step S45, after the I / O data is written, the NAND storage medium 12 can send an I / O data write completion signal, i.e., NAND Done, to the BE module 113. In step S46, after receiving the I / O data write completion signal, the BE module 113 can modify the available state of the SRAM I / O data buffer 1141 to available, so as to release the SRAM I / O data buffer 1141.

[0106] Figure 5 This is a schematic diagram of the data writing process according to an embodiment of the present invention. Figure 5As shown, in step S51, the FE module 111 can receive a data write request sent by the host 40 and parse the data write request. Then, in step S52, the I / O data carried in the data write request is temporarily stored in the SRAM 114, specifically the I / O data buffer 1141 of the SRAM. In step S53, the I / O data buffer 1141 of the SRAM is controlled to transfer the I / O data to the buffer 121 of the NAND storage medium 12. In step S54, after the I / O data transfer is completed, the NAND storage medium 12 can send an I / O data transfer completion signal, i.e., DMA Done, to the BE module 113. In step S55, after receiving the I / O data transfer completion signal, the BE module 113 can modify the available state of the I / O data buffer 1141 of the SRAM to available, thereby releasing the I / O data buffer 1141 of the SRAM. In step S56, after the I / O data is written, the NAND storage medium 12 can send an I / O data writing completion signal to the BE module 113, that is, NAND Done.

[0107] By comparison Figure 4 and Figure 5 It can be determined that, in this embodiment of the invention, the release time of the internal buffer of the control unit is advanced from after receiving the signal that the input and output data has been written to after receiving the signal that the input and output data has been transmitted. Therefore, the time that input and output data occupy the internal buffer of the control unit is effectively reduced, the utilization rate of the internal buffer of the control unit is improved, and thus the writing efficiency of input and output data can be effectively improved.

[0108] In this embodiment of the invention, the control unit of the storage device temporarily stores the data to be written in the source cache, controls the source cache to transfer the data to be written to the target cache, and releases the source cache after the data transfer is complete, thereby controlling the target cache to write the data to be written to the storage medium of the storage device. This embodiment of the invention reduces the time the source cache is occupied by releasing it after data transfer is complete, thus improving data writing efficiency.

[0109] Figure 6 This is a flowchart of a data writing method according to an embodiment of the present invention. Figure 6 As shown, the method in this embodiment includes the following steps:

[0110] Step S601: Receive data write request.

[0111] In this embodiment, the implementation of step S601 is similar to that of step S301, and will not be described again here.

[0112] Step S602: Parse the data write request and obtain the target data in the data write request.

[0113] In this step, the control unit of the storage device can parse the data write request and determine the input / output data carried in the data write request as the target data.

[0114] Step S603: Verify the target data and obtain the verification data of the target data in the data write request.

[0115] To ensure the consistency and security of data transmission, the control unit of the storage device can verify the input and output data after the data transmission is completed, and obtain verification data. Depending on the actual settings, the control unit of the storage device can verify the input and output data after controlling the internal buffer of the storage device to transmit the input and output data to the internal buffer of the storage medium, or it can verify the input and output data after the data transmission is complete, depending on the transmission method. This embodiment does not impose any restrictions.

[0116] The verification process for input / output data also requires high data processing bandwidth. Therefore, the control unit of the storage device can use a cache to complete the verification process for input / output data and obtain the verification data. In this embodiment, the cache is an SRAM cache.

[0117] In one possible scenario, depending on actual needs, the SRAM cache is divided into two data caches: an input / output data cache and a parity data cache. Therefore, in this step, the control unit of the storage device can use the parity data cache in the SRAM to verify the input / output data.

[0118] In this step, the control unit of the storage device can use various existing verification methods to verify the input and output data, such as BBC (Block Check Character) XOR verification, Cyclic Redundancy Check (CRC), ECC (Error Checking and Correcting) verification, parity check, etc. This embodiment does not impose any restrictions.

[0119] Step S604: Determine the verification data as the data to be written.

[0120] After obtaining the verification data of the input and output data, the control unit of the storage device can determine the verification data as the data to be written.

[0121] Step S605: Temporarily store the data to be written in the source cache.

[0122] After acquiring the verification data of the input and output data, the control unit of the storage device can directly and temporarily store the verification data of the input and output data in the internal cache area of ​​the control unit, specifically the high-speed cache area of ​​the control unit. In this embodiment, the high-speed cache area can be an SRAM cache area. Furthermore, the control unit of the storage device can temporarily store the verification data of the input and output data in the verification data cache area of ​​the control unit's SRAM.

[0123] Step S606: Control the source buffer to transfer the data to be written to the target buffer.

[0124] In practical applications, storage devices also receive other types of data processing requests from the host, such as data read requests and data erase requests. These data processing requests are stored in a request queue so that the storage device can execute the corresponding operations according to the First-In-First-Out (FIFO) principle. Therefore, when the number of requests is large, it will put a high load on the storage medium of the storage device, and may prevent data in the storage device's cache from being transferred to the internal cache of the storage medium, thereby reducing the data processing capacity of the cache. At the same time, the verification data of input and output data does not have high requirements for write bandwidth.

[0125] Therefore, to ensure the data processing capability of the source cache, the storage device's control unit can control the cache to transfer the parity data of input / output data to the non-cache area, thereby reducing the time that the parity data occupies the cache area. Specifically, the non-cache area can be the DDR cache area.

[0126] In one possible scenario, the DDR cache is divided into multiple data caches, including a parity data cache. Therefore, in this step, the control unit of the storage device can identify the parity data cache in the DDR as the target cache and control the parity data cache in the SRAM to transfer the parity data of the input / output data to the parity data cache in the DDR.

[0127] Step S607: In response to the completion of the data transmission to be written, the source buffer is released.

[0128] In this step, the storage device's control unit can release the control unit's cache by changing its available state to "available" after determining that the status flags of the source or target cache indicate the completion of the verification data transmission for the input / output data. Specifically, the storage device can change the available state of the verification data cache in the SRAM to "available".

[0129] Step S608: Control the target cache to write the data to be written to the storage medium of the storage device.

[0130] Both the cache area and the non-cache area are internal cache areas of the control unit. Therefore, in this step, the control unit of the storage device can first control the target cache area to transfer the data to be written to the internal cache area of ​​the storage medium, and then control the storage medium of the storage device to write the data to be written to the corresponding storage unit, thus completing the process of writing the verification data of the input and output data.

[0131] Optionally, the control unit of the storage device may release the target buffer after receiving a transmission completion signal from the storage medium, or it may release the target buffer after receiving a write completion signal from the storage medium. This embodiment does not impose any limitations. The release method of the target buffer is similar to that of the source buffer, and will not be described in detail here.

[0132] Figure 7 This is a schematic diagram of the existing data writing process. It is easy to understand that the process of generating verification data can be referenced in this embodiment. Figure 7 The details are omitted here. After temporarily storing the I / O data verification data in the source buffer, i.e., the SRAM verification data buffer 1142, in step S71, the SRAM verification data buffer 1142 is controlled to transfer the I / O data verification data to the buffer 121 of the NAND storage medium 12. In step S72, after the I / O data verification data transfer is completed, the NAND storage medium 12 can send an I / O data verification data transfer completion signal, i.e., DMA Done, to the BE module 113. In step S73, after the I / O data verification data is written, the NAND storage medium 12 can send an I / O data verification data write completion signal, i.e., NAND Done, to the BE module 113. In step S74, after receiving the I / O data verification data write completion signal, the BE module 113 can modify the available state of the SRAM verification data buffer 1142 to available, thereby releasing the SRAM verification data buffer 1142.

[0133] Figure 8 This is a schematic diagram of the data writing process according to an embodiment of the present invention. It is easy to understand that the process of generating verification data can also refer to this embodiment. Figure 8The details are omitted here. After temporarily storing the I / O data verification data in the source buffer, i.e., the SRAM verification data buffer 1142, in step S81, the BE module 113 controls the SRAM verification data buffer 1142 to transfer the I / O data verification data to the DDR 115, specifically to the DDR verification data buffer 1151. In step S82, after determining that the I / O data verification data transfer is complete, the BE module 113 can change the available state of the SRAM verification data buffer 1142 to available, thereby releasing the SRAM verification data buffer 1142. In step S83, the BE module 113 controls the DDR verification data buffer 1151 to transfer the I / O data verification data to the buffer 121 of the NAND storage medium 12. In step S84, after the I / O data verification data transfer is complete, the NAND storage medium 12 can send an I / O data verification data transfer completion signal, i.e., DMA Done, to the BE module 113. In step S85, after the verification data of the I / O data has been written, the NAND storage medium 12 can send a signal indicating that the verification data of the I / O data has been written, i.e., NANDDone, to the BE module 113.

[0134] By comparison Figure 7 and Figure 8 It can be determined that, in this embodiment of the invention, the release timing of the high-speed cache of the control unit is advanced from after receiving the signal indicating that the verification data of the input and output data has been written or after receiving the signal indicating that the verification data of the input and output data has been transmitted to the non-high-speed cache, and the non-high-speed cache is controlled to complete the subsequent data writing process. Therefore, the time that the input and output data occupy the internal cache of the control unit is effectively reduced, the utilization rate of the internal cache of the control unit is improved, and thus the writing efficiency of the input and output data can be effectively improved.

[0135] In this embodiment of the invention, the control unit of the storage device temporarily stores the data to be written in the source cache, controls the source cache to transfer the data to be written to the target cache, and releases the source cache after the data transfer is complete, thereby controlling the target cache to write the data to be written to the storage medium of the storage device. This embodiment of the invention reduces the time the source cache is occupied by releasing it after data transfer is complete, thus improving data writing efficiency.

[0136] Figure 9 This is a schematic diagram of a data writing device according to an embodiment of the present invention, applicable to the control unit of a storage device. Figure 9 As shown, the data writing device in this embodiment includes a data temporary storage module 901, a data transmission module 902, a release module 903, and a data writing module 904.

[0137] The data temporary storage module 901 is used to temporarily store the data to be written in the source cache area; the data transmission module 902 is used to control the source cache area to transmit the data to be written to the target cache area; the release module 903 is used to release the source cache area in response to the completion of the data transmission; and the data writing module 904 is used to control the target cache area to write the data to be written to the storage medium of the storage device.

[0138] In this embodiment of the invention, the control unit of the storage device temporarily stores the data to be written in the source cache, controls the source cache to transfer the data to be written to the target cache, and releases the source cache after the data transfer is complete, thereby controlling the target cache to write the data to be written to the storage medium of the storage device. This embodiment of the invention reduces the time the source cache is occupied by releasing it after data transfer is complete, thus improving data writing efficiency.

[0139] Figure 10 This is a schematic diagram of a data access system according to an embodiment of the present invention. Figure 10 As shown, the data access system includes a host 1001 and a storage device 1002. The host 1001 is configured to send data write requests to the storage device 1002. The host 1001 and the storage device 1002 can be communicatively connected via a corresponding bus 1003. The storage device 1002 includes at least multiple caches and storage media. The multiple caches include a source cache and a target cache. Its specific circuit structure can be found in [reference needed]. Figure 1 This will not be elaborated further here. The control unit in storage device 1002 can execute corresponding instructions to implement the above data writing method.

[0140] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0141] In this embodiment of the invention, the control unit of the storage device temporarily stores the data to be written in the source cache, controls the source cache to transfer the data to be written to the target cache, and releases the source cache after the data transfer is complete, thereby controlling the target cache to write the data to be written to the storage medium of the storage device. This embodiment of the invention reduces the time the source cache is occupied by releasing it after data transfer is complete, thus improving data writing efficiency.

[0142] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0143] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0144] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data write method suitable for a control unit of a storage device, characterized by, The method comprises: temporarily storing the to-be-written data in a source buffer area; controlling the source buffer area to transmit the to-be-written data to a target buffer area; in response to the transmission of the to-be-written data being completed, releasing the source buffer area by modifying an available state; controlling the target buffer area to write the to-be-written data into a storage medium of the storage device; wherein the target buffer area is an internal buffer area of the storage medium, and the source buffer area is an internal buffer area of the control unit.

2. The method of claim 1, wherein, The method further comprises: receiving a data write request; parsing the data write request to obtain the to-be-written data in the data write request.

3. The method of claim 2, wherein, The to-be-written data is input / output data, the source buffer area is an input / output data buffer area in a static random access memory of the control unit, and the target buffer area is an internal buffer area of the storage medium.

4. The method of claim 3, wherein, The controlling the source buffer area to transmit the to-be-written data to a target buffer area comprises: controlling the source buffer area to transmit the to-be-written data to the target buffer area in a direct memory access mode.

5. The method of claim 4, wherein, The releasing the source buffer area by modifying an available state in response to the transmission of the to-be-written data being completed comprises: in response to receiving a transmission completion signal of the to-be-written data, modifying the available state of the source buffer area to available.

6. The method of claim 1, wherein, The method further comprises: receiving a data write request; parsing the data write request to obtain target data in the data write request; checking the target data to obtain check data of the target data; determining the check data as the to-be-written data.

7. The method of claim 6, wherein, The to-be-written data is check data of input / output data, the source buffer area is a check data buffer area in a static random access memory of the control unit, and the target buffer area is a check data buffer area in a dynamic random access memory of the control unit.

8. The method of claim 7, wherein, The controlling the target buffer area to write the to-be-written data into a storage medium of the storage device comprises: controlling the target buffer area to transmit the to-be-written data to an internal buffer area of the storage medium; controlling the internal buffer area to write the to-be-written data into the storage medium.

9. A storage device, comprising: The storage device comprises: a storage medium; a plurality of buffer areas, including a source buffer area and a target buffer area of to-be-written data; a control unit configured to temporarily store to-be-written data in a source buffer area, send a data transmission instruction to the source buffer area to control the source buffer area to transmit the to-be-written data to a target buffer area, in response to the transmission of the to-be-written data being completed, release the source buffer area by modifying an available state, and send a data write request to the target buffer area to control the target buffer area to write the to-be-written data into the storage medium; wherein the target buffer area is an internal buffer area of the storage medium, and the source buffer area is an internal buffer area of the control unit.

10. A data writing system, characterized by, The data write system comprises: the storage device of claim 9; a host configured to send a data write request to the storage device.

11. A data writing apparatus adapted for a control unit of a storage device, characterized by comprising: The apparatus comprises: a data temporary storage module configured to temporarily store to-be-written data in a source buffer area; a data transmission module, configured to control the source buffer to transmit the to-be-written data to a target buffer; a release module, configured to release the source buffer by modifying an available state in response to completion of the transmission of the to-be-written data; a data writing module, configured to control the target buffer to write the to-be-written data into a storage medium of the storage device; wherein the target buffer is an internal buffer of the storage medium, and the source buffer is an internal buffer of the control unit.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the method in any one of claims 1-8.

13. A computer program product, characterised in that, When the computer program product runs on the computer, the computer is caused to execute the method in any one of claims 1-8.

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