Instruction classification processing method, device, terminal equipment and storage medium

Abstract

The present application relates to the technical field of instruction processing, and discloses an instruction classification processing method, apparatus, terminal device, and storage medium. The method comprises: when receiving an instruction packet sent by a host computer, classifying the instructions in the instruction packet; assigning the instruction packet to a parallel thread of the corresponding category according to the type of the instruction, and caching the instruction packet in a cache space corresponding to the parallel thread; when the instruction packet is retrieved, it is retrieved from the cache space in the order in which it is stored, and the instruction packet is parsed to obtain a corresponding function execution signal, and the function execution signal is output. The instructions are processed in parallel and cached, which improves processing efficiency and avoids instruction loss.

Description

Technical Field

[0001] The present application relates to the technical field of instruction processing, and in particular to an instruction classification processing method, apparatus, terminal device and storage medium. Background Art

[0002] In electronic device development systems, communication between devices or chips is essential; only with communication can they interact. The typical communication process uses common buses like UART and PCIE, and then develops a communication protocol based on the application scenario to carry interaction instructions. When a device receives a communication, it parses it according to the established protocol and executes the corresponding operation. This is feasible for scenarios with slow, intermittent control instructions. However, if a device continuously receives various control instructions from a host computer and continues to parse and execute them serially, this can result in consecutive similar instructions being incomplete and subsequently lost, and different types of instructions being blocked. Clearly, such a device has limitations and is prone to errors. Summary of the Invention

[0003] In view of this, an embodiment of the present application provides an instruction classification processing method that can effectively solve problems such as instruction loss and blocking.

[0004] In a first aspect, an embodiment of the present application provides an instruction classification processing method, comprising:

[0005] When receiving an instruction packet sent by the host computer, classifying the instructions in the instruction packet;

[0006] Allocating the instruction packet to a corresponding type of parallel thread according to the type of the instruction, and caching the instruction packet in a cache space corresponding to the parallel thread;

[0007] When the instruction packet is retrieved, it is retrieved from the cache space in sequence according to the order in which it is stored, and the instruction packet is parsed to obtain a corresponding function execution signal, and the function execution signal is output.

[0008] In one embodiment, when receiving an instruction packet sent by a host computer, classifying the instructions in the instruction packet includes:

[0009] Receive an instruction packet from a host computer, and determine a communication protocol address of an instruction stored in the instruction packet according to a communication protocol;

[0010] The type of the instruction is determined according to the address segment where the communication protocol address is located.

[0011] In one embodiment, the instruction packets in the cache space are retrieved sequentially in the order in which they were stored, including:

[0012] If an instruction packet is currently being parsed, pausing to retrieve the instruction packet from the cache space;

[0013] If no instruction packet is currently parsed, the instruction packet stored first is retrieved from the cache space.

[0014] In one embodiment, parsing the instruction packet to obtain a corresponding function execution signal includes:

[0015] Determining, according to the communication protocol, an instruction location in the instruction packet where the instruction is stored, extracting the instruction and determining a corresponding communication protocol address;

[0016] The instruction is parsed to determine the type of function corresponding to the instruction, and a corresponding execution signal is generated according to the type of function.

[0017] In one embodiment, after determining the function type corresponding to the instruction, the method further includes:

[0018] Determining a matching type corresponding to the communication protocol address according to the communication protocol address and a preset function matching table;

[0019] If the matching type is different from the function type, the current instruction packet is discarded.

[0020] In one embodiment, after caching the instruction packet into the cache space corresponding to the parallel thread, the method further includes:

[0021] Outputting the storage capacity status of the cache space to provide debugging information.

[0022] In one embodiment, the communication protocol sets a frame width and an instruction field, and determining, according to the communication protocol, an instruction location storing the instruction in the instruction packet, extracting the instruction and determining a corresponding communication protocol address includes:

[0023] Taking the frame width as a unit, count and traverse from the packet header of the instruction packet to find the location of the instruction field, so as to obtain the instruction under the instruction field and the communication protocol address where the instruction is located.

[0024] In a second aspect, the present application further provides an instruction classification processing device, comprising:

[0025] A classification module is used to classify the instructions in the instruction packet when receiving the instruction packet sent by the host computer;

[0026] a cache module, configured to distribute the instruction packets to parallel threads of corresponding categories according to the types of the instructions, and cache the instruction packets in cache spaces corresponding to the parallel threads;

[0027] The parsing module is used to call the instruction packet from the cache space in sequence according to the storage order when the instruction packet is called, and to parse the instruction packet to obtain the corresponding function execution signal, and output the function execution signal.

[0028] In a third aspect, the present application further provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the instruction classification processing method.

[0029] In a fourth aspect, the present application also provides a computer-readable storage medium storing a computer program, which implements the instruction classification processing method when executed on a processor.

[0030] The embodiments of the present application have the following beneficial effects:

[0031] The instruction classification processing method of the present application adopts a design of parsing after classification instruction buffering, which has the ability to immediately process multiple communication instructions in parallel without causing blocking, thereby speeding up the response speed. In addition, the number of classifications can be configured to increase or decrease the ability of parallel lines and the cache space can be user-defined. Therefore, it has the characteristics of compatibility, high fault tolerance, and fast communication rate in electronic equipment systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic diagram of a flow chart of an instruction classification processing method according to an embodiment of the present application is shown;

[0034] Figure 2 A data flow diagram of instruction classification processing according to an embodiment of the present application is shown;

[0035] Figure 3 A schematic structural diagram of an instruction classification processing device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0037] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0038] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0040] The technical solution of the present application pre-sets classification rules. When the device receives an instruction packet, it can determine the instruction category based on the protocol address where the instruction is stored in the instruction packet. Instructions of different categories are processed and cached through different threads, thereby achieving parallel and cache processing between different instructions and avoiding instruction loss and blocking.

[0041] The method is described below with reference to some specific embodiments.

[0042] Example 1

[0043] Figure 1 A flow chart of the instruction classification processing method according to an embodiment of the present application is shown. Exemplarily, the instruction classification processing method includes the following steps:

[0044] Step S100: When receiving an instruction packet sent by a host computer, classify the instructions in the instruction packet.

[0045] This embodiment is applied to the scenarios of communication between devices or communication between devices and chips. The method of this embodiment is mainly applied to the processing device at the end receiving the instructions. These processing devices can be various engineering equipment or control equipment and other devices that can process instructions.

[0046] The host computer sends control instructions to the processing device or chip. These control instructions are encapsulated into an instruction packet through the communication protocol and then sent to the corresponding processing device. When the processing device receives the instruction packet, it classifies the instructions carried in it.

[0047] It should be noted that the various instructions in this embodiment have various functions. Each instruction is assigned a communication protocol address. This protocol address is the address reserved for storing the instruction within the instruction packet. When the control instruction is encapsulated into the instruction packet, it is stored in this communication protocol address. Instructions classified into the same category have their corresponding communication protocol addresses grouped into the same range. For example, instruction A and instruction B are both instructions of the same category, and although they have different addresses, the addresses assigned to both instructions fall within the same range.

[0048] In this way, when identifying an instruction packet, the address segment where the communication protocol address is located can be determined based on the communication protocol address of the instruction stored in the instruction packet to determine the type of the instruction.

[0049] The above instructions are categorized based on whether they are mutually exclusive, or whether they can be executed simultaneously. Instructions that cannot be executed simultaneously are classified into the same category. For example, instruction A opens a switch, and instruction B closes it. Obviously, a switch cannot be both on and off at the same time, so they cannot be executed in parallel. Therefore, instructions A and B are classified into the same category. However, instruction C controls the voltage level, so it can be executed simultaneously with instructions A and B. Therefore, instruction C is not in the same category as instructions A and B. Therefore, when assigning addresses, instruction C will not be in the same address range as instructions A and B.

[0050] It is understandable that the categories here can be completely customized by the user according to the actual working environment. Some instructions that do not exclude each other can be divided into different categories, and those that do exclude each other can be classified into the same category. At the same time, considering the large number of instructions, dividing too many categories may have a counterproductive effect. Therefore, to a certain extent, some non-exclusive instructions can be classified into the same category. In other words, as long as instructions of different categories can be run in parallel, the specific classification can be flexibly set according to the actual situation. This setting can be achieved through a custom communication protocol.

[0051] The corresponding relationship between the instruction and the protocol address can be pre-set through the communication protocol to ensure that the upper computer can store the instruction into the specified protocol address according to the corresponding relationship when assembling the package.

[0052] After receiving the instruction packet, the device can preliminarily determine the address range of the storage control instruction through the information carried in the packet (packet parsing operation is not required at this time), and can determine the category of the instruction in the received instruction packet.

[0053] It should be noted that this step only performs a classification operation and does not perform any parsing. Therefore, it can be considered that a classification operation is performed on the received instruction packet based on the instructions carried, thereby facilitating subsequent parsing.

[0054] Step S200 , allocating the instruction packet to a corresponding type of parallel thread according to the type of the instruction, and caching the instruction packet in a cache space corresponding to the parallel thread.

[0055] Based on the aforementioned classification operation, the instruction packet will be assigned to the corresponding parallel thread according to the grid category, where the parallel thread is a plurality of threads separated for parallel computing, and each thread corresponds to each instruction category one by one.

[0056] The correspondence between parallel threads and categories can also be pre-designed through the communication protocol. For example, category 1 corresponds to thread 1, and so on. If there are several categories, several threads will be generated, thereby realizing parallel processing of multiple instruction packets.

[0057] After receiving the instruction packet, each parallel thread will cache it. Each parallel thread has a corresponding cache space, so instruction packets of different categories will be stored in the cache space corresponding to the parallel thread respectively, and instruction packets of different categories will not be stored in the same cache space.

[0058] It should be noted that the instructions issued by the upper computer are all issued serially, one after another. This embodiment classifies the instruction packets according to categories and caches them through various threads to ensure that these instruction packets will not be discarded even if they cannot be parsed in the first time. At the same time, multiple threads process in parallel to increase the processing efficiency of the instruction packets.

[0059] Among them, after caching the instruction package, you can also output the storage capacity in the current cache space. Because storage resources are not infinite, outputting the storage capacity as a monitoring and debugging method can effectively locate problems when they occur, and provide a basis for further optimizing the storage space size used by each parallel cache logic.

[0060] For example, within a pre-set communication protocol, parameters for storing instruction packets, such as the base frame width of the communication instruction packet, the instruction storage location, and the storage space allocated for the instruction, can be set. The number of instruction categories can also be set, and based on these categories, a corresponding number of communication address segments can be allocated, enabling flexible configuration of instruction packet storage and classification. Furthermore, for different application scenarios, some unused instructions may be removed from the protocol and not categorized. This eliminates the need to allocate communication addresses for these unused instructions, thus saving space.

[0061] Step S300: When the instruction packet is retrieved, it is retrieved from the cache space in sequence according to the order in which it is stored, and the instruction packet is parsed to obtain a corresponding function execution signal, and the function execution signal is output.

[0062] The cache space may store instruction packets in the form of a queue, so that the cached instruction packets may be retrieved in sequence in a first-in-first-out order.

[0063] The purpose of retrieving an instruction packet is to parse it, obtain the instructions, and perform the corresponding operations. Each thread can parse only one instruction packet at a time. Therefore, if a packet is currently being parsed, no instruction packet will be retrieved from the cache. Once a packet is parsed and the parsing task is idle, the oldest instruction packet in the cache will be retrieved and parsed. Parsing the instruction packet retrieves the instructions within it, generating the corresponding execution signals. These execution signals, when combined with the corresponding execution devices, complete the task for the instruction packet.

[0064] It is understandable that each thread operates in parallel, so each instruction packet cached in different cache spaces will be parsed and executed in parallel. Combining the operations of steps S100 and S200, it can be seen that these instruction packets are classified, and instruction packets of different categories are not mutually exclusive and can be executed in parallel, ensuring the efficiency of instruction execution. In addition, when too many instructions are issued too quickly, these instructions can be pre-cached, so that the issued instructions will not be lost and can be executed in the original order.

[0065] When parsing the instruction packet, a communication protocol address storing the instruction in the instruction packet is determined according to the communication protocol.

[0066] The communication protocol sets the frame width and instruction field of the base frame of the communication protocol. The frame width is the byte width of the base frame, such as 1 bit or 2 bits, and the instruction field is the field name indicating the location of the storage instruction, such as "name" or "order".

[0067] During parsing, start from the header of the instruction packet and traverse in units of frame width, traversing one field at a time. Once the corresponding instruction field is found, the location where the instruction is stored is found, and the instruction can be obtained from the instruction field. Once the instruction is located, the specific communication protocol address where the instruction is stored can be obtained.

[0068] In the classification of the aforementioned step S100, only the address segment to which the communication protocol address belongs is determined, while this step determines the communication protocol address of the instruction. Because a communication protocol address corresponds to an instruction one-to-one, a matching verification can be performed based on the communication protocol address to determine whether the type of the instruction and the currently classified thread are correctly corresponding.

[0069] Among them, the correspondence between the types of the above-mentioned instructions and the threads currently classified can be recorded by presetting a function matching table. The function matching table is set synchronously when setting the communication protocol. After obtaining the communication protocol address, it can be determined based on the communication protocol address and the preset function matching table whether the instruction is correctly assigned to the current thread. If so, the corresponding execution signal can be generated according to the instruction.

[0070] Specifically, the communication protocol address of the instruction is compared with the address range of the instruction type corresponding to the current thread in the function matching table. If it falls into the range recorded in the function matching table, it means that the match is successful, otherwise the match fails.

[0071] The execution signal is a signal that controls the corresponding execution device to execute the instruction based on the above-mentioned instruction. The execution device is the downstream device that specifically executes the instruction. For example, a switch signal, the specific switch action is performed by the selected switch device.

[0072] This execution signal needs to be generated by the processing device that receives the instruction and then sent to the specific execution device. For example, the above instructions are often directly executable code instructions, such as "FF". These code instructions also have a one-to-one correspondence with specific execution information. As long as the aforementioned matching operation is successful, the instruction can be directly issued, and the instruction can be automatically matched to the corresponding execution signal output, and then the corresponding operation will be carried out.

[0073] Furthermore, when parsing instructions, if the instruction type is found to be incompatible with the current thread, the packet is discarded and the instruction is not executed. For example, during testing, the host computer may intentionally send a meaningless, erroneous instruction, resulting in an incorrect address. In these cases, packet discard is necessary. Alternatively, if the host computer encounters an error in the packet, packet discard is necessary to prevent simultaneous execution of mutually exclusive instructions, which could cause confusion.

[0074] like Figure 2FIG. 1 is a schematic diagram of the processing flow after the instruction is sent from the host computer in this embodiment.

[0075] The host computer sends instructions to the processing device 100. The instructions are instruction packets issued serially. After receiving these instruction packets, the processing device 100 performs classification operations according to the communication protocol and assigns each instruction packet to different threads for parallel processing. Each thread first caches these instructions, and according to the cache order of each instruction, takes out the instruction packet and performs parsing operations in turn, and then sends it to the corresponding execution device.

[0076] The instruction classification processing method of this embodiment adopts the operation of classifying and buffering instructions before parsing, so that multiple instructions can be processed in parallel without causing blocking and instruction loss, thereby accelerating the response speed. In addition, the number of classifications can be configured to increase or decrease the ability of parallel lines and the cache space can be user-defined. Therefore, it has the characteristics of compatibility, high fault tolerance, and fast communication rate in electronic equipment systems.

[0077] Example 2

[0078] like Figure 3 As shown, this embodiment further provides an instruction classification processing device, including:

[0079] The classification module 10 is used to classify the instructions in the instruction packet when receiving the instruction packet sent by the host computer;

[0080] a cache module 20 for allocating the instruction packets to corresponding types of parallel threads according to the types of the instructions, and caching the instruction packets in cache spaces corresponding to the parallel threads;

[0081] The parsing module 30 is used to sequentially retrieve the instruction packets from the cache space in the order in which they are stored when the instruction packets are retrieved, parse the instruction packets to obtain corresponding function execution signals, and output the function execution signals.

[0082] It can be understood that the apparatus of this embodiment corresponds to the method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0083] The present application also provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the instruction classification processing method.

[0084] The terminal device can be a device with computing capabilities such as a control chip that can receive and interpret instructions from the host computer and then transmit them to the execution device. Examples include memory with a chip, a solid-state drive, a single-chip microcomputer, etc.

[0085] The present application also provides a computer-readable storage medium storing a computer program, which implements the instruction classification processing method when executed on a processor.

[0086] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0087] The memory may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0088] For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0089] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0090] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0091] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0092] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A method for classifying and processing instructions, characterized in that: include: When receiving an instruction packet sent by the host computer, classifying the instructions in the instruction packet; Allocating the instruction packet to a corresponding type of parallel thread according to the type of the instruction, and caching the instruction packet in a cache space corresponding to the parallel thread; When the instruction packet is retrieved, the instruction packets are retrieved from the cache space in order of storage, the instruction packets are parsed to obtain corresponding function execution signals, and the function execution signals are output; When receiving the instruction packet sent by the host computer, classifying the instructions in the instruction packet includes: Receive the instruction packet sent by the host computer, and determine the communication protocol address of the instruction stored in the instruction packet according to the communication protocol; The type of the instruction is determined according to the address segment where the communication protocol address is located.

2. The instruction classification processing method according to claim 1, characterized in that: The step of sequentially retrieving data from the cache space in the order in which the data are stored comprises: If an instruction packet is currently being parsed, pausing to retrieve the instruction packet from the cache space; If no instruction packet is currently parsed, the instruction packet stored first is retrieved from the cache space.

3. The instruction classification processing method according to claim 1, characterized in that: The step of parsing the instruction packet to obtain a corresponding function execution signal includes: Determining, according to the communication protocol, an instruction location in the instruction packet where the instruction is stored, extracting the instruction and determining a corresponding communication protocol address; The instruction is parsed to determine the type of function corresponding to the instruction, and a corresponding execution signal is generated according to the type of function.

4. The instruction classification processing method according to claim 3, characterized in that: After determining the function type corresponding to the instruction, the method further includes: Determining a matching type corresponding to the communication protocol address according to the communication protocol address and a preset function matching table; If the matching type is different from the function type, the current instruction packet is discarded.

5. The instruction classification processing method according to claim 1, characterized in that: After caching the instruction packet into the cache space corresponding to the parallel thread, the method further includes: Outputting the storage capacity status of the cache space to provide debugging information.

6. The instruction classification processing method according to claim 3, characterized in that: The communication protocol sets the frame width and instruction field; The step of determining, according to the communication protocol, an instruction location in the instruction packet where the instruction is stored, extracting the instruction and determining a corresponding communication protocol address includes: Taking the frame width as a unit, count and traverse from the packet header of the instruction packet to find the location of the instruction field, so as to obtain the instruction under the instruction field and the communication protocol address where the instruction is located.

7. An instruction classification processing device, characterized in that: include: A classification module is used to classify the instructions in the instruction packet when receiving the instruction packet sent by the host computer; a cache module, configured to distribute the instruction packets to parallel threads of corresponding categories according to the types of the instructions, and cache the instruction packets in cache spaces corresponding to the parallel threads; a parsing module, configured to, when the instruction packet is retrieved, retrieve the instruction packets from the cache space in order of storage, parse the instruction packets to obtain corresponding function execution signals, and output the function execution signals; When receiving the instruction packet sent by the host computer, classifying the instructions in the instruction packet includes: Receive the instruction packet sent by the host computer, and determine the communication protocol address of the instruction stored in the instruction packet according to the communication protocol; The type of the instruction is determined according to the address segment where the communication protocol address is located.

8. A terminal device, characterized in that: The terminal device includes a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the instruction classification processing method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer program is stored therein, and when the computer program is executed on a processor, the instruction classification processing method according to any one of claims 1 to 6 is implemented.

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