Access method and access device for device register
By creating and optimizing the instruction set and merging multiple instructions of the same type, the system performance problems caused by frequent access to registers by low-speed device are solved, and more efficient register access is achieved, and system performance is improved.
Patent Information
- Application Number
- CN202310781080.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2024-12-31
AI Technical Summary
In computer systems, frequent access to registers of low-speed devices leads to impact system performance, especially in batch operation scenarios where multiple register units share addresses, excessive access times reduce system efficiency.
By creating an instruction set for accessing the device, selecting the execution unit with the minimum execution granularity, and performing merge optimization when multiple instructions of the same type are detected, an optimized execution unit is generated, reducing the number of accesses to low-speed devices.
It effectively reduces the number of accesses to low-speed equipment and improves system performance, especially in batch operation scenarios, and improves register access efficiency.
Smart Images
Figure CN119226180A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a method and device for accessing a device register. Background Art
[0002] The register is the core component of the central processing unit (CPU). It is a high-speed storage component used to temporarily store instructions, data and addresses. When executing instructions, the processor can store the data corresponding to the instructions in the register. The existence of registers greatly speeds up the efficiency of calculation and memory access.
[0003] In the computer system, there are some slow buses such as I2C / SMBus to manage some devices. Users can operate these devices by programming or configuring the registers of the devices under these buses. From the perspective of specific device functions, the configuration of registers often has a relatively fixed pattern: for example, when enabling a certain function of the device, a set of fixed registers need to be configured in a fixed order; when disabling a certain function of the device, a set of fixed registers are also configured in a fixed order. Registers can be roughly divided into two types, one is a register that includes only one register unit, and the register unit exclusively occupies the register address; the other is a register whose storage space is divided into multiple register units, and these register units share the register address. For registers including multiple register units, in the scenario of batch operations on certain functions of the device, such registers may be frequently configured.
[0004] Because it is a slow bus, when accessing the devices under these buses (hereinafter collectively referred to as low-speed devices), the overall performance of the system will be greatly affected. When executing certain batch functional operations, some registers divided into multiple register units will be frequently accessed, which will further affect the performance of the system.
[0005] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. The description herein is not admitted to be prior art as disclosed by inclusion in this section. Summary of the invention
[0006] The purpose of the present application is to provide a method and apparatus for accessing a device register, so as to reduce the number of accesses to low-speed devices and improve system performance.
[0007] The present application discloses a method for accessing a device register, wherein the device is connected to a CPU via a bus, the device comprises a plurality of registers, each register corresponds to a different address, the register comprises one or more register units, and the one or more register units share the address of the register, the access method comprises:
[0008] creating a set of instructions for accessing the device;
[0009] In response to an operation request from the CPU to the device, selecting a corresponding instruction from the instruction set to generate an execution unit of a minimum execution granularity corresponding to the operation request;
[0010] The execution units are detected, and when it is detected that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, the multiple execution units are merged and optimized to generate an optimized execution unit and send the optimized execution unit to the bus.
[0011] In a preferred example, the method further includes: detecting whether register addresses corresponding to the multiple instructions of the same type are marked as optimizable addresses, and when it is determined that the register addresses are optimizable addresses, merging and optimizing the multiple execution units.
[0012] In a preferred example, the merging and optimizing the multiple execution units includes: merging multiple instructions of the same type corresponding to the same register address in the multiple execution units and generating an optimized instruction.
[0013] In a preferred example, the merging and optimizing of the multiple execution units includes: sorting the instructions in the multiple execution units except for multiple instructions of the same type corresponding to the same address and the optimized instructions, so that the relative order between any two instructions in the optimized execution unit is the same as their relative order in the execution unit before optimization.
[0014] In a preferred example, the instructions in the instruction set include an operation field, an address field and a data field.
[0015] In a preferred example, the operation fields and address fields in the multiple instructions of the same type are the same, and the data fields correspond to different register units of the register respectively.
[0016] In a preferred example, the merging of multiple instructions of the same type corresponding to the same register address includes: calculating the data in the data field of the multiple instructions of the same type according to the operation field of the multiple instructions of the same type corresponding to the same register address to obtain the data in the data field of the optimized instruction, and the operation field and address field in the optimized instruction are respectively the same as the operation field and address field in the multiple instructions of the same type.
[0017] In a preferred example, the multiple instructions of the same type are bit operation instructions of the same type.
[0018] In a preferred embodiment, the instruction set is created in a domain specific language.
[0019] The present application also discloses a device for accessing a device register, wherein the device is connected to a CPU via a bus, the device comprises a plurality of registers, each register corresponds to a different address, the register comprises one or more register units, the one or more register units share the address of the register, and the access device comprises:
[0020] An instruction creation module, which creates an instruction set for accessing the device;
[0021] an execution unit generation module, in response to an operation request of the CPU to the device, selecting a corresponding instruction from the instruction set to generate an execution unit of a minimum execution granularity corresponding to the operation request;
[0022] The interpreter module detects the execution units, and when it is detected that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, the multiple execution units are merged and optimized to generate an optimized execution unit and send the optimized execution unit to the bus.
[0023] In an implementation manner of the present application, an instruction set for accessing a device is created. When operating the device, a corresponding instruction is selected from the instruction set and an execution unit with the minimum execution granularity corresponding to the operation request is generated. When it is detected that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, the multiple execution units are merged and optimized and an optimized execution unit is generated and sent to the bus. This can reduce the number of low-speed device accesses and improve system performance.
[0024] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 It is a schematic diagram of the structure of a device register according to an embodiment of the present application.
[0026] Figure 2 It is a flowchart of a method for accessing a device register according to an embodiment of the present application.
[0027] Figure 3 It is a schematic diagram of configuring a device register according to an embodiment of the present application.
[0028] Figure 4 Schematic diagram of performing multiple configuration operations on device registers according to an embodiment of the present application
[0029] Figure 5 It is a schematic diagram before and after the merger of multiple execution units according to an embodiment of the present application.
[0030] Figure 6 It is a structural diagram of a device register access apparatus according to an embodiment of the present application. DETAILED DESCRIPTION
[0031] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0033] An embodiment of the present application relates to a method for accessing a device register, wherein the device is connected to a CPU via a bus, and the device includes a plurality of registers, each register corresponding to a different address. It should be noted that the device described herein refers to a low-speed device based on a slow protocol (for example, I2C, SPI, and other protocols). From the perspective of register organization, the registers included in the low-speed device can be divided into two categories, one is a register including only one register unit, and the register unit occupies an exclusive address. This type of register is also referred to as a register occupying an independent addressing unit. The other type is a register including multiple register units, and the multiple register units share an address. Each register unit only occupies one or several bits of the register. This type of register is also referred to as a register sharing an addressing unit. Figure 1 As shown, suppose a low-speed device includes registers A, B, C, D, and E. The corresponding addresses of these registers are 0xA, 0xB, 0xC, 0xD, and 0xE respectively. Among them, registers A, B, C, and D only include one register unit, and this register unit exclusively occupies the address of the register. In other words, registers A, B, C, and D belong to registers that occupy independent addressing units. Register E includes 6 register units, namely E0, E1, E2, E3, E4, and E5. These register units share the address of register E. It can be understood that Figure 1 This is only for illustration. In actual applications, the number of registers included in each slow device, the number of register units included in the register, etc. can be set as needed.
[0034] The process of the device register access method of the present application embodiment is as follows: Figure 2 As shown, the method includes:
[0035] Step 101: Create an instruction set for accessing a device.
[0036] In one embodiment, an instruction set is created in a domain specific language (DSL), that is, a set of instructions defined for accessing device registers. The instruction set may include but is not limited to the following instructions: write instructions, read instructions, bit operation instructions (e.g., or instructions, and instructions), no-operation instructions, etc. Table 1 lists some instructions and briefly describes the meanings of these instructions.
[0037]
[0038] Table 1 Examples of some instructions in the DSL instruction set
[0039] It can be seen that most instructions include an operation field, an address field and a data field. Take the instruction "REG_WRITEreg_x,data" as an example, where "REG_WRITE" is the operation field, used to indicate the type of operation (i.e., a write operation), "reg_x" is the address field, used to indicate the address of the operation, and "data" is the data field, which is the object being operated.
[0040] Step 102 : In response to the CPU's operation request for the device, select an instruction for implementing the operation request from an instruction set to generate an execution unit with a minimum execution granularity corresponding to the operation request.
[0041] refer to Figure 1 as well as Figure 3 , for example, enable Figure 1 A function of a low-speed device in the Figure 3 The configuration operations shown. This set of operations is necessary to enable the function, and this set of operations can be called the minimum execution granularity for enabling the function. The above is just an example of the minimum execution granularity of the operation request. Enabling or disabling different functions requires different configuration operations.
[0042] When receiving an operation request from the CPU for a low-speed device (such as enabling a function of the low-speed device), a corresponding instruction can be selected from the created instruction set to form an execution unit with the minimum execution granularity corresponding to the operation request. Figure 1 as well as Figure 3 For example, each register unit (E0, E1, E2, ...) in register E can be a 1-bit register unit, and the operation of clearing a register (or register unit) is to set the value of the register (or register unit) to 0, and the operation of setting a register (or register unit) is to set the value of the register (or register unit) to 1. After describing each operation in the above minimum execution granularity by using the instructions in the instruction set, the following can be obtained: Figure 3 The set of instructions shown constitutes an execution unit.
[0043] It can be seen that the embodiment of the present application uses the corresponding instructions in the above instruction set to "describe" the configuration operation of the register. Each set of instructions describing the "minimum execution granularity" constitutes an execution unit.
[0044] Step 103, detecting the execution units, and when detecting that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, merging and optimizing the multiple execution units to generate an optimized execution unit, and sending the optimized execution unit to the bus.
[0045] In the scenario where there is only one execution unit, since the execution unit corresponds to the "minimum execution granularity", each instruction in the execution unit points to the address of a different register, and the instructions in the execution unit cannot be merged for execution. Therefore, for the scenario with a single execution unit, the instructions in the execution unit can be directly sent to the bus in the execution order, and the bus transmits them to the corresponding low-speed device. In the scenario where there are multiple execution units (such as the scenario of batch operations on certain functions), there may be multiple instructions of the same type pointing to the address of the same register. At this time, if the multiple instructions of the same type can be merged for execution, the number of accesses to the register can be reduced, thereby improving the performance of the system. For example, when enabling Figure 1 When the three groups of functions of the low-speed device in Figure 4 The three groups of operations shown in the figure are executed from top to bottom. The three groups of operations can be converted into the following using the instructions in the instruction set: Figure 4 The three execution units shown in the figure, namely the first execution unit, the second execution unit, and the third execution unit, are executed sequentially from top to bottom, and the instructions in each execution unit are also executed sequentially according to the sequence of their sequence numbers. For example, each execution unit includes three instructions I, II, and III, and the three instructions I, II, and III in each execution unit are executed sequentially in the order of the first, second, and third execution units, and a total of 9 instructions need to be executed.
[0046] It can be seen that the I instructions in the above three execution units, namely "REG_AND E_addr, 0x1E", "REG_AND E_addr, 0x1D", and "REG_AND E_addr, 0x1B", all have the operation field "REG_AND", the address field "0xE", and the data field corresponds to different register units of register E. These three instructions are multiple instructions of the same type pointing to the same register address. Similarly, the III instructions in the above three execution units, namely "REG_OR E_addr, 0x1", "REG_OR E_addr, 0x2", and "REG_OR E_addr, 0x4", also belong to multiple instructions of the same type pointing to the same register address.
[0047] When there are multiple execution units, and there are multiple instructions of the same type pointing to the same register address in the multiple execution units, after determining that these instructions meet the optimization rules, these instructions of the same type are merged and optimized to form a merged optimized instruction (also referred to as "merged instruction" or "optimized instruction" in this article). Judging whether the instruction meets the optimization rules includes judging whether the merging of these instructions will affect the final execution effect. Taking the above three execution units as an example, assuming that the multiple instructions of the same type pointing to the same register address in the above three execution units can be merged and optimized, the merged execution unit is as follows: Figure 5 As shown, the 9 instructions before merging become 5 instructions after merging, wherein the positions of the merged instructions can be filled with NOP, which is a no-operation and does not perform any operation, and may not be counted in the number of instructions in the embodiments of the present application.
[0048] Among them, the first instruction in the three execution units, namely "REG_AND E_addr, 0x1E", "REG_AND E_addr, 0x1D", and "REG_AND E_addr, 0x1B", are merged into the instruction "REG_AND E_addr, 0x18". For the instruction REG_AND, the data values 0x1E, 0x1D, and 0x1B in the data fields of the three instructions before the merger are ANDed to obtain the data value 0x18 of the data field in the merged instruction. It can be understood that the operation field and address field of the merged instruction are the same as the operation field and address field of the three instructions before the merger, and the data field of the merged instruction is calculated based on the data fields (i.e., 0x1E, 0x1D, 0x1B) of the three instructions before the merger, so as to ensure that the result of the operation on the data field after the merger is equal to the result of the operation on the data field of each instruction before the merger. Similarly, the instructions III "REG_OR E_addr, 0x1", "REG_OR E_addr, 0x2", and "REG_OR E_addr, 0x4" of the three execution units are merged into the instruction "REG_OR E_addr, 0x7". For the OR instruction REG_OR, the data values 0x1, 0x2, and 0x4 in the data fields of the three instructions before the merge are ORed to obtain the data value 0x7 of the data field in the merged instruction.
[0049] After the merge optimization, the execution order of each instruction has changed. For example, the instruction I (REG_AND E_addr, 0x1D) in the second execution unit before the merge was originally executed at the 4th place, but after the merge, it was merged to the 1st place. Similarly, the instruction III in the first execution unit before the merge was originally executed at the 3rd place, but after the merge, it was executed at the last place.
[0050] However, it is not difficult to find that the relative order of instructions in each execution unit before merging remains unchanged after merging. Figure 5 As shown in the figure, the execution order of the three instructions in the second execution unit before merging is 4, 5, and 6 respectively. After merging, although the execution order becomes 1, 3, and 5, the relative order remains unchanged.
[0051] Whether this sequential characteristic will affect the final execution effect is determined by the optimization rules. Specifically, the embodiment of the present application predefines a set of optimization rules according to the characteristics of each chip / device, and each register address is marked in the optimization rule. If a register address is marked as an optimizable address, it indicates that the merge optimization of multiple instructions of the same type pointing to the register address will not affect the final execution effect. For example, as long as the relative order in which the instructions of each execution unit are executed after the merger remains unchanged, the expected execution effect can still be produced. Therefore, after detecting the existence of multiple instructions of the same type pointing to the same register address, the embodiment of the present application can check the optimization rules to determine whether the register addresses corresponding to the multiple instructions of the same type are marked as optimizable, and when it is determined that the register address is an optimizable address, the merge optimization is performed.
[0052] In some embodiments, the above-mentioned same type of instructions may include bit operation instructions, such as or instructions, and instructions, shift instructions, etc. That is to say, the embodiment of the present application may choose to merge and optimize multiple bit operation instructions of the same type pointing to the same register address. Figure 4 , Figure 5 The process of merging and optimizing the OR instruction and the AND instruction is described in detail. The merging process of other instructions is similar and will not be described again here.
[0053] like Figure 4 , Figure 5 As shown, before the merger, the Ith instruction in the three execution units belongs to three instructions of the same type (the operation fields are all REG_AND) pointing to the same register address (the address of register E) (all are AND instructions), and the IIIth instruction in the three execution units belongs to three instructions of the same type (the operation fields are all REG_OR) pointing to the same register address (the address of register E) (all are OR instructions). If the register address (the address of register E) has been marked as optimizable in the optimization rules, the Ith instruction in the three execution units can be merged and optimized, and the IIIth instruction in the three execution units can be merged and optimized at the same time. That is to say, the Ith instruction and the IIIth instruction in the three execution units are both instructions to be merged.
[0054] Before merging, first record the predecessor instructions (instructions executed before the instruction to be merged) and successor instructions (instructions executed after the instruction to be merged) of the instructions to be merged in each execution unit. For example, in the first execution unit, there is no predecessor instruction for instruction I, and its successor instructions are instructions II and III. The predecessor instructions of instruction III are instructions I and II, and there is no successor instruction. Similarly, in the second execution unit, there is no predecessor instruction for instruction I, and its successor instructions are instructions II and III. The predecessor instructions of instruction III are instructions I and II, and there is no successor instruction. In the third execution unit, there is no predecessor instruction for instruction I, and its successor instructions are instructions II and III. The predecessor instructions of instruction III are instructions I and II, and there is no successor instruction.
[0055] Afterwards, the instructions to be merged are merged to generate a merged OR instruction. Among them, the operation field and address field of the merged OR instruction are the same as the operation field and address field of the OR instruction before the merger, and the data field of the merged OR instruction is generated according to the data fields of all the OR instructions before the merger. Taking the III instruction in the above three execution units as an example, the III instruction in the three execution units is the three OR instructions to be merged. The masks of the three OR instructions can be obtained first, and the masks of all the OR instructions obtained are ORed to generate the merged mask, which is the merged mask. The data field of the merged OR instruction. It can be seen that the instruction after the three instructions are merged is "REG_ORE_addr, 0x7". The merging process of the AND instruction is similar to this, and it will not be repeated here. The instruction after the I instruction in the above three execution units (i.e., the three AND instructions to be merged) is merged is "REG_AND E_addr, 0x18".
[0056] Next, according to the order of the execution units and the relative order between the instructions in each execution unit, all the preceding instructions can be moved before the merged instruction, and all the following instructions can be moved after the merged instruction, so as to form a merged execution unit. For example, for the Ith instruction in the above three execution units, it has no preceding instruction, so the instruction after the merger of the Ith instruction in the above three execution units ranks first, and for the IIIth instruction in the above three execution units, it has no following instruction, so the instruction after the merger of the IIIth instruction in the above three execution units ranks last, and the remaining three instructions (i.e., the IIth instruction in the three execution units) are the following instructions of the Ith instruction in the above three execution units, and are the preceding instructions of the IIIth instruction in the above three execution units, so the remaining three instructions are ranked between the first and the last, and considering the order of the execution units, it can be obtained. Figure 5The merged execution unit.
[0057] Specifically, after merging and optimizing multiple instructions of the same type pointing to the same register address, it is also necessary to sort the instructions in the multiple execution units except for the multiple instructions of the same type corresponding to the same address (i.e., the instructions that did not participate in the merge optimization) and the merged instructions formed after the merge optimization according to the order of each execution unit and the relative order between the instructions in each execution unit, so as to ensure that the relative order between the instructions remains unchanged.
[0058] The embodiment of the present application relates to a device register access apparatus, wherein the device is connected to a CPU via a bus, the device comprises a plurality of registers, each register corresponds to a different address, the register comprises one or more register units, and the one or more register units share the address of the register, and the structure of the access apparatus is as follows: Figure 6 As shown, the access device includes: an instruction creation module 601, an execution unit generation module 602, and an interpreter module 603. The instruction creation module 601 creates an instruction set for accessing the device. In response to the CPU's operation request for the device, the execution unit generation module 602 selects the corresponding instruction from the instruction set to generate an execution unit with the minimum execution granularity corresponding to the operation request. The interpreter module 603 detects the execution unit, and when it is detected that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, the multiple execution units are merged and optimized, and an optimized execution unit is generated and sent to the bus.
[0059] This embodiment is a device embodiment corresponding to the above-mentioned method embodiment. The technical details in the above-mentioned method embodiment can be applied to this embodiment, and the technical details in this embodiment can also be applied to the above-mentioned method embodiment.
[0060] From the above, it can be seen that compared with the traditional bus access in which the access request to the register (configuration operation) is directly sent to the bus, in the scenario of batch operation, it may be necessary to frequently access certain registers including multiple register units, thereby reducing the performance of the system. The present application first uses a predefined instruction set to convert the access request to the register into an instruction, and then merges and optimizes some instructions according to the characteristics of the instructions, and then sends the optimized instructions to the bus. This approach greatly reduces the number of accesses to the corresponding registers and improves the performance of the system.
[0061] It should be noted that those skilled in the art should understand that the implementation functions of each module shown in the implementation of the access device of the device register can be understood with reference to the relevant description of the access method of the device register. The functions of each module shown in the implementation of the access device of the device register can be implemented by a program (executable instruction) running on a processor, or by a specific logic circuit. If the access device of the device register of the embodiment of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM, ReadOnlyMemory), a disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific combination of hardware and software.
[0062] Accordingly, the present application also provides a computer-readable storage medium in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media do not include temporary computer-readable media (transitory media), such as modulated data signals and carriers.
[0063] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.
[0064] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.
[0065] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims
1. A method for accessing a device register, characterized in that: The device is connected to the CPU via a bus, the device includes a plurality of registers, each register corresponds to a different address, the register includes one or more register units, the one or more register units share the address of the register, and the access method includes: creating an instruction set for accessing the device; In response to an operation request from the CPU to the device, selecting a corresponding instruction from the instruction set to generate an execution unit of a minimum execution granularity corresponding to the operation request; The execution units are detected, and when it is detected that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, the multiple execution units are merged and optimized to generate an optimized execution unit and send the optimized execution unit to the bus.
2. The access method according to claim 1, characterized in that: The method further includes: detecting whether register addresses corresponding to the multiple instructions of the same type are marked as optimizable addresses, and when it is determined that the register addresses are optimizable addresses, merging and optimizing the multiple execution units.
3. The access method according to claim 1, characterized in that: The merging and optimizing the multiple execution units includes: merging multiple instructions of the same type corresponding to the same register address in the multiple execution units and generating an optimized instruction.
4. The access method according to claim 3, characterized in that: The merging and optimizing of the multiple execution units includes: sorting the instructions in the multiple execution units except for multiple instructions of the same type corresponding to the same address and the optimized instructions, so that the relative order between any two instructions in the optimized execution unit is the same as their relative order in the execution unit before optimization.
5. The access method according to claim 3, characterized in that: The instructions in the instruction set include an operation field, an address field and a data field.
6. The access method according to claim 5, characterized in that: The operation fields and address fields in the multiple instructions of the same type are the same, and the data fields correspond to different register units of the register respectively.
7. The access method according to claim 5, characterized in that: The merging of multiple instructions of the same type corresponding to the same register address includes: calculating the data in the data field of the multiple instructions of the same type corresponding to the same register address according to the operation field of the multiple instructions of the same type to obtain the data in the data field of the optimized instruction, and the operation field and address field in the optimized instruction are respectively the same as the operation field and address field in the multiple instructions of the same type.
8. The access method according to claim 7, characterized in that: The multiple instructions of the same type are bit operation instructions of the same type.
9. The access method according to claim 1, characterized in that: The instruction set is created in a domain specific language.
10. A device for accessing a device register, characterized in that: The device is connected to the CPU via a bus, the device includes a plurality of registers, each register corresponds to a different address, the register includes one or more register units, the one or more register units share the address of the register, and the access device includes: An instruction creation module, which creates an instruction set for accessing the device; an execution unit generation module, in response to an operation request of the CPU to the device, selecting a corresponding instruction from the instruction set to generate an execution unit of a minimum execution granularity corresponding to the operation request; The interpreter module detects the execution units, and when it is detected that there are multiple execution units corresponding to the same operation request and the multiple execution units include multiple instructions of the same type corresponding to the same register address, the multiple execution units are merged and optimized to generate an optimized execution unit and send the optimized execution unit to the bus.