Computing accelerators for MCU chips, MCU chips

Abstract

A computing accelerator for an MCU chip and an MCU chip, the computing accelerator receives a computing instruction from a central processing unit and requests the central processing unit to read the execution result of the computing instruction; if the computing instruction is a single combined instruction, the computing accelerator maps the single combined instruction into multiple basic computing instructions and executes the multiple basic computing instructions to obtain the execution result. The computing accelerator provided by the present application can reduce the bus occupancy problem caused by the frequent reading and writing of the central processing unit to the general digital signal processing module in the traditional MCU chip, which is conducive to improving the processing efficiency of the MCU chip.

Description

Technical Field

[0001] The present invention relates to the technical field of microprocessors, and in particular to a microprocessor. Background Art

[0002] A microcontroller unit (MCU) chip is a single chip that integrates a processor, a memory device, an input / output (I / O) port, and other functions. MCU chips are widely used in home appliance control, automotive electronics, industrial automation, and other fields. At present, the mainstream uses general-purpose MCU chips to implement control functions. In general-purpose MCU chips, control and calculation are all completed by the central processing unit (CPU) in the MCU chip. This type of MCU has a large calculation delay and low processing efficiency. Summary of the invention

[0003] The technical problem to be solved by the embodiments of the present application is how to improve the processing efficiency of the MCU chip.

[0004] To solve the above technical problems, an embodiment of the present application provides a computing accelerator, which receives a computing instruction from a central processing unit and requests the central processing unit to read the execution result of the computing instruction; if the computing instruction is a single combined instruction, the computing accelerator maps the single combined instruction into multiple basic computing instructions, and executes the multiple basic computing instructions to obtain the execution result.

[0005] Optionally, the computing accelerator is a digital signal processor.

[0006] Optionally, if the operation instruction is the basic operation instruction, the operation accelerator executes the basic operation instruction to obtain the execution result.

[0007] Optionally, the multiple basic operation instructions include instructions for at least one of the following basic operations: division operation, square root operation, trigonometric function operation, hyperbolic function operation, shift operation, saturation operation, truncation operation, branch jump, immediate number construction, data movement, blocking operation, interrupt operation, response operation, and trigger operation.

[0008] Optionally, if the combined instruction is a first combined instruction, the operation performed by the operation accelerator is an algorithm-level operation; if the combined instruction is a second combined instruction, the operation performed by the operation accelerator is an intermediate operation; wherein the intermediate operation includes multiple basic operations, and the algorithm-level operation includes multiple intermediate operations and multiple basic operations.

[0009] Optionally, the intermediate operation includes at least one of the following: coordinate transformation operation, space vector pulse width modulation, PID regulation, filtering operation, back electromotive force observation, rotation speed estimation, and angle estimation.

[0010] Optionally, the algorithm-level operation includes: a magnetic field oriented control algorithm and / or a commutation control algorithm.

[0011] Optionally, the magnetic field oriented control algorithm includes at least one of the following: a sensorless magnetic field oriented control algorithm, an encoder-based magnetic field oriented control algorithm, and a Hall position sensor-based magnetic field oriented control algorithm.

[0012] Optionally, the computing accelerator is used for motor control.

[0013] Optionally, the computing accelerator is a multi-issue structure.

[0014] The embodiment of the present application also provides an MCU chip, including: a central processing unit, and the above-mentioned computing accelerator.

[0015] Compared with the prior art, the technical solution of the embodiment of the present application has the following beneficial effects:

[0016] In the scheme of the embodiment of the present application, the operation accelerator receives the operation instruction from the CPU and requests the CPU to read the execution result of the operation instruction. In the scheme of the embodiment of the present application, the operation instruction can be a single combination instruction. If the operation instruction is a single combination instruction, the operation accelerator maps the single combination instruction to multiple basic operation instructions, and executes multiple basic operation instructions to obtain the execution result of the single combination instruction. In the above scheme, the operation accelerator maps the single combination instruction to multiple basic operation instructions, and then requests the CPU to read the execution result of the single combination instruction. The CPU does not need to send basic operation instructions to the operation accelerator one by one, and wait for the execution result of the single basic operation instruction, and then send the next basic operation instruction. Therefore, the scheme of the embodiment of the present application effectively reduces the number of times the CPU reads and writes the operation accelerator, thereby reducing the bus occupancy caused by the frequent reading and writing of the CPU to the operation accelerator, which is conducive to improving the processing efficiency of the MCU chip.

[0017] Further, in the scheme of the embodiment of the present application, the combined instruction includes a first combined instruction and a second combined instruction, the operation corresponding to the first combined instruction is an algorithm-level operation, the operation corresponding to the second combined instruction is an intermediate operation, the intermediate operation includes multiple basic operations, and the algorithm-level operation includes multiple intermediate operations and multiple basic operations. That is, the scheme of the embodiment of the present application provides combined instructions of multiple granularities, and users can flexibly select operation instructions of appropriate granularity according to actual needs. Therefore, the scheme provided by the embodiment of the present application can take into account the flexibility and operation speed of the MCU chip.

[0018] Furthermore, in the solution of the embodiment of the present application, the computing accelerator is a multi-issue structure, which is conducive to optimizing the execution order of instructions, improving the efficiency of the computing accelerator in executing instructions, and thus improving the computing speed of the MCU chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the hardware architecture of an MCU chip in an embodiment of the present application;

[0020] Figure 2 It is a schematic diagram of the relationship between a combination instruction and a basic operation instruction in an embodiment of the present application;

[0021] Figure 3 It is a schematic diagram of the architecture of the instruction set in the embodiment of the present application;

[0022] Figure 4 It is a schematic diagram of the relationship between another combination instruction and basic operation instructions in an embodiment of the present application. DETAILED DESCRIPTION

[0023] As described in the background art, the processing efficiency of current MCU chips needs to be improved.

[0024] In order to improve the processing efficiency of the MCU chip, it is possible to consider introducing an operation accelerator for the CPU of the MCU chip. In this MCU chip, the MCU chip includes a CPU and an operation accelerator. The CPU assigns part of the operation tasks to the operation accelerator for execution to improve the overall processing efficiency of the MCU chip. In order to take into account the development flexibility and processing efficiency of the MCU chip, in the MCU with a built-in operation accelerator, the CPU usually operates the operation accelerator in a fine-grained manner. In other words, the instructions sent by the CPU to the operation accelerator are all basic operation instructions, such as addition instructions, multiplication instructions, division instructions, subtraction instructions, sine function (sin) instructions, etc. In the case where the CPU needs the operation accelerator to perform a more complex operation task, the above solution requires the CPU to communicate with the operation accelerator frequently, resulting in long-term bus occupancy, and the overall processing efficiency of the MCU still needs to be improved.

[0025] In one example, the CPU expects the computing task to be implemented by the computing accelerator to be sin((A+B)*C). The communication between the CPU and the computing accelerator includes the following:

[0026] Step 1. The CPU sends the operand A required for addition to the computation accelerator;

[0027] Step 2. The CPU sends the operand B required for addition to the computation accelerator;

[0028] Step 3. The CPU sends an addition instruction to the computing accelerator;

[0029] Step 4. The computing accelerator requests the CPU to read the result; for example, the computing accelerator requests the CPU to read the result in the form of an interrupt or bus back pressure;

[0030] Step 5. The CPU reads the result of (A+B) from the computing accelerator;

[0031] Step 6. The CPU sends the operands required for multiplication (A+B) to the computing accelerator;

[0032] Step 7. The CPU sends the operand C required for multiplication to the computing accelerator;

[0033] Step 8. The CPU sends a multiplication instruction to the computing accelerator;

[0034] Step 9. The computing accelerator requests the CPU to read the result;

[0035] Step 10. The CPU reads the result of (A+B)*C from the computing accelerator;

[0036] Step 11. The CPU sends the operand (A+B)*C required by sin to the computing accelerator;

[0037] Step 12. The CPU sends a sin execution instruction to the computing accelerator;

[0038] Step 13. The computing accelerator requests the CPU to read the result;

[0039] Step 14. The CPU reads the result of sin((A+B)*C) from the computing accelerator.

[0040] From the above, it can be seen that when the CPU needs an operation accelerator to perform a more complex operation task, the above solution requires the CPU to communicate with the operation accelerator frequently, resulting in long-term bus occupancy, thereby causing the MCU chip to operate at a slower speed.

[0041] In view of this, in the scheme of the embodiment of the present application, the operation accelerator receives the operation instruction from the CPU and requests the CPU to read the execution result of the operation instruction. The operation instruction can be a single combined instruction. If the operation instruction is a single combined instruction, the operation accelerator maps the single combined instruction to multiple basic operation instructions, and executes multiple basic operation instructions to obtain the execution result of the single combined instruction. In the above scheme, the operation accelerator supports the execution of combined instructions. The operation accelerator maps the single combined instruction to multiple basic operation instructions, and then requests the CPU to read the execution result of the single combined instruction. The CPU does not need to send basic operation instructions to the operation accelerator one by one, and wait for the execution result of the single basic operation instruction, and then send the next basic operation instruction. Therefore, the scheme of the embodiment of the present application effectively reduces the number of times the CPU reads and writes the operation accelerator, thereby reducing the bus occupancy caused by the frequent reading and writing of the CPU to the operation accelerator, which is conducive to improving the processing efficiency of the microcontroller.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Reference Figure 1 , Figure 1 Schematic diagram of the hardware architecture of an MCU chip in the embodiment of the present application. Figure 1 As shown, the MCU chip 10 may include: a CPU 101, a computing accelerator 102, and a bus 103. For example, the MCU chip 10 may be used for motor control. In this case, the "computing accelerator" may be referred to as a "motor control accelerator". For example, the MCU chip 10 may be used for temperature control, etc. This embodiment does not limit the application field of the MCU chip 10.

[0044] In one embodiment of the present application, the computing accelerator 102 may be a digital signal processor (DSP). In other embodiments, the computing accelerator 102 may also be other devices, modules or apparatuses having data transmission, reception and data processing functions, which are not limited in this embodiment.

[0045] like Figure 1 As shown, CPU 101 and computing accelerator 102 can communicate via bus 103. Specifically, CPU 101 can send computing instructions to computing accelerator 102, computing accelerator 102 can execute the computing instructions, and after the computing instructions are executed, request CPU 101 to read the execution result of the computing instructions.

[0046] In the solution of the embodiment of the present application, the operation instruction sent by the CPU 101 can be a combination instruction or a basic operation instruction. That is, the operation accelerator 102 supports the combination instruction and also supports the basic operation instruction. Among them, the orthogonality of the basic operation instruction is better than the orthogonality of the combination instruction.

[0047] Specifically, the basic operation instruction refers to an instruction for executing a basic operation. In an embodiment of the present application, the basic operation may be an operation of the smallest granularity executed by the operation accelerator 102 .

[0048] Exemplarily, the basic operation may include at least one of the following: division operation, square root operation, trigonometric function operation, hyperbolic function operation, shift operation, saturation operation, truncation operation, branch jump, immediate number construction, data movement, blocking operation, interrupt operation, response operation, trigger operation. In other embodiments, it may also be other operations defined by the developer of MCU10.

[0049] If the operation instruction sent by CPU 101 is a single basic operation instruction, the operation accelerator 102 executes the basic operation instruction, and after the execution of the basic operation instruction is completed, requests CPU 101 to read the result of executing the basic operation instruction.

[0050] As described above, the computing accelerator 102 in the embodiment of the present application also supports combined instructions. Specifically, if the computing instruction sent by the CPU 101 is a single combined instruction, the computing accelerator 102 maps the single combined instruction to multiple basic computing instructions, and executes the multiple basic computing instructions, thereby obtaining the execution result of the single combined execution. In addition, the CPU 101 also sends the operands required for the combined instruction to the computing accelerator 102.

[0051] In a specific implementation, the mapping relationship between each combined instruction and the basic operation instruction is pre-configured in the computing accelerator 102. Therefore, whenever the computing accelerator 102 receives a combined instruction, the computing accelerator 102 can determine the multiple basic operation instructions corresponding to the combined instruction based on the mapping relationship between the combined instruction and the basic operation instruction, and execute the corresponding multiple basic operation instructions in sequence to obtain the execution result of the combined instruction.

[0052] Reference Figure 2 , Figure 2 Schematic diagram of the relationship between a combination instruction and a basic operation instruction in the embodiment of the present application. Figure 2 As shown, the computing accelerator 102 is pre-configured with a mapping relationship between the combined instruction 1 and (n+1) basic computing instructions. After receiving the combined instruction 1, the computing accelerator 102 performs the mapping according to Figure 2According to the mapping relationship shown, the computing accelerator 102 can determine the (n+1) basic computing instructions (basic computing instruction 0, basic computing instruction 1, basic computing instruction 2, ... basic computing instruction n) corresponding to the combined instruction 1, where n is a positive integer. Then, the computing accelerator 102 sequentially executes the (n+1) basic computing instructions corresponding to the combined instruction 1, thereby obtaining the execution result of the combined instruction 1.

[0053] In one example, the CPU 101 expects the computing task to be implemented by the computing accelerator 102 to be sin((A+B)*C), and the communication between the CPU 101 and the computing accelerator 102 includes the following:

[0054] Step A: CPU 101 sends operand A required for the computing task sin((A+B)*C) to computing accelerator 102;

[0055] Step B: CPU 101 sends operand B required for the computing task sin((A+B)*C) to computing accelerator 102;

[0056] Step C: CPU 101 sends operand C required for the computing task sin((A+B)*C) to computing accelerator 102;

[0057] Step D: CPU 101 sends an M instruction to the computing accelerator 102, where the M instruction is used to instruct the computing accelerator to implement a sin((A+B)*C) operation;

[0058] Step E: The computing accelerator 102 requests the CPU 101 to read the result of the operation of sin((A+B)*C). For example, the computing accelerator 102 may request the CPU 101 to read the result in the form of an interrupt or bus back pressure;

[0059] Step F: CPU 101 reads the calculation result of sin((A+B)*C) from the calculation accelerator 102 .

[0060] Specifically, after receiving the M instruction, the computing accelerator 102 determines that the multiple basic computing instructions corresponding to the M instruction are: addition instruction, multiplication instruction and sin instruction in sequence. The computing accelerator 102 executes the multiple basic computing instructions corresponding to the M instruction in sequence, thereby obtaining the result of sin((A+B)*C), and requests the CPU 101 to read the result of sin((A+B)*C), and the CPU 101 responds to the request and reads the result of sin((A+B)*C).

[0061] It can be seen from the above that the solution of the present application can reduce the bus occupancy caused by the CPU's frequent reading and writing of the computing accelerator, which is beneficial to improving the computing speed of the microcontroller.

[0062] Furthermore, in the solution of the embodiment of the present application, the computing accelerator 102 supports combination instructions of multiple granularities, the CPU 101 can send combination instructions of multiple granularities to the computing accelerator 102, and the user of the MCU 10 can select the appropriate combination instruction according to actual needs.

[0063] Specifically, the combined instruction may be a first combined instruction, and the operation task corresponding to the first combined instruction is an algorithm-level operation. For example, MCU10 is applied to motor control, and the operation task corresponding to the first combined instruction is a field-oriented control (FOC) algorithm or a commutation control algorithm. Among them, the FOC algorithm may be any of the following: a sensorless FOC algorithm, an encoder-based FOC algorithm, or a Hall position sensor-based FOC algorithm.

[0064] More specifically, CPU 101 sends a first combination instruction to the computing accelerator 102, and the computing accelerator 102 executes multiple basic computing instructions corresponding to the first combination instruction to complete the algorithm-level operation and requests CPU 101 to read the result of the algorithm-level operation.

[0065] For example, the CPU 101 sends a K instruction to the computing accelerator 102, and the K instruction is used to instruct the computing accelerator 102 to execute the sensorless FOC algorithm. In addition, the CPU 101 also sends the operands required by the sensorless FOC algorithm to the computing accelerator 102. The computing accelerator 102 executes a plurality of basic computing instructions corresponding to the sensorless FOC algorithm, thereby obtaining the execution result of the sensorless FOC algorithm.

[0066] In addition, the combined instruction may also be a second combined instruction, and the operation corresponding to the second combined instruction is an intermediate operation. In the solution of the embodiment of the present application, the intermediate operation includes multiple basic operations, and the algorithm-level operation may include multiple intermediate operations. That is, the complexity of the intermediate operation corresponding to the second combined instruction is between the algorithm-level operation and the basic operation. In addition, the algorithm-level operation may include multiple intermediate operations and multiple basic operations.

[0067] For example, the MCU chip 10 is applied to motor control, and the second combination of instructions supported by the computing accelerator 102 may include instructions for at least one of the following intermediate operations: coordinate transformation operation, space vector pulse width modulation (Space Vector Pulse Width Modulation, SVPWM), PID regulation, filtering operation, back-EMF observation, speed estimation, angle estimation. Among them, the coordinate transformation operation can be: Park transformation operation, inverse Park transformation operation, Clarke transformation operation, inverse Clarke transformation operation. PID regulation can be: a standard three-channel PI loop, a series three-channel PI loop, a parallel three-channel PI loop, etc. Back-EMF observation can be: back-EMF observation based on sliding membrane, back-EMF observation based on Romberg observer, and back-EMF observation based on direct estimation of flux linkage. Speed ​​and angle estimation can be based on inverse tangent or based on a phase-locked loop (Phase Locked Loop, PLL).

[0068] As can be seen from the above, in the solution of this embodiment, the basic operation instruction can be a fine-grained operation instruction, the second combination instruction can be a medium-grained operation instruction, and the first combination instruction can be a coarse-grained operation instruction. The operation accelerator 102 supports instructions of multiple granularities, wherein the coarser the granularity of the instruction, the more basic operations a single instruction corresponds to.

[0069] Reference Figure 3 , Figure 3 Schematic diagram of an instruction set architecture in an embodiment of the present application. Figure 3 As shown, the instruction set of the computing accelerator 102 may include a basic computing instruction, a second combination instruction, and a first combination instruction. Specifically, the second combination instruction may be mapped to a plurality of basic computing instructions, and the first combination instruction may be mapped to a plurality of second combination instructions. In other words, the second combination instruction may be an instruction block composed of a plurality of basic computing instructions, and the first combination instruction may be an instruction block composed of a plurality of second combination instructions.

[0070] In one embodiment, the first combination instruction may be mapped to a plurality of second combination instructions and a plurality of basic operation instructions. Wherein, each second combination instruction corresponding to the first combination instruction may be further mapped to a plurality of basic operation instructions. In other words, the first combination instruction may be an instruction block composed of a plurality of second combination instructions and a plurality of basic operation instructions.

[0071] In a specific implementation, if the operation instruction received by the operation accelerator 102 is a second combination instruction, the operation accelerator 10 maps the second combination instruction into multiple basic operation instructions according to the mapping relationship between the second combination instruction and the basic operation instruction, and executes the multiple basic operation instructions corresponding to the second combination instruction to obtain the execution result of the second combination instruction.

[0072] If the operation instruction received by the operation accelerator 102 is a first combination instruction, the operation accelerator 102 maps the single first combination instruction into multiple second combination instructions and multiple basic operation instructions according to the mapping relationship between the first combination instruction, the second combination instruction, and the basic operation instruction. Among them, the basic operation instruction obtained by the first combination instruction through one mapping can be used for the transfer processing between the multiple second combination instructions corresponding to the first combination instruction. For each second combination instruction corresponding to the first combination instruction, according to the mapping relationship between the second combination instruction and the basic operation instruction, each second combination instruction is mapped into multiple basic operation instructions, thereby obtaining multiple basic operation instructions corresponding to the first combination instruction.

[0073] As can be seen from the above, if the operation instruction received by the operation accelerator 102 is a first combination instruction, the operation accelerator 10 can perform two mappings. Through the first mapping, the first combination instruction is mapped to multiple second combination instructions and multiple basic operation instructions. Among them, the basic operation instruction obtained by the first mapping is used for the transit processing between the two intermediate operations corresponding to two adjacent second combination instructions. Through the second mapping, each second combination instruction obtained by the first mapping is mapped to multiple basic operation instructions. Through two mappings, the multiple basic operation instructions corresponding to the first combination instruction can be determined. Further, the operation accelerator 102 executes the multiple basic operation instructions corresponding to the first combination instruction to obtain the execution result of the first combination instruction.

[0074] Reference Figure 4 , Figure 4 FIG. 1 is a schematic diagram showing the relationship between another combination instruction and a basic operation instruction in an embodiment of the present application. Figure 4 As shown, the instruction set of the computing accelerator 102 includes: a first combination instruction 0. The instruction set also includes: a second combination instruction 0, a second combination instruction 1, and a second combination instruction k, where k is a positive integer greater than 1. The instruction set also includes: a basic computing instruction 0, a basic computing instruction 1, a basic computing instruction 2, a basic computing instruction 3, a basic computing instruction 4, a basic computing instruction 5, ..., a basic computing instruction m-2, a basic computing instruction m-1, a basic computing instruction m, a basic computing instruction 10, a basic computing instruction 11, etc. m is a positive integer greater than 1.

[0075] Among them, if the computing accelerator 102 receives the second combination instruction 0, the computing accelerator maps the second combination instruction 0 to the basic computing instruction 0, the basic computing instruction 1, and the basic computing instruction 2, and executes the basic computing instruction 0, the basic computing instruction 1, and the basic computing instruction 2 in sequence to obtain the result of the second combination instruction 0.

[0076] If the computing accelerator 102 receives the second combination instruction 1, the computing accelerator maps the second combination instruction 0 to basic computing instruction 3, basic computing instruction 4, and basic computing instruction 5, and executes basic computing instruction 3, basic computing instruction 4, and basic computing instruction 5 in sequence to obtain the result of the second combination instruction 1.

[0077] If the computing accelerator 102 receives the second combination instruction k, the computing accelerator 102 maps the second combination instruction 0 to the basic computing instruction m-2, the basic computing instruction m-1, and the basic computing instruction m, and executes the basic computing instruction m-2, the basic computing instruction m-1, and the basic computing instruction m in sequence to obtain the result of the second combination instruction k.

[0078] If the computing accelerator 102 receives the first combination instruction 0, the computing accelerator 102 performs the first mapping based on the mapping relationship between the first combination instruction, the second combination instruction, and the basic operation instruction, and the computing accelerator 102 maps the first combination instruction 0 to the second combination instruction 0, the basic operation instruction 10, the second combination instruction 1, the basic operation instruction 11...the second combination instruction k. Further, the computing accelerator 102 performs the second mapping based on the mapping relationship between the second combination instruction and the basic operation instruction, and maps the second combination instruction 0, the second combination instruction 1...the second combination instruction k to multiple basic operation instructions, thereby mapping the first combination instruction 0 to the basic operation instruction 0, the basic operation instruction 1, the basic operation instruction 2...the basic operation instruction m, the basic operation instruction 10, the basic operation instruction 11, etc., and executes the mapped multiple basic operation instructions in sequence to obtain the execution result of the first combination instruction 0.

[0079] In a specific implementation, when the user of the MCU chip 10 develops the MCU chip 10, the corresponding instructions can be flexibly selected according to the desired functions. For example, if the user of the MCU chip 10 expects to perform an addition, the instruction from the CPU 101 to the operation accelerator 102 is a basic operation instruction. For another example, if the user of the MCU chip 10 expects to perform a PID operation, the instruction from the CPU 101 to the operation accelerator 102 is a second combination instruction. For another example, if the user of the MCU chip 10 expects to execute the FOC algorithm, the instruction from the CPU 101 to the operation accelerator 102 is a first combination instruction.

[0080] From the above, in the solution of the embodiment of the present application, the computing accelerator 102 can support instructions of multiple granularities, and the user of the MCU chip 10 can flexibly select and combine the computing instructions used according to actual needs, which is conducive to reducing the software development cost of the MCU chip, and users with different R&D capabilities can realize the optimized motor control solution with the minimum development cost within their capabilities. Therefore, the solution provided by the embodiment of the present application can take into account the flexibility and computing speed of the MCU chip.

[0081] In addition, in the solution of the embodiment of the present application, the computing accelerator 102 adopts a multi-issue structure. That is, in the solution of the embodiment of the present application, the instruction execution order is optimized in hardware, and multiple instructions are executed in hardware parallel multi-issue, which is conducive to further improving the processing efficiency of the computing accelerator 102, thereby improving the overall processing efficiency of the MCU.

[0082] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0083] The "multiple" in the embodiments of the present application refers to two or more. The first, second, etc. descriptions in the embodiments of the present application are only used for illustration and distinction of the described objects, and have no order, nor do they represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A computing accelerator, characterized in that: The computing accelerator receives a computing instruction from the central processing unit, and requests the central processing unit to read an execution result of the computing instruction; If the operation instruction is a single combined instruction, the operation accelerator maps the single combined instruction into a plurality of basic operation instructions, and executes the plurality of basic operation instructions to obtain the execution result; Wherein, if the combined instruction is a first combined instruction, the operation performed by the operation accelerator is an algorithm-level operation; If the combined instruction is a second combined instruction, the operation performed by the computing accelerator is an intermediate operation; Wherein, the intermediate operation includes a plurality of basic operations, and the algorithm-level operation includes a plurality of the intermediate operations and a plurality of the basic operations; Among them, if the operation instruction received by the operation accelerator is the first combination instruction, the operation accelerator performs two mappings, wherein, through the first mapping, the first combination instruction is mapped into multiple second combination instructions and multiple basic operation instructions, wherein the basic operation instruction obtained by the first mapping is used for the transit processing between two intermediate operations corresponding to two adjacent second combination instructions; through the second mapping, each second combination instruction obtained by the first mapping is mapped into multiple basic operation instructions; through two mappings, the multiple basic operation instructions corresponding to the first combination instruction are determined, and the operation accelerator executes the multiple basic operation instructions corresponding to the first combination instruction to obtain the execution result of the first combination instruction.

2. The computing accelerator according to claim 1, characterized in that: The computing accelerator is a digital signal processor.

3. The computing accelerator according to claim 1, characterized in that: If the operation instruction is the basic operation instruction, the operation accelerator executes the basic operation instruction to obtain the execution result.

4. The computing accelerator according to claim 1, characterized in that: The plurality of basic operation instructions include at least one of the following basic operation instructions: Division operation, square root operation, trigonometric function operation, hyperbolic function operation, shift operation, saturation operation, truncation operation, branch jump, immediate number construction, data movement, blocking operation, interrupt operation, response operation, trigger operation.

5. The computing accelerator according to claim 1, characterized in that: The intermediate operation includes at least one of the following: coordinate transformation operation, space vector pulse width modulation, PID regulation, filtering operation, back electromotive force observation, rotation speed estimation, and angle estimation.

6. The computing accelerator according to claim 1, characterized in that: The algorithm-level operation includes: a magnetic field oriented control algorithm and / or a commutation control algorithm.

7. The computing accelerator according to claim 6, characterized in that: The magnetic field oriented control algorithm includes at least one of the following: a sensorless magnetic field oriented control algorithm, an encoder-based magnetic field oriented control algorithm, and a Hall position sensor-based magnetic field oriented control algorithm.

8. The computing accelerator according to claim 1, characterized in that: The computing accelerator is used for motor control.

9. The computing accelerator according to claim 1, characterized in that: The computing accelerator is a multi-issue structure.

10. An MCU chip, characterized in that: include: CPU; and the computing accelerator according to any one of claims 1 to 9.

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