Display device and method of driving same

Abstract

The invention relates to a display device and a method of driving the same. The display device includes a pixel including a first transistor having a drain electrode connected to a first power voltage node and a source electrode connected to a second power voltage node, a second transistor connected between a data line and a gate electrode of the first transistor, and a third transistor connected between the data line and the gate electrode of the first transistor, the third transistor is connected between the sensing line and the source electrode of the first transistor; a data driver applying a bias voltage to the data lines during the sensing period; a sensing driver sensing an electrical characteristic of the pixel through the sensing line during a sensing period; and a controller configured to control the first power voltage according to input image data and adjust the bias voltage according to the first power voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0084444 filed in the Korean Intellectual Property Office on June 29, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a display device and a method of driving the display device, and more particularly, to a display device and a method of driving the display device capable of compensating a sensing error according to a change in power voltage when sensing is performed in real time. Background Art

[0004] As information technology develops, the importance of display devices that connect users with information increases. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0005] The display device includes pixels, and each of the pixels includes a light-emitting element and a driving transistor for supplying a driving current to the light-emitting element. The pixel may deteriorate over time, and the characteristics of the threshold voltage and mobility of the driving transistor included in the pixel may change. Therefore, a technology for sensing characteristic information of a pixel (e.g., a driving transistor) through an external compensation circuit is used for the display device.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore the above information may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0007] Embodiments provide a display device capable of performing sensing with improved reliability. For example, the display device can prevent or at least reduce errors in sensing data caused by power voltage changes occurring according to an input image.

[0008] Embodiments also provide a method of driving a display device.

[0009] According to one aspect of the present disclosure, a display device is provided, which includes: a pixel, including a first transistor, a second transistor and a third transistor, the first transistor having a drain electrode connected to a first power voltage node and a source electrode connected to a second power voltage node, the second transistor connected between a data line and a gate electrode of the first transistor, and the third transistor connected between a sensing line and the source electrode of the first transistor; a data driver connected to the pixel through the data line, the data driver applying a bias voltage to the data line during a sensing period of a frame period, wherein the frame period includes the sensing period and a display period; a sensing driver connected to the pixel through the sensing line, the sensing driver sensing an electrical characteristic of the pixel through the sensing line during the sensing period; and a controller configured to control a first power voltage applied during the frame period according to input image data, and the controller adjusts the bias voltage according to the first power voltage.

[0010] The display device may further include a memory configured to store target voltage levels respectively corresponding to one or more reference voltage levels within a predetermined voltage range.

[0011] The controller may select a first reference voltage level (among one or more reference voltage levels) based on the level of the first power voltage, and adjust the bias voltage to have a first target voltage level corresponding to the first reference voltage level among multiple target voltage levels.

[0012] The controller may control the level of the first power voltage applied during a next frame period of the frame period according to the next input image data of the input image data, and adjust the bias voltage applied to the data line during the sensing period of the next frame period according to the level of the first power voltage applied during the next frame period.

[0013] The controller can select a second reference voltage level related to the level of the first power voltage applied during the next frame period from among the one or more reference voltage levels, and adjust the bias voltage to have a second target voltage level corresponding to the second reference voltage level from among the multiple target voltage levels.

[0014] The second reference voltage level may be different from the first reference voltage level, and the second target voltage level may be different from the first target voltage level.

[0015] The one or more reference voltage levels and the target voltage level may be stored in the memory in the form of a lookup table.

[0016] When the first power voltage has a first reference voltage level among a plurality of reference voltage levels and the bias voltage has a first target voltage level among a plurality of target voltage levels corresponding to the first reference voltage level, a first value may be sensed through the sensing line as the electrical characteristic of the pixel. When the first power voltage has a second reference voltage level among the plurality of reference voltage levels and the bias voltage has a second target voltage level among the plurality of target voltage levels corresponding to the second reference voltage level, a second value may be sensed through the sensing line as the electrical characteristic of the pixel. The first value and the second value may be the same.

[0017] The one or more reference voltage levels and the target voltage level may be stored in the memory in the form of a lookup table for a particular value sensed as the electrical characteristic.

[0018] The lookup table may be updated at each predetermined cycle period.

[0019] The data driver may supply data voltages corresponding to the input image data to the pixels in the display period.

[0020] According to another aspect of the present disclosure, a method for driving a display device is provided, the display device including a pixel, the pixel including a first transistor, a second transistor and a third transistor, the first transistor having a drain electrode connected to a first power voltage node and a source electrode connected to a second power voltage node, the second transistor being connected between a data line and a gate electrode of the first transistor, and the third transistor being connected between a sensing line and the source electrode of the first transistor, wherein the method includes: providing a first power voltage and a second power voltage to the first power voltage node and the second power voltage node, respectively, in a frame period, wherein the first power voltage applied during the frame period varies according to input image data, and the frame period includes a display period and a sensing period; applying a bias voltage to the data line during the sensing period; and sensing the electrical characteristics of the pixel through the sensing line during the sensing period, and adjusting the bias voltage according to the first power voltage.

[0021] The method may store target voltage levels respectively corresponding to one or more reference voltage levels within a predetermined voltage range.

[0022] The adjusting the bias voltage may include: selecting a first reference voltage level among one or more reference voltage levels based on the level of the first power voltage; and controlling the bias voltage to have a first target voltage level among target voltage levels corresponding to the first reference voltage level.

[0023] The method may also include: controlling the level of the first power voltage applied during a next frame period of the frame period according to next input image data of the input image data; and adjusting the bias voltage applied to the data line during the sensing period of the next frame period according to the level of the first power voltage applied during the next frame period.

[0024] The adjustment of the bias voltage applied to the data line during the sensing period of the next frame period may include: selecting a second reference voltage level among the one or more reference voltage levels based on the level of the first power voltage applied during the next frame period; and adjusting the bias voltage to have a second target voltage level among the target voltage levels corresponding to the second reference voltage level.

[0025] The second reference voltage level may be different from the first reference voltage level, and the second target voltage level may be different from the first target voltage level.

[0026] When the first power voltage has a first reference voltage level among reference voltage levels and the bias voltage has a first target voltage level among target voltage levels corresponding to the first reference voltage level, a first value may be sensed through the sensing line as the electrical characteristic of the pixel. When the first power voltage has a second reference voltage level among the reference voltage levels and the bias voltage has a second target voltage level among the target voltage levels corresponding to the second reference voltage level, a second value may be sensed through the sensing line as the electrical characteristic of the pixel. The first value and the second value may be the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, these example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always refer to the same elements.

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown that the Figure 1 A circuit diagram of an embodiment of a pixel in a display device shown in FIG.

[0031] Figure 3 It is shown that the Figure 1 A circuit diagram of an embodiment of a data driver in a display device is shown in FIG.

[0032] Figure 4 It is shown that the Figure 1 A block diagram of an embodiment of a controller in a display device shown in FIG.

[0033] Figure 5 is a graph showing the relationship between the first power voltage and the sense current associated with each of the two target voltage levels.

[0034] Figure 6 is a graph showing the relationship between the first power voltage and the sense current associated with different target voltage levels.

[0035] Figure 7 is a diagram illustrating an embodiment of a lookup table including a level of a first power voltage for each sensing current and a target voltage level corresponding thereto.

[0036] Figure 8 It shows the period of one frame. Figure 1 0047 is a timing diagram of an embodiment of signals of a display device shown in FIG.

[0037] Fig. 9 is a graph showing the number of frame periods. Figure 1 0047 is a timing diagram of an embodiment of signals of a display device shown in FIG.

[0038] Fig.10 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the necessary parts for understanding the operation according to the present disclosure are described, and the description of other parts is omitted so as not to blur the subject matter of the present disclosure. In addition, the present disclosure is not limited to the exemplary embodiments described herein, but can be implemented in various different forms. On the contrary, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosed content, and fully convey the ideas of the present disclosure to those of ordinary skill in the art.

[0040] Throughout the specification, when an element is referred to as "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or indirectly connected or coupled to the other element, and one or more intermediate elements are interposed therebetween. The technical terms used in this article are only for the purpose of illustrating a specific embodiment, and are not intended to limit the embodiment. It will be understood that when a component "includes" an element, unless there is another description to the contrary, it will be understood that the component does not exclude another element, but may further include the other element. It will be understood that, for the purpose of this disclosure, "at least one (kind / person) of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more items in X, Y and Z (e.g., XYZ, XY, YZ and XZ). Similarly, for the purpose of this disclosure, "at least one (kind / person) selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more items in X, Y and Z (e.g., XYZ, XY, YZ and XZ).

[0041] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0042] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0043] refer to Figure 1 , the display device 100 may include a display panel 110 , a data driver 120 , a gate driver 130 , a controller 140 , a power supplier 150 , and a sensing driver 160 .

[0044] and DLm (m is a positive integer), gate lines GL1, GL2, . . . and GLn (n is a positive integer), sensing lines SEN1, SEN2, . . . and SENm, control lines CL1, CL2, . . . and CLn, and pixels PX.

[0045] The pixels PX may be disposed in a region divided by the data lines DL1 to DLm and the gate lines GL1 to GLn. The pixels PX may be electrically connected to the data lines DL1 to DLm and the sensing lines SEN1 to SENm. In addition, the pixels PX may be electrically connected to the gate lines GL1 to GLn and the control lines CL1 to CLn.

[0046] In addition, the pixel PX may be supplied with a first power voltage VDD, a second power voltage VSS, and a bias voltage VREF from a power supply 150 to be described later. The pixel PX may receive a first power voltage VDD and a second power voltage VSS provided through a first power voltage node and a second power voltage node, respectively. In addition, the pixel PX may receive a bias voltage VREF provided through data lines DL1 to DLm. The first power voltage VDD and the second power voltage VSS may be power voltages required to drive the pixel PX. In addition, the bias voltage VREF may be a sensing voltage for sensing a threshold voltage of a driving transistor included in each of the pixels PX. In the present disclosure, the bias voltage VREF may be specified as a sensing voltage applied to the gate electrode of the driving transistor to measure the characteristics of the driving transistor.

[0047] The data driver 120 may be supplied with a data control signal DCS and image data DATA2 from the controller 140, convert the image data DATA2 (or digital image data) into an analog data signal (or data voltage) based on the data control signal DCS, and provide the data voltage (or data signal) to the data lines DL1 to DLm. The data control signal DCS is a signal for controlling the operation of the data driver 120, and may include a data enable signal, etc. For example, the data driver 120 may provide a data voltage (or data signal) corresponding to the input image data DATA1 to the pixel PX through the data lines DL1 to DLm in a display period (e.g., an activation period) of one frame. The data voltage is a voltage for displaying a valid image, and may be a value corresponding to the image data DATA2 (or digital image data).

[0048] The data driver 120 may apply the bias voltage VREF supplied from the power supplier 150 to the sensing lines SEN1 to SENm under the control of the controller 140. For example, the data driver 120 may provide the bias voltage VREF to the data lines DL1 to DLm in a sensing period (eg, a vertical blanking period) of one frame.

[0049] The gate driver 130 (or the scan driver 130) may generate a gate signal based on the gate control signal GCS and provide the gate signal to the gate lines GL1 to GLn. The gate control signal GCS is a signal for controlling the operation of the gate driver 130 and may include an initial signal and a clock signal, etc. For example, the gate driver 130 may sequentially generate and output a gate signal corresponding to the initial signal (e.g., a gate signal having a waveform identical or similar to that of the initial signal) using a clock signal. The gate driver 130 may include a shift register.

[0050] In addition, the gate driver 130 may generate a control signal based on the gate control signal GCS and provide the control signal to the control lines CL1 to CLn. For example, the gate driver 130 may sequentially generate and output the control signal using a clock signal. Although the case where the gate driver 130 generates the gate signal and the control signal has been shown, the circuit for generating the control signal may be implemented as a separate driver independent of the gate driver 130.

[0051] For example, the gate driver 130 may generate a gate signal (and a control signal) composed of a combination of a gate-on voltage and a gate-off voltage. The gate-on voltage may have a voltage level that turns on a transistor provided in each pixel PX or the gate driver 130, etc., and the gate-off voltage may have a voltage level that turns off the transistor.

[0052] The controller 140 may receive a control signal CS from the outside (eg, a graphics processor) and generate a gate control signal GCS and a data control signal DCS based on the control signal CS. The input image data DATA1 may include a grayscale value corresponding to each pixel PX, and the control signal CS may include a clock signal, a horizontal synchronization signal, a data enable signal, and the like.

[0053] In addition, the controller 140 may receive input image data DATA1 (eg, RGB data) from the outside, convert the input image data DATA1 into image data DATA2 corresponding to the pixel arrangement of the display panel 110 , and then output the converted image data DATA2 .

[0054] According to an embodiment, the controller 140 may determine the first power voltage VDD and the second power voltage VSS of the display device 100 based on the input image data DATA1. For example, the controller 140 may determine the first voltage control signal VCS1 using the maximum data voltage for each frame, the current drop (IR-Drop) of each position, and the energy margin (EL margin), etc. based on the input image data DATA1 provided at the current time. The first voltage control signal VCS1 is a voltage control signal for the first power voltage VDD and the second power voltage VSS, and may be provided to the first power supplier 151 in the power supplier 150. In addition, the controller 140 may determine the first power voltage VDD and / or the second power voltage VSS by using a frame period as a unit based on various methods.

[0055] In addition, the controller 140 may determine the second voltage control signal VCS2 applied to the data line according to the level of the first power voltage VDD. The second voltage control signal VCS2 is a voltage control signal for the bias voltage VREF and may be provided to the second power supplier 152 in the power supplier 150.

[0056] The power supplier 150 may be configured with a first power supplier 151 generating a first power voltage VDD and a second power voltage VSS and a second power supplier 152 generating a bias voltage VREF.

[0057] The power supplier 150 may generate a first power voltage VDD and a second power voltage VSS and provide the first power voltage VDD and the second power voltage VSS to the display panel 110. For example, the power supplier 150 may generate a first power voltage VDD and a second power voltage VSS that vary according to input image data DATA1 and provide the first power voltage VDD and the second power voltage VSS to the display panel 110.

[0058] The power supplier 150 may generate a bias voltage VREF to provide the bias voltage VREF to the data driver 120. In the sensing period, the data driver 120 may apply the bias voltage VREF to the data lines DL1 to DLm. In an embodiment, the bias voltage VREF may have a voltage level lower than a voltage level of a threshold value of the light emitting element. For example, the bias voltage VREF may be a voltage controlled based on the first power voltage VDD provided to each pixel PX. Figure 1 , it is shown that the first power supplier 151 and the second power supplier 152 are components distinguished from each other. However, the embodiment is not limited thereto. For example, the first power supplier 151 and the second power supplier 152 may be integrated into one.

[0059] The sensing driver 160 may be connected to the sensing lines SEN1 to SENm and sense deviation information of each of the sensing lines SEN1 to SENm. Figure 1 , it is shown that the sensing driver 160 is connected to the sensing lines SEN1 to SENm. However, the present disclosure is not limited thereto. For example, the sensing driver 160 may be connected to the data lines DL1 to DLm to which various external compensation methods currently known in the art may be applied.

[0060] In the sensing period, the sensing driver 160 may sense characteristic information of the pixel PX. For example, when the bias voltage VREF is applied to the data lines DL1 to DLm, the sensing driver 160 may receive a value sensed from each pixel PX through the sensing lines SEN1 to SENm. More specifically, the sensing driver 160 may sense a charging voltage of a capacitor connected to each of the sensing lines SEN1 to SENm, thereby sensing characteristic information of the pixel PX, the characteristic information including threshold voltage information and mobility information of a driving transistor included in the pixel PX and / or degradation information of a light emitting element included in the pixel PX. In another example, the sensing driver 160 may receive a charging voltage sensed from a pixel PX on one horizontal line in a sensing period between adjacent display periods.

[0061] The sensing driver 160 may calculate a sensing current by converting the sensed charging voltage, and convert characteristic information of the pixel PX including the calculated sensing current into sensing data DATA_S in a digital form, and then provide the converted sensing data DATA_S to the controller 140. To this end, the sensing driver 160 may include an analog-to-digital converter (ADC). The sensing data DATA_S output from the sensing driver 160 may be stored in a memory.

[0062] Each of the data driver 120, the gate driver 130, the controller 140, the power supply 150, and the sensing driver 160 may be directly mounted on the display panel 110 in the form of at least one integrated circuit chip, attached to the display panel 110 in the form of a tape carrier package (TCP), or mounted on a separate printed circuit board.

[0063] Figure 2 It is shown that the Figure 1 A circuit diagram of an embodiment of a pixel in a display device shown in FIG. Figure 2 Description included in Figure 1 The structure of a pixel in the display device shown in .

[0064] refer to Figure 2, the pixel PX may include a light emitting element LD, a first transistor TR1 (or a driving transistor), a second transistor TR2 (or a switching transistor), a third transistor TR3 (or a sensing transistor), and a storage capacitor Cst.

[0065] The light emitting element LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first power voltage VDD through the first transistor TR1. The light emitting element LD may include a first electrode and a second electrode. The first electrode may be connected to a second node N2, and the second electrode may be connected to a second power line PL2, and the second power line PL2 is connected to a second power voltage node to which a second power voltage VSS is applied. In an embodiment, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode. Alternatively, the first electrode may be a cathode electrode, and the second electrode may be an anode electrode.

[0066] According to an embodiment, the light emitting element LD may be an inorganic light emitting element formed of an inorganic material or an organic light emitting diode including an organic light emitting layer. In addition, the light emitting element LD may be a light emitting element made of a combination of an inorganic material and an organic material.

[0067] The first electrode of the first transistor TR1 may be connected to the first power line PL1, the first power line PL1 is connected to the first power voltage node to which the first power voltage VDD is applied, and the second electrode of the first transistor TR1 may be connected to the first electrode (or the second node N2) of the light emitting element LD. The gate electrode of the first transistor TR1 may be connected to the first node N1. The first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0068] The first transistor TR1 may control current flowing through the light emitting element LD corresponding to the voltage of the first node N1. The first transistor TR1 may be turned on when the voltage between the first node N1 and the second node N2 (ie, the gate-source voltage) is higher than the threshold voltage of the first transistor TR1.

[0069] The first electrode of the second transistor TR2 may be connected to the mth data line DLm, and the second electrode of the second transistor TR2 may be connected to the first node N1 (or the gate electrode of the first transistor TR1). The gate electrode of the second transistor TR2 may be connected to the nth gate line GLn. When a high level voltage is supplied to the nth gate line GLn, the second transistor TR2 may be turned on to transfer the data voltage VDATA from the mth data line DLm to the first node N1.

[0070] The first electrode of the third transistor TR3 may be connected to the mth sensing line SENm, and the second electrode of the third transistor TR3 may be connected to the second node N2 (or the second electrode of the first transistor TR1). The gate electrode of the third transistor TR3 may be connected to the nth control line CLn. When a high level voltage is supplied to the nth control line CLn, the third transistor TR3 may be turned on so that the mth sensing line SENm and the second node N2 are electrically connected to each other. Therefore, within a predetermined time, a sensing current Ids corresponding to the initialization voltage or the voltage of the second node N2 may be transmitted to the second node N2 through the mth sensing line SENm. The sensing current Ids may be provided to the sensing driver 160 (see Figure 1 ).

[0071] The storage capacitor Cst may be connected between the first node N1 and the second node N2. The storage capacitor Cst may charge a data voltage VDATA corresponding to a data signal supplied to the first node N1 during one frame. Therefore, the storage capacitor Cst may store a voltage corresponding to a voltage difference between the first node N1 and the second node N2. When the data voltage VDATA is supplied, an initialization voltage may be supplied to the second node N2, and therefore, the storage capacitor Cst may store a voltage corresponding to a difference between the data voltage VDATA and the initialization voltage. The on / off of the first transistor TR1 may be determined according to the voltage stored in the storage capacitor Cst.

[0072] However, Figure 2 The circuit structure of the pixel PX shown in FIG. 1 is not limited thereto. For example, Figure 2 The transistors shown in FIG. 1 are implemented with N-channel metal oxide semiconductor (NMOS) transistors. However, at least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be implemented with a P-channel metal oxide semiconductor (PMOS) transistor, or at least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a thin film transistor including at least one of an oxide semiconductor, an amorphous silicon semiconductor, and a polycrystalline silicon semiconductor.

[0073] Figure 3 It is shown that the Figure 1 A circuit diagram of an embodiment of a data driver in a display device is shown in FIG.

[0074] exist Figure 3 , the data driver 120 is briefly illustrated based on a portion of the sensing driver 160 connected to the pixel PX through the mth sensing line SENm to sense characteristics of the pixel PX. Figure 3 The pixel PX shown in FIG. Figure 2 The pixel PX described is the same as that described above, and therefore, the description of the pixel PX will be omitted. Figure 2 The description of part of the pixel PX shown in FIG. 1 repeats the description of part of the pixel PX shown in FIG.

[0075] refer to Figure 3 , also refer to Figure 1 and Figure 2 , the data driver 120 may include a digital-to-analog converter (DAC). The DAC may generate a data voltage VDATA corresponding to the image data DATA2 of the frame. For example, the DAC may select one of the gamma voltages based on the image data DATA2 and output the selected gamma voltage as the data voltage VDATA. Meanwhile, the data driver 120 may further include an output buffer (not shown), and provide the data voltage VDATA to the mth data line DLm through the output buffer.

[0076] The data driver 120 may further include a sensing driver 160 and an analog-to-digital converter (ADC) connected to the mth sensing line SENm.

[0077] The sensing driver 160 may include an initialization switch SW_VINIT, a sensing capacitor CSEN, a sampling switch SW_SPL, a first capacitor C1, a sharing switch SW_SHARE, a reset switch SW_RST, a second capacitor C2, and an output switch SW_CH. However, Figure 3 An example of the sensing driver 160 is shown, and the present disclosure is not limited thereto. For example, when the sensing driver 160 can detect the voltage of the second node N2 of the pixel PX (or the current corresponding thereto), the sensing driver 160 can be implemented with various circuits (e.g., a sensing circuit that converts the sensing current into a sensing voltage using an amplifier and samples and holds the converted sensing voltage).

[0078] refer to Figure 3 , the initialization switch SW_VINIT may be connected between the power line to which the initialization voltage VINIT is applied and the mth sensing line SENm. The initialization voltage VINIT may be provided from the power supplier 150 and has a voltage level lower than the voltage level of the voltage at which the light emitting element LD can operate. When the initialization switch SW_VINIT is turned on, the initialization voltage VINIT may be applied to the mth sensing line SENm. When the third transistor TR3 of the pixel PX is turned on, the initialization voltage VINIT may be applied to the second node N2 of the pixel PX. Since the initialization voltage VINIT has a voltage level lower than the voltage level of the voltage at which the light emitting element LD can operate, the light emitting element LD may not emit light even when the first transistor TR1 is turned on.

[0079] The sensing capacitor CSEN may be connected between the mth sensing line SENm and a reference power source. The reference power source may have a ground voltage, but the present disclosure is not limited thereto. When the initialization switch SW_VINIT is turned off and the third transistor TR3 of the pixel PX is turned on, the sensing capacitor CSEN may be charged by the sensing current Ids provided via the second node N2 for a certain time. In particular, when the second transistor TR2 is turned on and the sampling switch SW_SPL is turned off for a certain time, the sensing capacitor CSEN may be charged from the bias voltage VREF applied to the first node N1 by the sensing current Ids provided via the second node N2. The characteristic information (e.g., characteristic information of the driving transistor) of the pixel PX provided through the second node N2 may be stored in the voltage charged in the sensing capacitor CSEN.

[0080] The sampling switch SW_SPL may be connected between the mth sensing line SENm and the third node N3. The first capacitor C1 may be connected between the third node N3 and the reference power supply. When the sampling switch SW_SPL is turned on, the first capacitor C1 may sample characteristic information of the pixel PX (or the first transistor TR1) stored in the sensing capacitor CSEN. That is, the data driver 120 may sample the sensing signal through the sampling switch SW_SPL and the first capacitor C1.

[0081] The sharing switch SW_SHARE may be connected between the third node N3 and the fourth node N4, the reset switch SW_RST may be connected between the fourth node N4 and the reference power supply, and the second capacitor C2 may be connected between the fourth node N4 and the reference power supply. When the sharing switch SW_SHARE is turned on and the first capacitor C1 and the second capacitor C2 share charge, the node voltage of the fourth node N4 (and the node voltage of the third node N3) may change. The sharing switch SW_SHARE, the reset switch SW_RST and the second capacitor C2 may function as a buffer according to the operation of the sharing switch SW_SHARE and the reset switch SW_RST.

[0082] The output switch SW_CH may be connected between the fourth node N4 and the ADC. A node voltage of the fourth node N4 may be applied to the ADC.

[0083] The data driver 120 may convert the sampled sensing signal from an analog form to a digital form through the ADC. The sensing signal in a digital form may be provided to the controller 140.

[0084] Figure 4 It is shown that the Figure 1 A block diagram of an embodiment of a controller in a display device shown in FIG.

[0085] refer to Figure 4, also refer to Figure 1 , Figure 3 and Figure 7 , the controller 140 may include an input image analyzing unit 141 , a driving voltage determining unit 142 , and a bias voltage determining unit 143 .

[0086] According to an embodiment, the controller 140 may determine the first power voltage VDD and the second power voltage VSS based on the input image data DATA1. In order to determine the power voltage, the controller 140 may receive the input image data DATA1 at the current time by using a frame as a unit through the input image analysis unit 141, and analyze the input image data DATA1 for each frame. For example, the controller 140 may analyze the maximum brightness (Max Gray) or analyze a histogram of brightness data and grayscale data of each pixel PX included in the input image data DATA1 of each frame.

[0087] In addition, the controller 140 may determine the first power voltage VDD and the second power voltage VSS supplied to each pixel PX through the driving voltage determination unit 142. Compared with the second power voltage VSS, the first power voltage VDD may be a high-level voltage. For example, when the fluctuation of the input image data DATA1 is large, the level of the first power voltage VDD supplied to each pixel PX does not have a constant value, but may fluctuate within a wide range. Since a voltage drop occurs in the first power voltage VDD when the brightness of the input image data DATA1 changes to the maximum brightness, the controller 140 may determine the first power voltage VDD as the minimum voltage level at which the driving transistor can operate in the saturation region. That is, the controller 140 may generate a first voltage control signal VCS1 by determining the first power voltage VDD and the second power voltage VSS using the analysis result of the input image data DATA1 of each frame. In addition, the controller 140 may provide the first voltage control signal VCS1 to the first power supplier 151.

[0088] In addition, the controller 140 may determine a bias voltage VREF for measuring the real-time changing characteristics of the driving transistor through a bias voltage determination unit 143. In real-time sensing, when the level of the first power voltage VDD changes, the real-time sensed value may change. Therefore, in order to accurately measure the characteristics of the driving transistor, the controller 140 may control the bias voltage VREF according to the change in the level of the first power voltage VDD. That is, in order to prevent the fluctuation of the sensing current Ids caused by the change in the level of the first power voltage VDD, the controller 140 may generate a second voltage control signal VCS2 by determining the bias voltage VREF to be suitable for the range of change of the level of the first power voltage VDD. In addition, the controller 140 may provide the second voltage control signal VCS2 to the second power supplier 152.

[0089] like Figure 4 As shown in FIG. 1 , the bias voltage determination unit 143 may receive a sensing current obtained by converting a charging voltage of the sensing capacitor CSEN sensed from the sensing driver 160 as sensing data DATA_S in a digital form. Figure 3 , the ADC shown in FIG. 1 receives the sensing data DATA_S. In addition, the bias voltage determination unit 143 may receive information about a target voltage level corresponding to a reference voltage level included in the lookup table LUT from the memory 170. In addition, the bias voltage determination unit 143 may determine the bias voltage VREF to have a first target voltage level corresponding to a first reference voltage level of the first power voltage VDD for the sensing current in the lookup table LUT.

[0090] Figure 5 is a graph showing the relationship between the first power voltage and the sense current associated with each of the two target voltage levels. Figure 5 , the horizontal axis represents the level of the first power voltage VDD, and the vertical axis represents the amount of the sensing current Ids.

[0091] refer to Figure 5 , also refer to Figure 1 and Figure 2 , the first graph 510 represents the relationship between the first power voltage VDD and the sensing current Ids when the bias voltage VREF has a first target voltage level. The second graph 520 represents the relationship between the first power voltage VDD and the sensing current Ids when the bias voltage VREF has a second target voltage level higher than the first target voltage level.

[0092] According to an embodiment, when the bias voltage VREF has a first target voltage level, when the first power voltage VDD has a voltage within a predetermined voltage range (eg, Figure 1The sensing current Ids may have a first current level Ids1 when the maximum voltage level SVL2 is within the voltage range of the first power voltage VDD supported by the display device 100 shown in FIG. 5A . In other words, at the maximum voltage level SVL2 of the first power voltage VDD, the sensing current Ids having the first current level Ids1 may flow through the first transistor TR1. However, the voltage level of the first power voltage VDD may be changed to a minimum voltage level SVL1 within a predetermined voltage range according to the input image data DATA1. When the bias voltage VREF is constantly at the first target voltage level, the current level of the sensing current Ids may be changed to a second current level Ids2 (point B) according to the first curve graph 510.

[0093] That is, when the bias voltage VREF is constantly maintained at the first target voltage level, as the voltage level of the first power voltage VDD changes from the maximum voltage level SVL2 (point A) to the minimum voltage level SVL1 (point B), the current level of the sensing current Ids can change from the first current level Ids1 corresponding to point A to the second current level Ids2 corresponding to point B.

[0094] On the other hand, when the voltage level of the bias voltage VREF is changed to the second target voltage level, according to the second graph 520, when the first power voltage VDD has the minimum voltage level SVL1 within the predetermined voltage range, the sensing current Ids may have the first current level Ids1 (point C). Therefore, when the voltage level of the bias voltage VREF is adjusted from the first target voltage level to the second target voltage level, the sensing current Ids may have the first current level Ids1 corresponding to point C when the first power voltage VDD has the minimum voltage level SVL1.

[0095] In this way, even when the voltage level of the first power voltage VDD changes, the sensing current Ids flowing through the first transistor TR1 of the same pixel PX can be maintained at the same current level by adjusting the bias voltage VREF. For example, when the voltage level of the first power voltage VDD changes from the maximum voltage level SVL2 to the minimum voltage level SVL1, the voltage level of the bias voltage VREF can be controlled from the first target voltage level to the second target voltage level.

[0096] In addition, if Figure 5 As shown in the first graph 510 and the second graph 520, the relationship between the first power voltage VDD and the sense current Ids can be stored in the memory in the form of a lookup table for each target voltage level. Figure 7 Describe the lookup table in detail.

[0097] Figure 6is a graph showing the relationship between the first power voltage and the sense current associated with different target voltage levels.

[0098] refer to Figure 1 , Figure 2 and Figure 6 , the controller 140 can select a reference voltage level related to the level of the first power voltage VDD from one or more reference voltage levels within the variable voltage range of the first power voltage VDD, and adjust the bias voltage VREF to have a target voltage level corresponding to the reference voltage level from among the target voltage levels.

[0099] According to an embodiment, the controller 140 may control the power supplier 150 according to the input image data DATA1 and the next input image data DATA1, thereby controlling the level of the first power voltage VDD applied during the next frame period of the frame period. Therefore, the controller 140 may control the bias voltage VREF applied to the data line in the sensing period of the next frame period in advance according to the level of the first power voltage VDD applied during the next frame period.

[0100] like Figure 5 and Figure 6 As shown, when the first power voltage VDD has a voltage within a predetermined voltage range (eg, Figure 1 When the bias voltage VREF having the first target voltage level is applied, the sensing current Ids may have the first current level Ids1 according to the first graph 510 when the first power voltage VDD has a maximum voltage level SVL2 within the voltage range of the first power voltage VDD supported by the display device 100 shown in FIG. 5 , for example, when the bias voltage VREF is applied as 5V as the first target voltage level when the first power voltage VDD has 24V as the maximum voltage level SVL2, the sensing current Ids may be sensed as 5A as the first current level Ids1.

[0101] In addition, when the first power voltage VDD has a minimum voltage level SVL1 within a predetermined voltage range, when the bias voltage VREF having a second target voltage level is applied, the sense current Ids may have a first current level Ids1 according to the second graph 520. For example, when the first power voltage VDD is 20V as the minimum voltage level SVL1, when the bias voltage VREF is applied as 10V as the second target voltage level, the sense current Ids may be constantly sensed as 5A as the first current level Ids1.

[0102] When the voltage level of the first power voltage VDD changes to a first reference voltage level VL1 between a minimum voltage level SVL1 and a maximum voltage level SVL2, the sensing current Ids can be sensed as being at a changed current level. In response to the changed current level, the bias voltage VREF can be dynamically adjusted to keep the sensing current Ids at the first current level Ids1. As used herein, "dynamically adjusting" refers to an adjustment that occurs in real time in response to continuous or sustained sensing of the sensing current Ids. For example, the bias voltage VREF can be adjusted to have a third target voltage level corresponding to the third graph 530. The third target voltage level can be a target voltage level corresponding to the third graph 530 that matches the first current level Ids1 and the first reference voltage level VL1. For example, when the first power voltage VDD has 22V as the first reference voltage level VL1, the bias voltage VREF can be selected to have 7V as the third target voltage level, so that the sensing current Ids to be applied can be constantly sensed as 5A as the first current level Ids1.

[0103] In addition, when the voltage level of the first power voltage VDD is changed to a second reference voltage level VL2 between the first reference voltage level VL1 and the maximum voltage level SVL2 in the next frame period, the sensing current Ids can be sensed at the newly changed current level. In response to this newly changed current level, the bias voltage VREF can be dynamically readjusted to keep the sensing current Ids at the first current level Ids1. The bias voltage VREF can be controlled to have a fourth target voltage level corresponding to the fourth graph 540. The fourth target voltage level can be a target voltage level corresponding to the fourth graph 540 that matches the first current level Ids1 and the second reference voltage level VL2. For example, when the first power voltage VDD has 21V as the second reference voltage level VL2, the bias voltage VREF can be controlled to have 9V as the fourth target voltage level, so that the sensing current Ids to be applied can be constantly sensed as 5A as the first current level Ids1.

[0104] refer to Figure 6 , when the first power voltage VDD has the same reference voltage level, as the bias voltage VREF is applied at a higher target voltage level, the sense current Ids flowing through the first transistor TR1 can be sensed at a higher current level. In addition, when the reference voltage level of the first power voltage VDD decreases, the sense current Ids flowing through the first transistor TR1 can be sensed at the same current level only when the bias voltage VREF is to be applied at a high target voltage level.

[0105] In this way, in order to constantly maintain the sensing current Ids when the first power voltage VDD decreases, the bias voltage VREF will be controlled to have a high target voltage level. For example, when the first power voltage VDD decreases from 24V to 22V, the bias voltage VREF can be controlled from 5V to 7V. In addition, the sensing current Ids can be constantly sensed as 5A.

[0106] Therefore, the controller 140 controls the bias voltage VREF to have an optimal voltage level suitable for the first power voltage VDD applied to each frame in real-time sensing, so that the variation of the first power voltage VDD can be compensated, thereby constantly maintaining the sensing current Ids. In addition, the characteristics of the driving transistor can be more accurately measured by the same sensing current Ids.

[0107] Figure 7 is a diagram illustrating an embodiment of a lookup table including a level of a first power voltage for each sensing current and a target voltage level corresponding thereto.

[0108] refer to Figure 7 , also refer to Figure 1 , the display device 100 may include a memory that stores target voltage levels VREF_TL1, VREF_TL2, VREF_TL3, ..., VREF_TL21, VREF_TL22, ..., and VREF_TLmn corresponding to one or more reference voltage levels VDD1, VDD2, VDD3, VDD4, ..., and VDDn within a predetermined voltage range of the first power voltage VDD, respectively. In addition, one or more reference voltage levels VDD1 to VDDn and target voltage levels VREF_TL1 to VREF_TLmn may be stored in the memory in the form of a lookup table LUT. According to an embodiment, the lookup table LUT may include target voltage levels VREF_TL1 to VREF_TLmn corresponding to one or more reference voltage levels VDD1 to VDDn associated with each current level (e.g., the first current level Ids1) of the sensing current Ids, respectively. Figure 7 , target voltage levels VREF_TL1 to VREF_TLmn corresponding to reference voltage levels VDD1 to VDDn associated with each of the first current level Ids1, the second current level Ids2, the third current level Ids3, the fourth current level Ids4, . . . and the mth current level Idsm, respectively, are shown.

[0109] According to an embodiment, the lookup table LUT stored in the memory may include a reference voltage level of the first power voltage VDD, a current amount of the sensing current Ids, and a target voltage level VREF_TL of the bias voltage VREF. In addition, the lookup table LUT may store representative values ​​commonly applied to all pixels PX so that the corresponding values ​​are easily applied to products, or store values ​​divided according to pixel units or block units.

[0110] In addition, the lookup table LUT stored in the memory may be updated for each predetermined cycle period. The drive transistor included in each pixel PX may function differently with aging. Therefore, before the product is released, the lookup table LUT is updated for each cycle period so that the target voltage level VREF_TL of the bias voltage VREF is updated to reflect any changes caused by degradation of the drive transistor. In an embodiment, the cycle period for updating the lookup table LUT may be set to a period in which a certain amount of change may occur in the drive transistor. The corresponding cycle period may be 1000 hours, but the present disclosure is not limited thereto.

[0111] According to an embodiment, the controller 140 may control the bias voltage VREF to have a target voltage level VREF_TL matched from a lookup table LUT. Corresponding to the reference voltage level of the first power voltage VDD provided for each frame and the sensing current Ids sensed as an electrical characteristic, the target voltage level VREF_TL may be a voltage level that becomes a reference for controlling the bias voltage VREF. For example, when the reference voltage level of the first power voltage VDD is 24V with reference to the same sensing current Ids, the target voltage level VREF_TL matched from the lookup table LUT stored in the memory may be 5V. In addition, when the reference voltage level of the first power voltage VDD is 22V, the target voltage level VREF_TL matched from the lookup table LUT stored in the memory may be 7V. However, this is merely illustrative, and the present disclosure is not limited thereto.

[0112] Figure 8 It shows the period of one frame. Figure 1 0047 is a timing diagram of an embodiment of signals of a display device shown in FIG.

[0113] refer to Figure 8 , can be performed for each pixel PX (see Figure 1 The frame period FR may include a display period AP and a sensing period BP between adjacent display periods AP.

[0114] The data enable signal DE defines a display period AP (eg, an active period) in which image data is input, and thus a period in which the data enable signal DE is not applied may be a sensing period BP (eg, a vertical blanking period).

[0115] refer to Figure 3 and Figure 8 In the display period AP between the first time T1 and the second time T2, the nth gate signal GSn may be supplied to the second transistor TR2 through the nth gate line GLn, and the nth control signal CSn may be supplied to the third transistor TR3 through the nth control line CLn. Therefore, the second transistor TR2 may be turned on so that the data voltage VDATA (see Figure 2 ) is transmitted to the first node N1. In addition, the third transistor TR3 may be turned on so that the initialization voltage VINIT is transmitted to the second node N2.

[0116] A voltage corresponding to the difference between the data voltage VDATA and the initialization voltage VINIT may be stored in the storage capacitor Cst. Therefore, the first transistor TR1 may apply a current corresponding to the voltage stored in the storage capacitor Cst to the light emitting element LD. Therefore, the light emitting element LD may generate light with a predetermined brightness.

[0117] In the sensing period BP between the second time T2 and the sixth time T6, the driving of at least one pixel PX may include a sensing period and a data rewriting period. That is, the display device may select at least one pixel PX for each sensing period BP, thereby sensing the characteristics of the pixel PX, and reapplying the data voltage VDATA to restore the image display state after the sensing to the image display state before the sensing.

[0118] The period between the second time T2 and the third time T3 may be provided as a sensing period. In the period between the second time T2 and the third time T3, a bias voltage VREF may be supplied as the data signals DS1 to DSm applied to the data lines DL1 to DLm. The second transistor TR2 may be turned on according to the nth gate signal GSn activated as a high level, and thus, the bias voltage VREF may be supplied to the first node N1. The third transistor TR3 may be turned on according to the nth control signal CSn activated as a high level, so that the initialization voltage VINIT is supplied to the second node N2 during a predetermined period. In addition, when the initialization switch SW_VINIT of the sensing driver 160 is disconnected after the predetermined period has passed, the second node N2 may float. The sensing driver 160 may sense the characteristics of the driving transistor (e.g., the voltage charged in the sensing capacitor CSEN) from the second node N2.

[0119] After that, the period between the fourth time T4 and the fifth time T5 is a data rewriting period. In order to restore the image display state after sensing to the image display state before sensing, the data voltage VDATA can be resupplied to the first node N1 by turning on the second transistor TR2, and the initialization voltage VINIT can be supplied to the second node N2 by turning on the third transistor TR3.

[0120] In an embodiment, as the voltage of the second node N2 increases due to the light emission of the light emitting element LD in the display period AP before the sensing period, when the data voltage VDATA is reapplied to the first node N1 to correspond to the initialization voltage VINIT transmitted to the second node N2 in the data rewriting period after the sensing period, the difference between the driving current supplied by the first transistor TR1 in the display period AP before the sensing period and the driving current supplied by the first transistor TR1 in the data rewriting period after the sensing period can be reduced. That is, in the display device, the visibility phenomenon that may occur due to real-time sensing using an external compensation circuit can be reduced or prevented.

[0121] Fig. 9 is a graph showing the number of frame periods. Figure 1 0047 is a timing diagram of an embodiment of signals of a display device shown in FIG.

[0122] In the following, reference will be made to Figure 1 and Fig. 9 The display device 100 is described as comprising Figure 8 An example of operating in units of a frame period FR of a display period AP and a sensing period BP shown in FIG. Fig. 9 The operations shown in the reference Figure 8 The operations in a single frame period described are the same, and therefore, repeated descriptions will be omitted.

[0123] refer to Figure 1 and Fig. 9 , in the first frame period FR1, the first image data DATA1_1 may be received as the input image data DATA1. According to the first image data DATA1_1, the first gray voltage GV1 may be applied to the data lines DL1 to DLm as the data signals DS1 to DSm.

[0124] The controller 140 may control the power supplier 150 so as to provide the first power voltage VDD applied during the first display period AP1 and the first sensing period PB1 to have a first reference voltage level VDD1. In addition, the controller 140 may control the power supplier 150 so as to control the bias voltage VREF applied as the data signals DS1 to DSm during the sensing period included in the first sensing period BP1 to have a first target voltage level VREF1 according to the first reference voltage level VDD1 of the first power voltage VDD. In addition, the first data voltage R1 may be provided as the data signals DS1 to DSm during the data rewrite period included in the first sensing period BP1 so as to restore the image display state after sensing to the image display state before sensing. In some embodiments, the first data voltage R1 may be equal to the first grayscale voltage GV1. More specifically, when the input image data DATA1 in the first frame period FR1 is a 100% white image, the controller 140 may provide the first power voltage VDD applied during the first frame period FR1 to have 24V as the maximum voltage level within the variable voltage range. Therefore, the controller 140 may control the bias voltage VREF applied in the first sensing period BP1 of the first frame period FR1 to have 5V as a target voltage level corresponding to 24V of the first power voltage VDD.

[0125] In addition, in the second frame period FR2 which is the next frame period of the first frame period FR1, second image data DATA1_2 may be received as the input image data DATA1. According to the second image data DATA1_2, second gray voltages GV2 may be applied to the data lines DL1 to DLm as the data signals DS1 to DSm.

[0126] The controller 140 may control the power supplier 150 so as to provide the first power voltage VDD applied during the second display period AP2 and the second sensing period PB2 to have a second reference voltage level VDD2 adjusted from the first reference voltage level VDD1. In addition, the controller 140 may control the power supplier 150 so as to control the bias voltage VREF applied as the data signals DS1 to DSm during the sensing period included in the second sensing period BP2 to have a second target voltage level VREF2 according to the second reference voltage level VDD2 of the first power voltage VDD. In addition, the second data voltage R2 may be provided as the data signals DS1 to DSm during the data rewrite period included in the second sensing period BP2 so as to restore the image display state after sensing to the image display state before sensing. In an embodiment, the second data voltage R2 may be equal to the second grayscale voltage GV2. More specifically, when the input image data DATA1 in the second frame period FR2 is a 1% white image, the controller 140 may provide the first power voltage VDD applied during the second frame period FR2 to have 22V reduced from the maximum voltage level. Therefore, the controller 140 may control the bias voltage VREF applied in the second sensing period BP2 of the second frame period FR2 to have 7V as a target voltage level corresponding to 22V as a level of the first power voltage VDD.

[0127] In addition, in the third frame period FR3 which is the next frame period after the second frame period FR2, third image data DATA1_3 may be received as input image data DATA1. According to the third image data DATA1_3, third gray voltages GV3 may be applied to the data lines DL1 to DLm as data signals DS1 to DSm.

[0128] The controller 140 may control the power supplier 150 so as to provide the first power voltage VDD applied during the third display period AP3 and the third sensing period PB3 to have a third reference voltage level VDD3 adjusted from the second reference voltage level VDD2, which is adjusted from the first reference voltage level VDD1. In addition, the controller 140 may control the power supplier 150 so as to control the bias voltage VREF applied as the data signals DS1 to DSm during the sensing period included in the third sensing period BP3 to have a third target voltage level VREF3 according to the third reference voltage level VDD3 of the first power voltage VDD. In addition, the third data voltage R3 may be provided as the data signals DS1 to DSm during the data rewrite period included in the third sensing period BP3 so as to restore the image display state after sensing to the image display state before sensing. In an embodiment, the third data voltage R3 may be equal to the third grayscale voltage GV3. More specifically, when the input image data DATA1 in the third frame period FR3 is also a 100% white image, the controller 140 may provide the first power voltage VDD applied during the third frame period FR3 to have a maximum voltage level of 24 V. Therefore, the controller 140 may control the bias voltage VREF applied in the third sensing period BP3 of the third frame period FR3 to have a target voltage level of 5 V corresponding to 24 V as the level of the first power voltage VDD.

[0129] Therefore, in real-time sensing, the controller 140 can compensate the bias voltage VREF based on a pre-stored target voltage level according to the first power voltage VDD, which varies according to the input image data DATA1. Therefore, unlike the varying first power voltage VDD, the sensing current Ids is constantly maintained, so that the display device 100 can more accurately sense the characteristics of the driving transistor and prevent the degradation of the driving transistor due to the fluctuation of the sensing current Ids in advance.

[0130] Fig.10 1 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure. Hereinafter, a method will be described in which a display device including a pixel connected to a data line and a sensing line and having a light emitting element connected between a first power voltage node and a second power voltage node controls a bias voltage according to a controlled level of a first power voltage.

[0131] refer to Figure 1 and Fig.10 , also refer to Figure 8, in step S1010, the display device 100 may control the level of the first power voltage VDD applied during the frame period FR according to the input image data DATA1. The display device 100 may provide the first power voltage VDD and the second power voltage VSS to the first power voltage node and the second power voltage node connected to the pixel PX in the frame period FR, respectively. For example, the display device 100 may control the power supplier 150 according to the input image data DATA1 of the frame period FR, thereby controlling the level of the first power voltage VDD applied during the corresponding frame period FR. Therefore, the display device 100 may provide the pixel PX with a controlled level of the first power voltage VDD during the display period AP and the sensing period BP of the corresponding frame period FR.

[0132] In step S1020, the display device 100 may apply a bias voltage VREF to the data line. For example, the display device 100 may apply the bias voltage VREF to the pixel PX through the data line, and may provide the bias voltage VREF to the pixel PX during the sensing period BP of the corresponding frame period FR. The display device 100 may provide the bias voltage VREF to the pixel PX to measure the characteristics of the driving transistor included in the pixel PX. However, the bias voltage VREF may be applied as a voltage determined based on the level of the first power voltage VDD provided during the frame period FR.

[0133] In step S1030, the display device 100 may control the bias voltage VREF according to the controlled voltage level of the first power voltage VDD. When sensing is performed by applying the bias voltage VREF, as the first power voltage VDD changes according to the input image data DATA1 that changes within each frame period FR, the sensing current for sensing the characteristics of the driving transistor may change. Therefore, it is necessary to prevent the fluctuation of the sensing current caused by the change of the first power voltage VDD by controlling and applying the bias voltage VREF according to the change of the first power voltage VDD by the display device 100.

[0134] The display device 100 can control the bias voltage VREF provided to the pixel PX during the sensing period PB by using target voltage levels corresponding to one or more reference voltage levels within the voltage range of the first power voltage VDD, respectively. The display device 100 can select a first reference voltage level matching the controlled level of the first power voltage VDD among the one or more reference voltage levels, and control the bias voltage VREF to have a first target voltage level corresponding to the first reference voltage among the target voltage levels. For example, the display device 100 can control the level of the first power voltage VDD applied during the next frame period FR according to the next input image data DATA1 of the input image data DATA1, and control the bias voltage VREF applied to the data line in the sensing period BP of the next frame period FR according to the level of the first power voltage VDD applied during the next frame period FR. That is, the display device 100 can select a second reference voltage level matching the level of the first power voltage VDD for the next frame period FR, and control the bias voltage VREF to have a second target voltage level corresponding to the second reference voltage level among the target voltage levels.

[0135] In addition, the display device 100 may store a target voltage level corresponding to one or more reference voltage levels within a predetermined voltage range of the first power voltage VDD to control the bias voltage VREF. The display device 100 may store the reference voltage level and the target voltage level in advance. The reference voltage level and the target voltage level may be stored in the form of a lookup table for a specific value sensed as an electrical characteristic. In addition, the lookup table may be stored before the product is released and updated for each predetermined cycle period.

[0136] In step S1040, the display device 100 may sense the electrical characteristics of the pixel PX through the sensing line. For example, the display device 100 may apply a bias voltage VREF to the pixel PX through the sensing line, and sense the sensing capacitor CSEN by applying the bias voltage VREF during the sensing period BP of the corresponding frame period FR (see Figure 3 The charging voltage of the sensing capacitor CSEN may be a voltage charged by the sensing current by applying the bias voltage VREF for a certain period of time.

[0137] When the first power voltage VDD has a first reference voltage level and the bias voltage VREF has a first target voltage level corresponding to the first reference voltage level, the display device 100 can sense a first value as an electrical characteristic of the pixel PX through the sensing line. In addition, when the first power voltage VDD has a second reference voltage level and the bias voltage VREF has a second target voltage level corresponding to the second reference voltage level, the display device 100 can sense a second value as an electrical characteristic of the pixel PX through the sensing line. The first value and the second value correspond to the sensing current Ids (see Figure 2 ), and can be the same.

[0138] According to the present disclosure, a display device capable of sensing with improved reliability and a method of driving the display device may be provided.

[0139] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: A pixel, comprising a first transistor, a second transistor and a third transistor, wherein the first transistor has a drain electrode connected to a first power voltage node and a source electrode connected to a second power voltage node, the second transistor is connected between a data line and a gate electrode of the first transistor, and the third transistor is connected between a sensing line and the source electrode of the first transistor; a data driver connected to the pixel through the data line, the data driver applying a bias voltage to the data line during a sensing period of a frame period, wherein the frame period includes the sensing period and a display period; a sensing driver connected to the pixel through the sensing line, the sensing driver sensing an electrical characteristic of the pixel through the sensing line during the sensing period; and A controller is configured to control a first power voltage applied during the frame period according to input image data, and the controller adjusts the bias voltage according to the first power voltage.

2. The display device according to claim 1, wherein: The display device further includes a memory configured to store target voltage levels respectively corresponding to one or more reference voltage levels within a predetermined voltage range.

3. The display device according to claim 1, wherein: The controller selects a first reference voltage level from among one or more reference voltage levels, wherein the first reference voltage level is selected based on the level of the first power voltage, and the controller adjusts the bias voltage to a first target voltage level from among a plurality of target voltage levels corresponding to the first reference voltage level.

4. The display device according to claim 3, wherein: The controller: controlling the level of the first power voltage applied during a next frame period of the frame period according to next input image data of the input image data; as well as The bias voltage applied to the data line during the sensing period of the next frame period is adjusted according to the level of the first power voltage applied during the next frame period.

5. The display device according to claim 4, wherein: The controller selects a second reference voltage level from among the one or more reference voltage levels based on the level of the first power voltage applied during the next frame period, and adjusts the bias voltage to have a second target voltage level from among the multiple target voltage levels corresponding to the second reference voltage level.

6. The display device according to claim 5, wherein: The second reference voltage level is different from the first reference voltage level, and the second target voltage level is different from the first target voltage level.

7. The display device according to claim 2, wherein: The one or more reference voltage levels and the target voltage level are stored in the memory in the form of a lookup table.

8. The display device according to claim 1, wherein: when the first power voltage has a first reference voltage level among a plurality of reference voltage levels and the bias voltage has a first target voltage level among a plurality of target voltage levels corresponding to the first reference voltage level, sensing a first value as the electrical characteristic of the pixel through the sensing line, wherein, when the first power voltage has a second reference voltage level among the plurality of reference voltage levels and the bias voltage has a second target voltage level among the plurality of target voltage levels corresponding to the second reference voltage level, a second value is sensed as the electrical characteristic of the pixel through the sensing line, and The first value and the second value are the same.

9. The display device according to claim 2, wherein: The one or more reference voltage levels and the target voltage level are stored in the memory in the form of a lookup table for a particular value sensed as the electrical characteristic.

10. A method of driving a display device, the display device comprising a pixel, the pixel comprising a first transistor, a second transistor and a third transistor, the first transistor having a drain electrode connected to a first power voltage node and a source electrode connected to a second power voltage node, the second transistor connected between a data line and a gate electrode of the first transistor, the third transistor connected between a sensing line and the source electrode of the first transistor, in, The method comprises: providing a first power voltage and a second power voltage to the first power voltage node and the second power voltage node, respectively, in a frame period, wherein the first power voltage applied during the frame period varies according to input image data, and the frame period includes a display period and a sensing period; applying a bias voltage to the data line during the sensing period; and sensing an electrical characteristic of the pixel via the sensing line during the sensing period, and The bias voltage is adjusted according to the first power voltage.

Images