Content-addressable storage device and content-addressable storage controller

Abstract

The present disclosure provides a content-addressable storage device and a content-addressable storage controller, relating to the field of semiconductor technology. The device includes: N address registers, each for storing different address information; N counter circuits, each for storing the count value of the corresponding address register; N address comparison circuits, each for matching an input address with the address information stored in its corresponding address register; wherein, when the input address does not match the address information stored in any of the N address registers, and all of the N address registers store address information, the first counter circuit and its corresponding first address register are reset, the first address register stores the input address, the first counter circuit increases its count value, and the other unreset counter circuits decrease their count values. According to the embodiments of the present disclosure, accurate statistics can be performed on each address information in the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a content addressable storage device and a content addressable storage controller. Background Art

[0002] In the development of semiconductor technology, memories such as dynamic random access memory (DRAM) often involve various address information.

[0003] However, it is currently not possible to count address information.

[0004] Therefore, how to accurately count each address information in the memory has become a technical problem that needs to be solved urgently.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The present disclosure provides a content addressable storage device and a content addressable storage controller, which at least to some extent overcome the problem in the related art that it is impossible to accurately count the address information in the memory.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to one aspect of the present disclosure, there is provided a content-addressable storage device, comprising:

[0009] N address registers, each used to store different address information, where N is an arbitrary positive integer;

[0010] N counter circuits correspond to the N address registers one by one and are respectively used to store the count values ​​of the corresponding address registers;

[0011] N address comparison circuits correspond to N address registers one by one, and each address comparison circuit is used to match the input address with the address information stored in its corresponding address register;

[0012] When the input address matches the address information stored in one of the address registers, the count value of the counter circuit corresponding to the address register increases;

[0013] When the input address does not match the address information stored in the N address registers, and the N address registers all store address information, the first counter circuit and its corresponding first address register are reset, the first address register stores the input address, the first counter circuit increases its count value, and the other unreset counter circuits decrease their count values, wherein the first counter circuit is a counter to be reset determined among the N counter circuits based on the count value;

[0014] When the input address does not match the address information stored in the N address registers and there is a second address register, the input address is stored in the second address register and the count value of the corresponding second counter circuit is increased. The second address register is an address register in which no address information is stored among the N address registers.

[0015] In one embodiment, when the input address does not match the address information stored in any of the N address registers and the N address registers all store address information, the target counter circuit having a count value less than or equal to a preset number threshold is the first counter circuit, wherein resetting the first address register corresponding to the target counter circuit is used to clear the stored noise address;

[0016] When the input address does not match the address information stored in the N address registers, the N address registers all store address information, and no target counter circuit exists, one of the counter circuits with the smallest count value serves as the first counter circuit.

[0017] In one embodiment, the count value is M-bit binary data, and the i-th counter circuit includes M stages of counting units, wherein the j-th stage counting unit is used to record the j-th bit of the M-bit binary data, i is any positive integer less than or equal to N, M is any positive integer, and j is any positive integer less than or equal to M;

[0018] When increasing the count value of the i-th counter circuit, the M-stage counting unit is used to add 1 to the original count value to obtain the increased count value;

[0019] Furthermore, when the count value of the i-th counter circuit is reduced, the M-stage counting unit is used to store the reduced count value obtained by subtracting 1 from the original count value.

[0020] In one embodiment, the j-th stage counting unit includes a j-th stage DFF flip-flop among M stages of DFF flip-flops.

[0021] The inverting output terminal of the j-th stage DFF flip-flop is connected to the trigger terminal of the j+1-th stage DFF flip-flop, and the j-th stage DFF flip-flop is used to switch the recorded data between 0 and 1 according to the received trigger signal, and send a trigger signal to the j+1-th stage DFF flip-flop when the recorded data switches from 1 to 0. The trigger terminal of the first-stage DFF flip-flop is connected to the output terminal of the i-th address comparison circuit, and is used to switch between 0 and 1 when the i-th address comparison circuit outputs a first count signal. The i-th address comparison circuit outputs the first count signal when the input address matches the address information stored in the i-th address register.

[0022] The j-th stage DFF flip-flop includes a reset terminal and a set terminal. The j-th stage DFF flip-flop is further configured to: receive the j-th bit of the first reset signal through the reset terminal, receive the j-th bit of the first set signal through the set terminal, and adjust the recorded data to the j-th bit of binary data of the reduced count value according to the j-th bit of the first reset signal and the j-th bit of the first set signal.

[0023] The first reset signal and the first set signal are generated by the content addressable memory controller and are used to adjust the numerical value stored in the M-stage counting unit to the reduced counting value.

[0024] In one embodiment, the device further includes N status query circuits, and the N status query circuits correspond one-to-one to the N address registers.

[0025] Among them, the i-th state query circuit is used to output a first state signal for indicating that the i-th address register is in a storage state when the i-th address register stores address information; and to output a second state signal for indicating that the i-th address register is in an idle state when the i-th address register does not store address information.

[0026] In one embodiment, the first state signal includes: a first level signal of an idle state bit and / or a second level signal of a storage state bit;

[0027] The second state signal includes: a third level signal of an idle state bit and / or a fourth level signal of a storage state bit.

[0028] In one embodiment, the i-th state query circuit includes an SR trigger and a NOT gate unit.

[0029] The set input terminal of the SR trigger is used to receive the second set signal, the reset input terminal of the SR trigger is used to receive the second reset signal, and the output terminal of the SR trigger is used to output the level signal of the idle state bit.

[0030] The input end of the NOT gate unit is connected to the output end of the SR trigger, and the output end of the NOT gate unit is used to output the level signal of the storage status bit.

[0031] Among them, when the i-th address register stores address information, the i-th SR trigger receives a second set signal corresponding to the first level state, so that the i-th SR trigger outputs a first level signal of the idle state bit; and when the i-th address register does not store address information, the i-th SR trigger receives a second reset signal corresponding to the second level state, so that the i-th SR trigger outputs a third level signal of the idle state bit.

[0032] In one embodiment, the input address includes a P bit,

[0033] Wherein, the i-th address comparison circuit includes:

[0034] P address comparison units, wherein the kth address comparison unit is configured to output a first level signal when the kth bit of the address information stored in the ith address register is the same as the kth bit of the input address; wherein P is any positive integer, and k is any positive integer less than or equal to P;

[0035] A signal processing unit is connected to the P address comparison units and is used to generate a first counting signal when receiving the first level signals output by each of the P address comparison units. The first counting signal is used to indicate that the input address matches the address information stored in the i-th address register.

[0036] In one embodiment, the input address is a row address of an accessed physical row sent by a chip controller;

[0037] Each address register includes a first input terminal and a first output terminal, wherein the first input terminal is connected to the chip controller for obtaining a row address; and the first output terminal is used to output the stored address information;

[0038] Each address comparison circuit includes a second input terminal, a third input terminal, and a second output terminal, wherein the second input terminal is connected to the chip controller and is used to obtain the row address of the accessed physical row; the third input terminal is connected to the first output terminal of the corresponding address register; the second output terminal is connected to the fourth input terminal of the corresponding counter circuit and is used to provide a first counting signal to the fourth input terminal when the row address matches the address information stored in the corresponding address register;

[0039] Each counter circuit includes a fourth input terminal and a fifth output terminal. The fifth output terminal is connected to the row hammer attack controller and is used to provide the row hammer attack controller with the count value stored in the counter circuit, so that the row hammer attack controller recognizes the address information stored in the address register corresponding to the counter circuit as the row hammer attack address when the count value is greater than or equal to a preset row hammer threshold.

[0040] According to another aspect of the present disclosure, a content addressable storage controller is provided, configured to control the content addressable storage device, comprising:

[0041] a count value processing circuit connected to the output terminals of the N counter circuits, configured to obtain count values ​​of the N address registers; and when an input address does not match address information stored in the N address registers and the N address registers all store address information, determining a first address register according to the count values ​​of the N address registers;

[0042] The control circuit is used to reset the first counter circuit, update the count value of the reset first counter circuit, and control other unreset counter circuits to reduce their count values.

[0043] The content-addressable storage device and content-addressable storage controller provided by the embodiments of the present disclosure, for any counter circuit, the address counting module can increase the count value of the address counting circuit when the corresponding address comparison circuit determines that the input address matches the stored address information, thereby achieving correct counting of the input address stored in the address register. In addition, when all address registers store address information and the input address does not match the stored address information, the first address register to be reset can be determined among the N address registers, the count value of the counter circuit corresponding to the first address register can be reset and re-counted, and the count values ​​of other unreset counter circuits can be reduced, thereby ensuring counting accuracy while avoiding the impact of the counting results of each counter circuit being too large and exceeding the counting range of the address counting module on counting accuracy. In addition, since the second address register is an address register that does not store address information, when the input address does not match the stored address information and there is an idle second address register, the input address can be stored in the second address register to accurately count the newly appeared input address. Accordingly, the technical solution provided by the embodiment of the present disclosure can accurately count the input addresses stored in the address registers and the new input addresses not stored in the address registers when the N address registers are not full of addresses. Moreover, when the N address registers are full of addresses, while ensuring the counting accuracy, it can avoid the counting results of each counter circuit being too large and exceeding the counting range of the address counting module, which affects the counting accuracy, thereby realizing accurate counting of each address information in the memory.

[0044] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0046] Figure 1 A system architecture diagram of a CAM storage system provided by an embodiment of the present disclosure is shown;

[0047] Figure 2 A schematic structural diagram of a CAM storage device provided by an embodiment of the present disclosure is shown;

[0048] Figure 3 A schematic diagram showing the structure of an exemplary address register provided by an embodiment of the present disclosure is shown;

[0049] Figure 4 A schematic structural diagram of an exemplary counter circuit provided by an embodiment of the present disclosure is shown;

[0050] Figure 5 A schematic structural diagram of an address comparison circuit provided by an embodiment of the present disclosure is shown;

[0051] Figure 6 A schematic structural diagram of an exemplary address comparison circuit provided by an embodiment of the present disclosure is shown;

[0052] Figure 7 FIG2 shows a schematic structural diagram of another exemplary address comparison circuit provided by an embodiment of the present disclosure;

[0053] Figure 8 A counting logic diagram of an exemplary CAM storage device provided by an embodiment of the present disclosure is shown;

[0054] Figure 9 FIG2 shows another exemplary counting logic diagram of a CAM storage device provided by an embodiment of the present disclosure;

[0055] Figure 10 A counting logic diagram of another exemplary CAM storage device provided by an embodiment of the present disclosure is shown;

[0056] Figure 11 A counting logic diagram of another exemplary CAM storage device provided by an embodiment of the present disclosure is shown;

[0057] Figure 12 A schematic structural diagram of another CAM storage device provided by an embodiment of the present disclosure is shown;

[0058] Figure 13 A counting logic diagram of an exemplary CAM storage device provided by an embodiment of the present disclosure is shown;

[0059] Figure 14 A schematic structural diagram of another exemplary status query circuit provided by an embodiment of the present disclosure is shown;

[0060] Figure 15 A counting logic diagram of another exemplary CAM storage device provided by an embodiment of the present disclosure is shown;

[0061] Figure 16 A schematic structural diagram of an exemplary CAM storage device provided by an embodiment of the present disclosure is shown;

[0062] Figure 17 A schematic structural diagram of a CAM storage controller provided by an embodiment of the present disclosure is shown;

[0063] Figure 18 A schematic diagram of a flow chart of an address counting method provided by an embodiment of the present disclosure is shown;

[0064] Figure 19 A flow chart of an exemplary address counting method provided by an embodiment of the present disclosure is shown;

[0065] Figure 20 A flow chart of an address counting control method provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0066] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0067] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0068] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0069] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0070] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0071] In various scenarios in the field of semiconductor technology, it is often necessary to use the count value of address information to solve problems in various scenarios.

[0072] Taking the row hammer attack scenario as an example, over the past few decades, with the evolution of memory technology such as DRAM, the chip size of DRAM and other memories has gradually shrunk to reduce manufacturing costs. However, the threat posed by chip size to chip reliability is mainly reflected in the following two aspects. First, as the capacitor size of the memory cell decreases, the noise margin of the memory cell gradually decreases. Second, as the distance between adjacent memory cells gradually decreases, the memory cell becomes more susceptible to electromagnetic coupling and produces unpredictable field effects. Under the threats of the above two aspects, existing memory technology inevitably produces a new problem called row hammer attack. Since row hammer attack affects the reliability and security of memories such as DRAM, how to identify the row hammer attack address has become a technical problem that needs to be solved urgently.

[0073] Through research, the inventors discovered that when the number of accesses to the row hammer attack address of an attacking row reaches the row hammer threshold, data corruption will occur. Therefore, by counting the number of accesses to each physical row, a physical row with an access count greater than the row hammer threshold can be accurately identified as an attacking row, and the physical address of the attacking row can be identified as the row hammer attack address. In this solution, since the number of accesses to the physical row affects the accuracy of identifying the row hammer attack address, accurately counting the number of accesses to address information such as the physical row address becomes the key to accurately identifying the attacking row.

[0074] In summary, a technical solution is needed that can accurately count address information in a memory.

[0075] Based on this, the embodiments of the present disclosure provide a content-addressable storage device and a content-addressable storage controller, which can be applied to the address information counting scenario. Optionally, it can be applied to the recognition scenario of the row hammer attack address. Through the embodiments of the present disclosure, when the N address registers are not full of addresses, the input addresses stored in the address registers and the new input addresses not stored in the address registers can be accurately counted, and when the N address registers are full of addresses, while ensuring the counting accuracy, it is possible to avoid the counting results of each counter circuit being too large and exceeding the counting range of the address counting module, thereby achieving accurate counting of each address information in the memory.

[0076] Before introducing the technical solutions provided by the embodiments of the present disclosure, for ease of understanding, the technical terms involved in the embodiments of the present disclosure are first explained.

[0077] (1) Row Hammer attack: When a physical row in a chip is frequently accessed, it may cause capacitors in adjacent rows to lose too much charge before the refresh signal arrives, resulting in data loss. Specifically, it refers to the situation where the attacking row is frequently accessed within a refresh window, causing charge loss in the memory cells of the adjacent victim row.

[0078] (2) Row hammer attack address, i.e., the physical address of the attack row. In the disclosed embodiment, the row address to be detected whose access times reach a preset row hammer threshold can be used as the row hammer attack address to refresh the attack row and victim row corresponding to the row hammer attack address.

[0079] (3) Content-addressable memory (CAM), a type of memory that is addressed by content, is a special type of random access memory (RAM). Its main working mechanism is to automatically and simultaneously compare an input data item with all the data items stored in the CAM, determine whether the input data item matches the data items stored in the CAM, and output the matching information corresponding to the data item.

[0080] After introducing the above technical terms, in order to facilitate overall understanding, before starting to introduce the technical solutions provided by the embodiments of the present disclosure, the CAM storage system involved in the embodiments of the present disclosure will be described below.

[0081] Figure 1 FIG. 1 shows a system architecture diagram of a CAM storage system provided by an embodiment of the present disclosure. Figure 1 As shown, the CAM memory system may include a CAM memory device 10 and a CAM memory controller 20 .

[0082] The CAM storage device 10 is used to store different input addresses and count the number of inputs of each input address. Figure 1 In order to facilitate counting of address information in the chip, the CAM storage device 10 can be connected to the chip controller 30 so as to obtain input addresses from the chip controller 30.

[0083] The CAM memory controller 20 is connected to the CAM memory device 10 and is configured to control each counter circuit in the CAM memory device 10 to reduce its count value. Exemplarily, when all N address registers store address information and the input address does not match the address information stored in the N address registers, the CAM memory controller 20 is configured to send the reduced count value to the remaining counters that have not been reset, so that the remaining counters that have not been reset are reset to the reduced count value.

[0084] Optionally, embodiments of the present disclosure may further provide a row hammer attack control system, which may include the aforementioned CAM storage system and a row hammer attack controller. The row hammer attack controller may be connected to the CAM storage device 10, and the row hammer attack controller may be connected to the CAM storage controller 20. For example, the row hammer attack controller may obtain the number of accesses to each physical row from the CAM storage device 10, and identify physical row addresses with accesses greater than or equal to a preset row hammer threshold as row hammer attack addresses.

[0085] After introducing the CAM storage system provided by the embodiment of the present disclosure, the CAM storage device 10 and the CAM storage controller 20 are described one by one.

[0086] Figure 2 FIG. 1 shows a schematic diagram of the structure of a CAM storage device provided by an embodiment of the present disclosure. Figure 2 As shown, the CAM memory device 20 may include N address registers 111 to 11N, N counter circuits 121 to 12N, and N address comparison circuits 131 to 13N, where N is any positive integer.

[0087] The N address registers 111 to 11N are each used to store different address information. For example, each address register can store address information when it is stored. Furthermore, when it is not stored, it remains idle. For example, the first address register can store address A1, the second address register can store address A2, ..., and the Nth address register can store address AN.

[0088] The address information may be an address to be counted. For example, it may be an address in binary format. For example, it may include P bits of binary data. P may be any positive integer, such as 17. It should be noted that P may be set to other values ​​based on the actual chip situation and specific chip requirements, and there is no specific limitation on this. In one embodiment, to accurately count the input address, the address information may be an input address previously input into the CAM storage device. In another embodiment, to accurately count a specific address, the address information may be a pre-set specific address.

[0089] In one embodiment, when the address information includes P bits, each address register may include P latches. The kth latch is used to store the kth bit of the address information. Each latch may be an edge trigger or a level trigger, which is not specifically limited. For example, when the rising edge of the clock signal arrives, each latch may store the data provided by the input terminal. Furthermore, the latched data can be read through the output terminal of each latch.

[0090] In one example, Figure 3 FIG. 1 shows a schematic diagram of the structure of an exemplary address register provided by an embodiment of the present disclosure. Figure 3 As shown, the i-th address register 11i may include P latches L1 to LP. Wherein, i can be any positive integer less than or equal to N. For each latch, it may include an input terminal D, a clock signal input terminal CK, an output terminal Q, and an inverting output terminal / Q. In a specific example, each latch may include a P-type metal-oxide semiconductor field effect transistor (P Metal Oxide Semiconductor, PMOS) and / or an N-type metal-oxide semiconductor field effect transistor (NMetal Oxide Semiconductor, NMOS). For example, PMOS and / or NMOS with a small W / L (width-to-length ratio) (for example, less than a preset width-to-length ratio threshold, wherein the preset width-to-length ratio threshold can be set according to actual conditions or specific needs) can be selected. It should be noted that, compared with standard cells (StandCell), latches composed of PMOS and / or NMOS with a small W / L can save more area resources while ensuring functionality.

[0091] For example, when the clock signal at the clock signal input terminal CK is at a rising edge, each latch is triggered by the rising edge of the clock signal to output the data at the input terminal D to the output terminal Q. <p-1:0>, the input terminal D of latch L1 outputs the address information RA <p-1:0>The first RA <0> And output RA_CAM through output terminal Q <0> , the input terminal D of latch L2 outputs the second bit RA <1> And output RA_CAM through output terminal Q <1> , ..., the input terminal D of the latch LP outputs the Pth bit RA <p-1>And output RA_CAM through output terminal Q <p-1>.

[0092] It should be noted that the address register may also be implemented as other circuits, functional modules or devices with address information storage functions, and there is no specific limitation on this.

[0093] In one embodiment, the output terminal of each address register is further connected to the address output terminal for outputting the stored address information from the address output terminal. For example, the address information N*RA_CAM stored in the N address registers 111 to 11N can be output from the address output terminal.<P-1:0> , for example 6*RA_CAM<16:0>.

[0094] After introducing the address register, we will continue to explain the counter circuit.

[0095] The N counter circuits 121 to 12N correspond one-to-one with the N address registers 111 to 11N, and are respectively used to store the count value of the corresponding address register. For example, the first counter circuit 121 corresponds to the first address register 111. For example, the first counter circuit 121 is used to store the count value of the first address register 111; the second counter circuit 122 corresponds to the second address register 112 and is used to store the count value of the second address register 112; ...; the Nth counter circuit 12N corresponds to the Nth address register 11N and is used to store the count value of the Nth address register 11N.

[0096] The count value of each address register can be used to represent the number of times the input address is the address information stored in the address register. In some embodiments, each count value can be M-bit binary data in binary format, that is, a binary string RA_CNT consisting of M data "1" or "0". <m-1:0>, M is any positive integer. Accordingly, the count value of each address register can be in the range of 0 to 2M-1.

[0097] In one example, in a row hammer attack address counting scenario, to accurately count row hammer attack addresses and reduce counter costs, M can be set to 6. For example, the count value can be represented as RA_CNT<5:0>. It should be noted that the value of M can also be set to other values ​​based on the specific counting scenario and specific counting requirements, and there is no limitation on this.

[0098] In some embodiments, when the count value includes M-bit binary data, the i-th counter circuit includes M-stage counting units, where i is any positive integer less than or equal to N. That is, any counter circuit may include M-stage counting units.

[0099] The j-th stage counting unit in each counter circuit is used to record the j-th bit of M-bit binary data, where j is any positive integer less than or equal to M. Exemplarily, for each counter circuit, the first-stage counting unit is used to record the first bit of the count value, the second-stage counting unit is used to record the second bit of the count value, ..., and the M-th stage counting unit is used to record the M-th bit of the count value.

[0100] When increasing the count value of the i-th counter circuit, the M-stage counting unit is used to add 1 to the original count value to obtain the increased count value. For example, if the original count value is "111000", the increased count value can be "111001".

[0101] Furthermore, when the count value of the i-th counter circuit is decreased, the M-stage counting unit is configured to store the decreased count value obtained by decrementing the original count value by 1. Exemplarily, the decreased count value may be obtained by the CAM memory controller decrementing the pre-decrement count value by 1. Exemplarily, if the original count value is "111000," the CAM memory controller may decrement the original count value by 1 to obtain "110111," and store "110111" in the counter circuit.

[0102] Exemplarily, the jth stage counting unit in the M stages of counting units is used to store the jth bit of the decremented count value. For example, if the decremented count value is "110111", the 1st-3rd and 5th-6th stage counting units are used to store data "1", and the 4th stage counting unit is used to store data "0".

[0103] Through the counter circuit provided in this embodiment, the M-bit binary data of the count value can be stored respectively through the M-level counting units of each counter circuit, and when the count value is increased, the original count value of the counter circuit can be added by 1, and when the count value is decreased, the original count value can be subtracted by 1 and then stored in the counter circuit. The address can be added and subtracted flexibly and accurately, thereby improving the accurate counting of address information.

[0104] In one example, the i-th counter circuit includes M-stage DFF triggers, and the j-th stage counting unit includes the j-th stage DFF trigger among the M-stage DFF triggers. Figure 4 FIG. 1 shows a schematic structural diagram of an exemplary counter circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the i-th counter circuit 12i may include M stages of DFF flip-flops D1 to DM. In a specific example, the DFF flip-flops may be composed of PMOS and / or NMOS. For example, PMOS and / or NMOS with a small W / L (width-to-length ratio) (e.g., less than a preset width-to-length ratio threshold, where the preset width-to-length ratio threshold can be set based on actual conditions or specific requirements) may be selected. It should be noted that, compared to standard cells, DFF flip-flops composed of PMOS and / or NMOS with a small W / L can save significant area resources while ensuring functionality.

[0105] Wherein, the inverting output terminal of the j-th level DFF trigger is connected to the trigger terminal of the j+1-th level DFF trigger, and the j-th level DFF trigger is used to switch the recorded data between 0 and 1 according to the received trigger signal, and when the recorded data switches from 1 to 0, send a trigger signal to the j+1-th level DFF trigger, wherein the trigger terminal of the first-level DFF trigger is connected to the output terminal of the i-th address comparison circuit, and is used to switch between 0 and 1 when the i-th address comparison circuit outputs the first counting signal. Wherein, the i-th address comparison circuit outputs the first counting signal when the input address matches the address information stored in the i-th address register. Exemplarily, the first counting signal can be set to a high-level signal or a low-level signal according to actual conditions and specific scenarios. For example, the first counting signal can be a high-level signal. In a specific example, continue to refer to Figure 4 The trigger terminal of the first-stage DFF flip-flop D1 is connected to the output terminal of the address comparison module 13i, and is used to receive the first counting signal match_bit (e.g., a high-level signal) output by the address comparison module 13i. The first counting signal match_bit serves as the trigger signal for the first-stage DFF flip-flop D1. The inverting output terminal / Q of the first-stage DFF flip-flop D1 is connected to the trigger terminal of the second-stage DFF flip-flop D2, and is used to send a trigger signal (e.g., a high-level signal) to the second-stage DFF flip-flop. ... The inverting output terminal / Q of the M-th-stage DFF flip-flop DM is connected to the trigger terminal of the M-1-th-stage DFF flip-flop DM-1. Upon receiving the trigger signal, each DFF flip-flop can switch the stored data from "0" to "1" or from "1" to "0." Furthermore, when the stored data switches from "1" to "0," the inverting output terminal / Q of the DFF flip-flop in that stage outputs a high-level signal as the trigger signal for the next-stage DFF flip-flop.

[0106] Furthermore, the first reset signal and the first set signal generated by the content addressable memory controller can be used to adjust the value stored in the M-stage counting unit to the reduced count value. Accordingly, the j-th stage DFF trigger includes a reset terminal and a set terminal. The j-th stage DFF trigger is further configured to: receive the j-th bit of the first reset signal through the reset terminal, and receive the j-th bit of the first set signal through the set terminal, and adjust the recorded data to the j-th bit of binary data of the reduced count value according to the j-th bit of the first reset signal and the j-th bit of the first set signal. In a specific example, see further. Figure 4 Each level of the DFF flip-flop may include a reset terminal CLR and a set terminal SET. When the j-th bit of the DFF flip-flop of this level needs to be set to "1," a second-level signal (e.g., a high-level signal) may be applied to its set terminal SET. When the j-th bit of the DFF flip-flop needs to be reset to "0," a second-level signal may be applied to its reset terminal CLR.

[0107] Optionally, continue with Figure 4 The i-th counter circuit 12i can receive the set signal SET provided by the CAM memory controller <m-1:0>, where the set signal SET <m-1:0>The jth bit in is used to set the jth level DFF trigger. And, the set signal SET <m-1:0>The reset signal of the i-th counter circuit 12i is obtained by inverting the reset signal, wherein the j-th bit of the reset signal is used to reset the j-th stage DFF trigger. <m-1:0>The first SET <0> Used to set the first-stage DFF trigger and the first bit SET <0> After inversion, the first bit of the reset signal is obtained. The first bit of the reset signal is used to reset the first-stage DFF flip-flop; the set signal SET <m-1:0>The second SET <1> Used to set the second-stage DFF trigger and the second bit SET <1> After inversion, the second bit of the reset signal is obtained. The second bit of the reset signal is used to reset the second-stage DFF flip-flop; the set signal SET <m-1:0>The Mth bit SET <m-1>Used to set the M-th level DFF trigger, and the M-th bit SET <m-1>After inversion, the Mth bit of the reset signal is obtained, and the Mth bit of the reset signal is used to reset the Mth stage DFF flip-flop.

[0108] The M-level DFF trigger provided in this embodiment can connect the inverting output terminal / Q of the previous-level trigger of the M-level DFF trigger to the trigger terminal of the next-level trigger. When the value stored in the previous-level trigger is "0", the stored value can be increased to 1 in response to a trigger signal; and when the previous-level trigger switches from 1 to 0, the next-level trigger can be controlled to switch between 0 and 1, thereby realizing a carry of the count value. When the address comparison circuit outputs the first counting signal to the first-level DFF trigger, the M-level DFF trigger can be used to coordinate the counting to add 1 to the original count value, thereby realizing the accumulation of the count value. In addition, by sending the set signal and reset signal corresponding to the reduced count value to the M-level trigger, the count value can be decremented. Therefore, the M-level DFF trigger of the disclosed embodiment can realize the counting functions of accumulation and decrement, thereby improving the counting accuracy of address information.

[0109] Furthermore, it should be noted that, due to the characteristics of a simple structure and a small area, the DFF trigger can reduce the cost and area of ​​a CAM storage device, facilitate integration, and save costs.

[0110] It should be noted that the M-level counting unit in the embodiment of the present disclosure may also be implemented as other devices with counting functions, and there is no specific limitation on this.

[0111] Furthermore, it should be noted that the counter circuit provided in the embodiments of the present disclosure may also be implemented as other devices, circuits, or chips with counting functions, and there is no specific limitation on this.

[0112] In one embodiment, the output end of each counter circuit is further connected to the output end of each DFF flip-flop, so as to output the stored count value from the output end of each DFF flip-flop. For example, the count value N*RA_CNT stored by the N counter circuits 121 to 12N can be output from the output end of each DFF flip-flop. <m-1:0>, for example 6*RA_CNT<5:0>.

[0113] After introducing the counter circuit, we will continue to explain the address comparison circuit.

[0114] The N address comparison circuits 131 to 13N correspond one-to-one to the N address registers 111 to 11N. Each address comparison circuit is configured to match an input address with the address information stored in its corresponding address register. For example, the first address comparison circuit 131 corresponds to the first address register 111 and is configured to match the input address with address A1 stored in the first address register; the second address comparison circuit 132 corresponds to the second address register 112 and is configured to match the input address with address A2; ...; the Nth address comparison circuit 13N corresponds to the Nth address register 11N and is configured to match the input address with address AN.

[0115] Exemplarily, for each address comparator, when the input address is consistent with the address information stored in its corresponding address register, it can be determined that the two match; similarly, when the input address is inconsistent with the address information stored in the address register, it can be determined that the two do not match.

[0116] In one embodiment, Figure 5 FIG. 1 shows a schematic diagram of the structure of an address comparison circuit provided by an embodiment of the present disclosure. Figure 5 As shown, the i-th address comparison circuit 13i includes: P address comparison units 13i1 and a signal processing unit 13i2.

[0117] The kth address comparison unit 13i1 is used to compare the address information RA_CAM stored in the i-th address register. <p-1:0>The kth RA_CAM <k-1>With input address RA <p-1:0>The kth RA <k-1>Under the same circumstances, a first level signal is output. Wherein, P is any positive integer, and k is any positive integer less than or equal to P. Exemplarily, the first level signal can be a low level signal or a high level signal, which can be set according to specific circumstances and actual needs, and is not specifically limited to this. For example, the first level signal can be a low level signal.

[0118] In one example, Figure 6 FIG. 1 shows a schematic diagram of an exemplary address comparison circuit provided by an embodiment of the present disclosure. Figure 6 As shown, the address comparison unit 13i1 includes an XOR gate XOR_1. The kth XOR gate XOR_1 includes a first input terminal X11, a second input terminal X12 and an output terminal Y1. The first input terminal X11 is used to receive the address information RA_CAM stored in the i-th address register. <p-1:0>The kth RA_CAM <k-1>The second input terminal X12 is used to receive the input address RA <p-1:0>The kth RA <k-1>, the output terminal Y1 is used to store the kth bit of the address information RA_CAM <k-1>and the kth bit RA of the input address <k-1>When the first level signal matches the first level signal, the first level signal is output.

[0119] In this example, since the XOR gate can output a low level when the two input terminals are the same, and output a high level when the two input terminals are different, the kth bit RA_CAM of the address information is input to the two input terminals of each XOR gate. <k-1>and the kth bit RA of the input address <k-1>If the two are the same, the output of the XOR gate outputs a low-level signal, and if they are different, the output of the XOR gate outputs a high-level signal. Therefore, based on the logical function of the XOR gate, it is possible to accurately determine whether the input address and the same bit data of the stored address information are the same, thereby improving the accuracy of determining whether the input address and the stored address information are the same, thereby improving the accuracy of counting.

[0120] It should also be noted that the XOR gate has the characteristics of simple structure and small area, which can reduce the manufacturing cost and occupied area of ​​the CAM storage device.

[0121] In another example, Figure 7 FIG. 1 shows a schematic diagram of another exemplary address comparison circuit provided by an embodiment of the present disclosure. Figure 7 As shown, the address comparison unit 13i1 includes an exclusive OR gate XOR_2 and a NOT gate NOT_1.

[0122] like Figure 7 As shown, the kth XOR gate XOR_2 includes a third input terminal X31, a fourth input terminal X32 and an output terminal Y3. The third input terminal X31 is used to receive the address information RA_CAM stored in the i-th address register. <p-1:0>The kth RA_CAM <k-1>The fourth input terminal X32 is used to receive the input address RA <p-1:0>The kth RA <k-1>The output terminal Y3 is connected to the input terminal X41 of the NOT gate NOT_1, and the output terminal Y4 of the NOT gate NOT_1 is used to store the kth bit RA_CAM of the address information. <k-1>and the kth bit RA of the input address <k-1>When the first level signal matches the first level signal, the first level signal is output.

[0123] In this example, since the XOR gate can output a low level when the two input terminals are the same, and output a high level when the two input terminals are different, the kth bit RA_CAM of the address information is input to the two input terminals of each XOR gate. <k-1>and the kth bit RA of the input address <k-1>When the two are identical, the output of the XOR gate outputs a low-level signal, and after being inverted by the NOT gate, outputs a high-level first-level signal. And if the two are different, the output of the XOR gate outputs a high-level signal, and after being inverted by the NOT gate, outputs a low-level signal. Thus, based on the logical functions of the XOR gate and the NOT gate, it is possible to accurately determine whether the input address and the stored address information are identical, thereby improving the accuracy of determining whether the input address and the stored address information are identical, and thus improving counting accuracy. It should be noted that the XOR gate and the NOT gate have the characteristics of a simple structure and a small area, which can reduce the manufacturing cost and occupied area of ​​the CAM storage device.

[0124] It should be noted that the address comparison unit 13i1 can also be set as a device, circuit or functional module that can generate an output signal according to whether the signals at the first input terminal and the second input terminal are the same. For example, it can be implemented as a comparator, etc., and there is no specific limitation on this.

[0125] After the address comparison unit 13i1 has been described, the signal processing unit 13i2 will be described.

[0126] Continue to see Figure 5 The signal processing unit 13i2 is connected to the P address comparison units 13i1 and is used to generate a first counting signal match_bit when receiving the first level signals output by each of the P address comparison units. The first counting signal match_bit is used to represent the input address RA <p-1:0>The address information stored in the i-th address register RA_CAM <p-1:0>Match.

[0127] In one example, when the first level signal is at a low level, for example, when the address comparison unit 13i1 includes an XOR gate XOR_1, see Figure 6 The signal processing unit 13i2 may include a NOR gate NOR_1. Multiple input terminals X21 to X2P of the NOR gate are connected in a one-to-one correspondence with the output terminals of the P exclusive-OR gates XOR_1. The output terminal Y2 of the NOR gate is configured to output a high-level first counting signal when all input terminals X21 to X2P receive low-level signals.

[0128] In this example, since each address comparison unit outputs a low-level signal when the input address matches the stored address information, and since the NOR gate can output a high-level signal when all input terminals receive a low-level signal, the logic function of the NOR gate can be used to generate a high-level first count signal when each address comparison unit outputs a low-level signal. Consequently, when the input address matches the stored address information, the first count signal can be sent to accumulate the existing count value, thereby improving the cumulative counting accuracy of the CAM storage device. It should be noted that the NOR gate has a simple structure and a small footprint, which can reduce the manufacturing cost and occupied area of ​​the CAM storage device.

[0129] In another example, when the first level signal is at a high level, see Figure 7 The signal processing unit 13i2 may include an AND gate AND_1. The AND gate AND_1 includes P input terminals X51 to X5P and an output terminal Y5. The P input terminals X51 to X5P are connected to the output terminals Y4 of the P NOT gates in a one-to-one correspondence. The output terminal Y5 is configured to output a first counting signal match_bit when all the P input terminals X51 to X5P receive a high-level first level signal.

[0130] In this example, since the AND gate can output a high-level signal when high levels are input to multiple input terminals, accordingly, when the input address is the same as the stored address information, each address comparison unit will output a high-level signal, and a high-level first counting signal can be generated through the AND gate.

[0131] It should also be noted that the AND gate has the characteristics of simple structure and small area, which can reduce the manufacturing cost and occupied area of ​​the CAM storage device.

[0132] It should be noted that the signal processing unit 13i2 can also be set as a device, circuit or functional module that can generate an output signal based on whether the signals at the first input end and the second input end are the same. For example, it can be implemented as a comparator, etc., and there is no specific limitation on this.

[0133] After introducing the components of the CAM storage device 20 , the CAM storage device 20 will be further described in combination with three matching situations between address information and input addresses.

[0134] In the first matching case, when the input address matches the address information stored in one of the address registers, the count value of the counter circuit corresponding to the address register increases.

[0135] For example, Figure 8 FIG. 1 shows a counting logic diagram of an exemplary CAM storage device provided by an embodiment of the present disclosure. Figure 8 As shown, taking a CAM storage device including 6 address registers, which respectively store addresses A1 to A6, as an example, if the input address is address A4, the count value of the fourth counter circuit corresponding to the fourth address register can be increased by 1 from the original count value "111000" to obtain a new count value "111001", and the count values ​​of other counter circuits remain unchanged.

[0136] In the second matching situation, when the input address does not match the address information stored in the N address registers, and the N address registers all store address information, the first counter circuit and its corresponding first address register are reset. Also, the first address register stores the input address, the first counter circuit updates its count value, and the other unreset counter circuits reduce their count values. Among them, the first counter circuit is a counter to be reset determined among the N counter circuits based on the count value. Exemplarily, when the first address register is reset, the address information stored therein can be cleared. Exemplarily, when the first counter circuit is reset, its count value can be updated to an initial value, and the initial value can be binary data corresponding to the value 0 or binary data corresponding to the value 1, without specific limitation.

[0137] For example, Figure 9 FIG. 2 shows another exemplary counting logic diagram of a CAM storage device provided by an embodiment of the present disclosure. Figure 9 Continuing with the previous example, when the input address is address A7, since the six address registers already store addresses A1-A6, if the fifth counter circuit (i.e., storing the count value "000001" corresponding to address 5) is determined to be the first counter circuit, the corresponding address register, i.e., the fifth address register, can be reset. This means that address A5 in the fifth address register is cleared and the count value of the fifth counter circuit is reset to "000000." Then, address A7 can be written to the fifth counter circuit, and the count value of the fifth counter circuit is updated to "000001."

[0138] Furthermore, the count values ​​of the counter circuits corresponding to the remaining five address registers except the fifth address register may be reduced by 1.

[0139] The first counter is described in detail as follows.

[0140] In one embodiment, the first counter may be a counter circuit corresponding to a first address register storing a noise address.

[0141] For example, when the input address does not match the address information stored in any of the N address registers, and all of the N address registers store address information, the target counter circuit having a count value less than or equal to a preset number threshold is the first counter circuit. Resetting the first address register corresponding to the target counter circuit is used to clear the stored noise address. For example, the preset number threshold can be set based on actual conditions and specific requirements, such as 1, and is not specifically limited thereto.

[0142] For example, when the preset number of times threshold is 1, continue to refer to Figure 9 , since the count value of address A5 is less than or equal to 1, address A5 can be determined as a noise address, and the 5th address register and the 5th counter circuit are reset, and the input address A7 and the count value of input address A7 are written.

[0143] Through this embodiment, when the address register of the CAM storage device is full of address information, useless noise addresses can be discarded, and the position of the address register can be reserved for valid address information, thereby improving the accuracy and efficiency of address counting. In addition, when discarding noise addresses, in order to avoid the influence of noise addresses on the count value of stored address information, the count value of the remaining address information is reduced by 1, so as to avoid the influence of noise addresses on the counting result, thereby improving the accuracy of address counting. Furthermore, in the recognition scenario of row hammer attack addresses, by discarding row hammer noise addresses, row hammer noise addresses can be screened out in advance during subsequent row hammer attack address recognition, ensuring that row hammer attack addresses can be recognized based on valid address information and access at this time. In addition, the counting accuracy of the number of accesses to each physical row address is improved, thereby improving the row hammer noise recognition accuracy and recognition efficiency.

[0144] In another embodiment, when there is no target counting circuit, the first counter may be a counter circuit with the smallest count value.

[0145] For example, when the input address does not match the address information stored in the N address registers, the N address registers all store address information, and no target counter circuit exists, one of the counter circuits with the smallest count value serves as the first counter circuit.

[0146] For example, Figure 10 FIG. 2 shows another exemplary counting logic diagram of a CAM storage device provided by an embodiment of the present disclosure. Figure 10 As shown, since the count values ​​of addresses A1-A7 are all greater than 1, addresses A1-A7 are not noise addresses. At this time, since the count value of address A4 is the smallest, the address register storing address A4 (the 4th address register) and the count value of the counter circuit (the 4th counter circuit) corresponding to address A4 can be reset.

[0147] Through this embodiment, the address register and counter circuit for the address information with the minimum count value can be reset when no noise addresses are present. Since the minimum count value indicates that the address information has not been input for a long time within a preset time period, this embodiment can clear the address information that has not been input for a long time, thus avoiding waste of address register resources. Furthermore, it can count address information that is input frequently, improving counting accuracy and reliability. Furthermore, in the identification scenario of row hammer attack addresses, the minimum count value indicates that the address information has a low access frequency within the preset time period. By clearing this count value, it can prevent low-frequency addresses from wasting resources on the CAM storage device. Furthermore, since the access frequency of a physical row address determines the probability that it is a row hammer attack address, by clearing physical row addresses with low access frequencies, it is possible to count physical row addresses with high access frequencies. Therefore, when CAM storage device resources are limited, row hammer attack addresses can be identified from physical row addresses with a high probability of being row hammer attack addresses, thereby improving the recognition accuracy of row hammer attack addresses.

[0148] It should be noted that the first counter circuit may also be determined by other reset conditions related to the count value, and there is no specific limitation on this.

[0149] In the third matching scenario, when the input address does not match any of the address information stored in the N address registers and a second address register exists, the input address is stored in the second address register and the count value of the corresponding second counter circuit is updated. The second address register is an address register among the N address registers that does not store address information. Alternatively, when multiple second address registers exist, the input addresses may be stored in the order of the second address registers.

[0150] For example, Figure 11 FIG. 2 shows another exemplary counting logic diagram of a CAM storage device provided by an embodiment of the present disclosure. Figure 11 As shown, when neither the 5th address register nor the 6th address register stores address information, that is, when both are in an idle state, the input address A5 can be stored in the 5th address register, and the count value of the 5th counter circuit (that is, the second counter circuit) can be updated to "000001".

[0151] The CAM storage device provided by the embodiment of the present disclosure has an address counting module for any counter circuit. When the address comparison circuit corresponding to the address counting module determines that the input address matches the stored address information, the count value of the address counting circuit is increased, thereby achieving correct counting of the input address stored in the address register. Furthermore, when all address registers store address information and the input address does not match the stored address information, the first address register to be reset can be determined among the N address registers, the count value of the counter circuit corresponding to the first address register is reset and re-counted, and the count values ​​of other unreset counter circuits are reduced. This ensures counting accuracy while preventing the counting results of each counter circuit from being too large and exceeding the counting range of the address counting module. Furthermore, since the second address register is an address register that does not store address information, when the input address does not match the stored address information and there is an idle second address register, the input address can be stored in the second address register to accurately count the newly appearing input address. Accordingly, the technical solution provided by the embodiment of the present disclosure can accurately count the input addresses stored in the address registers and the new input addresses not stored in the address registers when the N address registers are not full of addresses. Moreover, when the N address registers are full of addresses, while ensuring the counting accuracy, it can avoid the counting results of each counter circuit being too large and exceeding the counting range of the address counting module, which affects the counting accuracy, thereby realizing accurate counting of each address information in the memory.

[0152] Optionally, in the row hammer attack address identification scenario, by resetting the first counter circuit and the first address register, the retained address can be a row address with a high access frequency, that is, a row hammer attack address, and a refresh operation can be performed on the retained row address.

[0153] In some embodiments, in order to accurately identify the row hammer attack address, the input address may be a row address of the accessed physical row sent by the chip controller.

[0154] Accordingly, for each address register, taking the i-th address register 11i as an example, the address register 11i includes a first input terminal and a first output terminal. The first input terminal is connected to the chip controller and is used to obtain the row address of the accessed physical row sent by the chip controller. The first output terminal is used to output the stored address information Ai. Exemplarily, the address register may also include a clock signal input terminal. When the clock signal is at a rising edge, the row address received at the first input terminal may be stored.

[0155] For each address comparison circuit 13i, taking the i-th address comparison circuit 13i as an example, the address comparison circuit 13i includes a second input terminal, a third input terminal, and a second output terminal. The second input terminal is connected to the chip controller and is used to obtain the row address of the accessed physical row. The third input terminal is connected to the first output terminal of its corresponding address register (address register 11i). The second output terminal is connected to the fourth input terminal of its corresponding counter circuit (counter circuit 12i) and is used to provide a first count signal to the fourth input terminal when the row address of the accessed physical row matches the address information Ai stored in the address register 11i.

[0156] For each counter circuit, taking the i-th counter circuit 12i as an example, the counter circuit 12 includes a fourth input terminal and a fifth output terminal. The fifth output terminal is connected to the row hammer attack controller and is used to provide the count value stored in the counter circuit to the row hammer attack controller, so that the row hammer attack controller recognizes the address information Ai stored in the address register 11i as the row hammer attack address when the count value is greater than or equal to the preset row hammer threshold.

[0157] Through this embodiment, the number of accesses to the row address of the physical row can be accurately counted, and based on the high-accuracy access number, it can be accurately detected whether the stored row address to be detected is a row hammer attack address, thereby improving the recognition accuracy of the row hammer attack address.

[0158] Based on the same inventive concept, Figure 12 A schematic structural diagram of another CAM storage device provided by an embodiment of the present disclosure is shown. Figure 12 and Figure 11 The difference is that the CAM memory device may further include N status query circuits 141 to 14N.

[0159] The N status query circuits 141-14N correspond one-to-one to the N address registers 111-11N. For example, the status query circuit 141 corresponds to the address register 111, the status query circuit 142 corresponds to the address register 112, ..., and the status query circuit 14N corresponds to the address register 11N.

[0160] The i-th state query circuit 14i is configured to output a first state signal indicating that the i-th address register 11i is in a storage state when the i-th address register 11i stores address information Ai, and to output a second state signal indicating that the i-th address register 11i is in an idle state when the i-th address register 11i does not store address information Ai.

[0161] In some embodiments, different levels of at least one bit may be used to represent the first state signal and the second state signal respectively.

[0162] In one example, the state of the address register can be represented by an idle state bit OP and a storage state bit LO. Figure 13 FIG. 1 shows a counting logic diagram of an exemplary CAM storage device provided by an embodiment of the present disclosure. Figure 13 As shown, the first state signal includes: a first level signal of the idle state bit OP and a second level signal of the storage state bit LO. The second state signal includes: a third level signal of the idle state bit OP and a fourth level signal of the storage state bit LO. Exemplarily, one of the first level signal and the third level signal is a high level signal, and the other is a low level signal. Exemplarily, one of the second level signal and the fourth level signal is a high level signal, and the other is a low level signal.

[0163] The idle state bit OP is used to indicate whether the address register is in an idle state. Optionally, when the idle state bit OP is a high-level signal, it indicates that the address register stores an address. Correspondingly, when the idle state bit OP is a low-level signal, it indicates that the address register is in an idle state.

[0164] Furthermore, the storage status bit LO is used to indicate whether the address register is in a storage state. Optionally, when the storage status bit LO is a low-level signal, it indicates that the address register stores an address. Correspondingly, when the storage status bit LO is a high-level signal, it indicates that the address register is in an idle state.

[0165] In another example, the state of the address register can be represented by the idle state bit OP. Accordingly, the first state signal includes a high level signal of the idle state bit OP. The second state signal includes a low level signal of the idle state bit OP.

[0166] In yet another example, the state of the address register may be represented by a storage state bit LO. Accordingly, the first state signal includes a low-level signal of the storage state bit LO. The second state signal includes a high-level signal of the storage state bit LO.

[0167] In the above examples, the state query circuit can accurately characterize whether each address register stores an address by the level of the idle state bit and / or the storage state bit. Then, during the address counting process, the state of each address register can be determined according to the idle state bit and / or the storage state bit of the state query circuit to perform different counting methods. For example, if it is determined according to the idle state bit and / or the storage state bit that N address registers all store address information and the input address is inconsistent with each address information, the first counter circuit is reset. For another example, if it is determined according to the idle state bit and / or the storage state bit that the input address does not match the stored address information and there is an idle address register, the input address is stored in the idle address register, etc. This allows for accurate and efficient address counting, improving counting accuracy and counting efficiency.

[0168] It should be noted that the first state signal and the second state signal may also be implemented as other bits, and there is no specific limitation on this.

[0169] After introducing the first state signal and the second state signal, the specific structure of the state query circuit will be described next.

[0170] In one example, Figure 14 A structural diagram of another exemplary status query circuit provided by an embodiment of the present disclosure is shown.

[0171] like Figure 14 As shown, the second set signal CAM_RST <n-1:0>The N SR flip-flops SR1 are set, and the second reset signal CLK_LA <n-1:0>Reset the N SR flip-flops SR1.

[0172] For example, for any state query circuit, take the i-th state query circuit 14i as an example, the state query circuit 14i includes an SR flip-flop SR1 and a NOT gate unit NOT_2.

[0173] The set input terminal / S of the SR trigger SR1 is used to receive the second set signal CAM_RST The reset input terminal / R of the SR trigger SR1 is used to receive the second reset signal CLK_LA The output terminal Q of the SR flip-flop SR1 is used to output the level signal ST_OPEN of the idle state bit .

[0174] The input end of the NOT gate unit NOT_2 is connected to the output end Q of the SR trigger SR1, and the output end of the NOT gate unit NOT_2 is used to output the level signal ST_LOCK of the storage status bit .

[0175] In which, when the i-th address register 11i stores address information Ai, the i-th SR flip-flop receives a second set signal corresponding to a first level state, so that the i-th SR flip-flop outputs a first level signal of an idle state bit; and, when the i-th address register 11i does not store address information, the i-th SR flip-flop receives a second reset signal corresponding to a second level state, so that the i-th SR flip-flop outputs a third level signal of an idle state bit. Exemplarily, the first level state can be a high level state or a low level state, for example, a low level state. In another exemplary embodiment, the second level state can be a high level state or a low level state, for example, a low level state.

[0176] In this embodiment, when address information is stored in any address register, a low-level second set signal can be provided to the set input terminal / S of the SR flip-flop SR1 corresponding to the address register. In this case, / S=0, and the output terminal Q can be set to 1. In this case, the storage state bit of the output terminal Q corresponds to a high-level signal. Also, when the address of any address register is cleared, a low-level second reset signal can be provided to the reset input terminal / R of the SR flip-flop SR1 corresponding to the address register. In this case, / R=0, the output terminal Q can be reset to 0. In this case, the storage state bit of the output terminal Q corresponds to a low-level signal. Thus, in the embodiment of the present disclosure, when the address register stores address information or clears address information, the second reset signal and the second set signal can be used to reset or set the SR flip-flop, thereby controlling the level of the SR flip-flop output terminal Q, so that the level of the SR flip-flop output terminal Q can accurately represent whether the address register stores an address, thereby improving the counting accuracy.

[0177] It should be noted that, since the SR trigger has the characteristics of simple structure and small area, it can reduce the cost and area of ​​the CAM storage device, facilitate integration and save costs.

[0178] In another example, the state query circuit 14i includes an SR flip-flop SR1, and the output terminal Q of the SR flip-flop SR1 is used to output the level signal ST_OPEN of the idle state bit. The inverting output terminal / Q of the SR trigger SR1 is used to output the level signal ST_LOCK of the storage status bit .

[0179] In one example, in order to improve the accuracy of the storage state recorded by the state query circuit, the second reset signal of the state query circuit 14i can be used as the clock signal of the i-th address register 11i. Figure 14 , the second reset signal CLK_LA <n-1:0>The second reset signal CLK_LA can be output to the clock signal input terminal CK of each address register through line B1. <0> Output to the clock signal input terminal CK of the address register 111, the second reset signal CLK_LA <1> Output to the clock signal input terminal CK of the address register 112, ..., the second reset signal CLK_LA <n-1>Output to the clock signal input terminal CK of the address register 11N.

[0180] In this example, by sharing the same signal between the second reset signal of the status query circuit and the clock signal of the address register, the status query circuit can be controlled to be modified to the first status signal while the address register is writing the address, so that the status signal output by the status query circuit can accurately represent whether the address register is idle or stores address information.

[0181] After introducing the specific structure of the status query circuit, the function of the status query circuit will be described next.

[0182] Figure 15 FIG. 2 shows another exemplary counting logic diagram of a CAM storage device provided by an embodiment of the present disclosure. Figure 15 As shown, the data "10" in status query circuits 141-143 corresponds to the first status signal, indicating that addresses A1-A3 are stored in address registers 111-113, respectively. The data "01" in status query circuits 144-146 corresponds to the second status signal, indicating that address registers 114-116 are in the idle state. At this point, if the fourth address register 114 is determined to be in the idle state based on the second status signal, input address A4 can be stored in the fourth address register 114. After storage, the status value of the fourth status query circuit 144 is changed from "01" to "10."

[0183] After introducing the status query circuit, for ease of understanding, the CAM storage device provided by the embodiment of the present disclosure is described below with an example.

[0184] Figure 16 FIG. 1 shows a schematic structural diagram of an exemplary CAM storage device provided by an embodiment of the present disclosure. Figure 16 As shown, the CAM storage device may include 6 state query circuits SR1. Among them, the 6 state query circuits SR1 can be set or reset under the control of the second set signal CAM_RST<5:0> and the second reset signal CLK_LA<5:0>. In addition, the 6 state query circuits SR1 can output the level signal ST_OPEN<5:0> of the idle state bit to indicate whether the address register corresponding to each state query circuit is in an idle state. In addition, the level signal ST_LOCK<5:0> of the storage state bit can be output through the NOT gate to indicate whether the address register corresponding to each state query circuit is in a storage state. Optionally, the second reset signal CLK_LA<5:0> can also be output to the clock signal input terminal CK of each latch to serve as the clock signal of each latch. For example, continue to refer to Figure 13 , the idle state bit can be represented as OP, and the storage state bit can be represented as LO.

[0185] In addition, the CAM storage device may include 6 groups of corresponding address registers and address comparison circuits. Among them, a group of address registers may include 17 latches, which are used to store one bit of address information respectively. Specifically, the input end of each address register is used to receive the input address RA<16:0> sent by the chip controller. Each address comparison circuit is used to compare the input address RA<16:0> sent by the chip controller with the address information RA_CAM<16:0> stored in the corresponding address register. If the two are the same, 1 is output, that is, match_bit=1. If the two are not the same, 0 is output, that is, match_bit=0. Exemplarily, the address information 6*RA_CAM<16:0> stored in each address register can also be provided to the outside through the output terminal. Exemplarily, continue to refer to Figure 13 , the address information stored in each address register can be expressed as RA_DLUT<16:0>.

[0186] Furthermore, the CAM storage device may further include 6 counter circuits, wherein each counter circuit may include 6 DFF flip-flops, which may implement counting functions of addition and subtraction. If the received match_bit=1, the count value of the corresponding counter circuit is added by 1. Furthermore, if each address register stores address information, when new address information is input, the count value subtraction function may be executed. Exemplarily, the count value 6*RA_CNT<5:0> stored in each counter circuit may also be provided to the outside through the output terminal. Exemplarily, continue to refer to Figure 13 The count value stored in each counter circuit can be expressed as RA_CNT<5:0>, and the counter circuit has the functions of +1 and -1.

[0187] Through the above examples, a dedicated CAM storage device is provided that can perform address register status query, address storage, and address counting functions. Furthermore, this dedicated CAM storage device can be applied to row hammer attack architectures in advanced process DRAMs, accurately capturing row hammer attack addresses while consuming fewer resources.

[0188] Based on the same inventive concept, an embodiment of the present disclosure further provides a CAM storage controller. Figure 17 A schematic structural diagram of a CAM storage controller provided by an embodiment of the present disclosure is shown.

[0189] like Figure 17 As shown, the CAM memory controller 1700 may include a count value processing circuit 1710 and a control circuit 1720 .

[0190] The count value processing circuit 1710 is connected to the output ends of the N counter circuits and is used to obtain the count values ​​of the N address registers; and when the input address does not match the address information stored in the N address registers and the N address registers all store address information, determine the first address register according to the count values ​​of the N address registers.

[0191] The control circuit 1720 is used to reset the first counter circuit, update the count value of the reset first counter circuit, and control other unreset counter circuits to reduce their count values.

[0192] In some embodiments, the CAM memory controller 1700 may include a memory status detection circuit.

[0193] The storage status detection circuit is connected to the N status query circuits and is used for detecting whether the N address registers all store address information according to status signals output by the N status query circuits.

[0194] In some embodiments, the count value processing circuit 1710 is specifically configured to:

[0195] When there is a target counter circuit among the N counter circuits whose count value is less than or equal to the preset number threshold, address information stored in the address register corresponding to the target counter circuit is determined as a hammer attack noise address, and the address register corresponding to the target counter circuit is determined as a first address register;

[0196] When the count values ​​of the N counter circuits are all greater than a preset number threshold, one of the counter circuits with the smallest count value is used as the first counter circuit.

[0197] In some embodiments, the count value is M-bit binary data, the i-th counter circuit includes M stages of counting units, wherein the j-th stage counting unit is used to record the j-th bit of the M-bit binary data, i is any positive integer less than or equal to N, M is any positive integer, and j is any positive integer less than or equal to M;

[0198] The CAM memory controller 1700 may include a counter control circuit.

[0199] The counter control circuit is specifically used for:

[0200] Obtaining count values ​​of other unreset counter circuits;

[0201] For each count value of the unreset counter circuit, the count value is subtracted by 1 to obtain a reduced count value, and a first reset signal and a first set signal corresponding to the reduced count value are generated, wherein when the j-th bit of the reduced count value is 0, the j-th bit of the first reset signal is 1; when the j-th bit of the reduced count value is 1, the j-th bit of the first set signal is 1.

[0202] The CAM storage controller provided by the embodiment of the present disclosure can determine the first address register to be reset among N address registers when all address registers store address information and the input address does not match the stored address information, reset and recount the count value of the counter circuit corresponding to the first address register, and reduce the count values ​​of other counter circuits that have not been reset, thereby ensuring counting accuracy while avoiding the impact of the counting results of each counter circuit being too large and exceeding the counting range of the address counting module on counting accuracy.

[0203] Based on the same inventive concept, the embodiment of the present disclosure provides an address counting method, which can be executed by a CAM storage device. The CAM storage device can refer to the relevant description of the above embodiment of the present disclosure, and will not be described in detail.

[0204] Figure 18 A flow chart of an address counting method provided by an embodiment of the present disclosure is shown. Figure 18 As shown, the address counting method provided in the embodiment of the present disclosure includes the following steps S1810 to S1840.

[0205] S1810 , each address comparison circuit matches the input address with the address information stored in its corresponding address register.

[0206] S1820: When the input address matches the address information stored in one of the address registers, the count value of the counter circuit corresponding to the address register increases.

[0207] S1830: When the input address does not match the address information stored in any of the N address registers, and all of the N address registers store address information, the first counter circuit and its corresponding first address register are reset, the first address register stores the input address, the first counter circuit increments its count value, and the other counter circuits that have not been reset decrement their count values. The first counter circuit is a counter to be reset determined among the N counter circuits based on the count value.

[0208] S1840: When the input address does not match any of the address information stored in the N address registers and a second address register exists, the input address is stored in the second address register and a count value of a corresponding second counter circuit is updated. The second address register is an address register in the N address registers that does not store address information.

[0209] In some embodiments, S1830 includes:

[0210] When the input address does not match the address information stored in the N address registers and the N address registers all store address information, the target counter circuit whose count value is less than or equal to the preset number threshold is the first counter circuit, wherein the resetting of the first address register corresponding to the target counter circuit is used to clear the stored noise address.

[0211] When the input address does not match the address information stored in the N address registers, the N address registers all store address information, and no target counter circuit exists, one of the counter circuits with the smallest count value serves as the first counter circuit.

[0212] No address register among the N address registers stores address information.

[0213] In some embodiments, the count value is M-bit binary data, the i-th counter circuit includes M stages of counting units, wherein the j-th stage counting unit is used to record the j-th bit of the M-bit binary data, i is any positive integer less than or equal to N, M is any positive integer, and j is any positive integer less than or equal to M;

[0214] When the count value of the i-th counter circuit is increased, the M-stage counting unit adds 1 to the original count value to obtain the increased count value;

[0215] And, when the count value of the i-th counter circuit is reduced, the M-stage counting unit stores the reduced count value,

[0216] The count value after reduction is obtained by the content addressable memory controller subtracting 1 from the count value before reduction.

[0217] In some embodiments, the address counting method further includes: when the i-th address register stores address information, the i-th state query circuit outputs a first state signal used to indicate that the i-th address register is in a storage state; and when the i-th address register does not store address information, the i-th address query circuit outputs a second state signal used to indicate that the i-th address register is in an idle state.

[0218] In some embodiments, the first state signal includes: a high level signal of an idle state bit and / or a low level signal of a storage state bit;

[0219] The second state signal includes: a low level signal of an idle state bit and / or a high level signal of a storage state bit.

[0220] In some embodiments, the i-th state query circuit includes an SR trigger and a NOT gate unit.

[0221] The set input terminal of the SR trigger is used to receive the second set signal, the reset input terminal of the SR trigger is used to receive the second reset signal, and the output terminal of the SR trigger is used to output the level signal of the idle state bit.

[0222] The input end of the NOT gate unit is connected to the output end of the SR trigger, and the output end of the NOT gate unit is used to output the level signal of the storage status bit.

[0223] Among them, when the i-th address register stores address information, the i-th SR trigger receives a second set signal corresponding to a low-level state, so that the i-th SR trigger outputs a high-level signal of the idle state bit; and when the i-th address register does not store address information, the i-th SR trigger receives a second set signal corresponding to a low-level state, so that the i-th SR trigger outputs a low-level signal of the idle state bit.

[0224] In some embodiments, the input address includes P bits, wherein the i-th address comparison circuit includes: P address comparison units and a signal processing unit.

[0225] S1810 includes: the kth address comparison unit outputting a first level signal when the kth bit of the address information stored in the i-th address register is the same as the kth bit of the input address. P is any positive integer, and k is any positive integer less than or equal to P. Furthermore, the signal processing unit generates a first count signal upon receiving the first level signals output by each of the P address comparison units. The first count signal is used to indicate that the input address matches the address information stored in the i-th address register.

[0226] In some embodiments, the input address is a row address for accessing a physical row sent by a chip controller.

[0227] S1810 includes: the second input terminal of each address comparison circuit obtains the row address of the accessed physical row from the chip controller. The second output terminal provides a first counting signal to the fourth input terminal when the row address matches the address information stored in the corresponding address register.

[0228] In addition, the address counting method also includes: each counter circuit provides the count value stored in the counter circuit to the row hammer attack controller, so that when the count value is greater than or equal to the preset row hammer threshold, the row hammer attack controller identifies the address information stored in the address register corresponding to the counter circuit as the row hammer attack address.

[0229] The address counting method provided by the embodiment of the present disclosure is that for any counter circuit, the address counting module can increase the count value of the address counting circuit when the corresponding address comparison circuit determines that the input address matches the stored address information, thereby achieving correct counting of the input address stored in the address register. In addition, when all address registers store address information and the input address does not match the stored address information, the first address register to be reset can be determined among the N address registers, the count value of the counter circuit corresponding to the first address register is reset and re-counted, and the count values ​​of other unreset counter circuits are reduced, thereby ensuring the counting accuracy while avoiding the impact of the counting results of each counter circuit being too large and exceeding the counting range of the address counting module on the counting accuracy. In addition, since the second address register is an address register that does not store address information, when the input address does not match the stored address information and there is an idle second address register, the input address can be stored in the second address register to accurately count the newly appeared input address. Accordingly, the technical solution provided by the embodiment of the present disclosure can accurately count the input addresses stored in the address registers and the new input addresses not stored in the address registers when the N address registers are not full of addresses. Moreover, when the N address registers are full of addresses, while ensuring the counting accuracy, it can avoid the counting results of each counter circuit being too large and exceeding the counting range of the address counting module, which affects the counting accuracy, thereby realizing accurate counting of each address information in the memory.

[0230] It should be noted that Figure 18 The address counting method 1800 shown can be used by Figures 2 to 16 One or more components of the device shown are executed and implemented Figures 2 to 16 The various processes and effects in the illustrated device embodiment are not described in detail here.

[0231] To facilitate an overall understanding of the address counting method provided by the embodiment of the present disclosure, an example is used below to illustrate the method.

[0232] In one example, Figure 19 FIG. 1 shows a flow chart of an exemplary address counting method provided by an embodiment of the present disclosure. Figure 19 As shown, the address counting method provided by the embodiment of the present disclosure includes S1901 to S1915.

[0233] S1901: The CAM storage device is initialized. Exemplarily, during initialization, the CAM may be completely empty. For example, the status signal output by the status query circuit indicates that each address register is in an idle state. Each address register stores an initial address value, such as RA<16:0> = 17'b1FFFF, which means the initial address value may include 17 ones. Each counter circuit stores an initial count value, such as CNT = 6'b0, which means it stores 6 zeros.

[0234] S1902, loading address information. For example, in the initialization phase, the address stream data (input address) sent by the chip controller (such as DRAM controller) can be loaded into the CAM storage device in sequence according to the first-in-first-out principle.

[0235] S1903: Determine whether a sampling flag is received. If yes, execute S1904; if no, execute S1910. For example, the sampling flag may be sent by the CAM memory controller.

[0236] S1904: Determine whether the input address matches each address information i. If yes, execute S1905; if no, it indicates that the input address does not match the address stored in the address register, and continue to execute S1905.

[0237] S1905, add 1 to the count value Cnti corresponding to the address information i.

[0238] S1906: Determine whether there is an address register with OP=1 or LO=0 (i.e., determine whether the OP output by the status query circuit corresponding to each address register is 1 or LO is 0). If the determination result is yes, execute S1908; if the determination result is no, continue to execute S1907.

[0239] S1907: Discard the input address.

[0240] S1908, store the address information into the idle address register n1.

[0241] S1909, increase the count value of address register n1 from 0 to 1.

[0242] S1910: Determine whether a discarding flag is received. If so, proceed to S19011. For example, if not, determine whether a row hammer attack refresh (RHR) flag is received. The RHR flag is used to indicate the use of each count value to identify rows under row hammer attack and / or to perform a refresh operation on the rows under row hammer attack.

[0243] S1911, determine whether there is an idle address register. If the judgment result is yes, execute S1912, if the judgment result is no, execute S1913.

[0244] S1912, store the input address.

[0245] S1913, determine whether there is an address register n2 whose count value cnt is less than or equal to 1. If the determination result is yes, execute S1914, if the determination result is no, execute S1915.

[0246] S1914: discard the address information of the address register n2 as a noise address and store it into the input address, and decrement the count values ​​of the other address registers except the address register n2 by 1.

[0247] S1915 , discard the address information of the address register n3 with the smallest count value and store it into the input address, and subtract 1 from the count values ​​of the other address registers except the address register n2 .

[0248] Based on the same inventive concept, the embodiment of the present disclosure provides a method for controlling address counting, which can be executed by a CAM memory controller. The CAM memory controller can refer to the relevant description of the above embodiment of the present disclosure, and will not be described in detail here.

[0249] Figure 20 FIG. 1 shows a flow chart of a method for controlling address counting provided by an embodiment of the present disclosure, such as Figure 20 As shown, the address counting control method provided in the embodiment of the present disclosure includes the following steps S2010 to S2030.

[0250] S2010: The count value processing circuit obtains count values ​​of N address registers.

[0251] S2020: When the input address does not match the address information stored in the N address registers, and the N address registers all store address information, determine a first address register according to the count values ​​of the N address registers.

[0252] S2030: The control circuit 1720 resets the first counter circuit, updates the count value of the reset first counter circuit, and controls other unreset counter circuits to reduce their count values.

[0253] In some embodiments, the address counting control method further includes: the storage status detection circuit detects whether all the N address registers store address information according to status signals output by the N status query circuits.

[0254] In some embodiments, S2020 may include:

[0255] When there is a target counter circuit among the N counter circuits whose count value is less than or equal to the preset number threshold, address information stored in the address register corresponding to the target counter circuit is determined as a hammer attack noise address, and the address register corresponding to the target counter circuit is determined as a first address register;

[0256] When the count values ​​of the N counter circuits are all greater than a preset number threshold, one of the counter circuits with the smallest count value is used as the first counter circuit.

[0257] In some embodiments, the count value is M-bit binary data, the i-th counter circuit includes M stages of counting units, wherein the j-th stage counting unit is used to record the j-th bit of the M-bit binary data, i is any positive integer less than or equal to N, M is any positive integer, and j is any positive integer less than or equal to M;

[0258] The control method of address counting also includes:

[0259] Obtaining count values ​​of other unreset counter circuits;

[0260] For each count value of the unreset counter circuit, the count value is subtracted by 1 to obtain a reduced count value, and a first reset signal and a first set signal corresponding to the reduced count value are generated, wherein when the j-th bit of the reduced count value is 0, the j-th bit of the first reset signal is 1; when the j-th bit of the reduced count value is 1, the j-th bit of the first set signal is 1.

[0261] The address counting control method provided by the embodiment of the present disclosure can determine the first address register to be reset among N address registers when all address registers store address information and the input address does not match the stored address information, reset and recount the count value of the counter circuit corresponding to the first address register, and reduce the count values ​​of other counter circuits that have not been reset, thereby ensuring the counting accuracy while avoiding the impact of the counting results of each counter circuit being too large and exceeding the counting range of the address counting module on the counting accuracy.

[0262] It should be noted that Figure 20 The control method of address counting shown can be achieved by Figure 18 One or more components of the device shown are executed and implemented Figure 18 The various processes and effects in the illustrated device embodiment are not described in detail here.

[0263] Based on the same inventive concept, an embodiment of the present disclosure further provides a memory, which may include a storage module and a CAM storage device.

[0264] The storage module may include multiple storage arrays (banks).

[0265] And the CAM storage device provided by any of the above embodiments of the present disclosure. The specific content of the CAM storage device can be found in the above embodiments of the present disclosure. Figure 2-Figure 16 The relevant description is omitted here.

[0266] For example, the memory in the embodiments of the present disclosure may be any one of the following dynamic random access memories, such as the fourth-generation double-bit data rate synchronous dynamic random access memory (DDR4 SDRAM), the fourth-generation low-power double-bit data rate synchronous dynamic random access memory (LPDDR4 SDRAM), the fifth-generation double-bit data rate synchronous dynamic random access memory (DDR5 SDRAM), and the fifth-generation low-power double-bit data rate synchronous dynamic random access memory (LPDDR5 SDRAM), without specific limitation. It should be noted that the memory may also be other memory besides dynamic random access memory, without specific limitation.

[0267] In some embodiments, the memory may further include a CAM memory controller. The specific contents of the CAM memory controller may be found in the above-mentioned embodiments of the present disclosure. Figure 17 The relevant description is omitted here.

[0268] The memory provided by the embodiment of the present disclosure, for any counter circuit, the address counting module can increase the count value of the address counting circuit when the corresponding address comparison circuit determines that the input address matches the stored address information, thereby achieving correct counting of the input address stored in the address register. In addition, when all address registers store address information and the input address does not match the stored address information, the first address register to be reset can be determined among the N address registers, the count value of the counter circuit corresponding to the first address register is reset and re-counted, and the count values ​​of other unreset counter circuits are reduced, thereby ensuring the counting accuracy while avoiding the impact of the counting results of each counter circuit being too large and exceeding the counting range of the address counting module on the counting accuracy. In addition, since the second address register is an address register that does not store address information, when the input address does not match the stored address information and there is an idle second address register, the input address can be stored in the second address register to accurately count the newly appeared input address. Accordingly, the technical solution provided by the embodiment of the present disclosure can accurately count the input addresses stored in the address registers and the new input addresses not stored in the address registers when the N address registers are not full of addresses. Moreover, when the N address registers are full of addresses, while ensuring the counting accuracy, it can avoid the counting results of each counter circuit being too large and exceeding the counting range of the address counting module, which affects the counting accuracy, thereby realizing accurate counting of each address information in the memory.

[0269] Based on the same inventive concept, an electronic device is also provided in an embodiment of the present disclosure. The electronic device may include the memory provided in any of the above embodiments of the present disclosure. The specific contents of the memory can be found in the relevant description of the above embodiments of the present disclosure, and will not be repeated here.

[0270] Among them, the electronic device of the embodiment of the present disclosure can be an electronic device equipped with a memory. For example, the electronic device can be a mobile terminal, a computer, a server, a virtual reality device, an Internet of Things device, etc.

[0271] In the electronic device provided by the embodiment of the present disclosure, for any counter circuit, the address counting module can increase the count value of the address counting circuit when the corresponding address comparison circuit determines that the input address matches the stored address information, thereby achieving correct counting of the input address stored in the address register. In addition, when all address registers store address information and the input address does not match the stored address information, a first address register to be reset can be determined among the N address registers, the count value of the counter circuit corresponding to the first address register is reset and re-counted, and the count values ​​of other unreset counter circuits are reduced, thereby ensuring counting accuracy while avoiding the impact of the counting results of each counter circuit being too large and exceeding the counting range of the address counting module on counting accuracy. In addition, since the second address register is an address register that does not store address information, when the input address does not match the stored address information and there is an idle second address register, the input address can be stored in the second address register to accurately count the newly appearing input address. Accordingly, the technical solution provided by the embodiment of the present disclosure can accurately count the input addresses stored in the address registers and the new input addresses not stored in the address registers when the N address registers are not full of addresses. Moreover, when the N address registers are full of addresses, while ensuring the counting accuracy, it can avoid the counting results of each counter circuit being too large and exceeding the counting range of the address counting module, which affects the counting accuracy, thereby realizing accurate counting of each address information in the memory.

[0272] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods, or program products. Therefore, various aspects of the present disclosure may be implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as "circuits," "modules," or "systems."

[0273] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. The method embodiment is described relatively simply, and for relevant details, please refer to the description of the system embodiment. The present disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications and additions, or change the order of the steps after understanding the spirit of the present disclosure. In addition, for the sake of brevity, a detailed description of known method technologies is omitted here.

[0274] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some ports, devices or units, which can be electrical, mechanical or other forms.

[0275] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0276] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0277] The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this disclosure, and they should all be covered by the protection scope of the present disclosure.

[0278] Therefore, the scope of protection of the present disclosure shall be based on the scope of protection of the claims. The present disclosure is intended to cover any modifications, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A content addressable storage device, characterized in that: include: N address registers, each used to store different address information, where N is an arbitrary positive integer; N counter circuits, corresponding one to one with the N address registers, and respectively used to store count values ​​of the corresponding address registers; N address comparison circuits, corresponding one to one with the N address registers, each of the address comparison circuits being configured to match an input address with the address information stored in its corresponding address register; in When the input address matches the address information stored in one of the address registers, the count value of the counter circuit corresponding to the address register increases; When the input address does not match the address information stored in the N address registers, and the N address registers all store address information, the first counter circuit and its corresponding first address register are reset, the first address register stores the input address, the first counter circuit increases its count value, and the other unreset counter circuits decrease their count values, wherein the first counter circuit is a counter to be reset determined among the N counter circuits based on the count value; When the input address does not match any of the address information stored in the N address registers and a second address register exists, the input address is stored in the second address register and a count value of a second counter circuit corresponding thereto is increased, where the second address register is an address register in which no address information is stored among the N address registers; The count value is M-bit binary data, the i-th counter circuit includes M-stage counting units, wherein the j-th stage counting unit is used to record the j-th bit of the M-bit binary data, i is any positive integer less than or equal to N, M is any positive integer, and j is any positive integer less than or equal to M; Wherein, when increasing the count value of the i-th counter circuit, the M-stage counting unit is used to add 1 to the original count value to obtain the increased count value; Furthermore, when the count value of the i-th counter circuit is reduced, the M-stage counting unit is used to store the reduced count value obtained by subtracting 1 from the original count value.

2. The device according to claim 1, characterized in that When the input address does not match the address information stored in the N address registers and the N address registers all store address information, the target counter circuit whose count value is less than or equal to the preset number threshold is the first counter circuit, wherein resetting the first address register corresponding to the target counter circuit is used to clear the stored noise address; When the input address does not match the address information stored in the N address registers, the N address registers all store address information, and the target counter circuit does not exist, one of the counter circuits with the smallest count value serves as the first counter circuit.

3. The device according to claim 1, characterized in that The j-th stage counting unit includes a j-th stage DFF trigger among M stages of DFF triggers, The inverting output terminal of the j-th stage DFF trigger is connected to the trigger terminal of the j+1-th stage DFF trigger, and the j-th stage DFF trigger is used to switch the recorded data between 0 and 1 according to the received trigger signal, and send a trigger signal to the j+1-th stage DFF trigger when the recorded data switches from 1 to 0. The trigger terminal of the first-stage DFF trigger is connected to the output terminal of the i-th address comparison circuit, and is used to switch between 0 and 1 when the i-th address comparison circuit outputs a first count signal. The i-th address comparison circuit outputs the first count signal when the input address matches the address information stored in the i-th address register. Furthermore, the j-th stage DFF trigger includes a reset terminal and a set terminal, and the j-th stage DFF trigger is further configured to: receive the j-th bit of the first reset signal through the reset terminal, and receive the j-th bit of the first set signal through the set terminal, and adjust the recorded data to the j-th bit binary data of the reduced count value according to the j-th bit of the first reset signal and the j-th bit of the first set signal, The first reset signal and the first set signal are generated by a content addressable memory controller and are used to adjust the value stored in the M-stage counting unit to the reduced count value.

4. The device according to claim 1, characterized in that The device further includes N status query circuits, and the N status query circuits correspond one-to-one to the N address registers. Among them, the i-th state query circuit is used to output a first state signal for indicating that the i-th address register is in a storage state when the i-th address register stores the address information; and to output a second state signal for indicating that the i-th address register is in an idle state when the i-th address register does not store the address information.

5. The device according to claim 4, characterized in that The first state signal includes: a first level signal of an idle state bit and / or a second level signal of a storage state bit; The second state signal includes: a third level signal of the idle state bit and / or a fourth level signal of the storage state bit.

6. The device according to claim 5, characterized in that The i-th state query circuit includes an SR trigger and a NOT gate unit. The set input terminal of the SR trigger is used to receive a second set signal, the reset input terminal of the SR trigger is used to receive a second reset signal, and the output terminal of the SR trigger is used to output the level signal of the idle state bit. The input end of the NOT gate unit is connected to the output end of the SR trigger, and the output end of the NOT gate unit is used to output the level signal of the storage status bit. Wherein, when the i-th address register stores the address information, the i-th SR trigger receives the second set signal corresponding to the first level state, so that the i-th SR trigger outputs the first level signal of the idle state bit; and, when the i-th address register does not store the address information, the i-th SR trigger receives the second reset signal corresponding to the second level state, so that the i-th SR trigger outputs the third level signal of the idle state bit.

7. The device according to claim 1, characterized in that The input address includes P bits, Wherein, the i-th address comparison circuit includes: P address comparison units, wherein the kth address comparison unit is configured to output a first level signal when the kth bit of the address information stored in the ith address register is the same as the kth bit of the input address; wherein P is any positive integer, and k is any positive integer less than or equal to P; A signal processing unit, the signal processing unit being connected to the P address comparison units and being configured to generate a first counting signal upon receiving a first level signal output by each of the P address comparison units, wherein the first counting signal is configured to indicate that the input address matches the address information stored in the i-th address register.

8. The device according to claim 1, characterized in that The input address is a row address of an access physical row sent by a chip controller; Each of the address registers includes a first input terminal and a first output terminal, wherein the first input terminal is connected to the chip controller for obtaining the row address; and the first output terminal is used to output the stored address information; Each of the address comparison circuits includes a second input terminal, a third input terminal, and a second output terminal, wherein the second input terminal is connected to the chip controller and is used to obtain the row address of the accessed physical row; The third input terminal is connected to the first output terminal of the corresponding address register; the second output terminal is connected to the fourth input terminal of the corresponding counter circuit, and is configured to provide a first counting signal to the fourth input terminal when the row address matches the address information stored in the corresponding address register; Each of the counter circuits includes a fourth input terminal and a fifth output terminal. The fifth output terminal is connected to the row hammer attack controller and is used to provide the row hammer attack controller with a count value stored in the counter circuit, so that the row hammer attack controller recognizes the address information stored in the address register corresponding to the counter circuit as a row hammer attack address when the count value is greater than or equal to a preset row hammer threshold.

9. A content addressable storage controller, characterized in that: The controller is used to control the content addressable storage device according to any one of claims 1 to 8, and the controller includes: a count value processing circuit connected to the output terminals of the N counter circuits, configured to obtain count values ​​of the N address registers; and when the input address does not match the address information stored in the N address registers and the N address registers all store address information, determining the first address register according to the count values ​​of the N address registers; The control circuit is used to reset the first counter circuit, update the count value of the reset first counter circuit, and control other unreset counter circuits to reduce their count values.

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